US20020004875A1

US20020004875A1 - Memory device

Info

Publication number: US20020004875A1
Application number: US09/866,780
Authority: US
Inventors: Daping Chu
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 2000-05-31
Filing date: 2001-05-30
Publication date: 2002-01-10
Anticipated expiration: 2021-05-30
Also published as: US6498742B2; GB2362990B; JP4042351B2; JP2002100744A; GB2362990A; GB0013230D0

Abstract

A memory device comprising an n-channel transistor and p-channel transistor, both transistors having a source, a drain and a gate, the source and drains of the transistors being connected in series and the gates of the transistors being connected together, with each transistor having a ferroelectric material separating the gate from the source and drain thereof. Preferably a single ferroelectric material acts as the ferroelectric material for both transistors and a single gate acts as the gate for both transistors. Beneficially the device comprises a single substrate having an n-type source, an n-type drain, a p-type source and a p-type drain formed in a surface thereof and a single area of the substrate which separates all of these regions from each other has intrinsic doping only. The invention also relates to a method of manufacturing such memory devices.

Description

The present invention relates to a memory device for data storage and in particular the invention relates to a memory device which makes use of ferroelectric materials for data storage.

Ferroelectric materials can exhibit a non-volatile, bi-stable internal polarisation. The state of polarisation is established by the application of a voltage between opposing surfaces of the material. Having applied a sufficiently large voltage to internally polarise the material, it is subsequently possible to determine the direction of polarisation—which can be used as a binary indicator, whereby the material can act as a data storage medium. However, a problem arises in that the data read operation is destructive of the data. Specifically, the read operation consists of applying a voltage to set the polarisation in a specified direction. If the polarisation is already in that direction no charge exchange is required. However, if the polarisation is in the opposite direction a relatively large amount of charge exchange is required to establish the specified direction of polarisation. Thus, the previous direction of polarisation can be judged according to the high or low (zero) level of charge exchange required to establish the specified polarisation.

A ferroelectric data storage device in which the stored data can be read non-destructively is possible by detecting the polarisation of the ferroelectric material using the field effect. Specifically, using a ferroelectric material in place of the conventional gate oxide layer in a field effect transistor results in a detectable hysterisis in the transfer characteristic of the transistor. This device may conveniently be referred to as a ferroelectric field effect transistor, or FFET. Such a device is very attractive for many applications but it's widespread adoption is hindered by several problems. Firstly, high power consumption occurs during the read operation when the channel of the transistor is in the on state. Secondly, a high voltage is required to write data (switch polarisation direction) when the channel is in the off state.

It is an object of the present invention to provide a memory device which makes use of the internal polarisation of a ferroelectric material for data storage and in which a non-destructive data read operation can be undertaken. It is an object of one aspect of the present invention to avoid high power consumption during the read operation. It is an object of another aspect of the present invention to avoid the need for a high write voltage during the write operation.

According to a first aspect of the present invention there is provided a memory device comprising an n-channel transistor and p-channel transistor, both transistors having a source, a drain and a gate, the source and drains of the transistors being connected in series and the gates of the transistors being connected together, with each transistor having a ferroelectric material separating the gate from the source and drain thereof.

Preferably, the memory device comprises a single ferroelectric material which acts as the ferroelectric material for both transistors.

Preferably, the memory device comprises a single gate which acts as the gate for both transistors.

Preferably, the memory device comprises a single substrate having an n-type source, an n-type drain, a p-type source and a p-type drain formed in a surface thereof. Further, the memory device preferably has a single area of the substrate which separates all of the n-type source, n-type drain, a p-type source and p-type drain from each other which single area has intrinsic doping only. Additionally, the memory device is preferably such that each of the n-type source, n-type drain, a type source and p-type drain has a region of reduced doping so as to reduce leakage currents between the two transistors.

According to a second aspect of the present invention there is provided a method of reducing power consumption in a memory device which stores data using the polarisation of a ferroelectric material comprising the steps of: providing an n-channel transistor, providing a p-channel transistor, both transistors having a source, a drain and a gate, arranging for series connection of the source and drains of the transistors, arranging for the gates of the transistors to be connected together, and providing for each transistor to have a ferroelectric material separating the gate from the source and drain thereof.

Preferably, the method comprises the step of providing a single ferroelectric material which acts as the ferroelectric material for both transistors.

Preferably, the method comprises the step of providing a single gate which acts as the gate for both transistors.

Preferably, the method comprises the step of providing a single substrate having an n-type source, an n-type drain, a p-type source and a type drain formed in a surface thereof. Further, the method preferably comprises the step of providing for a single area of the substrate which separates all of the n-type source, n-type drain, a p-type source and p-type drain from each other to have intrinsic doping only. Additionally, the method preferably comprises the step of providing each of the n-type source, n-type drain, a type source and p-type drain with a respective region of reduced doping so as to reduce leakage currents between the two transistors.

Embodiments of the present invention will now be described in more detail, by way of further example only and with reference to the accompanying drawings, in which:

FIG. 1 a illustrates the structure of an n-channel ferroelectric field effect transistor; together with a circuit symbol used herein to denote such a transistor;

FIG. 1 b illustrates the structure of a p-channel ferroelectric field effect transistor; together with a circuit symbol used herein to denote such a transistor;

FIG. 2 is a circuit diagram of an embodiment of a memory device according to the present invention; and

FIG. 3 illustrates a structural implementation of the circuit shown in FIG. 2.

The basic structure of an n-channel and a p-channel ferroelectric field effect transistor is respectively shown in FIGS. 1[0018] a and 1 b. In each case an associated circuit symbol is shown. These circuit symbols are used in the circuit diagram of FIG. 2, which depicts an embodiment of the present invention. As readily seen from FIG. 2, the embodiment of the invention comprises a source/drain series connected n-channel ferroelectric transistor and n-channel ferroelectric transistor. The gates of the transistors arc connected in common, V_GS. An output, V_out, is taken at the source/drain connection between the transistors. The source of the channel transistor is annotated V_Sand the drain of the n-channel transistor is annotated V_DS.
Read-out from the memory cell illustrated in FIG. 2 is non-destructive and is voltage rather than current related. The circuit has the advantage of very low drain current and hence minimum power consumption for the Read operation. In particular, even when V[0019] _GSis zero one of the n-channel and p-channel transistors is nearly on and the other is nearly off, ie one is less resistive than the other. Switching between which of the two transistors is on and which is off is achieved by changing the polarisation of the ferroelectric material. That is, assuming that data has previously been written, so as to set the polarisation of the ferroelectric material in the two transistors to one of the two possible directions, that V_Sis set to zero and that V_DSis set to a small positive value: V_outis equal to V_DSor zero depending on the direction of polarisation of the ferroelectric material. One of the transistors is on and the other is off, so that V_outis connected to V_Sor V_DS. It is to be noted that V_DScan be set much smaller (typically several mV) than the voltage (typically 2V) required to change the direction of polarisation of the ferroelectric material in the two transistors. This ensures that the Read operation is non-destructive. It is assumed that V_Sis set at zero for simplicity of explanation only.
The Read operation is voltage based and the drain current involved is at leakage current level. Hence the Read operation can be very fast and its power consumption is minimal. [0020]
Data is written to the memory cell by setting V[0021] _DSand V_outto zero and then driving V_GSto a sufficiently large positive/negative voltage (typically 2V) to polarise the ferroelectric material to the positive/negative direction. Of course, the positive/negative directions are used to represent by states. Although it has been assumed that V_DS, V_Sand V_outare set to zero they can be at other voltages. What is required is a sufficient voltage differential across the ferroelectric material to set the internal polarisation thereof in the desired direction.
Typically the write voltage for a FFET can vary from +2V to −7V for a p-channel transistor, depending on the direction of polarisation. The electric field generated by the polarisation changes the channel resistance significantly, resulting in a considerably large write current. [0022]
FIG. 3 illustrates a structural implementation of the circuit shown in FIG. 2. Described simply, the structure has a substrate with an n-channel extending thereacross in one direction and a p-channel extending thereacross in a direction perpendicular to the n-channel. The n- and p-channels form a cross, the centre of which is covered by a single section of ferroelectric material separating the channels from a single gate electrode. Where the channels cross, beneath the ferroelectric material, is neither n- or p- doped but is instead left with the intrinsic doping of the material. Typically the substrate win be fabricated from amorphous or polycrystalline silicon. The doped regions , n- and p-, act as the source and drain of the respective n- and p-channel transistors. The channel of each transistor is the intrinsically doped area beneath the ferroelectric material. Preferably, a lower dosage doping is used adjacent the central area (as indicated by the grey shading in FIG. 3). This reduces the cross-leakage between the n- and p-channels. [0023]
In the structure illustrated in FIG. 3 there is always one channel path in a high resistance state and one channel path in a low resistance state, regardless of the direction of polarisation of the ferroelectric material. There is always a low resistance path and thus the voltage required for the Write operation is not increased by channel resistance. As a consequence the voltage required to switch the polarisation state (in the Write operation) is limited only by the materials used to fabricate the device. That is, the structure achieves the lowest possible write voltage. The Read operation remains as described above. [0024]
In addition to the remarkable effect upon the required write voltage, it will also be appreciated that the structure according to FIG. 3 shares the same ferroelectric material and gate electrode for both transistors. Thus, the total size of the device is considerably reduced compared with separate implementation of the two transistors. [0025]
Embodiments according to the present invention can be small in size, can achieve minimal power consumption and the lowest possible operating voltages. [0026]
The above described memory cells car be used in a large scale memory matrix and the driving scheme for matrix may be either active or passive. [0027]
The foregoing description has been given by way of example only and it will be appreciated by a person skilled in the art that modifications can be made without departing from the scope of the present invention. [0028]

Claims

1. A memory device comprising an n-channel transistor and p-channel transistor, both transistors having a source, a drain and a gate, the source and drains of the transistors being connected in series and the gates of the transistors being connected together, with each transistor having a ferroelectric material separating the gate from the source and drain thereof.

2. A memory device as claimed in claim 1, comprising a single ferroelectric material which acts as the ferroelectric material for both transistors.

3. A memory device as claimed in claim 1 or claim 2, comprising a single gate which acts as the gate for both transistors.

4. A memory device as claimed in any preceding claim, comprising a single substrate having an n-type source, an n-type drain, a p-type source and a p-type drain formed in a surface thereof.

5. A memory device as claimed in claim 4, wherein a single area of the substrate which separates all of the n-type source, n-type drain, a p-type source and p-type drain from each other has intrinsic doping only.

6. A memory device as claimed in claim 4 or claim 5, wherein each of the n-type source, n-type drain, a p-type source and p-type drain has a region of reduced doping so as to reduce leakage currents between the two transistors.

7. A method of reducing power consumption in a memory device which stores data using the polarisation of a ferroelectric material comprising the steps of: providing an n-channel transistor, providing a p-channel transistor, both transistors having a source, a drain and a gate, arranging for series connection of the source and drains of the transistors, arranging for the gates of the transistors to be connected together, and providing for each transistor to have a ferroelectric material separating the gate from the source and drain thereof.

8. A method as claimed in claim 7, comprising the step of providing a single ferroelectric material which acts as the ferroelectric material for both transistors.

9. A method as claimed in claim 7 or claim 8, comprising the step of providing a single gate which acts as the gate for both transistors.

10. A method as claimed in any of claims 7 to 9, comprising the step of providing a single substrate having an n-type source, an n-type drain, a p-type source and a p-type drain formed in a surface thereof.

11. A method as claimed in claim 10, comprising the step of providing for a single area of the substrate which separates all of the n-type source, n-type drain, a p-type source and p-type drain from each other to have intrinsic doping only.

12. A method as claimed in claim 10 or claim 11, comprising the step of providing each of the n-type source, n-type drain, a p-type source and p-type drain with a respective region of reduced doping so as to reduce leakage currents between the two transistors.