US20020046705A1 - Atomic layer doping apparatus and method - Google Patents

Atomic layer doping apparatus and method Download PDF

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US20020046705A1
US20020046705A1 US09/982,954 US98295401A US2002046705A1 US 20020046705 A1 US20020046705 A1 US 20020046705A1 US 98295401 A US98295401 A US 98295401A US 2002046705 A1 US2002046705 A1 US 2002046705A1
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doping
wafer
regions
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substrate
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Gurtej Sandhu
Trung Doan
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67167Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2254Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/6719Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/67213Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one ion or electron beam chamber
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67745Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices

Definitions

  • the present invention relates to the field of semiconductor integrated circuits and, in particular, to an improved method for doping wafers.
  • Doping by thermal diffusion is a two-step process.
  • the semiconductor In the first step, called predeposition, the semiconductor is either exposed to a gas stream containing excess dopant at low temperature to obtain a surface region saturated with the dopant, or a dopant is diffused into a thin surface layer from a solid dopant source coated onto the semiconductor surface.
  • the predeposition step is followed by the drive-in step, during which the semiconductor is heated at high temperatures in an inert atmosphere so that the dopant in the thin surface layer of the semiconductor is diffused into the interior of the semiconductor, and thus the predeposited dopant atoms are redistributed to a desired doping profile.
  • Ion implantation is preferred over thermal diffusion because of the capability of ion implantation to control the number of implanted dopant atoms, and because of its speed and reproducibility of the doping process.
  • the ion implantation process employs ionized-projectile atoms that are introduced into solid targets, such as a semiconductor substrate, with enough kinetic energy (3 to 500 KeV) to penetrate beyond the surface regions.
  • a typical ion implant system uses a gas source of dopant, such as, BF 3 , PF 3 , SbF 3 , or AsH 3 , for example, which is energized at a high potential to produce an ion plasma containing dopant atoms.
  • An analyzer magnet selects only the ion species of interest and rejects the rest of species.
  • the desired ion species are then injected into an accelerator tube, so that the ions are accelerated to a high enough velocity to acquire a threshold momentum to penetrate the wafer surface when they are directed to the wafers.
  • ion implantation has many advantages, such as the ability to offer precise dopant concentrations, for example, for silicon of about 10 14 to 10 21 atoms/cm 3 , there are various problems associated with this doping method.
  • a major drawback for ion implantation is the radiation damage, which occurs because of the bombardment involved with heavy particles and further affects the electrical properties of the semiconductor.
  • the most common radiation damage is the vacancy-interstitial defect, which occurs when an incoming dopant ion knocks substrate atoms from a lattice site and the newly dislocated atoms rest in a non-lattice position.
  • doping atoms are not electrically active right after implantation mainly because the dopant atoms do not end up on regular, active lattice sites.
  • the crystal lattice could be fully restored and the introduced dopant atoms are brought to electrically active lattice sites by diffusion.
  • Ion channeling is another drawback of ion implantation that could also change the electrical characteristics of a doped semiconductor. Ion channeling occurs when the major axis of the crystal wafer contacts the ion beam, and when ions travel down the channels, reaching a depth as much as ten times the calculated depth. Thus, a significant amount of additional dopant atoms gather in the channels of the major axis. Ion channeling can be minimized by several techniques, such as employing a blocking amorphous surface layer or misorienting the wafer so that the dopant ions enter the crystal wafer at angles different than a 90° angle. For example, misorientation of the wafer 3 to 7° off the major axis prevents the dopant ions from entering the channels. However, these methods increase the use of the expensive ionimplant machine and, thus, could be very costly for batch processing.
  • Another disadvantage of the conventional doping methods is the autodoping.
  • dopants After dopants are incorporated into a crystalline wafer to form various junctions, they undergo many subsequent processing steps for device fabrication.
  • efforts are made to use low-temperature processing techniques to minimize redistribution of incorporated dopant atoms, the dopants still redistribute during the course of further processing.
  • this redistribution of dopants becomes extremely important when an epitaxial film is grown over the top of the doped area, particularly because of the high temperature required for epitaxial growth.
  • the dopant diffuses into the growing epitaxial film during the epitaxial growth, and this phenomenon is referred to as autodoping.
  • This phenomenon also leads to unintentional doping of the film in between the doped regions, or into the nondiffused substrate. For this, integrated circuit designers must leave adequate room between adjacent regions to prevent the laterally diffused regions from touching and shorting.
  • the present invention provides an improved method and unique atomic layer doping system and method for wafer processing.
  • the present invention contemplates an apparatus provided with multiple doping regions in which individual monolayers of dopant species are first deposited by atomic layer deposition (ALD) on a wafer and then the respective dopants are diffused, by thermal reaction, for example, into the wafer surface.
  • ALD atomic layer deposition
  • Each doping region of the apparatus is chemically isolated from the other doping regions, for example, by an inert gas curtain.
  • a robot is programmed to follow pre-defined transfer sequences to move wafers into and out of respective doping regions for processing.
  • a multitude of wafers can be simultaneously processed in respective regions, each region depositing only one monolayer dopant species and subsequently diffusing the dopant into the wafer.
  • Each wafer can be moved through the cycle of regions until a desired doping concentration and profile is reached.
  • the present invention allows for the atomic layer doping of wafers with higher commercial productivity and improved versatility. Since each region may be provided with a pre-determined set of processing conditions tailored to one particular monolayer dopant species, cross contamination is also greatly reduced.
  • FIG. 1 illustrates a schematic top view of a multiple-chamber atomic layer doping apparatus according to the present invention.
  • FIG. 2 is a partial cross-sectional view of the atomic layer doping apparatus of FIG. 1, taken along line 2 - 2 ′ and depicting two adjacent doping regions according to a first embodiment of the present invention and depicting one wafer transfer sequence.
  • FIG. 3 is a partial cross-sectional view of the atomic layer doping apparatus of FIG. 1, taken along line 2 - 2 ′ and depicting two adjacent doping regions according to a second embodiment of the present invention.
  • FIG. 4 is a partial cross-sectional view of the atomic layer doping apparatus of FIG. 2, depicting a physical barrier between two adjacent doping chambers.
  • FIG. 5 is a schematic top view of a multiple-chamber atomic layer doping apparatus according to the present invention and depicting a second wafer transfer sequence.
  • substrate used in the following description may include any semiconductor-based structure. Structure must be understood to include silicon, silicon-on insulator (SOI), silicon-on sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures.
  • SOI silicon-on insulator
  • SOS silicon-on sapphire
  • the semiconductor need not be silicon-based.
  • the semiconductor could be silicon-geranium, germanium, or gallium arsenide.
  • previous process steps may have been utilized to form regions or junctions in or on the base semiconductor or foundation.
  • dopant is intended to include not only elemental dopant atoms, but dopant atoms with other trace elements or in various combinations with other elements as known in the semiconductor art, as long as such combinations retain the physical and chemical properties of the dopant atoms.
  • p-type dopant used in the following description may include any p-type impurity ions, such as zinc (Zn), magnesium (Mg), beryllium (Be), boron (B), gallium (Ga) or indium (In), among others.
  • n-type dopant may include any n-type impurity ions, such as silicon (Si), sulfur (S), tin (Sn), phosphorus (P), arsenic (As) or antimony (Sb), among others.
  • the present invention provides an atomic layer doping method and apparatus.
  • the apparatus is provided with multiple doping regions in which individual monolayer dopant species are first deposited on a substrate and then dopant atoms corresponding to each of the monolayer species are diffused into respective substrates.
  • Each doping region is chemically separated from the adjacent doping regions.
  • a robot is programmed to follow pre-defined transfer sequences for moving wafers into and out of the respective adjacent doping regions. According to the number of doping regions provided, a multitude of substrates could be simultaneously processed and run through the cycle of different doping regions until a desired doping concentration of a wafer surface is completed.
  • the present invention provides a simple and novel multi-chamber system for atomic layer doping processing.
  • the present invention will be described below with reference to the atomic layer deposition of a dopant species Ax and the subsequent diffusion of its dopant atoms into a wafer, it must be understood that the present invention has equal applicability for the formation of any doped material capable of being formed by atomic layer doping techniques using any number of species, where each dopant species is deposited in a reaction chamber dedicated thereto.
  • FIG. 1 A schematic top view of a multiple-chamber atomic layer doping apparatus 100 of the present invention is shown in FIG. 1.
  • doping regions 50 a, 50 b, 52 a, 52 b, 54 a, and 54 b are alternately positioned around a loading mechanism 60 , for example a robot.
  • These doping regions may be any regions for the atomic layer doping treatment of substrates.
  • the doping regions may be formed as cylindrical reactor chambers, 50 a, 50 b, 52 a, 52 b, 54 a, and 54 b, in which adjacent chambers are chemically isolated from one another.
  • the reactor chambers are arranged in pairs 50 a, 50 b; 52 a, 52 b; 54 a, 54 b.
  • One such pair, 50 a, 50 b is shown in FIG. 2. While one of the reactor chambers of a pair, for example 50 a, deposits one monolayer of the dopant species Ax, the other reactor chamber of the pair, for example 50 b, facilitates subsequent diffusion of the dopant atoms of species Ax into the wafer to complete the doping process.
  • the adjacent reactor chamber pairs are chemically isolated from one another, for example by a gas curtain, which keeps the monolayer of dopant species Ax in a respective region, for example 50 a, and which allows wafers treated in one reaction chamber, for example 50 a, to be easily transported by the robot 60 to the other reaction chamber 50 b, and vice versa.
  • the robot can also move wafers between chambers 52 a or 52 b, and 54 a and 54 b.
  • the paired reaction chambers show a wall through which the wafers may pass, with the gas curtain acting in effect as a chemical barrier preventing the gas mixture within one chamber, for example 50 a, from entering the paired adjacent chamber, for example 50 b.
  • the robot can simply move wafers back and forth between the adjacent chambers, for example 50 a, 50 b, until the desired doping profile and/or concentration of the wafer is obtained.
  • one or more additional chambers may also be used for deposition of additional respective monolayers of dopant species, such as By, for example, wit h the additional chambers being chemically isolated from the chambers depositing the Ax monolayer dopant species in the same way the chambers for depositing the Ax species are chemically isolated.
  • the loading assembly 60 of FIG. 1 may include an elevator mechanism along with a wafer supply mechanism.
  • the supply mechanism may be further provided with clamps and pivot arms, so that a wafer 55 can be maneuvered by the robot and positioned according to the requirements of the atomic layer doping processing described in more detail below.
  • a processing cycle for atomic layer doping on a wafer 55 begins by selectively moving a first wafer 55 , from the loading assembly 60 to the chamber reactor 50 a, in the direction of arrow A 1 (FIG. 1).
  • a second wafer 55 ′ may be selectively moved by the loading assembly 60 to the chamber reactor 52 a, in the direction of arrow A 2 .
  • a third wafer 55 ′′ is also selectively moved by the loading assembly 60 to the chamber reactor 54 a, in the direction A 3 .
  • each of chambers 50 a, 52 a, 54 a are ready for atomic layer deposition of a monolayer of a dopant species, for example Ax.
  • FIG. 2 illustrates a cross-sectional view of the apparatus 100 of FIG. 1, taken along line 2 - 2 ′.
  • FIG. 2 shows only a cross-sectional view of adjacent reactor chambers 50 a and 50 b.
  • the wafer 55 is placed inside of the reactor chamber 50 a, which may be provided as a quartz or aluminum container 120 .
  • the wafer 55 is placed by the loading assembly 60 (FIG. 1) onto a suscepter 140 a (FIG. 2), which in turn is situated on a heater assembly 150 a.
  • a dopant gas supply inlet 160 a Mounted on the upper wall of the reactor chamber 50 a is a dopant gas supply inlet 160 a, which is further connected to a dopant gas supply source 162 a for a first dopant gas precursor Ax.
  • An exhaust outlet 180 a connected to an exhaust system 182 a, is situated on the opposite wall from the dopant gas supply inlet 160 a.
  • the wafer 55 is positioned on top of the suscepter 140 a (FIG. 2) by the loading assembly 60 , and then a first dopant gas precursor Ax is supplied into the reactor chamber 50 a through the dopant gas inlet 160 a.
  • the first dopant gas precursor Ax flows at a right angle onto the wafer 55 and reacts with its top substrate surface to form a first monolayer 210 a of the first dopant species Ax, by an atomic layer deposition mechanism.
  • Preferred gas sources of dopants are hydrated forms of dopant atoms such as arsine (AsH 3 ) and diborane (B 2 H 6 ).
  • These gases are mixed in different dilutions in pressurized containers, such as the dopant gas supply source 162 a (FIG. 2), and connected directly to the dopant gas inlets, such as the dopant gas inlet 160 a (FIG. 2).
  • Gas sources offer the advantage of precise control through pressure regulators and are favored for deposition on larger wafers.
  • a liquid source of dopant such as chlorinated or brominated compounds of the desired element may be used.
  • a liquid source of dopant such as chlorinated or brominated compounds of the desired element
  • a boron liquid source for example boron tribromide (BBr 3 ), or a phosphorous liquid source, for example phosphorous oxychloride (POCl 3 )
  • an inert gas such as nitrogen (N 2 )
  • N 2 nitrogen
  • the inert gas carries the dopant vapors through a gas tube and creates a laminar flow of dopant atoms.
  • reaction gas is also required to create the elemental dopant form in the tube.
  • the reaction gas is oxygen, which creates the boron trioxide (B 2 O 3 ) which further deposits as a monolayer of boron trioxide on the surface of the wafer.
  • the processing cycle for the wafer 55 continues with the removal of the wafer 55 from the chamber reactor 50 a to the chamber reactor 50 b, in the direction of arrow B 1 , as also illustrated in FIG. 1.
  • the wafer 55 is moved from the reactor chamber 50 a, through a gas curtain 300 (FIG. 2), to the reactor chamber 50 b, by the loading assembly 60 (FIG. 1) and in the direction of arrow B 1 of FIG. 2. It is important to note that the gas curtain 300 provides chemical isolation between adjacent deposition regions.
  • the loading assembly 60 moves the wafer 55 through the gas curtain 300 , onto the suscepter 140 b situated in the reactor chamber 50 b, which, in contrast with the reactor chamber 50 a, contains no dopant source and no dopant species.
  • a heater assembly 150 b is positioned under the suscepter 140 b to facilitate the diffusion of the dopant atoms from the newly deposited first monolayer 210 a of the first dopant species Ax into the wafer 55 .
  • the heat from the heater assembly 150 b drives the dopant atoms into the wafer 55 and further redistributes the dopant atoms from the first monolayer 210 a deeper into the wafer 55 to form a doped region 210 b of the first dopant species Ax.
  • the surface concentration of dopant atoms is reduced and the distribution of dopant atoms continues, so that a precise and shallow doping distribution in the doped region 210 b of the wafer 55 is obtained. Accordingly, the depth of the doped region 210 b of the wafer 55 is controlled, first, by the repeatability of the atomic layer deposition for the monolayers of dopant species and, second, by the degree of diffusion of dopants form the monolayers of dopant species into the wafers.
  • a plasma of a non-reactive gas may be used to complete the diffusion of the dopant atoms into the doped region 210 b of the wafer 55 .
  • a supply inlet 160 b (FIG. 2), which is further connected to a non-reactive gas supply source 162 b, for the plasma of the non-reactive gas, is mounted on the upper wall of the reactor chamber 50 b.
  • An exhaust inlet 180 b, connected to an exhaust system 182 b, is further situated on the opposite wall to the non-reactive gas supply inlet 160 b.
  • the non-reactive gas By is supplied into the reactor chamber 50 b through the non-reactive gas inlet 160 b, the non-reactive gas By flowing at a right angle onto the deposited first monolayer 210 a of the first dopant species Ax. This way, particles of the non-reactive gas By “knock” the dopant atoms from the first monolayer 210 a of the first doping species Ax into the wafer 55 to form the doped region 210 b of the wafer 55 .
  • the process continues with the removal of the wafer 55 from the reactor chamber 50 b, through the gas curtain 300 , and into the reactor chamber 50 a to continue the doping process. This process is repeated cycle after cycle, with the wafer 55 traveling back and forth between the reactor chamber 50 a, and the reactor chamber 50 b, to acquire the desired doping profile of the region 210 b.
  • an anneal step in the atomic layer doping process is required, to restore any crystal damage and to electrically activate the dopant atoms.
  • annealing can be achieved by a thermal heating step.
  • the anneal temperature must be preferably below the diffusion temperature to prevent lateral diffusion of the dopants.
  • the anneal step could take place in the reactor chamber 50 b, for example, by controlling the heat from the heater assembly 150 b.
  • the anneal step may take place into an adjacent reactor chamber, for example reactor chamber 52 a, depending on the processing requirements and the desired number of wafers to be processed.
  • the present invention has the major advantage of allowing different processing conditions, for example, deposition or diffusion temperatures, in different reactor chambers. This is important since the chemisorption and reactivity requirements of the ALD process have specific temperature requirements, in accordance with the nature of the precursor gas. Accordingly, the apparatus of the present invention allows, for example, reactor chamber 50 a to be set to a different temperature than that of the reactor chamber 50 b. Further, each reactor chamber may be optimized either for improved chemisorption, reactivity or dopant conditions.
  • the configuration of the atomic layer doping apparatus illustrated above also improves the overall yield and productivity of the doping process, since each chamber could run a separate substrate, and therefore, a plurality of substrates could be run simultaneously at a given time.
  • each reactor chamber accommodates only one dopant species, cross-contamination from one wafer to another is greatly reduced.
  • the production time can be decreased since the configuration of the apparatus of the present invention saves a great amount of purging and reactor clearing time.
  • first and second reactor chambers 50 a, 50 b could also process another first substrate 55 , in a direction opposite to that of processing the other first substrate. For example, if one first substrate 55 travels in the direction of arrow B 1 (FIG. 2) the other first substrate 55 could travel in the opposite direction of arrow B 1 , that is from the second reactor chamber 50 b to the first reactor chamber 50 a.
  • the wafer 55 is then moved back by the assembly system 60 to the reactor chamber 50 a, where a second monolayer of the first dopant species Ax is next deposited over the first monolayer of the first dopant species Ax.
  • the wafer 55 is further moved to the reactor chamber 50 b for the subsequent diffusion of the dopant atoms from the second monolayer of the first dopant species Ax.
  • the cycle continues until a desired doping concentration on the surface of the wafer 55 is achieved, and, thus, the wafer 55 travels back and forth between reactor chambers 50 a and 50 b.
  • the same cycle process applies to the other two wafers 55 ′, 55 ′′ that are processed simultaneously in their respective reactor chambers.
  • the gas curtain 300 provides chemical isolation to all adjacent deposition regions.
  • the gas curtain 300 is provided between the two adjacent reactor chambers 50 a and 50 b so that an inert gas 360 , such as nitrogen, argon, or helium, for example, flows through an inlet 260 connected to an inert gas supply source 362 to form the gas curtain 300 , which keeps the first dopant gas Ax and the non-reactive gas By from flowing into adjacent reaction chambers.
  • An exhaust outlet 382 (FIG.
  • FIG. 3 illustrates a cross-sectional view of the apparatus 100 of FIG. 2, with same adjacent reactor chambers 50 a and 50 b, but in which the inert gas 360 shares the exhaust outlets 180 a and 180 b with the two doping gases Ax and By, respectively.
  • the atomic layer doping apparatus 100 may be designed so that the inert gas 360 of the gas curtain 300 could be exhausted through either one or both of the two exhaust outlets 180 a and 180 b, instead of being exhausted through its own exhaust outlet 382 , as illustrated in FIG. 2.
  • FIG. 4 shows another alternate embodiment of the apparatus in which the gas curtain 300 separating adjacent chambers in FIGS. 2 - 3 is replaced by a physical boundary, such as a wall 170 having a closeable opening 172 .
  • a door 174 (FIG. 4) can be used to open and close the opening 172 between the adjacent paired chambers 50 a, 50 b. This way, the wafer 55 can be passed between the adjacent chambers 50 a, 50 b through the open opening 172 by the robot 60 , with the door 174 closing the opening 172 during atomic layer doping processing.
  • two species for example, Ax and a second dopant species Cz
  • Cz the non-reactive gas
  • Other combinations are also possible.
  • the invention has been described with the wafer 55 traveling back and forth from the reactor chamber 50 a to the reactor chamber 50 b with reference to FIG. 2, it must be understood that, when more than two reactor chambers are used for doping with more than two monolayer species Ax, Cz, the wafer 55 will be transported by the loading assembly 60 among all the reaction chambers in a sequence required to produce a desired doping profile.
  • a processing cycle for atomic layer deposition on a plurality of wafers 55 begins by selectively moving each wafer 55 , from the loading assembly 60 to the chamber reactor 50 a, in the direction of arrow A 1 (FIG. 5), and then further to the reactor chamber 50 b, 52 a, 52 b, 54 a, and 54 b.
  • One reaction chamber, for example 50 a can serve as the initial chamber and another, for example 54 b, as the final chamber.
  • Each wafer 55 is simultaneously processed in a respective chamber and is moved sequentially through the chambers by the loading assembly 60 , with the cycle continuing with wafers 55 traveling in one direction to all the remaining reactors chambers.

Abstract

An improved atomic layer doping apparatus is disclosed as having multiple doping regions in which individual monolayer species are first deposited and then dopant atoms contained therein are diffused into the substrate. Each doping region is chemically separated from adjacent doping regions. A loading assembly is programmed to follow pre-defined transfer sequences for moving semiconductor substrates into and out of the respective adjacent doping regions. According to the number of doping regions provided, a plurality of substrates could be simultaneously processed and run through the cycle of doping regions until a desired doping profile is obtained.

Description

    FIELD OF THE INVENTION
  • The present invention relates to the field of semiconductor integrated circuits and, in particular, to an improved method for doping wafers. [0001]
  • BACKGROUND OF THE INVENTION
  • Incorporation of dopants or chosen impurities into a semiconductor material, commonly known as doping, is well known in the art. Thermal diffusion and ion implantation are two methods currently used to introduce a controlled amount of dopants into selected regions of a semiconductor material. [0002]
  • Doping by thermal diffusion is a two-step process. In the first step, called predeposition, the semiconductor is either exposed to a gas stream containing excess dopant at low temperature to obtain a surface region saturated with the dopant, or a dopant is diffused into a thin surface layer from a solid dopant source coated onto the semiconductor surface. The predeposition step is followed by the drive-in step, during which the semiconductor is heated at high temperatures in an inert atmosphere so that the dopant in the thin surface layer of the semiconductor is diffused into the interior of the semiconductor, and thus the predeposited dopant atoms are redistributed to a desired doping profile. [0003]
  • Ion implantation is preferred over thermal diffusion because of the capability of ion implantation to control the number of implanted dopant atoms, and because of its speed and reproducibility of the doping process. The ion implantation process employs ionized-projectile atoms that are introduced into solid targets, such as a semiconductor substrate, with enough kinetic energy (3 to 500 KeV) to penetrate beyond the surface regions. A typical ion implant system uses a gas source of dopant, such as, BF[0004] 3, PF3, SbF3, or AsH3, for example, which is energized at a high potential to produce an ion plasma containing dopant atoms. An analyzer magnet selects only the ion species of interest and rejects the rest of species. The desired ion species are then injected into an accelerator tube, so that the ions are accelerated to a high enough velocity to acquire a threshold momentum to penetrate the wafer surface when they are directed to the wafers.
  • Although ion implantation has many advantages, such as the ability to offer precise dopant concentrations, for example, for silicon of about 10[0005] 14 to 1021 atoms/cm3, there are various problems associated with this doping method. For example, a major drawback for ion implantation is the radiation damage, which occurs because of the bombardment involved with heavy particles and further affects the electrical properties of the semiconductor. The most common radiation damage is the vacancy-interstitial defect, which occurs when an incoming dopant ion knocks substrate atoms from a lattice site and the newly dislocated atoms rest in a non-lattice position. Further, most of the doping atoms are not electrically active right after implantation mainly because the dopant atoms do not end up on regular, active lattice sites. By a suitable annealing method, however, the crystal lattice could be fully restored and the introduced dopant atoms are brought to electrically active lattice sites by diffusion.
  • Ion channeling is another drawback of ion implantation that could also change the electrical characteristics of a doped semiconductor. Ion channeling occurs when the major axis of the crystal wafer contacts the ion beam, and when ions travel down the channels, reaching a depth as much as ten times the calculated depth. Thus, a significant amount of additional dopant atoms gather in the channels of the major axis. Ion channeling can be minimized by several techniques, such as employing a blocking amorphous surface layer or misorienting the wafer so that the dopant ions enter the crystal wafer at angles different than a 90° angle. For example, misorientation of the wafer [0006] 3 to 7° off the major axis prevents the dopant ions from entering the channels. However, these methods increase the use of the expensive ionimplant machine and, thus, could be very costly for batch processing.
  • Another disadvantage of the conventional doping methods is the autodoping. After dopants are incorporated into a crystalline wafer to form various junctions, they undergo many subsequent processing steps for device fabrication. Although efforts are made to use low-temperature processing techniques to minimize redistribution of incorporated dopant atoms, the dopants still redistribute during the course of further processing. For example, this redistribution of dopants becomes extremely important when an epitaxial film is grown over the top of the doped area, particularly because of the high temperature required for epitaxial growth. At high temperatures, the dopant diffuses into the growing epitaxial film during the epitaxial growth, and this phenomenon is referred to as autodoping. This phenomenon also leads to unintentional doping of the film in between the doped regions, or into the nondiffused substrate. For this, integrated circuit designers must leave adequate room between adjacent regions to prevent the laterally diffused regions from touching and shorting. [0007]
  • Furthermore, current doping systems today employ a batch processing, in which wafers are processed in parallel and at the same time. An inherent disadvantage of batch processing is cross contamination of the wafers from batch to batch, which further decreases the process control and repeatability, and eventually the yield, reliability and net productivity of the doping process. [0008]
  • Accordingly, there is a need for an improved doping system, which will permit minimal dopant redistribution, precise control of the number of implanted dopants, higher commercial productivity and improved versatility. There is also needed a new and improved doping system and method that will eliminate the problems posed by current batch processing technologies, as well as a method and system that will allow greater uniformity and doping process control with respect to layer thickness necessary for increasing density of integration in microelectronics circuits. [0009]
  • SUMMARY OF THE INVENTION
  • The present invention provides an improved method and unique atomic layer doping system and method for wafer processing. The present invention contemplates an apparatus provided with multiple doping regions in which individual monolayers of dopant species are first deposited by atomic layer deposition (ALD) on a wafer and then the respective dopants are diffused, by thermal reaction, for example, into the wafer surface. Each doping region of the apparatus is chemically isolated from the other doping regions, for example, by an inert gas curtain. A robot is programmed to follow pre-defined transfer sequences to move wafers into and out of respective doping regions for processing. Since multiple regions are provided, a multitude of wafers can be simultaneously processed in respective regions, each region depositing only one monolayer dopant species and subsequently diffusing the dopant into the wafer. Each wafer can be moved through the cycle of regions until a desired doping concentration and profile is reached. [0010]
  • The present invention allows for the atomic layer doping of wafers with higher commercial productivity and improved versatility. Since each region may be provided with a pre-determined set of processing conditions tailored to one particular monolayer dopant species, cross contamination is also greatly reduced. [0011]
  • These and other features and advantages of the invention will be apparent from the following detailed description which is provided in connection with the accompanying drawings, which illustrate exemplary embodiments of the invention.[0012]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates a schematic top view of a multiple-chamber atomic layer doping apparatus according to the present invention. [0013]
  • FIG. 2 is a partial cross-sectional view of the atomic layer doping apparatus of FIG. 1, taken along line [0014] 2-2′ and depicting two adjacent doping regions according to a first embodiment of the present invention and depicting one wafer transfer sequence.
  • FIG. 3 is a partial cross-sectional view of the atomic layer doping apparatus of FIG. 1, taken along line [0015] 2-2′ and depicting two adjacent doping regions according to a second embodiment of the present invention.
  • FIG. 4 is a partial cross-sectional view of the atomic layer doping apparatus of FIG. 2, depicting a physical barrier between two adjacent doping chambers. [0016]
  • FIG. 5 is a schematic top view of a multiple-chamber atomic layer doping apparatus according to the present invention and depicting a second wafer transfer sequence.[0017]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In the following detailed description, reference is made to various exemplary embodiments of the invention. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be employed, and that structural and electrical changes may be made without departing from the spirit or scope of the present invention. [0018]
  • The term “substrate” used in the following description may include any semiconductor-based structure. Structure must be understood to include silicon, silicon-on insulator (SOI), silicon-on sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. The semiconductor need not be silicon-based. The semiconductor could be silicon-geranium, germanium, or gallium arsenide. When reference is made to substrate in the following description, previous process steps may have been utilized to form regions or junctions in or on the base semiconductor or foundation. [0019]
  • The term “dopant” is intended to include not only elemental dopant atoms, but dopant atoms with other trace elements or in various combinations with other elements as known in the semiconductor art, as long as such combinations retain the physical and chemical properties of the dopant atoms. The term “p-type dopant” used in the following description may include any p-type impurity ions, such as zinc (Zn), magnesium (Mg), beryllium (Be), boron (B), gallium (Ga) or indium (In), among others. The term “n-type dopant” may include any n-type impurity ions, such as silicon (Si), sulfur (S), tin (Sn), phosphorus (P), arsenic (As) or antimony (Sb), among others. [0020]
  • The present invention provides an atomic layer doping method and apparatus. As it will be described in more details below, the apparatus is provided with multiple doping regions in which individual monolayer dopant species are first deposited on a substrate and then dopant atoms corresponding to each of the monolayer species are diffused into respective substrates. Each doping region is chemically separated from the adjacent doping regions. A robot is programmed to follow pre-defined transfer sequences for moving wafers into and out of the respective adjacent doping regions. According to the number of doping regions provided, a multitude of substrates could be simultaneously processed and run through the cycle of different doping regions until a desired doping concentration of a wafer surface is completed. [0021]
  • The present invention provides a simple and novel multi-chamber system for atomic layer doping processing. Although the present invention will be described below with reference to the atomic layer deposition of a dopant species Ax and the subsequent diffusion of its dopant atoms into a wafer, it must be understood that the present invention has equal applicability for the formation of any doped material capable of being formed by atomic layer doping techniques using any number of species, where each dopant species is deposited in a reaction chamber dedicated thereto. [0022]
  • A schematic top view of a multiple-chamber atomic [0023] layer doping apparatus 100 of the present invention is shown in FIG. 1. According to an exemplary embodiment of the present invention, doping regions 50 a, 50 b, 52 a, 52 b, 54 a, and 54 b are alternately positioned around a loading mechanism 60, for example a robot. These doping regions may be any regions for the atomic layer doping treatment of substrates. The doping regions may be formed as cylindrical reactor chambers, 50 a, 50 b, 52 a, 52 b, 54 a, and 54 b, in which adjacent chambers are chemically isolated from one another.
  • To facilitate wafer movement, and assuming that only one monolayer of a dopant species Ax is to be deposited per cycle, the reactor chambers are arranged in [0024] pairs 50 a, 50 b; 52 a, 52b; 54 a, 54 b. One such pair, 50 a, 50 b is shown in FIG. 2. While one of the reactor chambers of a pair, for example 50 a, deposits one monolayer of the dopant species Ax, the other reactor chamber of the pair, for example 50 b, facilitates subsequent diffusion of the dopant atoms of species Ax into the wafer to complete the doping process. The adjacent reactor chamber pairs are chemically isolated from one another, for example by a gas curtain, which keeps the monolayer of dopant species Ax in a respective region, for example 50 a, and which allows wafers treated in one reaction chamber, for example 50 a, to be easily transported by the robot 60 to the other reaction chamber 50 b, and vice versa. Simultaneously, the robot can also move wafers between chambers 52 a or 52 b, and 54 a and 54 b.
  • In order to chemically isolate the paired [0025] reaction chambers 50 a, 50 b; 52 a, 52 b; and 54 a, 54 b, the paired reaction chambers show a wall through which the wafers may pass, with the gas curtain acting in effect as a chemical barrier preventing the gas mixture within one chamber, for example 50 a, from entering the paired adjacent chamber, for example 50 b.
  • It should be noted that, when a particular doping concentration and/or profile is required, the robot can simply move wafers back and forth between the adjacent chambers, for example [0026] 50 a, 50 b, until the desired doping profile and/or concentration of the wafer is obtained.
  • It should also be noted that, while two adjacent chambers have been illustrated for doping of a substrate using monolayers of dopant species Ax, one or more additional chambers, for example [0027] 50 c, 52 c, 54 c, may also be used for deposition of additional respective monolayers of dopant species, such as By, for example, wit h the additional chambers being chemically isolated from the chambers depositing the Ax monolayer dopant species in the same way the chambers for depositing the Ax species are chemically isolated.
  • The [0028] loading assembly 60 of FIG. 1 may include an elevator mechanism along with a wafer supply mechanism. As well-known in the art, the supply mechanism may be further provided with clamps and pivot arms, so that a wafer 55 can be maneuvered by the robot and positioned according to the requirements of the atomic layer doping processing described in more detail below.
  • Further referring to FIG. 1, a processing cycle for atomic layer doping on a [0029] wafer 55 begins by selectively moving a first wafer 55, from the loading assembly 60 to the chamber reactor 50 a, in the direction of arrow A1 (FIG. 1). Similarly, a second wafer 55′ may be selectively moved by the loading assembly 60 to the chamber reactor 52 a, in the direction of arrow A2. Further, a third wafer 55″ is also selectively moved by the loading assembly 60 to the chamber reactor 54 a, in the direction A3. At this point, each of chambers 50 a, 52 a, 54 a are ready for atomic layer deposition of a monolayer of a dopant species, for example Ax.
  • FIG. 2 illustrates a cross-sectional view of the [0030] apparatus 100 of FIG. 1, taken along line 2-2′. For simplicity, FIG. 2 shows only a cross-sectional view of adjacent reactor chambers 50 a and 50 b. In order to deposit an atomic monolayer on the wafer 55, the wafer 55 is placed inside of the reactor chamber 50 a, which may be provided as a quartz or aluminum container 120. The wafer 55 is placed by the loading assembly 60 (FIG. 1) onto a suscepter 140 a (FIG. 2), which in turn is situated on a heater assembly 150 a. Mounted on the upper wall of the reactor chamber 50 a is a dopant gas supply inlet 160 a, which is further connected to a dopant gas supply source 162 a for a first dopant gas precursor Ax. An exhaust outlet 180 a, connected to an exhaust system 182 a, is situated on the opposite wall from the dopant gas supply inlet 160 a.
  • The [0031] wafer 55 is positioned on top of the suscepter 140 a (FIG. 2) by the loading assembly 60, and then a first dopant gas precursor Ax is supplied into the reactor chamber 50 a through the dopant gas inlet 160 a. The first dopant gas precursor Ax flows at a right angle onto the wafer 55 and reacts with its top substrate surface to form a first monolayer 210 a of the first dopant species Ax, by an atomic layer deposition mechanism. Preferred gas sources of dopants are hydrated forms of dopant atoms such as arsine (AsH3) and diborane (B2H6). These gases are mixed in different dilutions in pressurized containers, such as the dopant gas supply source 162 a (FIG. 2), and connected directly to the dopant gas inlets, such as the dopant gas inlet 160 a (FIG. 2). Gas sources offer the advantage of precise control through pressure regulators and are favored for deposition on larger wafers.
  • Alternatively, a liquid source of dopant such as chlorinated or brominated compounds of the desired element may be used. When a liquid source of dopant is used, a boron liquid source, for example boron tribromide (BBr[0032] 3), or a phosphorous liquid source, for example phosphorous oxychloride (POCl3), may be held in temperature-controlled flasks over which an inert gas, such as nitrogen (N2), is bubbled through the heated liquid, so that the gas becomes saturated with dopant atoms. The inert gas carries the dopant vapors through a gas tube and creates a laminar flow of dopant atoms. A reaction gas is also required to create the elemental dopant form in the tube. For BBr3, for example, the reaction gas is oxygen, which creates the boron trioxide (B2O3) which further deposits as a monolayer of boron trioxide on the surface of the wafer.
  • In any event, after the deposition of a monolayer of the first dopant species Ax on the [0033] wafer surface 55, the processing cycle for the wafer 55 continues with the removal of the wafer 55 from the chamber reactor 50 a to the chamber reactor 50 b, in the direction of arrow B1, as also illustrated in FIG. 1. After the deposition of the first monolayer 210 a of the first dopant species Ax, the wafer 55 is moved from the reactor chamber 50 a, through a gas curtain 300 (FIG. 2), to the reactor chamber 50 b, by the loading assembly 60 (FIG. 1) and in the direction of arrow B1 of FIG. 2. It is important to note that the gas curtain 300 provides chemical isolation between adjacent deposition regions.
  • The [0034] loading assembly 60 moves the wafer 55 through the gas curtain 300, onto the suscepter 140 b situated in the reactor chamber 50 b, which, in contrast with the reactor chamber 50 a, contains no dopant source and no dopant species. A heater assembly 150 b is positioned under the suscepter 140 b to facilitate the diffusion of the dopant atoms from the newly deposited first monolayer 210 a of the first dopant species Ax into the wafer 55. The heat from the heater assembly 150 b drives the dopant atoms into the wafer 55 and further redistributes the dopant atoms from the first monolayer 210 a deeper into the wafer 55 to form a doped region 210 b of the first dopant species Ax. During this step, the surface concentration of dopant atoms is reduced and the distribution of dopant atoms continues, so that a precise and shallow doping distribution in the doped region 210 b of the wafer 55 is obtained. Accordingly, the depth of the doped region 210 b of the wafer 55 is controlled, first, by the repeatability of the atomic layer deposition for the monolayers of dopant species and, second, by the degree of diffusion of dopants form the monolayers of dopant species into the wafers.
  • Alternatively, a plasma of a non-reactive gas may be used to complete the diffusion of the dopant atoms into the doped region [0035] 210 b of the wafer 55. In this embodiment, a supply inlet 160 b (FIG. 2), which is further connected to a non-reactive gas supply source 162 b, for the plasma of the non-reactive gas, is mounted on the upper wall of the reactor chamber 50 b. An exhaust inlet 180 b, connected to an exhaust system 182 b, is further situated on the opposite wall to the non-reactive gas supply inlet 160 b.
  • Next, the non-reactive gas By is supplied into the [0036] reactor chamber 50 b through the non-reactive gas inlet 160 b, the non-reactive gas By flowing at a right angle onto the deposited first monolayer 210 a of the first dopant species Ax. This way, particles of the non-reactive gas By “knock” the dopant atoms from the first monolayer 210 a of the first doping species Ax into the wafer 55 to form the doped region 210 b of the wafer 55.
  • Following the formation of the doped region [0037] 210 b of the wafer 55, the process continues with the removal of the wafer 55 from the reactor chamber 50 b, through the gas curtain 300, and into the reactor chamber 50 a to continue the doping process. This process is repeated cycle after cycle, with the wafer 55 traveling back and forth between the reactor chamber 50 a, and the reactor chamber 50 b, to acquire the desired doping profile of the region 210 b.
  • Once the desired doping profile of the [0038] wafer 55 has been achieved, an anneal step in the atomic layer doping process is required, to restore any crystal damage and to electrically activate the dopant atoms. As such, annealing can be achieved by a thermal heating step. However, the anneal temperature must be preferably below the diffusion temperature to prevent lateral diffusion of the dopants. Referring to FIG. 2, the anneal step could take place in the reactor chamber 50 b, for example, by controlling the heat from the heater assembly 150 b. Alternatively, the anneal step may take place into an adjacent reactor chamber, for example reactor chamber 52 a, depending on the processing requirements and the desired number of wafers to be processed.
  • By employing chemically separate reactor chambers for the deposition process of species Ax dopant and possibly others, the present invention has the major advantage of allowing different processing conditions, for example, deposition or diffusion temperatures, in different reactor chambers. This is important since the chemisorption and reactivity requirements of the ALD process have specific temperature requirements, in accordance with the nature of the precursor gas. Accordingly, the apparatus of the present invention allows, for example, [0039] reactor chamber 50 a to be set to a different temperature than that of the reactor chamber 50 b. Further, each reactor chamber may be optimized either for improved chemisorption, reactivity or dopant conditions.
  • The configuration of the atomic layer doping apparatus illustrated above also improves the overall yield and productivity of the doping process, since each chamber could run a separate substrate, and therefore, a plurality of substrates could be run simultaneously at a given time. In addition, since each reactor chamber accommodates only one dopant species, cross-contamination from one wafer to another is greatly reduced. Moreover, the production time can be decreased since the configuration of the apparatus of the present invention saves a great amount of purging and reactor clearing time. [0040]
  • Of course, although the doping process was explained above only with reference to the [0041] first substrate 55 in the first chamber reactor 50 a and the second chamber reactor 50 b, it is to be understood that same processing steps are carried out simultaneously on the second and third wafers 55′, 55″ for their respective chamber reactors. Further, the second and third wafers 55′, 55 ′ are moved accordingly, in the directions of arrows A2, B2 (corresponding to chamber reactors 52 a, 52 b) and arrows A3, B3 (corresponding to chamber reactors 54 a, 54 b). Moreover, while the doping process was explained above with reference to only one first substrate 55 for the first and second reactor chambers 50 a, 50 b, it must be understood that the first and second reactor chambers 50 a, 50 b could also process another first substrate 55, in a direction opposite to that of processing the other first substrate. For example, if one first substrate 55 travels in the direction of arrow B1 (FIG. 2) the other first substrate 55 could travel in the opposite direction of arrow B1, that is from the second reactor chamber 50 b to the first reactor chamber 50 a.
  • Assuming a specific doping concentration is desired on the [0042] wafer 55, after the diffusion of the dopant atoms from the first monolayer 210 a in the reactor chamber 50 b, the wafer 55 is then moved back by the assembly system 60 to the reactor chamber 50 a, where a second monolayer of the first dopant species Ax is next deposited over the first monolayer of the first dopant species Ax. The wafer 55 is further moved to the reactor chamber 50 b for the subsequent diffusion of the dopant atoms from the second monolayer of the first dopant species Ax. The cycle continues until a desired doping concentration on the surface of the wafer 55 is achieved, and, thus, the wafer 55 travels back and forth between reactor chambers 50 a and 50 b. As explained above, the same cycle process applies to the other two wafers 55′, 55″ that are processed simultaneously in their respective reactor chambers.
  • Although the invention is described with reference to reactor chambers, any other type of doping regions may be employed, as long as the [0043] wafer 55 is positioned under a flow of dopant source. The gas curtain 300 provides chemical isolation to all adjacent deposition regions. Thus, as illustrated in FIGS. 2-3, the gas curtain 300 is provided between the two adjacent reactor chambers 50 a and 50 b so that an inert gas 360, such as nitrogen, argon, or helium, for example, flows through an inlet 260 connected to an inert gas supply source 362 to form the gas curtain 300, which keeps the first dopant gas Ax and the non-reactive gas By from flowing into adjacent reaction chambers. An exhaust outlet 382 (FIG. 2) is further situated on the opposite wall to the inert gas inlet 260. It must also be noted that the pressure of the inert gas 360 must be higher than that of the first dopant gas Ax and that of the non-reactive gas By, so that the two doping gases Ax, By are constrained by the gas curtain 300 to remain within their respective reaction chambers.
  • FIG. 3 illustrates a cross-sectional view of the [0044] apparatus 100 of FIG. 2, with same adjacent reactor chambers 50 a and 50 b, but in which the inert gas 360 shares the exhaust outlets 180 a and 180 b with the two doping gases Ax and By, respectively. Thus, the atomic layer doping apparatus 100 may be designed so that the inert gas 360 of the gas curtain 300 could be exhausted through either one or both of the two exhaust outlets 180 a and 180 b, instead of being exhausted through its own exhaust outlet 382, as illustrated in FIG. 2.
  • FIG. 4 shows another alternate embodiment of the apparatus in which the [0045] gas curtain 300 separating adjacent chambers in FIGS. 2-3 is replaced by a physical boundary, such as a wall 170 having a closeable opening 172. A door 174 (FIG. 4) can be used to open and close the opening 172 between the adjacent paired chambers 50 a, 50 b. This way, the wafer 55 can be passed between the adjacent chambers 50 a, 50 b through the open opening 172 by the robot 60, with the door 174 closing the opening 172 during atomic layer doping processing.
  • Although the present invention has been described with reference to only three semiconductor substrates processed at relatively the same time in respective pairs of reaction chambers, it must be understood that the present invention contemplates the processing of any “n” number of wafers in their corresponding “m” number of reactor chambers, where n and m are integers. Thus, in the example shown in FIG. 1, n=3 and m=6, providing an atomic layer doping apparatus with at least 6 reaction chambers that could process simultaneously 3 wafers for a repeating two-step atomic layer doping using Ax as a dopant source and By as a non-reactive gas for diffusion. It is also possible to have n=2 and m=6 where two wafers are sequentially transported to and processed in the reaction chambers for sequential doping with two species, for example, Ax and a second dopant species Cz, while employing the non-reactive gas By to facilitate the diffusion of the dopant atoms Ax and Cz. Other combinations are also possible. Thus, although the invention has been described with the [0046] wafer 55 traveling back and forth from the reactor chamber 50 a to the reactor chamber 50 b with reference to FIG. 2, it must be understood that, when more than two reactor chambers are used for doping with more than two monolayer species Ax, Cz, the wafer 55 will be transported by the loading assembly 60 among all the reaction chambers in a sequence required to produce a desired doping profile.
  • Also, although the present invention has been described with reference to [0047] wafers 55, 55′ and 55″ being selectively moved by the loading assembly 60 to their respective reactor chambers 50 a and 50 b (for wafer 55), 52 a and 52 b (for wafer 55′), and 54 a and 54 b (for wafer 55″), it must be understood that each of the three above wafers or more wafers could be sequentially transported to, and processed in, all the reaction chambers of the apparatus 100. This way, each wafer could be rotated and moved in one direction only. Such a configuration is illustrated in FIG. 5, according to which a processing cycle for atomic layer deposition on a plurality of wafers 55, for example, begins by selectively moving each wafer 55, from the loading assembly 60 to the chamber reactor 50 a, in the direction of arrow A1 (FIG. 5), and then further to the reactor chamber 50 b, 52 a, 52 b, 54 a, and 54 b. One reaction chamber, for example 50 a, can serve as the initial chamber and another, for example 54 b, as the final chamber. Each wafer 55 is simultaneously processed in a respective chamber and is moved sequentially through the chambers by the loading assembly 60, with the cycle continuing with wafers 55 traveling in one direction to all the remaining reactors chambers. Although this embodiment has been described with reference to a respective wafer in each chamber, it must be understood that the present invention contemplates the processing of any “n” number of wafers in corresponding “m” number of reactor chambers, where n and m are integers and n≦m. Thus, in the example shown in FIG. 5, the ALD apparatus with 6 reaction chambers could process simultaneously up to 6 wafers.
  • The above description illustrates preferred embodiments that achieve the features and advantages of the present invention. It is not intended that the present invention be limited to the illustrated embodiments. Modifications and substitutions to specific process conditions and structures can be made without departing from the spirit and scope of the present invention. Accordingly, tie invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims. [0048]

Claims (45)

What is claimed as new and desired to be protected by Letters Patent of the United States is:
1. An atomic layer doping apparatus comprising:
a first atomic layer doping region for depositing a first dopant species on a first substrate as a monolayer;
a second atomic layer doping region for diffusing said first dopant species in said first substrate, said first and second doping regions being chemically isolated from one another; and
a loading assembly for moving said first substrate from said first doping region to said second doping region, thereby enabling deposition of a first atomic monolayer in said first doping region, followed by diffusion of said first atomic monolayer in said second doping region.
2. The doping apparatus of claim 1, wherein said first and second doping regions are adjacent to one another and chemically isolated.
3. The doping apparatus of claim 2, wherein said first and second doping regions are chemically isolated from one another by a gas curtain.
4. The doping apparatus of claim 3, wherein said gas curtain is formed of an inert gas.
5. The doping apparatus of claim 2, wherein said first and second doping regions are chemically isolated from one another by a physical barrier having a closeable opening through which said loading assembly can move a substrate.
6. The doping apparatus of claim 1, wherein said loading assembly is further able to move said substrate from said second doping region back to said first doping region.
7. The doping apparatus of claim 1 further comprising a plurality of first and second atomic layer doping regions.
8. The doping apparatus of claim 7, wherein said plurality of first and second doping regions are grouped in pairs of first and second doping regions, so that at least said first substrate and a second substrate can be treated simultaneously in respective pairs of first and second doping regions.
9. The doping apparatus of claim 8 further comprising a third pair of first and second atomic layer doping regions for processing a third substrate in said third pair of first and second atomic layer doping regions simultaneously with processing of said first and second substrates.
10. The doping apparatus of claim 7, wherein said loading assembly is located at the center of said doping regions.
11. The doping apparatus of claim 1 further comprising at least one third atomic layer doping region.
12. The doping apparatus of claim 11, wherein said first, second, and third doping regions are adjacent to one another and chemically isolated.
13. The doping apparatus of claim 12, wherein said first, second, and third doping regions are chemically isolated from one another by a gas curtain.
14. The doping apparatus of claim 13, wherein said gas curtain is formed of an inert gas.
15. The doping apparatus of claim 11, wherein said first, second, and third doping regions are chemically isolated from one another by a physical barrier having a closeable opening through which said loading assembly can move a substrate.
16. The doping apparatus of claim 11, wherein said loading assembly is further able to move sequentially said first substrate among said first doping region, said second doping region, and said third doping region.
17. The doping apparatus of claim 16, wherein said loading assembly is further able to move sequentially another substrate among said first doping region, said second doping region, and said third doping region.
18. A method of operating an atomic layer doping apparatus, said doping apparatus comprising a first doping region and a second doping region, said first and second doping regions being chemically isolated from one another, said method comprising the steps of:
positioning a wafer in said first doping region;
introducing a first dopant species into said first doping region and depositing said first dopant species on said wafer as a first atomic monolayer;
moving said wafer from said first doping region to said second doping region; and
introducing dopants from said first atomic monolayer into said wafer in said second doping region.
19. The method of claim 18 further comprising the act of annealing said wafer after said act of introducing said dopants into said wafer.
20. The method of claim 18, wherein said act of introducing said dopants into said wafer includes diffusion of said dopants.
21. The method of claim 18, wherein said act of introducing said dopants into said wafer includes contacting said wafer with a non-reactive plasma.
22. The method of claim 18 further comprising the act of moving said wafer back and forth between said first and second doping regions.
23. The method of claim 18 further comprising the act of moving said wafer back to said first doping region and depositing said first dopant species as a second atomic monolayer.
24. The method of claim 18, wherein said first and second doping regions are adjacent to each other.
25. The method of claim 18 further comprising the act of simultaneously processing at least two wafers among said first and second doping regions and depositing a respective dopant species in each of said doping regions.
26. The method of claim 18, wherein said least two wafers are sequentially moved among said first and second doping regions.
27. A method of conducting atomic layer doping comprising the steps of:
depositing a first atomic monolayer including atoms of a dopant species on a substrate in a first doping region;
moving said substrate from said first doping region to a second doping region, which is chemically isolated from said first doping region; and
introducing said atoms of said dopant species into said wafer.
28. The method of claim 27, wherein said act of depositing said first monolayer species further comprises introducing a first dopant species into said first doping region.
29. The method of claim 27, wherein said act of introducing said atoms of said dopant species into said wafer further comprises introducing a non-reactive plasma into said second doping region and contacting said non-reactive plasma with said first atomic monolayer species.
30. The method of claim 27, wherein said act of introducing said atoms of said dopant species into said wafer further comprises heating said wafer so that said atoms diffuse into a surface region of said wafer.
31. The method of claim 27 further comprising the act of annealing said wafer.
32. The method of claim 27 further comprising the act of moving said substrate back and forth between said first and second doping regions.
33. The method of claim 27, wherein a plurality of first and second doping regions are provided, and said method further comprising depositing said first monolayer on respective substrates and introducing atoms from said first monolayers into respective substrates in respective pairs of first and second doping regions, said first and second doping regions of each pair being adjacent to one another.
34. The method of claim 33, wherein a plurality of substrates, each of said plurality of substrates residing in respective regions, are moved sequentially from said first doping regions to said second doping regions.
35. A method of operating an atomic layer doping apparatus, said doping apparatus comprising a plurality of doping regions, said doping regions being chemically isolated from one another, said method comprising the steps of:
positioning a plurality of wafers in respective doping regions;
introducing a first dopant species into some of said plurality of doping regions and depositing said first dopant species on at least one of said plurality of wafers as a first atomic monolayer, said first atomic monolayer comprising dopant atoms of said first dopant species;
moving said plurality of wafers from said some of said plurality of doping regions to other doping regions; and
introducing a second gas species into said other doping regions and contacting said second gas species on at least one of said plurality of wafers to introduce said dopant atoms into said at least one of said plurality of wafers.
36. The method of claim 35 further comprising the act of sequentially moving said plurality of wafers through at least two of said plurality of doping regions in accordance with a predefined pattern.
37. The method of claim 35, wherein said second gas species is a non-reactive plasma.
38. The method of claim 35 further comprising the act of annealing said at least one of said plurality of wafers.
39. The method of claim 35 further comprising the act of sequentially moving said plurality of wafers through all said doping regions.
40. The method of claim 35 further comprising the act of sequentially moving said plurality of wafers through predetermined regions of said doping regions.
41. A method of conducting atomic layer doping comprising the steps of:
depositing a first atomic monolayer including atoms of a first dopant species on a substrate in a first doping region;
moving said substrate from said first doping region to a second doping region, which is chemically isolated from said first doping region, for depositing a second monolayer including atoms of a second dopant species on said substrate; and
moving said substrate from said second doping regions to a third doping region, which is chemically isolated from said first and second doping regions, for introducing said atoms of said first and second dopant species into said wafer.
42. The method of claim 41, wherein said act of introducing said atoms of said first and second dopant species into said wafer further comprises introducing a non-reactive plasma into said third doping region and contacting said non-reactive plasma with said first and second atomic monolayer species.
43. The method of claim 41, wherein said act of introducing said atoms of said first and second dopant species into said wafer further comprises heating said wafer so that said atoms diffuse into a surface region of said wafer.
44. The method of claim 41 further comprising the act of annealing said wafer.
45. The method of claim 41 further comprising the act of sequentially moving said substrate back and forth between said first, second and third doping regions.
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Cited By (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020100418A1 (en) * 2000-05-12 2002-08-01 Gurtej Sandhu Versatile atomic layer deposition apparatus
US20020122885A1 (en) * 2001-03-01 2002-09-05 Micron Technology, Inc. Methods, systems, and apparatus for uniform chemical-vapor depositions
US20030230549A1 (en) * 2002-06-13 2003-12-18 International Business Machines Corporation Method for etching chemically inert metal oxides
US20040043541A1 (en) * 2002-08-29 2004-03-04 Ahn Kie Y. Atomic layer deposited lanthanide doped TiOx dielectric films
US20040058293A1 (en) * 2002-08-06 2004-03-25 Tue Nguyen Assembly line processing system
US20040110348A1 (en) * 2002-12-04 2004-06-10 Micron Technology, Inc. Atomic layer deposited Zr-Sn-Ti-O films using TiI4
US20040110391A1 (en) * 2002-12-04 2004-06-10 Micron Technology, Inc. Atomic layer deposited Zr-Sn-Ti-O films
US20040175882A1 (en) * 2003-03-04 2004-09-09 Micron Technology, Inc. Atomic layer deposited dielectric layers
US20040187784A1 (en) * 2003-03-28 2004-09-30 Fluens Corporation Continuous flow deposition system
US20050020017A1 (en) * 2003-06-24 2005-01-27 Micron Technology, Inc. Lanthanide oxide / hafnium oxide dielectric layers
US20050124174A1 (en) * 2002-08-15 2005-06-09 Micron Technology, Inc. Lanthanide doped TiOx dielectric films by plasma oxidation
US20050145957A1 (en) * 2002-02-20 2005-07-07 Micron Technology, Inc. Evaporated LaAlO3 films for gate dielectrics
US20050158973A1 (en) * 2001-12-20 2005-07-21 Micron Technology, Inc. Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics
US20060006548A1 (en) * 2003-08-05 2006-01-12 Micron Technology, Inc. H2 plasma treatment
US20060046505A1 (en) * 2004-08-26 2006-03-02 Micron Technology, Inc. Ruthenium gate for a lanthanide oxide dielectric layer
WO2006031956A2 (en) * 2004-09-13 2006-03-23 Genus, Inc. Multi-single wafer processing apparatus
US20060125030A1 (en) * 2004-12-13 2006-06-15 Micron Technology, Inc. Hybrid ALD-CVD of PrxOy/ZrO2 films as gate dielectrics
US20060176645A1 (en) * 2005-02-08 2006-08-10 Micron Technology, Inc. Atomic layer deposition of Dy doped HfO2 films as gate dielectrics
US20060183272A1 (en) * 2005-02-15 2006-08-17 Micron Technology, Inc. Atomic layer deposition of Zr3N4/ZrO2 films as gate dielectrics
US7135369B2 (en) 2003-03-31 2006-11-14 Micron Technology, Inc. Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9
US20070049051A1 (en) * 2005-08-29 2007-03-01 Micron Technology, Inc. Atomic layer deposition of Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics
US20070151842A1 (en) * 2005-12-15 2007-07-05 Fluens Corporation Apparatus for reactive sputtering
US20070218290A1 (en) * 2004-06-24 2007-09-20 Beneq Oy Method for Doping Material and Doped Material
US20090004801A1 (en) * 2007-06-28 2009-01-01 Micron Technology, Inc. Method of forming lutetium and lanthanum dielectric structures
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US20100041244A1 (en) * 2006-08-31 2010-02-18 Micron Technology, Inc. Hafnium tantalum oxynitride dielectric
US7670646B2 (en) 2002-05-02 2010-03-02 Micron Technology, Inc. Methods for atomic-layer deposition
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7709402B2 (en) 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US7728626B2 (en) 2002-07-08 2010-06-01 Micron Technology, Inc. Memory utilizing oxide nanolaminates
US7727905B2 (en) 2004-08-02 2010-06-01 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US20100186669A1 (en) * 2008-12-29 2010-07-29 K.C. Tech Co., Ltd. Atomic layer deposition apparatus
US20100221426A1 (en) * 2009-03-02 2010-09-02 Fluens Corporation Web Substrate Deposition System
US7867919B2 (en) 2004-08-31 2011-01-11 Micron Technology, Inc. Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer
US8125038B2 (en) 2002-07-30 2012-02-28 Micron Technology, Inc. Nanolaminates of hafnium oxide and zirconium oxide
US8154066B2 (en) 2004-08-31 2012-04-10 Micron Technology, Inc. Titanium aluminum oxide films
US8278225B2 (en) 2005-01-05 2012-10-02 Micron Technology, Inc. Hafnium tantalum oxide dielectrics
US20140199854A1 (en) * 2013-01-16 2014-07-17 United Microelectronics Corp. Method of forming film on different surfaces
TWI471961B (en) * 2007-10-26 2015-02-01 Sosul Co Ltd Baffle, substrate supporting apparatus and plasma processing apparatus and plasma processing method
US20160002784A1 (en) * 2014-07-07 2016-01-07 Varian Semiconductor Equipment Associates, Inc. Method and apparatus for depositing a monolayer on a three dimensional structure

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7554829B2 (en) * 1999-07-30 2009-06-30 Micron Technology, Inc. Transmission lines for CMOS integrated circuits
DE10101014A1 (en) * 2001-01-05 2002-07-11 Zeiss Carl Coating of optical elements, especially for use with ultraviolet light
CA2439079C (en) * 2001-02-23 2008-04-29 The Gates Corporation Process for directly bonding rubber to at least a second substrate, and the resulting article
US6800172B2 (en) * 2002-02-22 2004-10-05 Micron Technology, Inc. Interfacial structure for semiconductor substrate processing chambers and substrate transfer chambers and for semiconductor substrate processing chambers and accessory attachments, and semiconductor substrate processor
DE10208450B4 (en) * 2002-02-27 2004-09-16 Infineon Technologies Ag Process for the deposition of thin layers by means of ALD / CVD processes in connection with fast thermal processes
US6962644B2 (en) * 2002-03-18 2005-11-08 Applied Materials, Inc. Tandem etch chamber plasma processing system
US6932871B2 (en) * 2002-04-16 2005-08-23 Applied Materials, Inc. Multi-station deposition apparatus and method
US6814813B2 (en) * 2002-04-24 2004-11-09 Micron Technology, Inc. Chemical vapor deposition apparatus
US6858264B2 (en) * 2002-04-24 2005-02-22 Micron Technology, Inc. Chemical vapor deposition methods
US6896730B2 (en) * 2002-06-05 2005-05-24 Micron Technology, Inc. Atomic layer deposition apparatus and methods
US7153542B2 (en) * 2002-08-06 2006-12-26 Tegal Corporation Assembly line processing method
US6790791B2 (en) * 2002-08-15 2004-09-14 Micron Technology, Inc. Lanthanide doped TiOx dielectric films
US6916374B2 (en) * 2002-10-08 2005-07-12 Micron Technology, Inc. Atomic layer deposition methods and atomic layer deposition tools
US6926775B2 (en) 2003-02-11 2005-08-09 Micron Technology, Inc. Reactors with isolated gas connectors and methods for depositing materials onto micro-device workpieces
US6970053B2 (en) * 2003-05-22 2005-11-29 Micron Technology, Inc. Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection
DE10339991A1 (en) * 2003-08-29 2005-03-31 Advanced Micro Devices, Inc., Sunnyvale Improved technique for adjusting a penetration depth during the implantation of ions into a semiconductor region
US7282239B2 (en) * 2003-09-18 2007-10-16 Micron Technology, Inc. Systems and methods for depositing material onto microfeature workpieces in reaction chambers
US7647886B2 (en) * 2003-10-15 2010-01-19 Micron Technology, Inc. Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers
US7258892B2 (en) 2003-12-10 2007-08-21 Micron Technology, Inc. Methods and systems for controlling temperature during microfeature workpiece processing, e.g., CVD deposition
US7906393B2 (en) 2004-01-28 2011-03-15 Micron Technology, Inc. Methods for forming small-scale capacitor structures
US8133554B2 (en) 2004-05-06 2012-03-13 Micron Technology, Inc. Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing materials onto microfeature workpieces
US7699932B2 (en) 2004-06-02 2010-04-20 Micron Technology, Inc. Reactors, systems and methods for depositing thin films onto microfeature workpieces
US7368368B2 (en) * 2004-08-18 2008-05-06 Cree, Inc. Multi-chamber MOCVD growth apparatus for high performance/high throughput
KR100579860B1 (en) * 2004-12-23 2006-05-12 동부일렉트로닉스 주식회사 Method for forming p type polysilicon using ald and iii group heavy metal
US7374964B2 (en) 2005-02-10 2008-05-20 Micron Technology, Inc. Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics
SG163544A1 (en) * 2005-03-30 2010-08-30 Panasonic Corp Impurity introducing apparatus and impurity introducing method
US20060237138A1 (en) * 2005-04-26 2006-10-26 Micron Technology, Inc. Apparatuses and methods for supporting microelectronic devices during plasma-based fabrication processes
US7544398B1 (en) * 2005-04-26 2009-06-09 The Regents Of The Univesity Of California Controlled nano-doping of ultra thin films
KR100760428B1 (en) * 2005-05-13 2007-09-20 오재응 Vapor Deposition Reactor
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US20070087581A1 (en) * 2005-09-09 2007-04-19 Varian Semiconductor Equipment Associates, Inc. Technique for atomic layer deposition
US20070065576A1 (en) * 2005-09-09 2007-03-22 Vikram Singh Technique for atomic layer deposition
CN1937175B (en) * 2005-09-20 2012-10-03 中芯国际集成电路制造(上海)有限公司 Method for depositing material atomic layer for semiconductor device by using atmosphere
US7569463B2 (en) * 2006-03-08 2009-08-04 Applied Materials, Inc. Method of thermal processing structures formed on a substrate
KR101447184B1 (en) * 2006-11-10 2014-10-08 엘아이지에이디피 주식회사 Process chamber having apparatus for opening and closing gate slit
US20080194072A1 (en) * 2007-02-12 2008-08-14 Chen-Hua Yu Polysilicon gate formation by in-situ doping
US7892909B2 (en) * 2007-02-12 2011-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Polysilicon gate formation by in-situ doping
US20090081356A1 (en) * 2007-09-26 2009-03-26 Fedorovskaya Elena A Process for forming thin film encapsulation layers
US7790535B2 (en) * 2008-09-16 2010-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Depletion-free MOS using atomic-layer doping
US8361895B2 (en) * 2008-09-16 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Ultra-shallow junctions using atomic-layer doping
JP2010153278A (en) * 2008-12-26 2010-07-08 Hitachi High-Technologies Corp Charged particle beam processing device
FI122940B (en) * 2009-02-09 2012-09-14 Beneq Oy reaction chamber
US8828835B2 (en) 2009-03-06 2014-09-09 Texas Instruments Incorporated Ultrashallow emitter formation using ALD and high temperature short time annealing
US8828138B2 (en) 2010-05-17 2014-09-09 International Business Machines Corporation FET nanopore sensor
US8518829B2 (en) 2011-04-22 2013-08-27 International Business Machines Corporation Self-sealed fluidic channels for nanopore array
US20140065799A1 (en) * 2012-09-03 2014-03-06 Intermolecular, Inc. Methods and Systems for Low Resistance Contact Formation
US8940646B1 (en) * 2013-07-12 2015-01-27 Lam Research Corporation Sequential precursor dosing in an ALD multi-station/batch reactor
KR102477302B1 (en) * 2015-10-05 2022-12-13 주성엔지니어링(주) Substrate treatment apparatus having exhaust gas cracker and exhaust gas treatment method of the same
KR102622159B1 (en) * 2021-07-14 2024-01-09 한국생산기술연구원 atomic layer deposition chamber

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3602192A (en) * 1969-05-19 1971-08-31 Ibm Semiconductor wafer processing
US3618919A (en) * 1969-11-03 1971-11-09 Btu Eng Corp Adjustable heat and gas barrier
US4089735A (en) * 1968-06-05 1978-05-16 Siemens Aktiengesellschaft Method for epitactic precipitation of crystalline material from a gaseous phase, particularly for semiconductors
US4576830A (en) * 1984-11-05 1986-03-18 Chronar Corp. Deposition of materials
US4593644A (en) * 1983-10-26 1986-06-10 Rca Corporation Continuous in-line deposition system
US5071670A (en) * 1990-06-11 1991-12-10 Kelly Michael A Method for chemical vapor deposition under a single reactor vessel divided into separate reaction chambers each with its own depositing and exhausting means
US5314538A (en) * 1991-04-22 1994-05-24 Semiconductor Process Laboratory Apparatus for manufacturing semiconductor device and method for manufacturing semiconductor device
US5374570A (en) * 1989-03-17 1994-12-20 Fujitsu Limited Method of manufacturing active matrix display device using insulation layer formed by the ale method
US5667592A (en) * 1996-04-16 1997-09-16 Gasonics International Process chamber sleeve with ring seals for isolating individual process modules in a common cluster
US5747113A (en) * 1996-07-29 1998-05-05 Tsai; Charles Su-Chang Method of chemical vapor deposition for producing layer variation by planetary susceptor rotation
US6143082A (en) * 1998-10-08 2000-11-07 Novellus Systems, Inc. Isolation of incompatible processes in a multi-station processing chamber
US20020100418A1 (en) * 2000-05-12 2002-08-01 Gurtej Sandhu Versatile atomic layer deposition apparatus
US6527866B1 (en) * 2000-02-09 2003-03-04 Conductus, Inc. Apparatus and method for deposition of thin films

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1758751A1 (en) * 1968-08-01 1971-02-25 Telefunken Patent Oven for the diffusion of interference points in semiconductor bodies
US3811826A (en) * 1972-11-03 1974-05-21 Sowell J Diffusion furnace process tube
JPS6055478B2 (en) 1982-10-19 1985-12-05 松下電器産業株式会社 Vapor phase growth method
US5298452A (en) * 1986-09-12 1994-03-29 International Business Machines Corporation Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
US4951601A (en) * 1986-12-19 1990-08-28 Applied Materials, Inc. Multi-chamber integrated process system
US4786616A (en) * 1987-06-12 1988-11-22 American Telephone And Telegraph Company Method for heteroepitaxial growth using multiple MBE chambers
JPH01278714A (en) * 1988-04-30 1989-11-09 Sharp Corp Atomic layer planar doping method
US5013683A (en) * 1989-01-23 1991-05-07 The Regents Of The University Of California Method for growing tilted superlattices
AU5977190A (en) 1989-07-27 1991-01-31 Nishizawa, Junichi Impurity doping method with adsorbed diffusion source
US5225366A (en) 1990-06-22 1993-07-06 The United States Of America As Represented By The Secretary Of The Navy Apparatus for and a method of growing thin films of elemental semiconductors
DE59010916D1 (en) 1990-12-21 2000-11-30 Siemens Ag Process for the production of a smooth polycrystalline silicon layer doped with arsenic for highly integrated circuits
JP3049894B2 (en) * 1991-11-27 2000-06-05 日本ゼオン株式会社 Acrylic ester copolymer plastisol composition
JPH0964336A (en) 1995-08-25 1997-03-07 Advantest Corp Ohmic electrode structure of semiconductor and its forming method by atomic layer doping
US5792700A (en) * 1996-05-31 1998-08-11 Micron Technology, Inc. Semiconductor processing method for providing large grain polysilicon films
US5916365A (en) * 1996-08-16 1999-06-29 Sherman; Arthur Sequential chemical vapor deposition
JP3239779B2 (en) * 1996-10-29 2001-12-17 日新電機株式会社 Substrate processing apparatus and substrate processing method
EP0856594B1 (en) * 1997-01-07 2001-06-13 Siegfried Dr. Strämke Apparatus for plasma treatment of substrates
US6174377B1 (en) * 1997-03-03 2001-01-16 Genus, Inc. Processing chamber for atomic layer deposition processes
US6321134B1 (en) * 1997-07-29 2001-11-20 Silicon Genesis Corporation Clustertool system software using plasma immersion ion implantation
US6305314B1 (en) * 1999-03-11 2001-10-23 Genvs, Inc. Apparatus and concept for minimizing parasitic chemical vapor deposition during atomic layer deposition
US6503330B1 (en) * 1999-12-22 2003-01-07 Genus, Inc. Apparatus and method to achieve continuous interface and ultrathin film during atomic layer deposition
US6576062B2 (en) * 2000-01-06 2003-06-10 Tokyo Electron Limited Film forming apparatus and film forming method
US6482733B2 (en) * 2000-05-15 2002-11-19 Asm Microchemistry Oy Protective layers prior to alternating layer deposition
US20030054133A1 (en) * 2000-08-07 2003-03-20 Wadley Hadyn N.G. Apparatus and method for intra-layer modulation of the material deposition and assist beam and the multilayer structure produced therefrom

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4089735A (en) * 1968-06-05 1978-05-16 Siemens Aktiengesellschaft Method for epitactic precipitation of crystalline material from a gaseous phase, particularly for semiconductors
US3602192A (en) * 1969-05-19 1971-08-31 Ibm Semiconductor wafer processing
US3618919A (en) * 1969-11-03 1971-11-09 Btu Eng Corp Adjustable heat and gas barrier
US4593644A (en) * 1983-10-26 1986-06-10 Rca Corporation Continuous in-line deposition system
US4576830A (en) * 1984-11-05 1986-03-18 Chronar Corp. Deposition of materials
US5374570A (en) * 1989-03-17 1994-12-20 Fujitsu Limited Method of manufacturing active matrix display device using insulation layer formed by the ale method
US5071670A (en) * 1990-06-11 1991-12-10 Kelly Michael A Method for chemical vapor deposition under a single reactor vessel divided into separate reaction chambers each with its own depositing and exhausting means
US5366555A (en) * 1990-06-11 1994-11-22 Kelly Michael A Chemical vapor deposition under a single reactor vessel divided into separate reaction regions with its own depositing and exhausting means
US5314538A (en) * 1991-04-22 1994-05-24 Semiconductor Process Laboratory Apparatus for manufacturing semiconductor device and method for manufacturing semiconductor device
US5667592A (en) * 1996-04-16 1997-09-16 Gasonics International Process chamber sleeve with ring seals for isolating individual process modules in a common cluster
US5747113A (en) * 1996-07-29 1998-05-05 Tsai; Charles Su-Chang Method of chemical vapor deposition for producing layer variation by planetary susceptor rotation
US6143082A (en) * 1998-10-08 2000-11-07 Novellus Systems, Inc. Isolation of incompatible processes in a multi-station processing chamber
US6527866B1 (en) * 2000-02-09 2003-03-04 Conductus, Inc. Apparatus and method for deposition of thin films
US20020100418A1 (en) * 2000-05-12 2002-08-01 Gurtej Sandhu Versatile atomic layer deposition apparatus
US20020195056A1 (en) * 2000-05-12 2002-12-26 Gurtej Sandhu Versatile atomic layer deposition apparatus

Cited By (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020100418A1 (en) * 2000-05-12 2002-08-01 Gurtej Sandhu Versatile atomic layer deposition apparatus
US20020122885A1 (en) * 2001-03-01 2002-09-05 Micron Technology, Inc. Methods, systems, and apparatus for uniform chemical-vapor depositions
US20080283940A1 (en) * 2001-12-20 2008-11-20 Micron Technology, Inc. LOW-TEMPERATURE GROWN HIGH QUALITY ULTRA-THIN CoTiO3 GATE DIELECTRICS
US8178413B2 (en) 2001-12-20 2012-05-15 Micron Technology, Inc. Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics
US20050158973A1 (en) * 2001-12-20 2005-07-21 Micron Technology, Inc. Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics
US7804144B2 (en) 2001-12-20 2010-09-28 Micron Technology, Inc. Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics
US20110014767A1 (en) * 2001-12-20 2011-01-20 Ahn Kie Y LOW-TEMPERATURE GROWN HIGH QUALITY ULTRA-THIN CoTiO3 GATE DIELECTRICS
US20050145957A1 (en) * 2002-02-20 2005-07-07 Micron Technology, Inc. Evaporated LaAlO3 films for gate dielectrics
US7670646B2 (en) 2002-05-02 2010-03-02 Micron Technology, Inc. Methods for atomic-layer deposition
US7887711B2 (en) * 2002-06-13 2011-02-15 International Business Machines Corporation Method for etching chemically inert metal oxides
US20030230549A1 (en) * 2002-06-13 2003-12-18 International Business Machines Corporation Method for etching chemically inert metal oxides
US7728626B2 (en) 2002-07-08 2010-06-01 Micron Technology, Inc. Memory utilizing oxide nanolaminates
US8228725B2 (en) 2002-07-08 2012-07-24 Micron Technology, Inc. Memory utilizing oxide nanolaminates
US8125038B2 (en) 2002-07-30 2012-02-28 Micron Technology, Inc. Nanolaminates of hafnium oxide and zirconium oxide
US20040058293A1 (en) * 2002-08-06 2004-03-25 Tue Nguyen Assembly line processing system
US20050124174A1 (en) * 2002-08-15 2005-06-09 Micron Technology, Inc. Lanthanide doped TiOx dielectric films by plasma oxidation
US20040043541A1 (en) * 2002-08-29 2004-03-04 Ahn Kie Y. Atomic layer deposited lanthanide doped TiOx dielectric films
US7923381B2 (en) 2002-12-04 2011-04-12 Micron Technology, Inc. Methods of forming electronic devices containing Zr-Sn-Ti-O films
US20050164521A1 (en) * 2002-12-04 2005-07-28 Micron Technology, Inc. Zr-Sn-Ti-O films
US6958302B2 (en) 2002-12-04 2005-10-25 Micron Technology, Inc. Atomic layer deposited Zr-Sn-Ti-O films using TiI4
US20040110348A1 (en) * 2002-12-04 2004-06-10 Micron Technology, Inc. Atomic layer deposited Zr-Sn-Ti-O films using TiI4
US8445952B2 (en) 2002-12-04 2013-05-21 Micron Technology, Inc. Zr-Sn-Ti-O films
US20040110391A1 (en) * 2002-12-04 2004-06-10 Micron Technology, Inc. Atomic layer deposited Zr-Sn-Ti-O films
US7101813B2 (en) 2002-12-04 2006-09-05 Micron Technology Inc. Atomic layer deposited Zr-Sn-Ti-O films
US7192892B2 (en) 2003-03-04 2007-03-20 Micron Technology, Inc. Atomic layer deposited dielectric layers
US20040175882A1 (en) * 2003-03-04 2004-09-09 Micron Technology, Inc. Atomic layer deposited dielectric layers
US20060001151A1 (en) * 2003-03-04 2006-01-05 Micron Technology, Inc. Atomic layer deposited dielectric layers
US20040187784A1 (en) * 2003-03-28 2004-09-30 Fluens Corporation Continuous flow deposition system
US6972055B2 (en) * 2003-03-28 2005-12-06 Finens Corporation Continuous flow deposition system
US7135369B2 (en) 2003-03-31 2006-11-14 Micron Technology, Inc. Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9
US20060255470A1 (en) * 2003-03-31 2006-11-16 Micron Technology, Inc. ZrAlxOy DIELECTRIC LAYERS
US20050020017A1 (en) * 2003-06-24 2005-01-27 Micron Technology, Inc. Lanthanide oxide / hafnium oxide dielectric layers
US20060006548A1 (en) * 2003-08-05 2006-01-12 Micron Technology, Inc. H2 plasma treatment
JP2008503433A (en) * 2004-06-24 2008-02-07 ベネク・オサケユキテュア Method for doping materials and doped materials
US20070218290A1 (en) * 2004-06-24 2007-09-20 Beneq Oy Method for Doping Material and Doped Material
US7776762B2 (en) 2004-08-02 2010-08-17 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US8765616B2 (en) 2004-08-02 2014-07-01 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7727905B2 (en) 2004-08-02 2010-06-01 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US8288809B2 (en) 2004-08-02 2012-10-16 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7719065B2 (en) 2004-08-26 2010-05-18 Micron Technology, Inc. Ruthenium layer for a dielectric layer containing a lanthanide oxide
US20060046505A1 (en) * 2004-08-26 2006-03-02 Micron Technology, Inc. Ruthenium gate for a lanthanide oxide dielectric layer
US8558325B2 (en) 2004-08-26 2013-10-15 Micron Technology, Inc. Ruthenium for a dielectric containing a lanthanide
US8907486B2 (en) 2004-08-26 2014-12-09 Micron Technology, Inc. Ruthenium for a dielectric containing a lanthanide
US8237216B2 (en) 2004-08-31 2012-08-07 Micron Technology, Inc. Apparatus having a lanthanum-metal oxide semiconductor device
US7867919B2 (en) 2004-08-31 2011-01-11 Micron Technology, Inc. Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer
US8154066B2 (en) 2004-08-31 2012-04-10 Micron Technology, Inc. Titanium aluminum oxide films
US8541276B2 (en) 2004-08-31 2013-09-24 Micron Technology, Inc. Methods of forming an insulating metal oxide
WO2006031956A3 (en) * 2004-09-13 2007-06-07 Genus Inc Multi-single wafer processing apparatus
WO2006031956A2 (en) * 2004-09-13 2006-03-23 Genus, Inc. Multi-single wafer processing apparatus
US20060137609A1 (en) * 2004-09-13 2006-06-29 Puchacz Jerzy P Multi-single wafer processing apparatus
US20060125030A1 (en) * 2004-12-13 2006-06-15 Micron Technology, Inc. Hybrid ALD-CVD of PrxOy/ZrO2 films as gate dielectrics
US8278225B2 (en) 2005-01-05 2012-10-02 Micron Technology, Inc. Hafnium tantalum oxide dielectrics
US8524618B2 (en) 2005-01-05 2013-09-03 Micron Technology, Inc. Hafnium tantalum oxide dielectrics
US8742515B2 (en) 2005-02-08 2014-06-03 Micron Technology, Inc. Memory device having a dielectric containing dysprosium doped hafnium oxide
US7508648B2 (en) 2005-02-08 2009-03-24 Micron Technology, Inc. Atomic layer deposition of Dy doped HfO2 films as gate dielectrics
US20090155976A1 (en) * 2005-02-08 2009-06-18 Micron Technology, Inc. Atomic layer deposition of dy-doped hfo2 films as gate dielectrics
US8481395B2 (en) 2005-02-08 2013-07-09 Micron Technology, Inc. Methods of forming a dielectric containing dysprosium doped hafnium oxide
US20060176645A1 (en) * 2005-02-08 2006-08-10 Micron Technology, Inc. Atomic layer deposition of Dy doped HfO2 films as gate dielectrics
US7989285B2 (en) 2005-02-08 2011-08-02 Micron Technology, Inc. Method of forming a film containing dysprosium oxide and hafnium oxide using atomic layer deposition
US7399666B2 (en) 2005-02-15 2008-07-15 Micron Technology, Inc. Atomic layer deposition of Zr3N4/ZrO2 films as gate dielectrics
US20060183272A1 (en) * 2005-02-15 2006-08-17 Micron Technology, Inc. Atomic layer deposition of Zr3N4/ZrO2 films as gate dielectrics
US8399365B2 (en) 2005-03-29 2013-03-19 Micron Technology, Inc. Methods of forming titanium silicon oxide
US8076249B2 (en) 2005-03-29 2011-12-13 Micron Technology, Inc. Structures containing titanium silicon oxide
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US20070049051A1 (en) * 2005-08-29 2007-03-01 Micron Technology, Inc. Atomic layer deposition of Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics
US8497542B2 (en) 2005-08-29 2013-07-30 Micron Technology, Inc. ZrXHfYSn1-X-YO2 films as high K gate dielectrics
US7393736B2 (en) 2005-08-29 2008-07-01 Micron Technology, Inc. Atomic layer deposition of Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics
US7875912B2 (en) 2005-08-29 2011-01-25 Micron Technology, Inc. Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics
US20080224240A1 (en) * 2005-08-29 2008-09-18 Micron Technology, Inc. ATOMIC LAYER DEPOSITION OF Zrx Hfy Sn1-x-y O2 FILMS AS HIGH k GATE DIELECTRICS
US20110121378A1 (en) * 2005-08-29 2011-05-26 Ahn Kie Y ZrXHfYSn1-X-YO2 FILMS AS HIGH K GATE DIELECTRICS
US20070151842A1 (en) * 2005-12-15 2007-07-05 Fluens Corporation Apparatus for reactive sputtering
US8067794B2 (en) 2006-02-16 2011-11-29 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US7709402B2 (en) 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US8785312B2 (en) 2006-02-16 2014-07-22 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride
US20100041244A1 (en) * 2006-08-31 2010-02-18 Micron Technology, Inc. Hafnium tantalum oxynitride dielectric
US8466016B2 (en) 2006-08-31 2013-06-18 Micron Technolgy, Inc. Hafnium tantalum oxynitride dielectric
US8084370B2 (en) 2006-08-31 2011-12-27 Micron Technology, Inc. Hafnium tantalum oxynitride dielectric
US8759170B2 (en) 2006-08-31 2014-06-24 Micron Technology, Inc. Hafnium tantalum oxynitride dielectric
US8847334B2 (en) 2007-06-28 2014-09-30 Micron Technology, Inc. Method of forming lutetium and lanthanum dielectric structures
US7759237B2 (en) 2007-06-28 2010-07-20 Micron Technology, Inc. Method of forming lutetium and lanthanum dielectric structures
US20090004801A1 (en) * 2007-06-28 2009-01-01 Micron Technology, Inc. Method of forming lutetium and lanthanum dielectric structures
US8071443B2 (en) 2007-06-28 2011-12-06 Micron Technology, Inc. Method of forming lutetium and lanthanum dielectric structures
TWI471961B (en) * 2007-10-26 2015-02-01 Sosul Co Ltd Baffle, substrate supporting apparatus and plasma processing apparatus and plasma processing method
US20100186669A1 (en) * 2008-12-29 2010-07-29 K.C. Tech Co., Ltd. Atomic layer deposition apparatus
US8968476B2 (en) 2008-12-29 2015-03-03 K.C. Tech Co., Ltd. Atomic layer deposition apparatus
US20100221426A1 (en) * 2009-03-02 2010-09-02 Fluens Corporation Web Substrate Deposition System
US20140199854A1 (en) * 2013-01-16 2014-07-17 United Microelectronics Corp. Method of forming film on different surfaces
US20160002784A1 (en) * 2014-07-07 2016-01-07 Varian Semiconductor Equipment Associates, Inc. Method and apparatus for depositing a monolayer on a three dimensional structure
US9847228B2 (en) 2014-07-07 2017-12-19 Varian Semiconductor Equipment Associates, Inc. Method for selectively depositing a layer on a three dimensional structure
US9929015B2 (en) 2014-07-07 2018-03-27 Varian Semiconductor Equipment Associates, Inc. High efficiency apparatus and method for depositing a layer on a three dimensional structure
US11031247B2 (en) 2014-07-07 2021-06-08 Varian Semiconductor Equipment Associates, Inc. Method and apparatus for depositing a monolayer on a three dimensional structure

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KR20030064395A (en) 2003-07-31

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