US20020053694A1 - Method of forming a memory cell with self-aligned contacts - Google Patents
Method of forming a memory cell with self-aligned contacts Download PDFInfo
- Publication number
- US20020053694A1 US20020053694A1 US10/002,903 US290301A US2002053694A1 US 20020053694 A1 US20020053694 A1 US 20020053694A1 US 290301 A US290301 A US 290301A US 2002053694 A1 US2002053694 A1 US 2002053694A1
- Authority
- US
- United States
- Prior art keywords
- bit line
- forming
- transfer gate
- storage node
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 65
- 230000015654 memory Effects 0.000 title claims description 36
- 238000012546 transfer Methods 0.000 claims abstract description 67
- 238000003860 storage Methods 0.000 claims abstract description 58
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000011810 insulating material Substances 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 57
- 229920005591 polysilicon Polymers 0.000 claims description 57
- 239000012212 insulator Substances 0.000 claims description 40
- 239000000463 material Substances 0.000 claims description 33
- 239000004020 conductor Substances 0.000 claims description 32
- 150000004767 nitrides Chemical class 0.000 claims description 27
- 238000000151 deposition Methods 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 19
- 230000000873 masking effect Effects 0.000 claims description 18
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 12
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 26
- 239000005380 borophosphosilicate glass Substances 0.000 description 16
- 239000000377 silicon dioxide Substances 0.000 description 13
- 235000012239 silicon dioxide Nutrition 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 229910021342 tungsten silicide Inorganic materials 0.000 description 9
- 230000008021 deposition Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000013459 approach Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 230000008030 elimination Effects 0.000 description 4
- 238000003379 elimination reaction Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000006731 degradation reaction Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 239000000872 buffer Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 241001279686 Allium moly Species 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical group CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/40—Response verification devices using compression techniques
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67075—Apparatus for fluid treatment for etching for wet etching
- H01L21/6708—Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/6715—Apparatus for applying a liquid, a resin, an ink or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/036—Making the capacitor or connections thereto the capacitor extending under the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
Definitions
- This invention relates generally to semiconductor devices and specifically to a method of forming a memory cell with an alternate self-aligned contact implementation.
- DRAMS As DRAMS increase in memory cell density, there is a continuous challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area.
- One way of increasing cell capacitance is to through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors.
- SAC Self Aligned Contacts
- the self aligned nature is accomplished by definition (patterning and etching) of a contact whose electrical contact (active) area is defined by pre-existing features and not the patterned contact area.
- the feature size is sufficiently small that complex photolithography processes (e.g., phase shifted reticules) are required for patterning and alignment is critical.
- the active contact area is defined by removing (etching) the contact oxide defined by the pattern (mask) and is self-aligned to some particular structures (e.g., the transfer gate and field oxide region).
- some particular structures e.g., the transfer gate and field oxide region.
- the dielectric exists on the top (defined at the previous gate patterning operation) and sides) formed at the previous sidewall formation) of the transfer gate.
- the active device area (moat), a silicon region is defined by the isolation oxide (field oxide).
- the implementation of this technique utilizes differences in etch rates of dissimilar materials (etch selectivity) to provide final film thickness and over-etch process margin.
- the present invention provides a method of forming a memory cell with a new approach for self-aligned contacts, which overcomes many of the problems exhibited by the prior art.
- the present invention decreases process complexity, decreases parasitic capacitance to adjacent electrical conductors (e.g., DRAM word line), increases patterning process margin and increases etching process margin by utilizing fewer process steps, lower dielectric constant materials, relaxing minimum feature size at the contact patterning and by elimination of the need for high silicon dioxide (SiO 2 ) to silicon nitride (SiN 4 ) selectively at contact etching.
- aspects of the invention will have specific application in 64 Meg and larger DRAM process flows and beyond.
- the present invention implements self aligned electrical connections without hole (contact) pattern definition.
- Planar conductive (polysilicon) and insulating (silicon dioxide and silicon nitride) films are used to enable the use of high selectivity etch processes for stacked memory structure cell definition.
- the present invention provides a method of forming a dynamic random access memory device, which utilizes self-aligned contact pads for the bit line and storage node contacts.
- a transfer gate is formed at the face of a semiconductor region.
- the semiconductor region includes a bit line contact region and a storage node contact region at opposite edges of the transfer gate.
- the transfer gate is surrounded with an insulating material, preferably silicon dioxide.
- a conductive layer is formed over the transfer gate, over the bit line contact region and over the storage node contact region. This conductive layer is then etched so that a first portion of the conductive layer provides an electrical contact to the bit line contact region and a second portion of the conductive layer provides an electrical contract to the storage node contact region.
- the bit line and storage nodes can then be formed in electrical contact with the first and second portions of the conductive layer, respectively.
- first and second transfer gates are formed at the face of a semiconductor region.
- the semiconductor region includes a bit line contact region located between the first an second transfer gates.
- the transfer gate is surrounded with an insulating material such as silicon dioxide.
- a conductive layer preferably polysilicon, is formed over the transfer gate, over the bit line contact region and over the storage node contact region.
- a masking layer preferably silicon dioxide, is then formed over the conductive layer.
- a contact window is then formed by removing a portion of the masking layer so as to expose a portion of the conductive layer over the bit line contact regions and over portions of the first and second transfer gates which are adjacent to the bit line contract region.
- a bit line layer(s) can then be formed over the masking layer and the exposed portion of the conductive layer.
- a bit line can then be formed by patterning and etching the bit line layer. This patterning and etching step also exposes a portion of the conductive layer between the masking layer and the bit line. The exposed portion of the conductive layer can then be removed using the masking layer as a mask.
- a storage node electrode can then be formed in electrical contact with a portion of the conductive layer, which overlies the storage node contact region.
- the method of the present invention can be used to fabricate a novel memory device.
- This device includes at least one transfer gate formed in an active region of a semiconductor device.
- the transfer gate is spaced from a field oxide region by a contact region within the active region.
- a top surface insulator is disposed along the top surface of the transfer gate and is formed from a first material (e.g., an oxide).
- a sidewall insulator is disposed along the sidewall of the transfer gate and is formed from a second material (e.g., an oxide).
- a conductive pad (e.g., polysilicon) extends from over a portion of the field oxide region to over a portion of the top surface insulator. This conductive pad abuts the contact region of the active area.
- a storage node conductor which serves as one plate of a capacitor, abuts the conductive pad.
- a novel memory device in another aspect, includes first and second transfer gates. Both gates have a top surface insulator and a sidewall insulator. The top surface insulator a sidewall insulator are formed from different materials. A conductive pad extends over a portion of the first top surface insulator, the first sidewall insulator, the contact region within the active area, the second sidewall insulator, and a portion of the second top surface insulator. The conductive pad abuts the contact region of the active area.
- a bit line conductor comprises a bit line within a memory array.
- the present invention has a number of advantages over prior art processes.
- process complexity is reduced by the elimination of two etches, two polysilicon depositions, one silicon dioxide deposition and one silicon nitride deposition as compared with other processes.
- contact etch margin is improved-by the elimination of special high selectivity processes. Only industry standard etch processes are required to implement the poly pad self aligned contact process. The industry standard interconnect contact etch process selectivity is sufficient to provide over etch margin.
- This processing approach also reduces word line (transfer gate) parasitic capacitance by utilization of silicon dioxide rather than silicon nitride as the masking and sidewall material.
- this processing approach provides an opportunity to improve the average and standard deviation of the DRAM device pause by elimination of one of the known causes of pause degradation.
- the process also provides an opportunity to perform special pause improvement process steps prior to sealing the single crystal silicon (moat) regions.
- Pause degradation is known to be due to silicon lattice damage and other lattice disruption. Since no contact etching comes in contact with the moat regions the normal degradation due to this process is eliminated.
- bit line contacts and undersized bit line are used. These elements in the contact region are sized for the proven production device design (layout) and Design Registration Accuracy (DRA) capability inherent in the present pattern and etch tool set.
- DRA Design Registration Accuracy
- the example embodiment of the new SAC structure uses a 2 transistor cell with common active region (Bit line contact) a separate storage node contacts. This invention can be equally implemented in a single transistor structure.
- FIG. 1 a is a cross-sectional view of a prior art DRAM device
- FIG. 1 b is a schematic diagram of the device of FIG. 1 a;
- FIG. 2 a is a schematic diagram of an array of DRAM cells
- FIGS. 2 b - 2 c are block diagrams of two embodiment DRAM devices
- FIGS. 3 - 12 are cross-sectional views of a device after various process steps of the present invention.
- FIGS. 13 - 15 are cross-sectional views of a device after various process steps of an alternate embodiment of the present invention.
- FIGS. 16 - 18 are cross-sectional views of a device after various process steps of a second alternate embodiment of the present invention.
- FIGS. 19 - 35 show further embodiments.
- FIG. 1 a illustrates two prior art DRAM cells, each of which includes a capacitor 12 coupled in series with a transfer transistor 10 .
- FIG. 1 b is a schematic diagram of the DRAM cells of FIG. 1 a.
- each DRAM cell includes a pass transistor 10 coupled in series with a capacitor 12 .
- the gate 14 of pass transistor 10 comprises one of the word lines WL of the memory array. (A memory array will be described in more detail with respect to FIG. 2 a ).
- a shared source/drain region 16 of each pass transistor 10 is coupled to bit line 18 .
- the other source/drain region 20 is coupled to the storage node electrode 22 of capacitor 12 .
- Capacitor 12 further includes dielectric layer 24 and cell plate 26 .
- FIG. 2 a A simplified schematic diagram of a DRAM array is illustrated in FIG. 2 a .
- a plurality of memory cells can be formed in an array of rows and columns.
- FIG. 2 a illustrates only six bit lines BL and for word lines WL in what in actuality would likely be a much larger array.
- the pass transistor Q of each memory cells has a gate G coupled to a word line WL and a source/drain region BLC (for bit line contact) coupled to a bit line BL.
- the transfer gate G of one pass transistor Q will be electrically coupled to the word line WL for a number of other pass transistors.
- FIG. 2 a also illustrates some of the peripheral circuitry, which would be included in a memory array.
- each pair of bit lines BL and BL (bar) is coupled to a sense amplifier SA.
- the bit lines BL and BI (bar) are also coupled to input/output lines I/O and I/O (bar) through select transistors Y 0 -Y 2 .
- Other peripheral circuitry such as the row decoders, column decoders, address buffers, I/O buffers and so on is not illustrated here.
- the memory cell and fabrication method independent of the memory architecture.
- the memory array can be designed as an asynchronous memory or as a synchronous memory.
- a synchronous memory can be timed with an internal clock (not shown) or an external clock (not shown).
- the device can have a single external data terminal or multiple external data terminals (i.e., wide word).
- the array can include a total of 4 megabits, 16 megabits, 64 megabits, 256 megabits, one gigabit or more.
- FIG. 2 b A simplified block diagram of a memory device is shown in FIG. 2 b .
- the internal device circuitry includes an array and peripheral circuitry.
- the array may be divided into a number of blocks depending upon the device architecture.
- Sense amplifiers may be interleaved within the array blocks.
- FIG. 2 b Several external terminals are illustrated in FIG. 2 b .
- Address terminals A 0 , A 1 , . . . , A n are provided for receiving row and column addresses. These terminals may be multiplexed (i.e., a first address is applied at a first time and a second address applied at a second time).
- a single data terminal D is also illustrated. This terminal may comprise an input, an output or an input/output. Other data terminals may also be included. For example, a wide word device will have multiple data terminals. In general, these terminals are provided for receiving input signals from circuitry (not shown) external of the array and for providing output signals to circuitry (not shown) external of the array.
- FIG. 2 b also illustrates a number of control/status signals. These signals are used to operate the memory device. For example, an asynchronous memory device may be operated by applying chip select, row address strobe and column address strobe signals. Other signals may indicate whether a read or write operation is being performed. In a synchronous device, one of the control signals may be a clock signal. Status signals may provide information about the device to the external system. For example, the device may include a signal indicating whether a refresh operation is taking place or which portion of the array is being accessed.
- a memory array of the present invention could also be embedded in a larger integrated circuit device.
- An embedded memory is a memory array and its associated control circuit on the same integrated circuit as a substantial amount of logic.
- FIG. 5 c has been included to illustrate a simple block diagram of an embedded memory.
- a DRAM array is included along with a processor (e.g., microprocessor, digital signal processor, specialty processor, microcontroller), another memory array (e.g., SRAM, non-volatile memory such as EPROM, EEPROM, flash memory, PROM, ROM, another DRAM array) and other logic circuitry.
- a processor e.g., microprocessor, digital signal processor, specialty processor, microcontroller
- another memory array e.g., SRAM, non-volatile memory such as EPROM, EEPROM, flash memory, PROM, ROM, another DRAM array
- SRAM non-volatile memory
- EPROM erasable programmable read-only memory
- EEPROM electrically erasable
- the present invention pertains to a novel method for forming self-aligned contacts.
- a first embodiment of the present invention will be described with respect to FIGS. 3 - 12 .
- semiconductor region 30 comprises a p-doped silicon substrate.
- Other semiconductor regions could also be used.
- n-doped silicon substrate can be used.
- semiconductor region 30 could alternatively be an epitaxially grown layer, a region within a region such as a well, a tank or a tub, a semiconductor layer over an insulating layer (e.g., S.O.I.) or just about any other semiconductor region.
- Field isolation regions 32 are also illustrated in FIG. 3.
- field oxide regions 32 are formed by the known LOCOS (local oxidation of silicon) process.
- LOCOS local oxidation of silicon
- a thin nitride layer (not shown) is blanket deposited over the substrate and then patterned to expose the areas where the field oxide 32 will be formed. These exposed regions are then oxidized.
- other isolation techniques such as trench isolation or field plate isolation can be used.
- transfer gates (word lines) 14 are formed.
- each transfer gate is a conductor formed by a layer of doped polysilicon 14 a with a layer of tungsten silicide 14 b overlying to lower the resistance.
- Transfer gate 14 is separated from substrate 30 by gate insulating layer (e.g., oxide, nitride, oxide-nitride stack) 36 .
- gate insulating layer e.g., oxide, nitride, oxide-nitride stack
- transfer gate 14 can be formed from other materials such a titanium silicide/poly, moly disilicide/poly, doped poly only, or tungsten/poly films could be used.
- the figures only show the word lines 14 for two pass transistors. It is noted, however, that word lines for memory cells not illustrated would also be formed simultaneously (see FIG. 1 a ).
- An insulating layer 34 preferably an oxide, is formed over each transfer gate 14 .
- transfer gates 14 are formed by sequentially depositing layers of polysilicon, tungsten silicide and then the insulator. These layers are then patterned using standard photolithography and etched.
- a low dielectric constant silicon dioxide sidewall 38 is applied to transfer gate 14 . This step is illustrated in FIG. 5.
- a different material can be used for sidewall 38 .
- nitride sidewall regions 38 are envisioned.
- the sidewall regions can be formed by blanket depositing an insulating layer such as silicon dioxide over the device.
- the layer can be anisotropically etched so that sidewall insulating regions 38 remain. Sidewall insulating region 38 along with insulating layer 34 will surround transfer gate 14 .
- a common conductive layer 40 is formed over the exposed moat regions and overlaps onto transfer gate 14 and field oxide regions 32 .
- conductive layer 40 comprises doped polysilicon but other materials could alternatively be used.
- Masking layer 42 is formed over the conductive layer 40 .
- this step entails depositing a layer 42 of silicon dioxide. In other embodiments, other materials could alternatively be used.
- FIG. 7 a a portion of masking layer 42 is removed so as to expose a portion of conductive layer 40 over a bit line contact region 44 within substrate 30 . This step will also expose portions of both of the transfer gates 14 which are adjacent to the bit line contact region 44 . This oversized contact window 41 is opened for the bit line contact (formation of bit line 18 will be illustrated in FIG. 8 a ). A plan view of the device is shown in FIG. 7 b.
- the contact window is an oversized window when it is patterned without using the minimum photolithographic distance.
- the minimum photlithographic distance is the smallest dimension that can be patterned using a given photolithography system. Since the contact window overlaps adjacent transfer gates 14 , there is no need to be confined to the photolithographic minimum distance. This capability provides an advantage since very precise patterning is not necessary. This capability also provides a further advantage in that the process is scalable. As future generations attempt to pack more memory cells into a smaller area, the contact window can be scaled to smaller dimensions. In this manner, higher density memories can be formed using the same processing steps, possibly by patterning contact window 41 at a photolithographic minimum distance.
- bit line 18 is formed. After deposition of the bit line film(s) (e.g., polysilicon 18 a and tungsten silicide 18 b ), bit line 18 is patterned and etched. The bit line pattern is undersized in the contact region to allow unwanted portions of the conductive layer 40 to be removed. In other words, the bit line layer is patterned and etched to expose a portion of conductive layer 40 between masking layer 42 and bit line 18 . The exposed portion of conductive layer 40 is then removed using masking layer 42 as a mask (along with a patterned photoresist layer over bit line 18 , which is not illustrated). This way the bit line contact portion 40 a of conductive layer 40 is electrically isolated form the remainder of conductive layer 40 .
- the bit line film(s) e.g., polysilicon 18 a and tungsten silicide 18 b
- FIG. 8 b illustrates a plan view of the device.
- the contacts 40 a and 40 b are symmetric and than can be printed with alternating phase shift.
- the moat symmetry should be sufficient to be printed with alternating phase shift as is now done with other processes. With the present invention, however, the packing density (i.e., the number of memory cells in a given area) should be higher.
- an insulating layer 46 / 48 / 50 is formed over the device.
- a multilayer insulator is formed.
- a deposited oxide layer 46 which can be formed by the decomposition of tetraethyloxysilane (TEOS).
- a nitride layer 48 is deposited.
- a planarizing film such as BPSG (borophosphosilicate glass) layer 50 is formed.
- storage node contact holes are opened.
- a photoresist layer (not shown) is applied to the device and patterned to expose a portion of the BPSG layer 50 over the storage node contact region.
- the multilayer insulator 46 / 48 / 50 is then etched to expose a storage node contact portion 40 b of conductive layer 40 .
- FIGS. 11 and 12 One method of forming storage node 22 is illustrated in FIGS. 11 and 12.
- a conductive layer 54 such as doped polysilicon is formed over the device.
- the conductive layer 54 abuts the storage contact portion 40 b of conductive layer 40 .
- sacrificial regions 56 are formed over the storage node contact.
- Another conductive layer 58 preferably of the same material as conductive layer 54 , is formed over sacrificial region 56 and conductive layer 54 .
- dielectric layer 24 and cell plate conductor 26 can then be formed over storage node conductor 22 .
- dielectric layer 24 can be an oxide/nitride/oxide layer or a layer of higher dielectric constant material such as tantalum pentoxide, barium strontium titanate, or lead zirconium titanate.
- the memory cell will be completed by forming a capacitor dielectric 24 and a cell plate electrode 26 over the storage node 22 .
- Other steps would also be performed but, for the sake of simplicity, will not be illustrated here.
- several layers of insulators and metal interconnects could be formed in order to properly interconnect the various circuits within the memory device.
- the device will also be tested and packaged. Steps such as these are known in the art and need not be described here.
- FIGS. 13 - 15 illustrate one such modification.
- the cross-sectional view of FIG. 13 is taken after additional processing is performed on the structure of FIG. 8 a .
- a sidewall 60 is formed along sidewalls of bit line 18 .
- the sidewall is preferably formed from an oxide material.
- the oxide sidewall 60 is formed by depositing an oxide layer and then etching back. The etch back step will also clear the oxide layer 42 over the storage node pad 40 b.
- an insulating layer 62 will be formed over the bit line 18 .
- This insulating layer 62 is preferably a low dielectric constant material such as an oxide. While nitride could alternatively be used, this material is not preferred since it will increase the capacitance between bit line 18 and other conductors (not shown).
- the storage node contact pad 40 b is opened without a pattern step and then the storage node polysilicon (or other conductor) layer 62 is deposited as shown in FIG. 14. Sacrificial regions 66 are then formed over the conductive layer 62 . These regions 66 were formed by depositing a thick planar material (e.g., oxide BPSG) and selectively etching. It is noted that unlike sacrificial region 56 of FIG. 11, sacrificial region 66 is patterned to expose rather than cover the storage node contact areas.
- a thick planar material e.g., oxide BPSG
- Another conductive layer 68 is formed over sacrificial region 66 and conductive layer 64 .
- an anisotropic etch can then be performed. This etch will remove the exposed portions of layers 64 and 66 leaving conductive sidewalls along sacrificial region 66 .
- a crown-shaped storage node electrode 22 remains. This structure is shown in FIG. 15.
- FIGS. 16 - 18 Another embodiment is illustrated in FIGS. 16 - 18 showing that some of the process steps could be modified yet again.
- a nitride layer 70 could be deposited as shown in FIG. 16.
- a layer 72 of BPSG could then be deposited and etched back in order to planarize the upper surface.
- the BPSG 72 could then be patterned to expose the storage node contact pad 40 b .
- This etch would be performed in two steps. First, there is an oxide etch which stops on nitride followed by nitride etch which stops on oxide. After the oxide 72 and nitride 70 are etched, the pad 40 b cleaned.
- polysilicon layer 74 could be deposited.
- Another BPSG layer 76 is then deposited and etched back to expose the polysilicon layer 74 .
- the exposed portions of polysilicon 74 are then etched as shown in FIG. 18. During this etching step, the layer 76 protects the pad region.
- This polysilicon etch is preferably an end point etch followed by a deglaze to remove any thin oxide layers.
- FIG. 18 illustrates the memory device after removal of the layers 72 and 76 .
- the regions 72 an 76 are removed with the nitride layer 70 over bit line 18 serving as an etch stop.
- This etch stop layer will protect the bit line 18 . Accordingly, the etch should be highly selective to oxide.
- a capacitor dielectric (not shown) and cell plate electrode (not shown) are formed over the storage node 22 . As before, other processing steps will be performed to complete the memory device.
- FIGS. 19 - 29 illustrate another embodiment.
- FIG. 19 shows filed isolation 32
- FIG. 20 shows wordlines in cross sectional view made of nitride 34 on tungsten silicide 14 b on polysilicon 14 a on gate oxide 36
- FIG. 21 illustrates sidewall oxide formed by conformal deposition and anisotropic etch.
- FIG. 22 shows deposited polysilicon 40 , which has been patterned to remove the portion away from the moats and covered with deposited oxide 42 .
- FIG. 23 shows oxide 42 patterned and etched by an oversize bit line contact pattern to expose polysilicon 40 in opening 41 .
- the tungsten silicide plus polysilicon etch (chlorine-based plasma) stops on the nitride 34 .
- oxidize the exposed surfaces of the polysilicon and tungsten silicide see FIG. 24, which shows tungsten silicide 18 b on polysilicon 18 a , which is on original polysilicon 40 .
- FIG. 25 shows the result of a blanket oxide deposition followed by anisotropic etching to form sidewall oxide 46 on the bit line plus sidewall oxide 47 on the portions of polysilicon 40 away from the bit lines. Note that the oxide on the surface of this portion polysilicon 40 is removed because it was not thick enough to survive the anisotropic etching.
- BPSG 56 deposit 25 nm nitride 55 and 550 nm BPSG 56 . Etch back the BPSG for planarization and pattern etch to for openings 71 for eventual capacitors; see FIG. 26. Then etch the exposed portion of nitride 55 and deposit 100 nm thick polysilicon 72 . Then deposit 400 nm of BPSG 57 and etch back; this leaves BPSG 72 in the openings as illustrated by FIG. 27.
- FIGS. 30 - 35 a variation of the preferred embodiment of FIGS. 11 - 12 .
Abstract
In one embodiment, the present invention provides a method of forming a dynamic random access memory device which utilizes self-aligned contact pads 40 a and 40 b for the bit line and storage node contacts. A transfer gate 14 is formed at the fact of a semiconductor region 30. The semiconductor 30 includes a bit line contact region 44 and storage node contact region adjacent opposite edges of the transfer gate 14. Transfer gate 14 is surrounded with an insulating material 34/38. A conductive layer 40 is formed over the transfer gate 14, over the bit line contact region 44 and over the storage node contact region. This conductive layer 40 is then etched so that a first portion 40 a of the conductive layer 40 provides an electrical contact to the bit line contact region 44 and a second portion 40 b of the conductive layer 40 provides an electrical contact to the storage node contact region. The bit line 18 and storage node electrode 22 can then be formed in electrical contact with the first and second portions of the conductive layer 40 a and 40 b, respectively.
Description
- This invention relates generally to semiconductor devices and specifically to a method of forming a memory cell with an alternate self-aligned contact implementation.
- As DRAMS increase in memory cell density, there is a continuous challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One way of increasing cell capacitance is to through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors.
- To increase feature density and thus decrease memory cell size, Self Aligned Contacts (SAC) have been employed. The self aligned nature is accomplished by definition (patterning and etching) of a contact whose electrical contact (active) area is defined by pre-existing features and not the patterned contact area. Even when utilizing self aligned processes, the feature size is sufficiently small that complex photolithography processes (e.g., phase shifted reticules) are required for patterning and alignment is critical.
- In some processes for forming DRAM devices, the active contact area is defined by removing (etching) the contact oxide defined by the pattern (mask) and is self-aligned to some particular structures (e.g., the transfer gate and field oxide region). To provide insulation and selectivity for the contact oxide to the self align structures an alternate dielectric material (e.g., silicon nitride=SiN4) is used to encapsulate the transfer gate. The dielectric exists on the top (defined at the previous gate patterning operation) and sides) formed at the previous sidewall formation) of the transfer gate. The active device area (moat), a silicon region, is defined by the isolation oxide (field oxide). The implementation of this technique utilizes differences in etch rates of dissimilar materials (etch selectivity) to provide final film thickness and over-etch process margin.
- The utilization of the silicon nitride to encapsulate the transfer gate sidewall material increases the parasitic capacitance to adjacent conductor lines due to the high dielectric constant of the material. This type of approach has high process complexity and low process margin. Both problems are the result of the small contact size and inadequate selectivity (ratio of silicon dioxide etch rate to silicon nitride etch rate) during silicon dioxide etching of the contact with the available etch technology (tools and processes).
- The present invention provides a method of forming a memory cell with a new approach for self-aligned contacts, which overcomes many of the problems exhibited by the prior art. For example, the present invention decreases process complexity, decreases parasitic capacitance to adjacent electrical conductors (e.g., DRAM word line), increases patterning process margin and increases etching process margin by utilizing fewer process steps, lower dielectric constant materials, relaxing minimum feature size at the contact patterning and by elimination of the need for high silicon dioxide (SiO2) to silicon nitride (SiN4) selectively at contact etching. Aspects of the invention will have specific application in 64 Meg and larger DRAM process flows and beyond.
- The present invention implements self aligned electrical connections without hole (contact) pattern definition. Planar conductive (polysilicon) and insulating (silicon dioxide and silicon nitride) films are used to enable the use of high selectivity etch processes for stacked memory structure cell definition.
- In one embodiment, the present invention provides a method of forming a dynamic random access memory device, which utilizes self-aligned contact pads for the bit line and storage node contacts. A transfer gate is formed at the face of a semiconductor region. The semiconductor region includes a bit line contact region and a storage node contact region at opposite edges of the transfer gate. The transfer gate is surrounded with an insulating material, preferably silicon dioxide. A conductive layer is formed over the transfer gate, over the bit line contact region and over the storage node contact region. This conductive layer is then etched so that a first portion of the conductive layer provides an electrical contact to the bit line contact region and a second portion of the conductive layer provides an electrical contract to the storage node contact region. The bit line and storage nodes can then be formed in electrical contact with the first and second portions of the conductive layer, respectively.
- Concentrating on another aspect of the present invention, first and second transfer gates are formed at the face of a semiconductor region. The semiconductor region includes a bit line contact region located between the first an second transfer gates. As before, the transfer gate is surrounded with an insulating material such as silicon dioxide.
- A conductive layer, preferably polysilicon, is formed over the transfer gate, over the bit line contact region and over the storage node contact region. A masking layer, preferably silicon dioxide, is then formed over the conductive layer. A contact window is then formed by removing a portion of the masking layer so as to expose a portion of the conductive layer over the bit line contact regions and over portions of the first and second transfer gates which are adjacent to the bit line contract region.
- A bit line layer(s) can then be formed over the masking layer and the exposed portion of the conductive layer. A bit line can then be formed by patterning and etching the bit line layer. This patterning and etching step also exposes a portion of the conductive layer between the masking layer and the bit line. The exposed portion of the conductive layer can then be removed using the masking layer as a mask. A storage node electrode can then be formed in electrical contact with a portion of the conductive layer, which overlies the storage node contact region.
- The method of the present invention can be used to fabricate a novel memory device. This device includes at least one transfer gate formed in an active region of a semiconductor device. The transfer gate is spaced from a field oxide region by a contact region within the active region. A top surface insulator is disposed along the top surface of the transfer gate and is formed from a first material (e.g., an oxide). A sidewall insulator is disposed along the sidewall of the transfer gate and is formed from a second material (e.g., an oxide). A conductive pad (e.g., polysilicon) extends from over a portion of the field oxide region to over a portion of the top surface insulator. This conductive pad abuts the contact region of the active area. A storage node conductor, which serves as one plate of a capacitor, abuts the conductive pad.
- In another aspect, a novel memory device includes first and second transfer gates. Both gates have a top surface insulator and a sidewall insulator. The top surface insulator a sidewall insulator are formed from different materials. A conductive pad extends over a portion of the first top surface insulator, the first sidewall insulator, the contact region within the active area, the second sidewall insulator, and a portion of the second top surface insulator. The conductive pad abuts the contact region of the active area. A bit line conductor comprises a bit line within a memory array.
- The present invention has a number of advantages over prior art processes. First, process complexity is reduced by the elimination of two etches, two polysilicon depositions, one silicon dioxide deposition and one silicon nitride deposition as compared with other processes. In addition, the contact etch margin is improved-by the elimination of special high selectivity processes. Only industry standard etch processes are required to implement the poly pad self aligned contact process. The industry standard interconnect contact etch process selectivity is sufficient to provide over etch margin.
- This processing approach also reduces word line (transfer gate) parasitic capacitance by utilization of silicon dioxide rather than silicon nitride as the masking and sidewall material.
- Fourth, this processing approach provides an opportunity to improve the average and standard deviation of the DRAM device pause by elimination of one of the known causes of pause degradation. The process also provides an opportunity to perform special pause improvement process steps prior to sealing the single crystal silicon (moat) regions. Pause degradation is known to be due to silicon lattice damage and other lattice disruption. Since no contact etching comes in contact with the moat regions the normal degradation due to this process is eliminated.
- Using the preferred embodiment of the present invention, oversized bit line contacts and undersized bit line are used. These elements in the contact region are sized for the proven production device design (layout) and Design Registration Accuracy (DRA) capability inherent in the present pattern and etch tool set. With an alternate layout the cell size can be decreased with the current DRA capability. As the DRA capability is improved the cell size can be decreased.
- It should also be noted that no changes to the standard ion implantation strategy are needed. All diffused regions are defined prior to the application of the polysilicon pad. Finally, since the polysilicon pad is applied after all ion implantation processes, the moat sealing and polysilicon landing pad formation can be integrated into the periphery circuit processing without other process modifications. The polysilicon pad is a satisfactory structure for interconnect contact connection after the cell processing.
- The example embodiment of the new SAC structure uses a 2 transistor cell with common active region (Bit line contact) a separate storage node contacts. This invention can be equally implemented in a single transistor structure.
- The above features of the present invention will be more clearly understood from consideration of the following descriptions in connection with accompanying drawings in which:
- FIG. 1a is a cross-sectional view of a prior art DRAM device;
- FIG. 1b is a schematic diagram of the device of FIG. 1a;
- FIG. 2a is a schematic diagram of an array of DRAM cells;
- FIGS. 2b-2 c are block diagrams of two embodiment DRAM devices;
- FIGS.3-12 are cross-sectional views of a device after various process steps of the present invention;
- FIGS.13-15 are cross-sectional views of a device after various process steps of an alternate embodiment of the present invention; and
- FIGS.16-18 are cross-sectional views of a device after various process steps of a second alternate embodiment of the present invention; and
- FIGS.19-35 show further embodiments.
- The making and use of the various embodiments are discussed below in detail. However, it should be appreciated that the present invention provides many applicable inventive concepts, which can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
- The present invention relates to a method for forming a dynamic random access memory (DRAM) cell. FIG. 1a illustrates two prior art DRAM cells, each of which includes a
capacitor 12 coupled in series with atransfer transistor 10. FIG. 1b is a schematic diagram of the DRAM cells of FIG. 1a. - Referring now to FIGS. 1a and 1 b together, each DRAM cell includes a
pass transistor 10 coupled in series with acapacitor 12. Thegate 14 ofpass transistor 10 comprises one of the word lines WL of the memory array. (A memory array will be described in more detail with respect to FIG. 2a). A shared source/drain region 16 of eachpass transistor 10 is coupled tobit line 18. The other source/drain region 20 is coupled to thestorage node electrode 22 ofcapacitor 12.Capacitor 12 further includesdielectric layer 24 andcell plate 26. - A simplified schematic diagram of a DRAM array is illustrated in FIG. 2a. As shown, a plurality of memory cells can be formed in an array of rows and columns. FIG. 2a illustrates only six bit lines BL and for word lines WL in what in actuality would likely be a much larger array. The pass transistor Q of each memory cells has a gate G coupled to a word line WL and a source/drain region BLC (for bit line contact) coupled to a bit line BL. The transfer gate G of one pass transistor Q will be electrically coupled to the word line WL for a number of other pass transistors.
- FIG. 2a also illustrates some of the peripheral circuitry, which would be included in a memory array. For example, each pair of bit lines BL and BL (bar) is coupled to a sense amplifier SA. The bit lines BL and BI (bar) are also coupled to input/output lines I/O and I/O (bar) through select transistors Y0-Y2. Other peripheral circuitry such as the row decoders, column decoders, address buffers, I/O buffers and so on is not illustrated here. For the purpose of this invention, the memory cell and fabrication method area independent of the memory architecture.
- As an example, the memory array can be designed as an asynchronous memory or as a synchronous memory. A synchronous memory can be timed with an internal clock (not shown) or an external clock (not shown). The device can have a single external data terminal or multiple external data terminals (i.e., wide word). The array can include a total of 4 megabits, 16 megabits, 64 megabits, 256 megabits, one gigabit or more.
- A simplified block diagram of a memory device is shown in FIG. 2b. The internal device circuitry includes an array and peripheral circuitry. The array may be divided into a number of blocks depending upon the device architecture. Sense amplifiers may be interleaved within the array blocks.
- Several external terminals are illustrated in FIG. 2b. Address terminals A0, A1, . . . , An are provided for receiving row and column addresses. These terminals may be multiplexed (i.e., a first address is applied at a first time and a second address applied at a second time). A single data terminal D is also illustrated. This terminal may comprise an input, an output or an input/output. Other data terminals may also be included. For example, a wide word device will have multiple data terminals. In general, these terminals are provided for receiving input signals from circuitry (not shown) external of the array and for providing output signals to circuitry (not shown) external of the array.
- FIG. 2b also illustrates a number of control/status signals. These signals are used to operate the memory device. For example, an asynchronous memory device may be operated by applying chip select, row address strobe and column address strobe signals. Other signals may indicate whether a read or write operation is being performed. In a synchronous device, one of the control signals may be a clock signal. Status signals may provide information about the device to the external system. For example, the device may include a signal indicating whether a refresh operation is taking place or which portion of the array is being accessed.
- A memory array of the present invention could also be embedded in a larger integrated circuit device. An embedded memory is a memory array and its associated control circuit on the same integrated circuit as a substantial amount of logic. FIG. 5c has been included to illustrate a simple block diagram of an embedded memory. In this example, a DRAM array is included along with a processor (e.g., microprocessor, digital signal processor, specialty processor, microcontroller), another memory array (e.g., SRAM, non-volatile memory such as EPROM, EEPROM, flash memory, PROM, ROM, another DRAM array) and other logic circuitry. These particular blocks have been chosen to illustrate the wide variety of other logic, which could be included. Any combination of the devices could be included.
- As related to a DRAM as shown in FIG. 1a, the present invention pertains to a novel method for forming self-aligned contacts. A first embodiment of the present invention will be described with respect to FIGS. 3-12.
- Referring now to FIG. 3, a
semiconductor region 30 is provided. In the preferred embodiment,semiconductor region 30 comprises a p-doped silicon substrate. Other semiconductor regions could also be used. For example, n-doped silicon substrate can be used. While illustrated as a substrate,semiconductor region 30 could alternatively be an epitaxially grown layer, a region within a region such as a well, a tank or a tub, a semiconductor layer over an insulating layer (e.g., S.O.I.) or just about any other semiconductor region. -
Field isolation regions 32 are also illustrated in FIG. 3. In the preferred embodiment,field oxide regions 32 are formed by the known LOCOS (local oxidation of silicon) process. In the process, a thin nitride layer (not shown) is blanket deposited over the substrate and then patterned to expose the areas where thefield oxide 32 will be formed. These exposed regions are then oxidized. In alternative embodiments which are illustrated, other isolation techniques such as trench isolation or field plate isolation can be used. - Referring to FIG. 4, transfer gates (word lines)14 are formed. In this embodiment, each transfer gate is a conductor formed by a layer of doped
polysilicon 14 a with a layer oftungsten silicide 14 b overlying to lower the resistance.Transfer gate 14 is separated fromsubstrate 30 by gate insulating layer (e.g., oxide, nitride, oxide-nitride stack) 36. In other embodiments,transfer gate 14 can be formed from other materials such a titanium silicide/poly, moly disilicide/poly, doped poly only, or tungsten/poly films could be used. For the sake of simplicity, the figures only show the word lines 14 for two pass transistors. It is noted, however, that word lines for memory cells not illustrated would also be formed simultaneously (see FIG. 1a). An insulatinglayer 34, preferably an oxide, is formed over eachtransfer gate 14. - In the preferred embodiment,
transfer gates 14 are formed by sequentially depositing layers of polysilicon, tungsten silicide and then the insulator. These layers are then patterned using standard photolithography and etched. - After definition of the moat (active device area) and the transfer gate14(cell word line), a low dielectric constant
silicon dioxide sidewall 38 is applied to transfergate 14. This step is illustrated in FIG. 5. In other embodiments, a different material can be used forsidewall 38. For example,nitride sidewall regions 38 are envisioned. - The sidewall regions can be formed by blanket depositing an insulating layer such as silicon dioxide over the device. The layer can be anisotropically etched so that
sidewall insulating regions 38 remain.Sidewall insulating region 38 along with insulatinglayer 34 will surroundtransfer gate 14. - Referring now to FIG. 6, a common
conductive layer 40 is formed over the exposed moat regions and overlaps ontotransfer gate 14 andfield oxide regions 32. In the preferred embodiment,conductive layer 40 comprises doped polysilicon but other materials could alternatively be used. -
Masking layer 42 is formed over theconductive layer 40. In the preferred embodiment, this step entails depositing alayer 42 of silicon dioxide. In other embodiments, other materials could alternatively be used. - Referring now to FIG. 7a, a portion of masking
layer 42 is removed so as to expose a portion ofconductive layer 40 over a bitline contact region 44 withinsubstrate 30. This step will also expose portions of both of thetransfer gates 14 which are adjacent to the bitline contact region 44. Thisoversized contact window 41 is opened for the bit line contact (formation ofbit line 18 will be illustrated in FIG. 8a). A plan view of the device is shown in FIG. 7b. - The contact window is an oversized window when it is patterned without using the minimum photolithographic distance. For the purpose of this patent, the minimum photlithographic distance is the smallest dimension that can be patterned using a given photolithography system. Since the contact window overlaps
adjacent transfer gates 14, there is no need to be confined to the photolithographic minimum distance. This capability provides an advantage since very precise patterning is not necessary. This capability also provides a further advantage in that the process is scalable. As future generations attempt to pack more memory cells into a smaller area, the contact window can be scaled to smaller dimensions. In this manner, higher density memories can be formed using the same processing steps, possibly by patterningcontact window 41 at a photolithographic minimum distance. - Referring now to FIG. 8a,
bit line 18 is formed. After deposition of the bit line film(s) (e.g.,polysilicon 18 a andtungsten silicide 18 b),bit line 18 is patterned and etched. The bit line pattern is undersized in the contact region to allow unwanted portions of theconductive layer 40 to be removed. In other words, the bit line layer is patterned and etched to expose a portion ofconductive layer 40 betweenmasking layer 42 and bitline 18. The exposed portion ofconductive layer 40 is then removed usingmasking layer 42 as a mask (along with a patterned photoresist layer overbit line 18, which is not illustrated). This way the bitline contact portion 40 a ofconductive layer 40 is electrically isolated form the remainder ofconductive layer 40. - FIG. 8b illustrates a plan view of the device. Several memory cells are included in this view. As illustrated in this figure, the
contacts - Referring to FIG. 9, an insulating
layer 46/48/50 is formed over the device. In the preferred embodiment, a multilayer insulator is formed. First, a depositedoxide layer 46 which can be formed by the decomposition of tetraethyloxysilane (TEOS). Next anitride layer 48 is deposited. Then a planarizing film such as BPSG (borophosphosilicate glass)layer 50 is formed. - Referring next to FIG. 10, storage node contact holes are opened. A photoresist layer (not shown) is applied to the device and patterned to expose a portion of the
BPSG layer 50 over the storage node contact region. Themultilayer insulator 46/48/50 is then etched to expose a storagenode contact portion 40 b ofconductive layer 40. - One method of forming
storage node 22 is illustrated in FIGS. 11 and 12. Referring first to FIG. 11, aconductive layer 54 such as doped polysilicon is formed over the device. Theconductive layer 54 abuts thestorage contact portion 40 b ofconductive layer 40. Next,sacrificial regions 56 are formed over the storage node contact. Anotherconductive layer 58, preferably of the same material asconductive layer 54, is formed oversacrificial region 56 andconductive layer 54. - An anisotropic etch can then be performed. This etch will remove the exposed portions of
layers sacrificial region 56. Oncesacrificial region 56 is removed, as shown in FIG. 12, a crown-shapedstorage node electrode 22 remains.Dielectric layer 24 andcell plate conductor 26 can then be formed overstorage node conductor 22. As examples,dielectric layer 24 can be an oxide/nitride/oxide layer or a layer of higher dielectric constant material such as tantalum pentoxide, barium strontium titanate, or lead zirconium titanate. - The memory cell will be completed by forming a
capacitor dielectric 24 and acell plate electrode 26 over thestorage node 22. Other steps would also be performed but, for the sake of simplicity, will not be illustrated here. For example, several layers of insulators and metal interconnects could be formed in order to properly interconnect the various circuits within the memory device. The device will also be tested and packaged. Steps such as these are known in the art and need not be described here. - Several modifications of the present invention are possible. FIGS.13-15 illustrate one such modification. The cross-sectional view of FIG. 13 is taken after additional processing is performed on the structure of FIG. 8a. Specifically, a
sidewall 60 is formed along sidewalls ofbit line 18. The sidewall is preferably formed from an oxide material. Theoxide sidewall 60 is formed by depositing an oxide layer and then etching back. The etch back step will also clear theoxide layer 42 over thestorage node pad 40 b. - During the
sidewall 60 formation, an insulatinglayer 62 will be formed over thebit line 18. This insulatinglayer 62 is preferably a low dielectric constant material such as an oxide. While nitride could alternatively be used, this material is not preferred since it will increase the capacitance betweenbit line 18 and other conductors (not shown). - The storage
node contact pad 40 b is opened without a pattern step and then the storage node polysilicon (or other conductor)layer 62 is deposited as shown in FIG. 14.Sacrificial regions 66 are then formed over theconductive layer 62. Theseregions 66 were formed by depositing a thick planar material (e.g., oxide BPSG) and selectively etching. It is noted that unlikesacrificial region 56 of FIG. 11,sacrificial region 66 is patterned to expose rather than cover the storage node contact areas. - Another
conductive layer 68, preferably of the same material asconductive layer 64, is formed oversacrificial region 66 andconductive layer 64. As the previously described embodiment, an anisotropic etch can then be performed. This etch will remove the exposed portions oflayers sacrificial region 66. Oncesacrificial region 66 is removed, a crown-shapedstorage node electrode 22 remains. This structure is shown in FIG. 15. - Another embodiment is illustrated in FIGS.16-18 showing that some of the process steps could be modified yet again. For example, after the
bit line sidewall 60 etch (FIG. 13), anitride layer 70 could be deposited as shown in FIG. 16. Alayer 72 of BPSG could then be deposited and etched back in order to planarize the upper surface. TheBPSG 72 could then be patterned to expose the storagenode contact pad 40 b. This etch would be performed in two steps. First, there is an oxide etch which stops on nitride followed by nitride etch which stops on oxide. After theoxide 72 andnitride 70 are etched, thepad 40 b cleaned. - Referring next to FIG. 17,
polysilicon layer 74 could be deposited. AnotherBPSG layer 76 is then deposited and etched back to expose thepolysilicon layer 74. The exposed portions ofpolysilicon 74 are then etched as shown in FIG. 18. During this etching step, thelayer 76 protects the pad region. This polysilicon etch is preferably an end point etch followed by a deglaze to remove any thin oxide layers. - FIG. 18 illustrates the memory device after removal of the
layers regions 72 an 76 are removed with thenitride layer 70 overbit line 18 serving as an etch stop. This etch stop layer will protect thebit line 18. Accordingly, the etch should be highly selective to oxide. - To complete the memory cell, a capacitor dielectric (not shown) and cell plate electrode (not shown) are formed over the
storage node 22. As before, other processing steps will be performed to complete the memory device. - FIGS.19-29 illustrate another embodiment. In particular, FIG. 19 shows filed
isolation 32, FIG. 20 shows wordlines in cross sectional view made ofnitride 34 ontungsten silicide 14 b onpolysilicon 14 a ongate oxide 36. FIG. 21 illustrates sidewall oxide formed by conformal deposition and anisotropic etch. FIG. 22 shows depositedpolysilicon 40, which has been patterned to remove the portion away from the moats and covered with depositedoxide 42. - FIG. 23 shows
oxide 42 patterned and etched by an oversize bit line contact pattern to exposepolysilicon 40 inopening 41. Then blanket deposit layers of polysilicon (40 nm), tungsten silicide (120 nm), and oxide (100 nm). Next, pattern to define the bit lines and etch. The etch is multistep and the oxide (plus BARC if used) etch (fluorine-based plasma) stops on the tungsten silicide. The tungsten silicide plus polysilicon etch (chlorine-based plasma) stops on thenitride 34. Lastly, oxidize the exposed surfaces of the polysilicon and tungsten silicide; see FIG. 24, which showstungsten silicide 18 b onpolysilicon 18 a, which is onoriginal polysilicon 40. - FIG. 25 shows the result of a blanket oxide deposition followed by anisotropic etching to form
sidewall oxide 46 on the bit line plussidewall oxide 47 on the portions ofpolysilicon 40 away from the bit lines. Note that the oxide on the surface of thisportion polysilicon 40 is removed because it was not thick enough to survive the anisotropic etching. - Next, deposit 25
nm nitride 55 and 550nm BPSG 56. Etch back the BPSG for planarization and pattern etch to foropenings 71 for eventual capacitors; see FIG. 26. Then etch the exposed portion ofnitride 55 and deposit 100 nmthick polysilicon 72. Then deposit 400 nm ofBPSG 57 and etch back; this leavesBPSG 72 in the openings as illustrated by FIG. 27. - Etch the exposed portion of
polysilicon 72 to uncoverBPSG 56; and then wet etch the BPSG 56-57. This leavespolysilicon 72 in the shape of a crown; see FIG. 28. These polysilicon crowns will be the bottom electrodes for the capacitors. Lastly, apply capacitor dielectric and top electrode polysilicon and etch the portion outside of the memory cell array. Then apply planarizing BPSG; see FIG. 29. - FIGS.30-35 a variation of the preferred embodiment of FIGS. 11-12. In particular, start with the structure of the FIG. 10 and
blanket deposit polysilicon 54; see FIG. 30. Next,deposit BPSG 56 and pattern and etch down to the polysilicon to form openings at the storage node locations; see FIG. 31. Then depositpolysilicon 58 and conformal oxide. Anisotropically etch back the oxide to formoxide sidewalls 60; see FIG. 32. - Repeat the polysilicon with oxide sidewall to form a crown with interior walls. In particular,
deposit polysilicon 62 and conformal oxide, which is anisotropically etched back to formoxide sidewall 64. Then deposit anotherpolysilicon layer 66; see FIG. 34. Lastly, do a planarization, such as CMP, or a polysilicon etch back to remove the horizontal top portions ofpolysilicon polysilicon 58 withinterior polysilicon walls
Claims (29)
1. A method of forming a memory cell, the method comprising the steps of:
Forming a transfer gate at the face of a semiconductor region, the semiconductor region including a bit line contact region and storage node contact region wherein the transfer gate includes a first edge adjacent the bit line contact region and a second edge adjacent the storage node contact region;
surrounding the transfer gate with an insulating material;
forming a conductive layer over the transfer gate, over the bit line contact region and over the storage node contact region;
forming a masking layer over the conductive layer;
etching the masking layer to form a bit line contact window over a portion of the conductive layer;
etching the conductive layer such that a portion of the conductive layer provides an electrical contact to the bit line contact region and a second portion of the conductive layer provides an electrical contact to the storage node contact region;
forming a bit line electrically coupled to the first portion of the conductive layer; and
forming a storage node electrode electrically coupled to the second portion of the conductive layer.
2. The method of claim 1 wherein the step of forming a transfer gate comprises depositing a conductive layer, depositing an insulating layer and patterning and etching the conductive layer and the insulating layer.
3. The method of claim 2 wherein the conductive layer comprises a multilayer conductor.
4. The method of claim 3 wherein the step of depositing a conductive layer comprises the steps of depositing a polysilicon layer and then forming a silicide layer over the polysilicon layer.
5. The method of claim 2 wherein the insulating layer comprises a nitride layer.
6. The method of claim 2 wherein the step of surrounding the transfer gate comprises said step of depositing an insulating layer and further comprises the step of forming a sidewall insulator adjacent sidewalls of the transfer gate.
7. The method of claim 6 wherein the sidewall insulator comprises an oxide, sidewall insulator.
8. The method of claim 1 wherein the step of forming a conductive layer comprises the step of depositing a polysilicon layer.
9. The method of claim 1 wherein the conductive layer physically abuts the bit line contact region and the storage node contact region.
10. A method of forming a memory device, the method comprising the steps of:
forming first and second transfer gates at the face of a semiconductor region, the semiconductor region including a bit line contact region located between the first and second transfer gates, a storage node contact region located adjacent the first transfer gate, and a second storage node contact region located adjacent the second transfer gate;
surrounding the transfer gate with an insulating material;
forming a conductive layer over the transfer gate, over the bit line contact region and over the storage node contact region;
forming a masking layer over the conductive layer;
removing a portion of the masking layer so as to expose a portion of the conductive layer over the bit line contact regions and over portions of the first and second transfer gates which are adjacent to the bit line contact region;
forming a bit line layer over the masking layer and the exposed portion of the conductive layer;
forming a bit line by patterning and etching the bit line layer, the patterning and etching step exposing a portion of the conductive layer between the masking layer and the bit line; and
removing the exposed portion of the conductive layer using the masking layer as a mask.
11. The method of claim 10 and further comprising the steps of:
Removing a portion of the masking layer over the first storage node contact region; and
forming a storage node electrode of a storage capacitor in electrical contact with the first storage node contact region.
12. The method of claim 10 and further comprising the step of forming a sidewall insulator along sidewalls of the bit line.
13. A method of forming a memory device, the method comprising the steps of;
forming a conductive gate layer over a semiconductor region, the conductive layer being electrically insulated from the semiconductor region;
forming oxide sidewalls along sidewalls of the gate;
forming a polysilicon layer over the gate and abutting a bit line contact portion of the semiconductor region adjacent a first edge of the gate, the polysilicon layer also abutting a storage node contact portion of the semiconductor region adjacent an opposite edge of the gate;
forming an oxide layer over the polysilicon layer;
forming a bit line contact window by removing a portion of the oxide layer to expose a bit line contact portion of the polysilicon layer over the bit line contact portion of the semiconductor region;
forming a bit line conductor in electrical contact with the exposes portion of the polysilicon layer, the step of forming a bit line conductor including an etching step which electrically isolates bit line contact portion of the polysilicon layer from the remainder of the polysilicon layer;
forming a storage node conductor in electrical contact with a portion of the polysilicon layer over the storage node contact region of the semiconductor region;
forming a dielectric over the storage node conductor; and
forming a cell plate conductor over the dielectric.
14. The method of claim 12 and further comprising the step of forming an oxide sidewall along sidewalls of the bit line conductor.
15. The method of claim 13 wherein the storage node conductor is formed so as to about the oxide sidewall along the bit line conductor.
16. A memory device comprising;
an active region disposed in a semiconductor region, the active region surrounded by a field oxide region,
a transfer gate over an upper surface of the active region, the transfer gate including a top surface and sidewall, the transfer gate spaced from the field oxide region by a contact region within the active region,
a top surface insulator disposed along the top surface of the transfer gate, the top surface insulator comprising a first material;
a sidewall insulator disposed along the sidewall of the transfer gate, the sidewall insulator comprising a second material which is different than the first material;
a conductive pad extending from over a portion of the field oxide region to over a portion of the insulator disposed along the top surface of the transfer gate, the conductive pad abutting the contact region of the active area; and
a storage node conductor abutting the conductive pad, the storage node conductor comprising one plate of a capacitor.
17. The device of claim 15 wherein the storage node conductor is formed in the shape of a crown cell conductor.
18. The device of claim 15 wherein the conductive pad comprises a polysilicon pad.
19. The device of claim 15 wherein the conductive pad abuts the sidewall insulator.
20. The device of claim 15 wherein the storage node conductor overlies a portion of the field oxide, the storage node conductor extending along the field oxide beyond the conductive pad.
21. The device of claim 15 and further comprising a bit line conductor electrically coupled to a portion of the active area, the storage node conductor overlying a portion of the bit line conductor and electrically insulated therefrom.
22. The device of claim 20 and further comprising a bit line sidewall region formed along sidewalls of the bit line conductor.
23. The device of claim 16 wherein the top surface insulator comprises a nitride material and the sidewall insulator comprises an oxide material.
24. A memory device comprising;
a first transfer gate disposed over an upper surface of a semiconductor region active region, the first transfer gate including a top surface and sidewall,
a first top surface insulator disposed along the top surface of the first transfer gate, the first top surface insulator comprising a first material;
a first sidewall insulator disposed along the sidewall of the first transfer gate, the first sidewall insulator comprising a second material which is different than the first material;
a second transfer gate disposed over the upper surface of the semiconductor region, the second transfer gate including a top surface and a sidewall, the second transfer gate spaced from the first transfer gate by a contact region within the active region;
a second top surface insulator disposed along the top surface of the second transfer gate, the second top surface insulator comprising the first material;
a second sidewall insulator disposed along the sidewall of the second transfer gate, the second sidewall insulator comprising the second material;
a conductive pad extending over a portion of the first top surface insulator, the first sidewall insulator, the contact region within the active area, the second sidewall insulator, and a portion of the second top surface insulator, the conductive pad abutting the contact region of the active area; and
a bit line conductor electrically coupled to the conductive pad, the bit line conductor comprising a bit line within a memory array.
25. The device of claim 24 wherein the conductive pad comprises a polysilicon pad.
26. The device of claim 24 wherein the conductive pad abuts the sidewall insulator.
27. The device of claim 24 wherein the conductive pad is aligned with the bit line conductor.
28. The device of claim 24 and further comprising a bit line sidewall region formed along sidewalls of the bit line conductor.
29. The device of claim 24 wherein the first material comprises a nitride material and the second material comprises an oxide material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/002,903 US20020053694A1 (en) | 1998-06-10 | 2001-11-01 | Method of forming a memory cell with self-aligned contacts |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/096,012 US6373088B2 (en) | 1997-06-16 | 1998-06-10 | Edge stress reduction by noncoincident layers |
US10237998P | 1998-09-29 | 1998-09-29 | |
US09/405,271 US6352890B1 (en) | 1998-09-29 | 1999-09-23 | Method of forming a memory cell with self-aligned contacts |
US10/002,903 US20020053694A1 (en) | 1998-06-10 | 2001-11-01 | Method of forming a memory cell with self-aligned contacts |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/096,012 Division US6373088B2 (en) | 1997-06-16 | 1998-06-10 | Edge stress reduction by noncoincident layers |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020053694A1 true US20020053694A1 (en) | 2002-05-09 |
Family
ID=27378044
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/002,903 Abandoned US20020053694A1 (en) | 1998-06-10 | 2001-11-01 | Method of forming a memory cell with self-aligned contacts |
US10/087,486 Expired - Lifetime US6615391B2 (en) | 1998-06-10 | 2002-03-01 | Current controlled multi-state parallel test for semiconductor device |
US10/121,109 Expired - Lifetime US6627558B2 (en) | 1998-06-10 | 2002-04-10 | Apparatus and method for selectively restricting process fluid flow in semiconductor processing |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/087,486 Expired - Lifetime US6615391B2 (en) | 1998-06-10 | 2002-03-01 | Current controlled multi-state parallel test for semiconductor device |
US10/121,109 Expired - Lifetime US6627558B2 (en) | 1998-06-10 | 2002-04-10 | Apparatus and method for selectively restricting process fluid flow in semiconductor processing |
Country Status (1)
Country | Link |
---|---|
US (3) | US20020053694A1 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030049936A1 (en) * | 2001-09-07 | 2003-03-13 | Samsung Electronics Co., Ltd. | Semiconductor device having local interconnection layer and method for manufacturing the same |
US20030061894A1 (en) * | 2001-09-28 | 2003-04-03 | Yoshiro Itagaki | Joystick |
US6696339B1 (en) | 2002-08-21 | 2004-02-24 | Micron Technology, Inc. | Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices |
US20150162913A1 (en) * | 2013-12-10 | 2015-06-11 | Imec Vzw | Filed programmable gate array device with programmable interconnect in back end of line portion of the device |
US20160149035A1 (en) * | 2012-11-23 | 2016-05-26 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor device and method of fabricating same |
US20200020695A1 (en) * | 2018-07-11 | 2020-01-16 | International Business Machines Corporation | Transistor and capacitor structures for analog memory neural network |
US11450668B2 (en) * | 2018-08-10 | 2022-09-20 | Micron Technology, Inc. | Integrated memory comprising secondary access devices between digit lines and primary access devices |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6932871B2 (en) | 2002-04-16 | 2005-08-23 | Applied Materials, Inc. | Multi-station deposition apparatus and method |
JP2003317499A (en) * | 2002-04-26 | 2003-11-07 | Mitsubishi Electric Corp | Semiconductor memory device and memory system using the same |
US6813748B2 (en) * | 2002-09-24 | 2004-11-02 | Infineon Technologies Ag | System and method for enabling a vendor mode on an integrated circuit |
JP2006515464A (en) * | 2002-12-11 | 2006-05-25 | ピー・デイ・エフ ソリユーシヨンズ インコーポレイテツド | System and method for fast positioning of electrical faults on integrated circuits |
US9495356B2 (en) * | 2006-03-30 | 2016-11-15 | International Business Machines Corporation | Automated interactive visual mapping utility and method for validation and storage of XML data |
KR101039859B1 (en) * | 2009-07-03 | 2011-06-09 | 주식회사 하이닉스반도체 | Semiconductor memory device |
US7972899B2 (en) * | 2009-07-30 | 2011-07-05 | Sisom Thin Films Llc | Method for fabricating copper-containing ternary and quaternary chalcogenide thin films |
US8381144B2 (en) * | 2010-03-03 | 2013-02-19 | Qualcomm Incorporated | System and method of test mode gate operation |
US8610451B2 (en) | 2010-11-16 | 2013-12-17 | International Business Machines Corporation | Post silicide testing for replacement high-k metal gate technologies |
WO2018075972A1 (en) | 2016-10-21 | 2018-04-26 | Quantumscape Corporation | Electrolyte separators including lithium borohydride and composite electrolyte separators of lithium-stuffed garnet and lithium borohydride |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4340462A (en) | 1981-02-13 | 1982-07-20 | Lam Research Corporation | Adjustable electrode plasma processing chamber |
JPS62250593A (en) | 1986-04-23 | 1987-10-31 | Hitachi Ltd | Dynamic ram |
US5091217A (en) * | 1989-05-22 | 1992-02-25 | Advanced Semiconductor Materials, Inc. | Method for processing wafers in a multi station common chamber reactor |
TW200603B (en) | 1991-04-11 | 1993-02-21 | Hitachi Seisakusyo Kk | Semiconductor memory device |
US5286297A (en) | 1992-06-24 | 1994-02-15 | Texas Instruments Incorporated | Multi-electrode plasma processing apparatus |
US5252178A (en) | 1992-06-24 | 1993-10-12 | Texas Instruments Incorporated | Multi-zone plasma processing method and apparatus |
US5453124A (en) | 1992-12-30 | 1995-09-26 | Texas Instruments Incorporated | Programmable multizone gas injector for single-wafer semiconductor processing equipment |
US5379302A (en) * | 1993-04-02 | 1995-01-03 | National Semiconductor Corporation | ECL test access port with low power control |
US5864565A (en) * | 1993-06-15 | 1999-01-26 | Micron Technology, Inc. | Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system and method for utilizing the semiconductor integrated circuit |
KR950020993A (en) | 1993-12-22 | 1995-07-26 | 김광호 | Semiconductor manufacturing device |
US6101618A (en) * | 1993-12-22 | 2000-08-08 | Stmicroelectronics, Inc. | Method and device for acquiring redundancy information from a packaged memory chip |
US5950925A (en) | 1996-10-11 | 1999-09-14 | Ebara Corporation | Reactant gas ejector head |
US6303045B1 (en) * | 1997-03-20 | 2001-10-16 | Lam Research Corporation | Methods and apparatus for etching a nitride layer in a variable-gap plasma processing chamber |
US5865984A (en) * | 1997-06-30 | 1999-02-02 | International Business Machines Corporation | Electrochemical etching apparatus and method for spirally etching a workpiece |
US6173673B1 (en) | 1999-03-31 | 2001-01-16 | Tokyo Electron Limited | Method and apparatus for insulating a high power RF electrode through which plasma discharge gases are injected into a processing chamber |
US6206972B1 (en) | 1999-07-08 | 2001-03-27 | Genus, Inc. | Method and apparatus for providing uniform gas delivery to substrates in CVD and PECVD processes |
-
2001
- 2001-11-01 US US10/002,903 patent/US20020053694A1/en not_active Abandoned
-
2002
- 2002-03-01 US US10/087,486 patent/US6615391B2/en not_active Expired - Lifetime
- 2002-04-10 US US10/121,109 patent/US6627558B2/en not_active Expired - Lifetime
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7122850B2 (en) * | 2001-09-07 | 2006-10-17 | Samsung Electronics Co., Ltd. | Semiconductor device having local interconnection layer and etch stopper pattern for preventing leakage of current |
US20030049936A1 (en) * | 2001-09-07 | 2003-03-13 | Samsung Electronics Co., Ltd. | Semiconductor device having local interconnection layer and method for manufacturing the same |
US7704892B2 (en) | 2001-09-07 | 2010-04-27 | Samsung Electronics Co., Ltd. | Semiconductor device having local interconnection layer and etch stopper pattern for preventing leakage of current |
US20070010090A1 (en) * | 2001-09-07 | 2007-01-11 | Dong-Kyun Nam | Semiconductor device having local interconnection layer and etch stopper pattern for preventing leakage of current |
US20030061894A1 (en) * | 2001-09-28 | 2003-04-03 | Yoshiro Itagaki | Joystick |
US20110005070A1 (en) * | 2002-08-21 | 2011-01-13 | Micron Technology, Inc. | Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices |
US8931169B2 (en) | 2002-08-21 | 2015-01-13 | Micron Technology, Inc. | Methods of fabricating components for microelectronic devices |
US20070022601A1 (en) * | 2002-08-21 | 2007-02-01 | Micron Technology, Inc. | Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices |
US20050003610A1 (en) * | 2002-08-21 | 2005-01-06 | Tang Sang Dang | Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices |
US7814650B2 (en) | 2002-08-21 | 2010-10-19 | Micron Technology, Inc. | Process of fabricating microelectronic structures |
US6696339B1 (en) | 2002-08-21 | 2004-02-24 | Micron Technology, Inc. | Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices |
US8234782B2 (en) | 2002-08-21 | 2012-08-07 | Micron Technology, Inc. | Methods of fabricating microelectronic devices |
US7115928B2 (en) | 2002-08-21 | 2006-10-03 | Micron Technology, Inc. | Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices |
US20160149035A1 (en) * | 2012-11-23 | 2016-05-26 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor device and method of fabricating same |
US9653600B2 (en) * | 2012-11-23 | 2017-05-16 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor device and method of fabricating same |
US20150162913A1 (en) * | 2013-12-10 | 2015-06-11 | Imec Vzw | Filed programmable gate array device with programmable interconnect in back end of line portion of the device |
US9553586B2 (en) * | 2013-12-10 | 2017-01-24 | Imec Vzw | Filed programmable gate array device with programmable interconnect in back end of line portion of the device |
US20200020695A1 (en) * | 2018-07-11 | 2020-01-16 | International Business Machines Corporation | Transistor and capacitor structures for analog memory neural network |
US10629601B2 (en) * | 2018-07-11 | 2020-04-21 | International Business Machines Corporation | Transistor and capacitor structures for analog memory neural network |
US10886281B2 (en) * | 2018-07-11 | 2021-01-05 | International Business Machines Corporation | Transistor and capacitor structures for analog memory neural network |
US11450668B2 (en) * | 2018-08-10 | 2022-09-20 | Micron Technology, Inc. | Integrated memory comprising secondary access devices between digit lines and primary access devices |
Also Published As
Publication number | Publication date |
---|---|
US20020080668A1 (en) | 2002-06-27 |
US6627558B2 (en) | 2003-09-30 |
US6615391B2 (en) | 2003-09-02 |
US20020108565A1 (en) | 2002-08-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5554557A (en) | Method for fabricating a stacked capacitor with a self aligned node contact in a memory cell | |
US6617205B1 (en) | Semiconductor storage device and process for manufacturing the same | |
US5168073A (en) | Method for fabricating storage node capacitor having tungsten and etched tin storage node capacitor plate | |
US5712202A (en) | Method for fabricating a multiple walled crown capacitor of a semiconductor device | |
US5192703A (en) | Method of making tungsten contact core stack capacitor | |
US5262662A (en) | Storage node capacitor having tungsten and etched tin storage node capacitor plate | |
US5459345A (en) | Semiconductor device high dielectric capacitor with narrow contact hole | |
US5686337A (en) | Method for fabricating stacked capacitors in a DRAM cell | |
KR100203538B1 (en) | Semiconductor memory device and manufacturing method of the same | |
US6069038A (en) | Method of manufacturing a semiconductor integrated circuit device | |
US20020053694A1 (en) | Method of forming a memory cell with self-aligned contacts | |
US6373090B1 (en) | Scheme of capacitor and bit-line at same level and its fabrication method for 8F2 DRAM cell with minimum bit-line coupling noise | |
US5543345A (en) | Method for fabricating crown capacitors for a dram cell | |
US5225699A (en) | Dram having a large dielectric breakdown voltage between an adjacent conductive layer and a capacitor electrode and method of manufacture thereof | |
KR100863780B1 (en) | Method of producing semiconductor integrated circuit device and semiconductor integrated circuit device | |
US6352890B1 (en) | Method of forming a memory cell with self-aligned contacts | |
US6238961B1 (en) | Semiconductor integrated circuit device and process for manufacturing the same | |
US5536673A (en) | Method for making dynamic random access memory (DRAM) cells having large capacitor electrode plates for increased capacitance | |
US5369048A (en) | Stack capacitor DRAM cell with buried bit-line and method of manufacture | |
US6791137B2 (en) | Semiconductor integrated circuit device and process for manufacturing the same | |
JP2917912B2 (en) | Semiconductor memory device and method of manufacturing the same | |
US6531358B1 (en) | Method of fabricating capacitor-under-bit line (CUB) DRAM | |
US5484744A (en) | Method for fabricating a stacked capacitor for dynamic random access memory cell | |
JP4215711B2 (en) | Semiconductor integrated circuit device and manufacturing method thereof | |
KR20020002339A (en) | Merged capacitor and capacitor contact process for concave shaped stack capacitor drams |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |