US20020084849A1 - Comparator with a large input voltage excursion - Google Patents
Comparator with a large input voltage excursion Download PDFInfo
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- US20020084849A1 US20020084849A1 US10/010,964 US1096401A US2002084849A1 US 20020084849 A1 US20020084849 A1 US 20020084849A1 US 1096401 A US1096401 A US 1096401A US 2002084849 A1 US2002084849 A1 US 2002084849A1
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- comparator
- stage
- transistor
- current source
- differential
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2436—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using a combination of bipolar and field-effect transistors
- H03K5/2445—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using a combination of bipolar and field-effect transistors with at least one differential stage
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The present invention relates to a BICMOS technology comparator including: a first stage with differential inputs capable of operating with input voltages which are, in the common mode, lower than a positive supply potential minus a first threshold voltage, the first stage controlling a first bipolar output transistor; a second stage with differential inputs for operating with input voltages which are, in the common mode, higher than a negative supply potential plus a second threshold voltage, the second stage controlling a second bipolar output transistor and the output transistors being connected in series between two terminals at the positive and negative supply potentials, and a midpoint of their series connection forming an output terminal of the comparator; and circuitry for controlling the differential stages according to the voltages applied on their inputs.
Description
- This application is a continuation of application Ser. No. 09/845,244, filed Apr. 30, 2001, entitled COMPARATOR WITH A LARGE INPUT VOLTAGE EXCURSION, which in turn is a continuation of application Ser. No. 09/631,202, filed Aug. 2, 2000, entitled COMPARATOR WITH A LARGE INPUT VOLTAGE EXCURSION which in turn is a continuation of application Ser. No. 09/057,970, filed Apr. 9, 1998, entitled COMPARATOR WITH A LARGE INPUT VOLTAGE EXCURSION, which prior applications are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a comparator having a large input voltage excursion, that is, the input voltage of the comparator is close to the high and low supply voltages. This type of comparator is generally called a rail-to-rail comparator.
- 2. Discussion of the Related Art
- FIG. 1 shows a first conventional example of such a comparator.
- The comparator is formed of a
differential stage 1, having two positive andnegative input voltages stage 1 controls a transistor Ts mounted in series with acurrent source 5 between two terminals A and M, on which are applied, respectively, high and low supply potentials Vdd and Vss. - In the example shown in FIG. 1,
stage 1 is formed of two P-channel MOS transistors MP1, MP2, the respective gates of which are connected toterminals current source 6, to terminal A. The drains of transistors MP1 and MP2 are respectively connected to the collector of an NPN-type bipolar transistor T1, T2, the emitter of which is connected to terminal M. Transistors T1 and T2 are connected as a current mirror and transistor T1 is diode-connected. Terminal 4 is formed by the drain of transistor MP2, connected to the base of NPN-type transistor Ts. The emitter of transistor Ts is connected to terminal M and its collector is connected to an output terminal S of the comparator connected, viacurrent source 5, to terminal A. - When voltage V+ is lower than voltage V−, the voltage difference ΔV between
terminals current source 5. This voltage drop corresponds, for example if the current sources are realized by means of bipolar transistors, to the collector-emitter drop of a saturating bipolar transistor. If the current sources are formed of MOS transistors, this voltage drop corresponds to a drain-source voltage drop.Current sources - When V+=V−(ΔV=0), current I1 and I2 are balanced and transistor Ts is non-conducting. Terminal S is then substantially at potential Vdd. When voltage V+ is higher than voltage V−(ΔV>0), current I2 is higher than current I1. The current mirror between transistors T1 and T2 maintains the collector currents of transistors T1 and T2 identical. As a result, transistor Ts saturates. Terminal S is then at potential Vss plus the collector-emitter voltage drop of saturating transistor Ts. Thus, the output voltage excursion substantially corresponds to the supply voltage. However, for such an assembly to function, input voltages V+ and V− must respect a common mode constraint, that is, a voltage level constraint (independently from differential voltage ΔV).
- If the potential of one of
terminals current source 6, the comparator no longer operates properly. If V−>Vdd-Vth, transistor MP2 is non-conducting and transistor Ts can receive no base current. Terminal S is thus substantially at potential Vdd, whatever voltage V+. If V+>Vdd-Vth, transistor MP1 is non-conducting and current I1 is zero. Transistors T1 and T2 are thus both non-conducting (they receive no base current). The only case where the result of the comparison is then nevertheless correct is when V−<Vdd-Vth since, assource 6 is not blocked, transistor Ts saturates and Vs≈Vss. - In practice, the comparator of FIG. 1 thus requires input voltages which are, in the common mode, lower by approximately 1 to 1.5 volts than the positive supply voltage.
- FIG. 2 shows a second example of comparator in which the operation of input
differential stage 1′ is limited to input voltages which are, in the common mode, higher than low supply potential Vss, plus a threshold voltage Vth′. Threshold voltage Vth′ corresponds to a threshold voltage Vgsn of an N-channel MOS transistor, plus voltage drop V6′ incurrent source 6′ ofstage 1′. - The assembly of FIG. 2 is similar to that of FIG. 1, but is inverted with respect to terminals A and M and uses N-channel transistors MN1 and MN2 instead of the P-channel MOS transistors of FIG. 1, and PNP-type bipolar transistors T'1, T'2, and T's instead of transistors T1, T2, Ts of the assembly of FIG. 1.
- In the voltage operating range of the comparator of FIG. 2, if ΔV≧0, transistor T's is blocked and Vs≈Vss. If ΔV<0, transistor T's saturates and Vs≈Vdd. However, if V−<Vss+Vth′, transistor MN2 is blocked and cannot take current from the base of transistor T's which is thus blocked. Voltage Vs is then in the low state, independently from differential voltage ΔV. If V+<Vss+Vth′, transistor MN1 is blocked. Transistors T'1 and T'2 are then blocked. The only case where the result of the comparison is nevertheless correct is when V−>Vss+Vth′, since, as
source 6′ is not blocked, transistor T's saturates and Vs≈Vdd. - In practice, the comparator of FIG. 2 thus requires input voltages which are, in the common mode, higher by approximately 1 to 1.5 volts than the negative supply voltage.
- It should be noted that the problems described hereabove, in relation to assemblies using both transistors in bipolar technology and in MOS technology, arise in the same manner for comparators realized in integrated bipolar technology or integrated MOS technology.
- It would be desirable to have a comparator operating at least over the entire range of common mode voltages of the circuit, that is, withstanding input voltages at least in the entire supply voltage range (Vdd-Vss) while keeping a large output voltage excursion.
- Document EP-A-0512795 describes a comparator consisting of MOS transistors combining two stages respectively designed for operating with a common mode input voltage substantially equal to one of the supply voltages. This combination allows, for the comparator as a whole, input voltages reaching the supply voltages in common mode. However, this circuit is limited to a use of MOS transistors with the output transistors.
- The present invention provides a novel structure of a comparator which operates with differential inputs withstanding common mode voltages which may exceed the range of the supply voltage of the comparator while keeping a large output voltage excursion.
- The invention more particularly provides a solution integrable in BICMOS technology.
- The present invention also provides such a comparator which has low power consumption and, in particular, the power consumption of which is independent from the common mode voltages present on its inputs.
- To achieve these and other objects, the present invention provides a BICMOS technology comparator including: a first stage with differential inputs capable of operating with input voltages which are, in the common mode, lower than a positive supply potential minus a first threshold voltage, the first stage controlling a first bipolar output transistor; a second stage with differential inputs for operating with input voltages which are, in the common mode, higher than a negative supply potential plus a second threshold voltage, the second stage controlling a second bipolar output transistor and the output transistors being connected in series between two terminals at the positive and negative supply potentials, a midpoint of their series connection forming an output terminal of the comparator; and means for controlling the differential stages according to the voltages applied on their inputs.
- According to an embodiment of the present invention, said means are formed of two switches connected in series between the supply terminals, the midpoint of the series connection of the switches being connected to the output terminal and each switch including a control terminal connected to the midpoint of a series connection of a first current source with the differential stage with which the switch is associated.
- According to an embodiment of the present invention, a second current source is interposed between each switch and the supply terminal associated therewith.
- According to an embodiment of the present invention, each second current source is connected as a current mirror on the first current source of the differential stage with which the corresponding switch is associated.
- According to an embodiment of the present invention, a control stage is interposed between each switch and the differential stage associated therewith.
- According to an embodiment of the present invention, each control stage of a switch includes a third current source connected as a current mirror on the second current source associated with the other switch.
- According to an embodiment of the present invention, each control stage is formed of a MOS transistor connected in series with the third current source between the supply terminals, the gate of the MOS transistor of each control stage being connected to the midpoint of the series connection of the first current source and of the differential stage with which the switch is associated.
- According to an embodiment of the present invention, each switch is formed of a MOS transistor.
- The foregoing and other objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
- FIGS. 1 and 2 previously described are meant to show the state of the art and the problem to solve;
- FIG. 3 shows, partially in block form, a first embodiment of a comparator according to the present invention; and
- FIG. 4 shows a second embodiment of a comparator according to the present invention.
- The same elements have been referred to with the same reference numbers in the different drawings. For clarity, only those elements necessary to the understanding of the present invention have been shown in the drawings.
- A characteristic of the present invention is to associate two differential stages that receive, on their respective inputs, different common mode voltages, and to provide an automatic selection of the differential stage which is operational, according to the common mode voltages of the differential inputs.
- FIG. 3 shows a first embodiment of a comparator according to the present invention.
- According to the present invention, the comparator includes two differential input stages1, 1′ which are each associated with a
current source source 6, to a terminal A for receiving a high supply potential Vdd. A second differential stage (DIF_N) 1′, similar to the differential stage shown in FIG. 2, is directly connected to terminal A and, viasource 6′, to terminal M. - A positive input of each
differential stage terminal 2 for receiving a first voltage V+, to be compared with a second voltage V− applied on aterminal 3 connected to a negative input of eachstage stages - According to the present invention, the
midpoints current sources differential stages switch Switches - A first function of
switches differential stages differential stages - A second function of
switches - Switches8 and 8′ are, for example, formed of MOS transistors, respectively a P-channel transistor MP3 and an N-channel transistor MN3, the respective drains of which are connected to source S. The sources of transistors MP3 and MN3 are respectively connected to terminals A and M and their gates are respectively connected to
terminals - It should be noted that the current sources formed by transistors MP3 and MN3 are not, according to the present invention, connected as current mirrors on
respective sources stage - Transistor MP3 is non-conducting when the potential of
node 7 is higher than potential Vdd, minus threshold voltage Vgsp of transistor MP3, and thus when one of voltages V+ or V− is, in the common mode, higher than potential Vdd plus two threshold voltages Vgsp (transistors MP1 and MP3). Transistor MN3 is non-conducting when the potential ofnode 7′ is lower than potential Vss, plus threshold voltage Vgsn of transistor MN3, and thus when one of voltages V+ or V− is lower, in the common mode, than potential Vss plus two threshold voltages Vgsn (transistors MN1 and MN3). - It should be noted that, according to the present invention, the range of each
stage - The operation of a comparator such as shown in FIG. 3 is the following for the different cases of voltages V+ and V− likely to occur.
- 1/V−>Vdd-2Vgsp. Transistor Ts is off and transistor MN3 is on. The result of the comparison is conditioned by
stage 1′. - If V+<Vdd-2Vgsp, transistor MP3 is on. Transistor T's saturates, even if V+ is lower than Vss+2Vgsn (since V− is high enough for
source 6′ not to be blocked). Thus, Vs≈Vdd. - If V+>Vdd-2Vgsp, transistor MP3 is off. If ΔV<0, transistor T's saturates and Vs Vdd. If ΔV>0, transistor T's is non-conducting and Vs≈Vss (through transistor MN3).
- 2/V−<Vss+2Vgsn. Transistor T's is off and transistor MP3 is on. The result of the comparison is conditioned by
stage 1. - If V+≧Vss+2Vgsn, transistor MN3 is on. Transistor Ts saturates, even if V+ is higher than Vdd-2Vgsp (since V− is low enough for
source 6 not to be blocked). Thus, Vs≈Vss. - If V+<Vss+2Vgsn, transistor MN3 is off. If ΔV>0, transistor Ts saturates and Vs≈Vss. If ΔV<0, transistor Ts is off and Vs≈Vdd (through transistor MP3).
- 3/Vss+2Vgsn≦V+≦Vdd-2Vgsp and Vss+2Vgsn≦V−≦Vdd-2Vgsp, both
stages - If ΔV>0, transistor Ts saturates and transistor T's is off, Vs≈Vss. In particular, the invention allows the use of voltages V+ and V− respectively greater than Vdd and smaller than Vss in a BICMOS technology circuit, independently of the manufacturing dispersions conditioning the thresholds of the transistors. In the circuit known from document EP-A-0512795, this is not possible due to the dispersions between the thresholds of the transistors from one circuit to the other of two different batches carried out with the same process. According to the invention, using active loads T1, T2, T′1, T′2 in bipolar technology overcomes these dispersions. The selection of the active loads as bipolar transistors necessitates the use of bipolar output transistors.
- If ΔV<0, transistor Ts is off and transistor T's saturates, Vs≈Vdd.
- It should be noted that voltages V+ and V− can even, in common mode, exceed potentials Vdd and Vss.
- An advantage of a comparator according to the present invention is that it operates whatever the common mode levels of the input voltages.
- FIG. 4 shows a second embodiment of a comparator according to the present invention.
- This assembly includes an improvement with respect to the first embodiment, to make the power consumption of the comparator independent from the common mode voltages. Indeed, in the assembly of the first embodiment, the power consumption depends on voltages V+ and V−.
- According to this second embodiment, each transistor MP3, MN3 is associated with a current source 9, 9′ connected as a current mirror on
source differential stage - Current sources9 and 9′ make the current taken from or issued to terminal S independent from voltages V+ and V−.
- An advantage of this second embodiment is that it makes the comparator power consumption independent from the common mode voltages present on its input terminals.
- Preferably, each transistor MP3, MN3 is further associated with a
control stage Stage 10 is formed of an N-channel MOS transistor MN4, the drain of which is connected to terminal A and the source of which is connected, via acurrent source 11, to terminal M. The gate of transistor MN4 is connected tonode 7 and its source is connected to the gate of transistor MP3.Current source 11 is mounted as a current mirror oncurrent source 6′ ofdifferential stage 1′.Stage 10′ is formed of a P-channel MOS transistor MP4, the drain of which is connected to terminal M and the source of which is connected, via acurrent source 11′, to terminal A. The gate of transistor MP4 is connected tonode 7′ and its source is connected to the gate of transistor MN3.Current source 11′ is connected as a current mirror oncurrent source 6 ofdifferential stage 1. - Transistor MN4 adds voltage V+ on the gate of transistor MP3 by compensating the gate-source voltage of transistor MP1. Similarly, transistor MP4 adds common mode voltage V− on the gate of transistor MN3 by compensating the gate-source voltage of transistor MN2.
- Transistors MP3 and MN3 are thus on in a larger voltage range than in the first embodiment. This has the advantage of optimizing the response times over the entire range of common mode voltages according to a fixed maximum power consumption. The response times can also be adjusted by modifying the gate width/length (W/L) ratios of transistors MP4 and MN4, without affecting the maximum power consumption thanks to the current mirrors of
sources - Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, although reference has been made in the preceding description to embodiments using bipolar and MOS technologies within the same assembly, the present invention also applies to a comparator realized in integrated bipolar technology or in integrated MOS technology. For a circuit in MOS technology, it is enough to replace the PNP-type bipolar transistors with P-channel MOS transistors and the NPN-type bipolar transistors with N-channel MOS transistors. Similarly, for a circuit in bipolar technology, the P-channel MOS transistors will be replaced with PNP-type bipolar transistors and the N-channel MOS transistors will be replaced with NPN-type bipolar transistors.
- Further, the respective sizings of the different components of the assembly according to the present invention are within the abilities of those skilled in the art according to the desired application.
- Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.
Claims (8)
1. A BICMOS technology comparator, comprising:
a first stage with differential inputs capable of operating with input voltages which are, in a common mode, lower than a positive supply potential minus a first threshold voltage, the first stage controlling a first bipolar output transistor;
a second stage with differential inputs for operating with input voltages which are, in the common mode, higher than a negative supply potential plus a second threshold voltage, the second stage controlling a second bipolar output transistor and the output transistors being connected in series between two terminals at the positive and negative supply potentials, a midpoint of their series connection forming an output terminal of the comparator; and
means for controlling the differential stages according to the voltages applied on their inputs.
2. The comparator of claim 1 , wherein said means are formed of two switches connected in series between the supply terminals, the midpoint of the series connection of the switches being connected to the output terminal and each switch including a control terminal connected to the midpoint of a series connection of a first current source with the differential stage with which the switch is associated.
3. The comparator of claim 2 , wherein a second current source is interposed between each switch and the supply terminal associated therewith.
4. The comparator of claim 3 , wherein each second current source is connected as a current mirror on the first current source of the differential stage with which the corresponding switch is associated.
5. The comparator of claim 2 , wherein a control stage is interposed between each switch and the differential stage associated therewith.
6. The comparator of claim 5 , wherein each control stage of a switch includes a third current source connected as a current mirror on the second current source associated with the other switch.
7. The comparator of claim 6 , wherein each control stage is formed of a MOS transistor connected in series with the third current source between the supply terminals, the gate of the MOS transistor of each control stage being connected to the midpoint of the series connection of the first current source and of the differential stage with which the switch is associated.
8. The comparator of claim 2 , wherein each switch is formed of a MOS transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/010,964 US20020084849A1 (en) | 1997-04-15 | 2001-10-26 | Comparator with a large input voltage excursion |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9704912A FR2762161B1 (en) | 1997-04-15 | 1997-04-15 | COMPARATOR WITH LARGE INPUT VOLTAGE EXCURSION |
FR97/04912 | 1997-04-15 | ||
US09/057,970 US6124759A (en) | 1997-04-15 | 1998-04-09 | Comparator with a large input voltage excursion |
US63120200A | 2000-08-01 | 2000-08-01 | |
US84524401A | 2001-04-30 | 2001-04-30 | |
US10/010,964 US20020084849A1 (en) | 1997-04-15 | 2001-10-26 | Comparator with a large input voltage excursion |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US84524401A Continuation | 1997-04-15 | 2001-04-30 |
Publications (1)
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US20020084849A1 true US20020084849A1 (en) | 2002-07-04 |
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/057,970 Expired - Lifetime US6124759A (en) | 1997-04-15 | 1998-04-09 | Comparator with a large input voltage excursion |
US10/010,964 Abandoned US20020084849A1 (en) | 1997-04-15 | 2001-10-26 | Comparator with a large input voltage excursion |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US09/057,970 Expired - Lifetime US6124759A (en) | 1997-04-15 | 1998-04-09 | Comparator with a large input voltage excursion |
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US (2) | US6124759A (en) |
FR (1) | FR2762161B1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6819148B2 (en) * | 2002-07-23 | 2004-11-16 | Texas Instruments Incorporated | CMOS comparator output stage and method |
US6844781B1 (en) | 2003-07-07 | 2005-01-18 | Ami Semiconductor, Inc. | Dual differential-input amplifier having wide input range |
DE102005001322B4 (en) * | 2005-01-11 | 2010-07-08 | Dspace Digital Signal Processing And Control Engineering Gmbh | Method and circuit for galvanically isolated transmission of a signal |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0618308B2 (en) * | 1985-04-08 | 1994-03-09 | ソニー株式会社 | Balanced differential amplifier |
EP0509113B1 (en) * | 1991-04-16 | 1998-10-07 | Siemens Aktiengesellschaft | Output buffer amplifier with high signal amplitude |
DE59108506D1 (en) * | 1991-04-16 | 1997-03-06 | Siemens Ag | Output buffer amplifier |
US5142244A (en) * | 1991-05-06 | 1992-08-25 | Harris Corporation | Full range input/output comparator |
DE69315251T2 (en) * | 1992-05-08 | 1998-05-14 | Koninkl Philips Electronics Nv | Differential amplifier with an input voltage range equal to the supply voltage and with square root current control |
US5337008A (en) * | 1993-02-25 | 1994-08-09 | Hewlett-Packard Corporation | High gain rail-to-rail CMOS amplifier |
JP2885120B2 (en) * | 1995-01-27 | 1999-04-19 | 日本電気株式会社 | Operational amplifier |
JP3392271B2 (en) * | 1995-11-02 | 2003-03-31 | シャープ株式会社 | Operational amplifier circuit |
-
1997
- 1997-04-15 FR FR9704912A patent/FR2762161B1/en not_active Expired - Fee Related
-
1998
- 1998-04-09 US US09/057,970 patent/US6124759A/en not_active Expired - Lifetime
-
2001
- 2001-10-26 US US10/010,964 patent/US20020084849A1/en not_active Abandoned
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Publication number | Publication date |
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FR2762161A1 (en) | 1998-10-16 |
US6124759A (en) | 2000-09-26 |
FR2762161B1 (en) | 1999-07-02 |
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