US20020088716A1 - Method of enhancing hardness of sputter deposited copper films - Google Patents

Method of enhancing hardness of sputter deposited copper films Download PDF

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US20020088716A1
US20020088716A1 US10/092,097 US9209702A US2002088716A1 US 20020088716 A1 US20020088716 A1 US 20020088716A1 US 9209702 A US9209702 A US 9209702A US 2002088716 A1 US2002088716 A1 US 2002088716A1
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copper alloy
seed layer
alloy seed
weight percent
layer
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US10/092,097
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Vikram Pavate
Murali Abburi
Murali Narasimhan
Seshadri Ramaswami
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Applied Materials Inc
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Priority claimed from US09/406,325 external-priority patent/US6432819B1/en
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Assigned to APPLIED MATERIALS, INC. reassignment APPLIED MATERIALS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ABBURI, MURALI, NARASIMHAN, MURALI, PAVATE, VIKRAM, RAMASWAMI, SESHADRI
Publication of US20020088716A1 publication Critical patent/US20020088716A1/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34Sputtering
    • C23C14/3407Cathode assembly for sputtering apparatus, e.g. Target
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34Sputtering
    • C23C14/35Sputtering by application of a magnetic field, e.g. magnetron sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/34Gas-filled discharge tubes operating with cathodic sputtering
    • H01J37/3411Constructional aspects of the reactor
    • H01J37/3414Targets
    • H01J37/3426Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233Copper alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to the deposition of a layer on a substrate. More specifically, the invention relates to deposition of a doped layer on a substrate.
  • Aluminum has traditionally been the choice of conductive materials used in metallization. However, smaller feature sizes have created a need for a conductive material with lower resistivity than aluminum. Copper is now being considered as an interconnect material to replace or complement aluminum because copper has a lower resistivity (1.7 ⁇ -cm compared to 3.1 ⁇ -cm for aluminum) and higher current carrying capacity.
  • Electromigration refers to the solid diffusion of ions in the presence of electric fields. Atoms in a conductive material are displaced as a consequence of a direct momentum transfer from the conduction electrons in the direction of their motion. The large flux of electrons interacts with the diffusing atoms in the metal lattice and sweeps these atoms in the direction of electron flow. The transport of mass causes removal of material in some locations, which generates voids and the accumulation of material in other locations. As a result, electromigration causes failures by opening interconnect lines.
  • the present invention generally provides a method and apparatus for forming a target material having enhanced hardness.
  • the target material is well suited for sputtering processes wherein a portion of the material is deposited on a substrate such as by physical vapor deposition (PVD) or Ionized Metal Plasma (IMP) PVD.
  • PVD physical vapor deposition
  • IMP Ionized Metal Plasma
  • the invention provides a method of sputtering a layer on a substrate, comprising generating a plasma in a substrate processing chamber, sputtering material from a conductive target, the target comprising a material having a vickers hardness between about 100 and about 250, and depositing the sputtered material on the substrate.
  • the target includes copper and another material selected from the group of magnesium, zinc, aluminum, iron, nickel, silicon and combinations thereof.
  • a conductive material having enhanced hardness is deposited on a substrate.
  • the material comprises at least copper and has a vickers hardness of between about 100 and about 250.
  • the material comprises primarily copper combined with another material selected from the group of magnesium, zinc, aluminum, iron, nickel, silicon and combinations thereof.
  • FIG. 1 is a schematic cross-sectional view of an IMP chamber.
  • FIG. 2 is a schematic cross-sectional view of a substrate with a seed layer formed on the substrate.
  • the present invention provides a method and apparatus for forming a copper layer on a substrate, preferably using a sputtering process.
  • the sputtering process involves bombarding a conductive member of enhanced hardness with ions to dislodge the copper from the conductive member.
  • the hardness of the target may be enhanced by alloying the copper conductive member with another material and/or mechanically working the material of the conductive member during its manufacturing in order to improve conductive member and film qualities.
  • working refers to any process by which a material is treated, conditioned or otherwise processed to affect the qualities, e.g. hardness, of the material.
  • the following description refers to the conductive member as a target, which typically provides the bulk of the material to be deposited on a substrate.
  • the conductive member may be any component which is sputtered and contributes to the deposition of material on the substrate.
  • qualities such as the hardness, grain size, crystallographic orientation, etc. of target materials affect the quality of the resulting film produced by sputtering the target as well as the sputtering characteristics of the target. According to the invention, such qualities and characteristics can be affected by the methods and materials used to manufacture the target. As an example, the susceptibility of the deposited film to electromigration can be reduced. Additionally, microarcing on the surface of the target during sputtering can be mitigated.
  • Solid metals are typically composed of separate and discreet grains of continuous crystal lattice rather than one continuous crystal structure. Depending on the composition and forming method of the metal, these grains can vary in size from the millimeter range to the micron range. By providing targets having smaller grain size the invention mitigates the problems of electromigration and microarcing.
  • each grain is a continuous crystal, with its crystal lattice oriented in some particular way relative to a reference plane such as the sputtering surface of the target. Since each grain is independent of others, each grain lattice has its own orientation relative to this plane. When grain orientation is not random and crystal planes tend to be aligned in some way relative to a reference plane, the material is said to have “texture”. These textures are noted using standard indices which define directions relative to crystallographic planes. For instance, a target made from a metal with cubic crystal structure, such as copper, may have a ⁇ 100>, a ⁇ 110> or other textures. The exact texture developed will depend on the metal type and the work and heat treatment history of the target.
  • a copper target is alloyed with another material (herein referred to as the alloy) to increase the hardness of the target.
  • the target is preferably made of copper and an alloy selected from the group of magnesium, zinc, aluminum, iron, nickel, silicon and any combination thereof.
  • the percentage by weight of the alloy is from about 0.01% to about 10%, and most preferably from about 0.01% to about 5%.
  • the vickers hardness of the target is between about 100 and about 250.
  • a number of processes known to metallurgists can be adapted to produce a copper-alloy target.
  • the target can be prepared, for example, by uniformly mixing the alloy into a molten copper material which is then cast and cooled to form the target.
  • the alloy material may be provided in the form of a pellet which is then added to the molten copper.
  • the copper-alloy target of the invention can then be sputtered to form a copper alloy film on a substrate.
  • the resulting alloyed film exhibits superior resistance to electromigration.
  • the target can be sputtered to produce a seed layer on features formed on a substrate.
  • the substrate may then undergo various additional processes including an electroplating process wherein the features are filled with a material, such as copper. It is believed that a portion of the alloy material diffuses into the fill material. As a result, the fill material is made more resistant to electromigration. Even though the alloy material will typically have a higher resistivity than copper, the amount of alloy used, by weight percentage of the target, is minimal compared to the weight percentage of copper in the target.
  • the proper proportions of alloy to be combined with the copper during the manufacturing of the target can be determined by the volume of the features to be filled, thereby ensuring that sufficient alloy is diffused into the fill material without compromising the resistivity of the deposited material.
  • the hardness of a copper target is increased by mechanically working the target material(s) by metallurgical methods. Work hardening the target allows the grain size of the target material to be changed to produce a relatively harder target.
  • a copper-alloy target has a vickers hardness between about 100 and about 250.
  • methods of manufacturing a copper-alloy target include casting, forming, annealing, rolling, forging, liquid dynamic compaction (LDC), equal channel angular extrusion (ECA) and other methods known and unknown in metallurgy.
  • LDC liquid dynamic compaction
  • ECA equal channel angular extrusion
  • one embodiment of the invention contemplates using known metallurgical methods, such methods have heretofore not been used in the production of copper-alloy targets for the purpose of enhancing their hardness.
  • the copper-alloy target of the invention can be utilized in any sputtering chamber.
  • One such sputtering chamber is the Ionized Metal Plasma (IMP) VectraTM chamber, available from Applied Materials, Inc. of Santa Clara, Calif.
  • IMP Ionized Metal Plasma
  • An IMP process provides a higher density plasma than standard PVD that causes the sputtered target material to become ionized. The ionization enables the sputtered material to be attracted in a substantially perpendicular direction to a biased substrate surface and to deposit a layer within high aspect ratio features.
  • FIG. 1 is a schematic cross-sectional view of an IMP chamber 100 , capable of generating a relatively high density plasma, i.e., one with a capability to ionize a significant fraction of both the process gas (typically argon) and the sputtered target material.
  • the chamber 100 includes sidewalls 101 , lid 102 , and bottom 103 .
  • the lid 102 includes a target backing plate 104 which supports a target 105 of the material to be deposited.
  • An opening 108 in the chamber 100 provides access for a robot (not shown) to deliver and retrieve substrates 110 to and from the chamber 100 .
  • a substrate support 112 supports the substrate 110 in the chamber and is typically grounded.
  • the substrate support 112 is mounted on a lift motor 114 that raises and lowers the substrate support 112 and a substrate 110 disposed thereon.
  • a lift plate 116 connected to a lift motor 118 is mounted in the chamber 100 and raises and lowers pins 120 a, 120 b mounted in the substrate support 112 .
  • the pins 120 a, 120 b raise and lower the substrate 110 from and to the surface of the substrate support 112 .
  • a coil 122 is mounted between the substrate support 112 and the target 105 and provides inductively-coupled magnetic fields in the chamber 100 to assist in generating and maintaining a plasma between the target 105 and substrate 110 .
  • the coil 122 is also sputtered due to its location between the target and the substrate 110 and preferably is made of similar constituents as the target 105 .
  • the coil comprises copper and an alloy selected from the group of magnesium, zinc, aluminum, iron, nickel, silicon and any combination thereof.
  • the alloy percentage of the coil 122 could vary compared to the target alloy percentage depending on the desired layer composition and is empirically determined by varying the relative weight percentages.
  • Power supplied to the coil 122 provides an electromagnetic field in the chamber 100 that induces currents in the plasma to increase the density of the plasma, thereby enhancing the ionization of the sputtered material.
  • the ionized material is then directed toward the substrate 110 and deposited thereon.
  • a shield 124 is disposed in the chamber 100 to shield the chamber sidewalls 101 from the sputtered material.
  • the shield 124 also supports the coil 122 by coil supports 126 .
  • the coil supports 126 electrically insulate the coil 122 from the shield 124 and the chamber 100 and can be made of similar material as the coil.
  • the clamp ring 128 is mounted between the coil 122 and the substrate support 112 and shields an outer edge and backside of the substrate from sputtered materials when the substrate 110 is raised into a processing position to engage the lower portion of the clamp ring 128 .
  • the shield 124 supports the clamp ring 128 when the substrate 110 is lowered below the shield 124 to enable substrate transfer.
  • a power supply 130 delivers preferably DC power to the target 105 to cause the processing gas to form a plasma, although RF power can be used.
  • Magnets 106 a, 106 b disposed behind the target backing plate 104 increase the density of electrons adjacent to the target 105 , thus increasing ionization at the target to increase the sputtering efficiency.
  • the magnets 106 a, 106 b generate magnetic field lines generally parallel to the face of the target, around which electrons are trapped in spinning orbits to increase the likelihood of a collision with, and ionization of, a gas atom for sputtering.
  • a power supply 132 preferably a RF power supply, supplies electrical power to the coil 122 to couple with and increase the density of the plasma.
  • Another power supply 134 typically a DC power supply, biases the substrate support 112 with respect to the plasma and provides directional attraction (or repulsion) of the ionized sputtered material toward the substrate 110 .
  • Processing gas such as an inert gas of argon or helium or a reactive gas such as nitrogen, is supplied to the chamber 100 through a gas inlet 136 from gas sources 138 , 140 as metered by respective mass flow controllers 142 , 144 .
  • a vacuum pump 146 is connected to the chamber 100 at an exhaust port 148 to exhaust the chamber 100 and maintain the desired pressure in the chamber 100 .
  • a controller 149 generally controls the functions of the power supplies, lift motors, mass flow controllers for gas injection, vacuum pump, and other associated chamber components and functions.
  • the controller 149 controls the power supply 130 coupled to the target 105 to cause the processing gas to form a plasma and sputter the target material.
  • the controller 149 also controls the power supply 132 coupled to the coil 122 to increase the density of the plasma and ionize the sputtered material.
  • the controller 149 also controls the power supply 134 to provide directional attraction of the ionized sputtered material to the substrate surface.
  • the controller 149 preferably comprises a central processing unit (CPU), a memory, and support circuits for the CPU.
  • the CPU may be one of any form of general purpose computer processor that can be used in an industrial setting for controlling various chambers and subprocessors.
  • the memory is coupled to the CPU.
  • the memory, or computer-readable medium may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk drive, hard disk, or any other form of digital storage, local or remote.
  • the support circuits are coupled to the CPU for supporting the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input/output circuitry and subsystems, and the like.
  • a deposition process is generally stored in the memory, typically as a software routine.
  • the software routine may also be stored and/or executed by a second CPU that is remotely located from the hardware being controlled by the CPU of the controller 149 .
  • a seed layer is deposited on a substrate by sputtering the target 105 .
  • a noble gas such as helium or argon, is flown into the chamber at a rate sufficient to produce a chamber pressure of about 5 to about 100 mTorr, preferably about 20 mTorr to about 50 mTorr.
  • the power supply 130 delivers about 200 Watts (W) to about 12 kW, preferably about 750 W to about 3 kW to the target 105 .
  • the power supply 132 delivers an AC signal to the coil 122 between about 500 W and about 5 kW, and preferably about 1.5 kW to about 2.5 kW.
  • the power supply 134 delivers about 0 W to about 600 W, preferably about 350 W to about 500 W to the substrate support 112 with a duty cycle between 0% to 100% and preferably about 50% to about 75%.
  • a surface temperature between about ⁇ 50° C. to about 150° C., preferably below 50° C. is useful for processing during the seed layer deposition.
  • the sputtered target material is deposited on the substrate to a thickness of about 500 ⁇ to about 4000 ⁇ , preferably about 2000 ⁇ .
  • the above parameters are preferably used to deposit a layer on a 200 mm substrate and are not intended to be limiting.
  • power densities may be determined from the given power ranges and scaled up to larger substrates, such as 300 mm substrates, or down to smaller substrates, such as 100 mm substrates.
  • the chamber described above is an IMP chamber other chambers may be used.
  • the target 105 is disposed in a PVD chamber.
  • the above described parameters are dependent on the particular chamber type.
  • the power level delivered to the target 105 by the power supply 130 is between about 200 W to about 12 kW.
  • the power level delivered to the target 105 by the power supply 130 is between about preferably about 750 W to about 3 kW.
  • FIG. 2 is a schematic cross-sectional view of an exemplary substrate 110 formed according to a process of the invention.
  • a dielectric layer 204 is deposited on the substrate 110 and etched to form the feature 200 , such as a via, contact, trench or line.
  • the term “substrate” is broadly defined as the underlying material and can include a series of underlying layers.
  • the dielectric layer 204 can be a pre-metal dielectric layer deposited over a silicon wafer or an interlevel dielectric layer.
  • a liner layer 206 such as a Ta layer, is deposited on the dielectric layer 204 as a transition layer to promote adhesion to the underlying material and reduce contact/via resistance.
  • the liner layer 206 is preferably deposited using an IMP PVD process and can be deposited by other PVD processes, such as collimated or long throw sputtering or other methods such as CVD.
  • Collimated sputtering is generally performed by placing a collimator (not shown) between the target and the substrate to filter sputtered material traveling obliquely through the collimator.
  • Long throw sputtering is generally performed by increasing the spacing between the target and the substrate.
  • a barrier layer 208 of tantalum nitride (TaN) is deposited on the liner layer 206 using PVD, and preferably an IMP PVD process, especially for high aspect ratio features.
  • the barrier layer prevents diffusion of copper into adjacent layers. While Ta/TaN are preferred, other liner and/or barrier layers that can be used are titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN) and other refractory metals and their nitrided counterparts.
  • a seed layer 210 is deposited over the TaN barrier layer 208 , using PVD and preferably IMP PVD.
  • the seed layer 210 is deposited by sputtering a copper/copper-alloy target of the invention.
  • the seed layer 210 is deposited over the barrier layer 208 as a seed layer for a subsequent copper fill 212 .
  • the copper fill 212 can be deposited by PVD, IMP, CVD, electroplating, electroless deposition, evaporation, or other known methods.
  • copper fill 212 is deposited using electroplating techniques.
  • Subsequent processing can include planarization by chemical mechanical polishing (CMP), additional deposition of layers, etching, and other processes known to substrate manufacturing.
  • CMP chemical mechanical polishing
  • the hardened target material of the invention is believed to reduce the potential for electromigration during operation of the devices formed on the substrate 110 surface. Additionally, empirical evidence suggests that harder targets result in reduced arcing between the target and an adjacent structure, where the arcing dislodges unwanted pieces of the target (splats) that are deposited on the substrate and contaminates the deposition.

Abstract

The present invention provides a method and apparatus for forming a copper layer on a substrate, preferably using a sputtering process. The sputtering process involves bombarding a conductive member of enhanced hardness with ions to dislodge the copper from the conductive member. The hardness of the target may be enhanced by alloying the copper conductive member with another material and/or mechanically working the material of the conductive member during its manufacturing process in order to improve conductive member and film qualities. The copper may be alloyed with magnesium, zinc, aluminum, iron, nickel, silicon and any combination thereof.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of co-pending U.S. patent application Ser. No. 09/518,004, filed Mar. 2, 2000 which is a continuation-in-part of U.S. patent application Ser. No. 09/406,325, filed on Sep. 27, 1999. Each of the aforementioned related patent applications is herein incorporated by reference.[0001]
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0002]
  • The present invention relates to the deposition of a layer on a substrate. More specifically, the invention relates to deposition of a doped layer on a substrate. [0003]
  • 2. Description of the Related Art [0004]
  • Consistent and fairly predictable improvement in integrated circuit design and fabrication has been observed in the last decade. One key to successful improvements is multilevel interconnect technology, which provides the conductive paths between the devices of an integrated circuit (IC) and other electronic devices. The conductive paths, or features, of an IC typically comprise horizontal interconnects (also referred to as lines) and vertical interconnects (also referred to as contacts or vias). The shrinking dimensions of features, presently in the sub-quarter micron range, has increased the importance of reducing capacitive coupling between interconnect lines and reducing resistance in the conductive features. [0005]
  • Aluminum has traditionally been the choice of conductive materials used in metallization. However, smaller feature sizes have created a need for a conductive material with lower resistivity than aluminum. Copper is now being considered as an interconnect material to replace or complement aluminum because copper has a lower resistivity (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum) and higher current carrying capacity. [0006]
  • As a result of the desirability of using copper for semiconductor device fabrication, current practice provides for sputtering high purity copper targets. High purity is considered desirable in order to ensure that the low resistivity of copper is not affected by contaminants. However, the inventors have discovered that high purity copper films suffer from electromigration. Electromigration refers to the solid diffusion of ions in the presence of electric fields. Atoms in a conductive material are displaced as a consequence of a direct momentum transfer from the conduction electrons in the direction of their motion. The large flux of electrons interacts with the diffusing atoms in the metal lattice and sweeps these atoms in the direction of electron flow. The transport of mass causes removal of material in some locations, which generates voids and the accumulation of material in other locations. As a result, electromigration causes failures by opening interconnect lines. [0007]
  • Therefore, there is a need for an improved copper based target material which mitigates the problems of electromigration. [0008]
  • SUMMARY OF THE INVENTION
  • The present invention generally provides a method and apparatus for forming a target material having enhanced hardness. The target material is well suited for sputtering processes wherein a portion of the material is deposited on a substrate such as by physical vapor deposition (PVD) or Ionized Metal Plasma (IMP) PVD. [0009]
  • In one aspect, the invention provides a method of sputtering a layer on a substrate, comprising generating a plasma in a substrate processing chamber, sputtering material from a conductive target, the target comprising a material having a vickers hardness between about 100 and about 250, and depositing the sputtered material on the substrate. In one embodiment, the target includes copper and another material selected from the group of magnesium, zinc, aluminum, iron, nickel, silicon and combinations thereof. [0010]
  • In yet another aspect, a conductive material having enhanced hardness is deposited on a substrate. The material comprises at least copper and has a vickers hardness of between about 100 and about 250. In one embodiment, the material comprises primarily copper combined with another material selected from the group of magnesium, zinc, aluminum, iron, nickel, silicon and combinations thereof.[0011]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • So that the manner in which the above recited features, advantages and objects of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. [0012]
  • It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. [0013]
  • FIG. 1 is a schematic cross-sectional view of an IMP chamber. [0014]
  • FIG. 2 is a schematic cross-sectional view of a substrate with a seed layer formed on the substrate.[0015]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • The present invention provides a method and apparatus for forming a copper layer on a substrate, preferably using a sputtering process. The sputtering process involves bombarding a conductive member of enhanced hardness with ions to dislodge the copper from the conductive member. The hardness of the target may be enhanced by alloying the copper conductive member with another material and/or mechanically working the material of the conductive member during its manufacturing in order to improve conductive member and film qualities. As referred to herein “working” refers to any process by which a material is treated, conditioned or otherwise processed to affect the qualities, e.g. hardness, of the material. Illustratively, the following description refers to the conductive member as a target, which typically provides the bulk of the material to be deposited on a substrate. However, the conductive member may be any component which is sputtered and contributes to the deposition of material on the substrate. [0016]
  • The inventors have discovered that qualities such as the hardness, grain size, crystallographic orientation, etc. of target materials affect the quality of the resulting film produced by sputtering the target as well as the sputtering characteristics of the target. According to the invention, such qualities and characteristics can be affected by the methods and materials used to manufacture the target. As an example, the susceptibility of the deposited film to electromigration can be reduced. Additionally, microarcing on the surface of the target during sputtering can be mitigated. [0017]
  • Solid metals are typically composed of separate and discreet grains of continuous crystal lattice rather than one continuous crystal structure. Depending on the composition and forming method of the metal, these grains can vary in size from the millimeter range to the micron range. By providing targets having smaller grain size the invention mitigates the problems of electromigration and microarcing. [0018]
  • Another factor which affects microarcing on the target surface and the electromigration characteristics of the deposited material, is the crystallographic orientation of the grains. Each grain is a continuous crystal, with its crystal lattice oriented in some particular way relative to a reference plane such as the sputtering surface of the target. Since each grain is independent of others, each grain lattice has its own orientation relative to this plane. When grain orientation is not random and crystal planes tend to be aligned in some way relative to a reference plane, the material is said to have “texture”. These textures are noted using standard indices which define directions relative to crystallographic planes. For instance, a target made from a metal with cubic crystal structure, such as copper, may have a <100>, a <110> or other textures. The exact texture developed will depend on the metal type and the work and heat treatment history of the target. [0019]
  • In one embodiment, a copper target is alloyed with another material (herein referred to as the alloy) to increase the hardness of the target. The target is preferably made of copper and an alloy selected from the group of magnesium, zinc, aluminum, iron, nickel, silicon and any combination thereof. The percentage by weight of the alloy is from about 0.01% to about 10%, and most preferably from about 0.01% to about 5%. In one embodiment, the vickers hardness of the target is between about 100 and about 250. [0020]
  • A number of processes known to metallurgists can be adapted to produce a copper-alloy target. The target can be prepared, for example, by uniformly mixing the alloy into a molten copper material which is then cast and cooled to form the target. The alloy material may be provided in the form of a pellet which is then added to the molten copper. By alloying the copper target in such a manner, it is believed the hardness of the target can be enhanced. The inventors have discovered that a target of enhanced hardness mitigates the problems of electromigration associated with the prior art high purity copper targets. Further, even where the alloy material has a higher resistivity than copper, such as where aluminum is used to alloy the copper target, the effect on the resistivity of the resulting film formed on the substrate is minimal because of the relative proportions of the alloy to the copper. [0021]
  • The copper-alloy target of the invention can then be sputtered to form a copper alloy film on a substrate. The resulting alloyed film exhibits superior resistance to electromigration. In one application, the target can be sputtered to produce a seed layer on features formed on a substrate. The substrate may then undergo various additional processes including an electroplating process wherein the features are filled with a material, such as copper. It is believed that a portion of the alloy material diffuses into the fill material. As a result, the fill material is made more resistant to electromigration. Even though the alloy material will typically have a higher resistivity than copper, the amount of alloy used, by weight percentage of the target, is minimal compared to the weight percentage of copper in the target. Thus, the effect on the overall resistivity is negligible. The proper proportions of alloy to be combined with the copper during the manufacturing of the target can be determined by the volume of the features to be filled, thereby ensuring that sufficient alloy is diffused into the fill material without compromising the resistivity of the deposited material. [0022]
  • In another embodiment, the hardness of a copper target is increased by mechanically working the target material(s) by metallurgical methods. Work hardening the target allows the grain size of the target material to be changed to produce a relatively harder target. In a preferred embodiment, a copper-alloy target has a vickers hardness between about 100 and about 250. Illustratively, methods of manufacturing a copper-alloy target include casting, forming, annealing, rolling, forging, liquid dynamic compaction (LDC), equal channel angular extrusion (ECA) and other methods known and unknown in metallurgy. Although one embodiment of the invention contemplates using known metallurgical methods, such methods have heretofore not been used in the production of copper-alloy targets for the purpose of enhancing their hardness. [0023]
  • The copper-alloy target of the invention can be utilized in any sputtering chamber. One such sputtering chamber is the Ionized Metal Plasma (IMP) Vectra™ chamber, available from Applied Materials, Inc. of Santa Clara, Calif. An IMP process provides a higher density plasma than standard PVD that causes the sputtered target material to become ionized. The ionization enables the sputtered material to be attracted in a substantially perpendicular direction to a biased substrate surface and to deposit a layer within high aspect ratio features. [0024]
  • FIG. 1 is a schematic cross-sectional view of an [0025] IMP chamber 100, capable of generating a relatively high density plasma, i.e., one with a capability to ionize a significant fraction of both the process gas (typically argon) and the sputtered target material. The chamber 100 includes sidewalls 101, lid 102, and bottom 103. The lid 102 includes a target backing plate 104 which supports a target 105 of the material to be deposited.
  • An [0026] opening 108 in the chamber 100 provides access for a robot (not shown) to deliver and retrieve substrates 110 to and from the chamber 100. A substrate support 112 supports the substrate 110 in the chamber and is typically grounded. The substrate support 112 is mounted on a lift motor 114 that raises and lowers the substrate support 112 and a substrate 110 disposed thereon. A lift plate 116 connected to a lift motor 118 is mounted in the chamber 100 and raises and lowers pins 120 a, 120 b mounted in the substrate support 112. The pins 120 a, 120 b raise and lower the substrate 110 from and to the surface of the substrate support 112.
  • A [0027] coil 122 is mounted between the substrate support 112 and the target 105 and provides inductively-coupled magnetic fields in the chamber 100 to assist in generating and maintaining a plasma between the target 105 and substrate 110. The coil 122 is also sputtered due to its location between the target and the substrate 110 and preferably is made of similar constituents as the target 105. Thus, the coil comprises copper and an alloy selected from the group of magnesium, zinc, aluminum, iron, nickel, silicon and any combination thereof. The alloy percentage of the coil 122 could vary compared to the target alloy percentage depending on the desired layer composition and is empirically determined by varying the relative weight percentages. Power supplied to the coil 122 provides an electromagnetic field in the chamber 100 that induces currents in the plasma to increase the density of the plasma, thereby enhancing the ionization of the sputtered material. The ionized material is then directed toward the substrate 110 and deposited thereon.
  • A [0028] shield 124 is disposed in the chamber 100 to shield the chamber sidewalls 101 from the sputtered material. The shield 124 also supports the coil 122 by coil supports 126. The coil supports 126 electrically insulate the coil 122 from the shield 124 and the chamber 100 and can be made of similar material as the coil. The clamp ring 128 is mounted between the coil 122 and the substrate support 112 and shields an outer edge and backside of the substrate from sputtered materials when the substrate 110 is raised into a processing position to engage the lower portion of the clamp ring 128. In some chamber configurations, the shield 124 supports the clamp ring 128 when the substrate 110 is lowered below the shield 124 to enable substrate transfer.
  • Three power supplies are used in this type of sputtering chamber. A [0029] power supply 130 delivers preferably DC power to the target 105 to cause the processing gas to form a plasma, although RF power can be used. Magnets 106 a, 106 b disposed behind the target backing plate 104 increase the density of electrons adjacent to the target 105, thus increasing ionization at the target to increase the sputtering efficiency. The magnets 106 a, 106 b generate magnetic field lines generally parallel to the face of the target, around which electrons are trapped in spinning orbits to increase the likelihood of a collision with, and ionization of, a gas atom for sputtering. A power supply 132, preferably a RF power supply, supplies electrical power to the coil 122 to couple with and increase the density of the plasma. Another power supply 134, typically a DC power supply, biases the substrate support 112 with respect to the plasma and provides directional attraction (or repulsion) of the ionized sputtered material toward the substrate 110.
  • Processing gas, such as an inert gas of argon or helium or a reactive gas such as nitrogen, is supplied to the [0030] chamber 100 through a gas inlet 136 from gas sources 138, 140 as metered by respective mass flow controllers 142, 144. A vacuum pump 146 is connected to the chamber 100 at an exhaust port 148 to exhaust the chamber 100 and maintain the desired pressure in the chamber 100.
  • A [0031] controller 149 generally controls the functions of the power supplies, lift motors, mass flow controllers for gas injection, vacuum pump, and other associated chamber components and functions. The controller 149 controls the power supply 130 coupled to the target 105 to cause the processing gas to form a plasma and sputter the target material. The controller 149 also controls the power supply 132 coupled to the coil 122 to increase the density of the plasma and ionize the sputtered material. The controller 149 also controls the power supply 134 to provide directional attraction of the ionized sputtered material to the substrate surface.
  • The [0032] controller 149 preferably comprises a central processing unit (CPU), a memory, and support circuits for the CPU. To facilitate control of the chamber, the CPU may be one of any form of general purpose computer processor that can be used in an industrial setting for controlling various chambers and subprocessors. The memory is coupled to the CPU. The memory, or computer-readable medium, may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk drive, hard disk, or any other form of digital storage, local or remote. The support circuits are coupled to the CPU for supporting the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input/output circuitry and subsystems, and the like. A deposition process is generally stored in the memory, typically as a software routine. The software routine may also be stored and/or executed by a second CPU that is remotely located from the hardware being controlled by the CPU of the controller 149.
  • In one embodiment, a seed layer is deposited on a substrate by sputtering the [0033] target 105. A noble gas, such as helium or argon, is flown into the chamber at a rate sufficient to produce a chamber pressure of about 5 to about 100 mTorr, preferably about 20 mTorr to about 50 mTorr. The power supply 130 delivers about 200 Watts (W) to about 12 kW, preferably about 750 W to about 3 kW to the target 105. The power supply 132 delivers an AC signal to the coil 122 between about 500 W and about 5 kW, and preferably about 1.5 kW to about 2.5 kW. The power supply 134 delivers about 0 W to about 600 W, preferably about 350 W to about 500 W to the substrate support 112 with a duty cycle between 0% to 100% and preferably about 50% to about 75%. When the substrate temperature is controlled, a surface temperature between about −50° C. to about 150° C., preferably below 50° C. is useful for processing during the seed layer deposition. The sputtered target material is deposited on the substrate to a thickness of about 500 Å to about 4000 Å, preferably about 2000 Å.
  • The above parameters are preferably used to deposit a layer on a 200 mm substrate and are not intended to be limiting. For example, power densities may be determined from the given power ranges and scaled up to larger substrates, such as 300 mm substrates, or down to smaller substrates, such as 100 mm substrates. [0034]
  • Further, although the chamber described above is an IMP chamber other chambers may be used. Thus, in one embodiment, the [0035] target 105 is disposed in a PVD chamber. In some cases, the above described parameters are dependent on the particular chamber type. For example, in one embodiment utilizing a PVD chamber, the power level delivered to the target 105 by the power supply 130 is between about 200 W to about 12 kW. In an embodiment utilizing an IMP chamber, the power level delivered to the target 105 by the power supply 130 is between about preferably about 750 W to about 3 kW.
  • FIG. 2 is a schematic cross-sectional view of an [0036] exemplary substrate 110 formed according to a process of the invention. A dielectric layer 204 is deposited on the substrate 110 and etched to form the feature 200, such as a via, contact, trench or line. The term “substrate” is broadly defined as the underlying material and can include a series of underlying layers. The dielectric layer 204 can be a pre-metal dielectric layer deposited over a silicon wafer or an interlevel dielectric layer.
  • A [0037] liner layer 206, such as a Ta layer, is deposited on the dielectric layer 204 as a transition layer to promote adhesion to the underlying material and reduce contact/via resistance. The liner layer 206 is preferably deposited using an IMP PVD process and can be deposited by other PVD processes, such as collimated or long throw sputtering or other methods such as CVD. Collimated sputtering is generally performed by placing a collimator (not shown) between the target and the substrate to filter sputtered material traveling obliquely through the collimator. Long throw sputtering is generally performed by increasing the spacing between the target and the substrate. The increased distance increases the probability that the sputtered material reaching the substrate is directed normal to the substrate surface. A barrier layer 208 of tantalum nitride (TaN) is deposited on the liner layer 206 using PVD, and preferably an IMP PVD process, especially for high aspect ratio features. The barrier layer prevents diffusion of copper into adjacent layers. While Ta/TaN are preferred, other liner and/or barrier layers that can be used are titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN) and other refractory metals and their nitrided counterparts.
  • A [0038] seed layer 210 is deposited over the TaN barrier layer 208, using PVD and preferably IMP PVD. The seed layer 210 is deposited by sputtering a copper/copper-alloy target of the invention. The seed layer 210 is deposited over the barrier layer 208 as a seed layer for a subsequent copper fill 212.
  • The copper fill [0039] 212 can be deposited by PVD, IMP, CVD, electroplating, electroless deposition, evaporation, or other known methods. Preferably, copper fill 212 is deposited using electroplating techniques. Subsequent processing can include planarization by chemical mechanical polishing (CMP), additional deposition of layers, etching, and other processes known to substrate manufacturing.
  • The hardened target material of the invention is believed to reduce the potential for electromigration during operation of the devices formed on the [0040] substrate 110 surface. Additionally, empirical evidence suggests that harder targets result in reduced arcing between the target and an adjacent structure, where the arcing dislodges unwanted pieces of the target (splats) that are deposited on the substrate and contaminates the deposition.
  • Variations in the orientation of the chambers and other system components are possible. Additionally, all movements and positions, such as “above,” “top,” “below,” “under,” “bottom,” “side,” described herein are relative to positions of objects such as the target, substrate, and coil. Accordingly, it is contemplated by the present invention to orient any or all of the components to achieve the desired support of substrates in a processing system. [0041]
  • While the foregoing is directed to the preferred embodiment of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof and the scope thereof is determined by the claims that follow. [0042]

Claims (20)

1. A method of depositing a seed layer over a surface of a substrate, comprising:
depositing a copper alloy seed layer over a surface of a substrate at a substrate temperature between about −50° C. and about 150° C., the copper alloy seed layer comprising an alloying material selected from the group of aluminum, magnesium, and combinations thereof, the alloying material being present in the copper alloy seed layer in a concentration between about 0.01 weight percent and about 10 weight percent.
2. The method of claim 1, wherein the copper alloy seed layer is deposited at a substrate temperature less than about 50° C.
3. The method of claim 1, wherein the copper alloy seed layer is deposited by physical vapor deposition.
4. The method of claim 3, wherein the copper alloy seed layer is deposited by utilizing a high density plasma.
5. The method of claim 1, wherein the alloying material is present in the copper alloy seed layer in a concentration between about 0.01 weight percent and about 5 weight percent.
6. A method of forming a feature, comprising:
depositing a barrier layer over a surface of a substrate; and
depositing a copper alloy seed layer over the barrier layer, the copper alloy seed layer comprising an alloying material selected from the group of aluminum, magnesium, and combinations thereof, the alloying material being present in the copper alloy seed layer in a concentration between about 0.01 weight percent and about 10 weight percent.
7. The method of claim 6, wherein the barrier layer comprises a material selected from the group consisting of tantalum nitride, tantalum, titanium, titanium nitride, tungsten, tungsten nitride, other refractory metals, other refractory metal nitrides, and combinations thereof.
8. The method of claim 6, further comprising depositing a bulk copper layer over the copper alloy seed layer.
9. The method of claim 8, wherein the bulk copper layer is deposited by electroplating.
10. The method of claim 6, wherein the copper alloy seed layer is deposited at a substrate temperature between about −50° C. and about 150° C.
11. The method of claim 10, wherein the copper alloy seed layer is deposited at a substrate temperature less than about 50° C.
12. The method of claim 6, wherein the alloying material is present in the copper alloy seed layer in a concentration between about 0.01 weight percent and about 5 weight percent.
13. A method of forming a feature, comprising:
depositing a barrier layer comprising tantalum nitride;
depositing a copper alloy seed layer over the barrier layer, the copper alloy seed layer comprising aluminum present in the copper alloy seed layer in a concentration between about 0.01 weight percent and about 10 weight percent; and
depositing a bulk copper layer over the copper alloy seed layer by electroplating.
14. The method of claim 13, wherein aluminum is present in the copper alloy seed layer in a concentration between about 0.01 weight percent and about 5 weight percent.
15. A structure, comprising:
a substrate having a dielectric layer formed thereon, the dielectric layer having an aperture formed therein;
a barrier layer formed over the dielectric layer; and
a copper alloy seed layer formed over the barrier layer, the copper alloy seed layer comprising an alloying material selected from the group of aluminum, magnesium, and combinations thereof, the alloying material being present in the copper alloy seed layer in a concentration between about 0.01 weight percent and about 10 weight percent.
16. The structure of claim 15, wherein the alloying material is present in the copper alloy seed layer in a concentration between about 0.01 weight percent and about 5 weight percent.
17. The method of claim 15, wherein the barrier layer comprises a material selected from the group consisting of tantalum nitride, tantalum, titanium, titanium nitride, tungsten, tungsten nitride, other refractory metals, other refractory metal nitrides, and combinations thereof.
18. The structure of claim 15, further comprising a bulk copper layer formed over the copper alloy seed layer.
19. A structure, comprising:
a substrate having a dielectric layer formed thereon, the dielectric layer having an aperture formed therein;
a barrier layer comprising tantalum nitride formed over the dielectric layer;
a copper alloy seed layer formed over the barrier layer, the copper alloy seed layer comprising aluminum present in the copper alloy seed layer in a concentration between about 0.01 weight percent and about 10 weight percent; and
a bulk copper layer formed over the copper alloy seed layer.
20. The structure of claim 19, wherein aluminum is present in the copper alloy seed layer in a concentration between about 0.01 weight percent and about 5 weight percent.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004008491A2 (en) * 2002-07-15 2004-01-22 Aviza Technology, Inc. Thermal processing system and configurable vertical chamber
US20040162029A1 (en) * 2002-07-17 2004-08-19 Jeff Grady Audio player assembly comprising an MP3 player
US20060030151A1 (en) * 2004-08-09 2006-02-09 Applied Materials, Inc. Sputter deposition and etching of metallization seed layer for overhang and sidewall improvement
US20060083495A1 (en) * 2002-07-15 2006-04-20 Qiu Taiquing Variable heater element for low to high temperature ranges
US20070243317A1 (en) * 2002-07-15 2007-10-18 Du Bois Dale R Thermal Processing System and Configurable Vertical Chamber
CN112680626A (en) * 2020-12-09 2021-04-20 爱发科电子材料(苏州)有限公司 Preparation process of copper-aluminum-silicon alloy target material for integrated circuit

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6348139B1 (en) * 1998-06-17 2002-02-19 Honeywell International Inc. Tantalum-comprising articles
US6878250B1 (en) * 1999-12-16 2005-04-12 Honeywell International Inc. Sputtering targets formed from cast materials
US20040072009A1 (en) * 1999-12-16 2004-04-15 Segal Vladimir M. Copper sputtering targets and methods of forming copper sputtering targets
US6331233B1 (en) * 2000-02-02 2001-12-18 Honeywell International Inc. Tantalum sputtering target with fine grains and uniform texture and method of manufacture
KR100853743B1 (en) * 2001-07-19 2008-08-25 허니웰 인터내셔널 인코포레이티드 Sputtering Targets, Sputter Reactors, Methods of Forming Cast Ingots, and Methods of Forming Metallic Articles
EP1471164B1 (en) * 2002-01-30 2013-01-23 JX Nippon Mining & Metals Corporation Copper alloy sputtering target and method for manufacturing the target
US20030145681A1 (en) * 2002-02-05 2003-08-07 El-Shall M. Samy Copper and/or zinc alloy nanopowders made by laser vaporization and condensation
US6683425B1 (en) * 2002-02-05 2004-01-27 Novellus Systems, Inc. Null-field magnetron apparatus with essentially flat target
US6958290B2 (en) * 2002-05-03 2005-10-25 Texas Instruments Incorporated Method and apparatus for improving adhesion between layers in integrated devices
JP4794802B2 (en) * 2002-11-21 2011-10-19 Jx日鉱日石金属株式会社 Copper alloy sputtering target and semiconductor device wiring
CN100439558C (en) * 2003-03-17 2008-12-03 日矿金属株式会社 Copper alloy sputtering target process for producing the same and semiconductor element wiring
CN100451161C (en) * 2005-09-07 2009-01-14 铼宝科技股份有限公司 Conductive membrane or its protective layer used alloy target material and manufacture thereof
US8691867B2 (en) * 2005-12-19 2014-04-08 Janssen Pharmaceutica Nv Use of benzo-fused heterocycle sulfamide derivatives for the treatment of substance abuse and addiction
US20070251818A1 (en) * 2006-05-01 2007-11-01 Wuwen Yi Copper physical vapor deposition targets and methods of making copper physical vapor deposition targets
JP5420328B2 (en) * 2008-08-01 2014-02-19 三菱マテリアル株式会社 Sputtering target for forming wiring films for flat panel displays
CN104694888B (en) * 2013-12-09 2017-05-10 有研亿金新材料股份有限公司 Preparation method of high-purity copper target
US9962914B2 (en) 2016-01-21 2018-05-08 King Abdulaziz University Method for transferring a large-area graphene sheet
CN112410742A (en) * 2020-10-30 2021-02-26 东莞市烽元科技有限公司 In Al2O3Method for plating nano-scale copper film on surface of ceramic substrate by magnetron sputtering
CN115233157A (en) * 2022-06-14 2022-10-25 沈阳大学 Method for preparing copper film on surface of zinc and zinc alloy through magnetron sputtering

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE299234C (en) *
US4094761A (en) 1977-07-25 1978-06-13 Motorola, Inc. Magnetion sputtering of ferromagnetic material
DE3142541C2 (en) 1981-10-27 1986-07-31 Demetron Gesellschaft für Elektronik-Werkstoffe mbH, 6540 Hanau Multi-component alloy for targets in cathode sputtering systems
US4620872A (en) 1984-10-18 1986-11-04 Mitsubishi Kinzoku Kabushiki Kaisha Composite target material and process for producing the same
FR2601175B1 (en) 1986-04-04 1993-11-12 Seiko Epson Corp CATHODE SPRAYING TARGET AND RECORDING MEDIUM USING SUCH A TARGET.
DE3631830A1 (en) 1986-09-19 1988-03-31 Demetron MULTI-MATERIAL ALLOY FOR TARGETS OF CATHODE SPRAYING SYSTEMS AND THEIR USE
US4885029A (en) 1987-03-09 1989-12-05 Scm Metal Products, Inc. Thin section dispersion strengthened copper body and method of making same
JP2602276B2 (en) * 1987-06-30 1997-04-23 株式会社日立製作所 Sputtering method and apparatus
JP2511289B2 (en) * 1988-03-30 1996-06-26 株式会社日立製作所 Semiconductor device
JPH03289156A (en) 1990-04-06 1991-12-19 Hitachi Ltd Semiconductor device and manufacture thereof
US5039570A (en) 1990-04-12 1991-08-13 Planar Circuit Technologies, Inc. Resistive laminate for printed circuit boards, method and apparatus for forming the same
US5178739A (en) * 1990-10-31 1993-01-12 International Business Machines Corporation Apparatus for depositing material into high aspect ratio holes
US5130274A (en) * 1991-04-05 1992-07-14 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
FR2698882B1 (en) 1992-12-04 1995-02-03 Castolin Sa Method for forming a protective coating on a substrate.
JPH06177117A (en) * 1992-12-07 1994-06-24 Japan Energy Corp Sputter target and fabrication of semiconductor device employing it
EP0601509A1 (en) * 1992-12-07 1994-06-15 Nikko Kyodo Co., Ltd. Semiconductor devices and method of manufacturing the same
US5330629A (en) 1992-12-15 1994-07-19 At&T Bell Laboratories Method for depositing aluminum layers on insulating oxide substrates
US5551970A (en) 1993-08-17 1996-09-03 Otd Products L.L.C. Dispersion strengthened copper
US5590389A (en) 1994-12-23 1996-12-31 Johnson Matthey Electronics, Inc. Sputtering target with ultra-fine, oriented grains and method of making same
US5685491A (en) 1995-01-11 1997-11-11 Amtx, Inc. Electroformed multilayer spray director and a process for the preparation thereof
US5599740A (en) 1995-11-16 1997-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Deposit-etch-deposit ozone/teos insulator layer method
JPH09199976A (en) * 1996-01-18 1997-07-31 Hitachi Ltd Surface acoustic wave device
US5997699A (en) * 1996-04-08 1999-12-07 Micron Technology Inc. Insitu faceting during deposition
US5693565A (en) 1996-07-15 1997-12-02 Dow Corning Corporation Semiconductor chips suitable for known good die testing
US5686335A (en) 1996-07-22 1997-11-11 Taiwan Semiconductor Manufacturing Company, Ltd Method of making high-performance and reliable thin film transistor (TFT) using plasma hydrogenation with a metal shield on the TFT channel
US5803342A (en) 1996-12-26 1998-09-08 Johnson Matthey Electronics, Inc. Method of making high purity copper sputtering targets
US5801100A (en) 1997-03-07 1998-09-01 Industrial Technology Research Institute Electroless copper plating method for forming integrated circuit structures
US6387805B2 (en) * 1997-05-08 2002-05-14 Applied Materials, Inc. Copper alloy seed layer for copper metallization
US6037257A (en) * 1997-05-08 2000-03-14 Applied Materials, Inc. Sputter deposition and annealing of copper alloy metallization
JP3616724B2 (en) * 1997-09-25 2005-02-02 アルプス電気株式会社 Manufacturing method of semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004008491A2 (en) * 2002-07-15 2004-01-22 Aviza Technology, Inc. Thermal processing system and configurable vertical chamber
WO2004008491A3 (en) * 2002-07-15 2004-06-03 Aviza Tech Inc Thermal processing system and configurable vertical chamber
US20060083495A1 (en) * 2002-07-15 2006-04-20 Qiu Taiquing Variable heater element for low to high temperature ranges
US20070243317A1 (en) * 2002-07-15 2007-10-18 Du Bois Dale R Thermal Processing System and Configurable Vertical Chamber
US20040162029A1 (en) * 2002-07-17 2004-08-19 Jeff Grady Audio player assembly comprising an MP3 player
US20060030151A1 (en) * 2004-08-09 2006-02-09 Applied Materials, Inc. Sputter deposition and etching of metallization seed layer for overhang and sidewall improvement
US7294574B2 (en) * 2004-08-09 2007-11-13 Applied Materials, Inc. Sputter deposition and etching of metallization seed layer for overhang and sidewall improvement
CN112680626A (en) * 2020-12-09 2021-04-20 爱发科电子材料(苏州)有限公司 Preparation process of copper-aluminum-silicon alloy target material for integrated circuit

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KR20010087288A (en) 2001-09-15

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