US20020114144A1 - Molded flip chip package - Google Patents

Molded flip chip package Download PDF

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Publication number
US20020114144A1
US20020114144A1 US10/051,980 US5198002A US2002114144A1 US 20020114144 A1 US20020114144 A1 US 20020114144A1 US 5198002 A US5198002 A US 5198002A US 2002114144 A1 US2002114144 A1 US 2002114144A1
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United States
Prior art keywords
chip package
flip chip
substrate
chip
package
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Abandoned
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US10/051,980
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Takashi Kumamoto
Kinya Ichikawa
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Individual
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Individual
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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Definitions

  • the invention relates generally to the field of integrated circuit packaging. More particularly, the invention relates to an epoxy package that is formed in a single molding operation.
  • solder bumps are applied to pads on the active side of the chip, the substrate or both.
  • solder bumps are melted and permitted to flow, ensuring that the bumps are fully wetted to the corresponding pads on the chip or substrate.
  • a tacky flux is typically applied to one or both of the surfaces to be joined.
  • the flux-bearing surfaces of the chip and substrate are then placed in contact with each other in general alignment.
  • a reflow is performed by heating the chip and substrate package to or above the solder's melting point.
  • the solder on the chip and the substrate combine and the surface tension of the molten solder causes the corresponding pads to self-align with each other.
  • the joined package is then cooled to solidify the solder.
  • the resulting height of the solder interconnects is determined based on a balance between the surface tension of the molten solder columns and the weight of the chip. Any flux or flux residue is removed from the chip and substrate combination in a defluxing operation.
  • an epoxy underfill is applied between the bottom surface of the chip and the top surface of the substrate, surrounding and supporting the solder columns.
  • the reliability and fatigue resistance of the chip substrate solder connection is increased significantly.
  • the underfill acts to carry a significant portion of the thermal loads induced by coefficient of thermal expansion (CTE) differences between the chip and substrate, rather than having all the thermal load transferred through the solder columns.
  • CTE coefficient of thermal expansion
  • thin substrates or films are comprised of a polymeric material and are 0.05 to 0.5 mm thick.
  • a thin substrate's shorter vias help reduce loop inductance within the substrate.
  • these thin substrates are very flexible making it difficult to attach solder balls or pins thereto.
  • solder balls or pins are susceptible to damage during installation and removal operations.
  • the current practice is to bond rigid blocks of a suitable material to the periphery of the substrate to stiffen the entire package. The additional operation of bonding the rigid blocks to the thin substrate significantly increases the cost of the thin substrate package compared to a comparable package with a thicker substrate.
  • FIG. 1 A typical prior art chip package utilizing a thin substrate is illustrated in FIG. 1.
  • a silicon chip 110 is electrically coupled and joined to a thin substrate 120 by reflowed solder bumps 130 .
  • the chip package may also include various passive components 140 , such as resistors and capacitors, also electrically coupled to the substrate 120 .
  • An epoxy underfill 160 supplements the solder bump joint 130 between the chip 110 and the thin substrate 120 .
  • a solder 145 may also be present around each of the passive components.
  • stiffening blocks 150 comprising a suitable polymeric or ceramic or metal material are attached to the general periphery of the thin substrate 120 with an adhesive 155 to increase the overall rigidity of the package.
  • the thin substrate may have attached to its backside a ball grid array (BGA) or pin grid array (PGA) to facilitate attachment of the chip package with a circuit board.
  • BGA ball grid array
  • PGA pin grid array
  • FIG. 1 is an illustration of a prior art package wherein a thin substrate is utilized.
  • FIGS. 2 a - f are illustrations of a chip package after various operations have been performed including the finished chip package as shown in FIG. 2 f according to one embodiment.
  • FIG. 3 is a flow chart describing a method of fabricating a chip package according to one embodiment.
  • a molded chip package and a method for fabricating the molded chip package are described.
  • a single molding process is utilized to both underfill the silicon chip and provide structure to increase the rigidity of a chip package. Therefore, the number of operations to fabricate a chip package utilizing a thin substrate is decreased.
  • FIG. 3 is a flow chart listing the various operations that are performed in molding the chip package.
  • an incomplete chip package in which a chip and a substrate have been joined using a flip chip process such as illustrated in FIG. 2 a
  • the mold comprising both the bottom half 210 and the top half 220 may be comprised of any suitable material including various metals, plastics, ceramics and composites.
  • the mold should have sufficient rigidity to retain its form while an encapsulating resin is injected into the mold under pressure.
  • the bottom mold half 210 may be coated with a release agent or it may be covered in part with a release film.
  • FIG. 2 b illustrates a chip/substrate package placed in the bottom mold half 210 .
  • the top mold half 220 is placed over the chip/substrate package as shown in FIG. 2 c .
  • a runner 230 is formed at the intersection of both mold halves through which a resin may be injected. Very small air vents are also present in the mold, generally opposite the runner so that the displaced air within the mold can escape when displaced by injected resin.
  • a release film 240 may be utilized as a barrier between the mold cavity and the interior mold surfaces of the top mold half 220 .
  • Typical release films comprise fluorocarbon-based polymers and are typically 0.5 to 5 mils thick.
  • a release agent could be applied to the inner surface of the upper mold half 220 . Release agents are typically comprised of fluorocarbon polymers held in a liquid suspension that may be wiped onto a mold surface.
  • the fluorocarbon polymers may include reactive molecules that cross-link during a curing operation to create a continuous film on the mold surface.
  • the bottom surface of the chip 110 butts directly up against the mold surface of the top mold half 220 except for any applicable intervening layer of release film 240 .
  • This configuration ensures that the resin will not encapsulate the bottom surface of the chip 110 during molding, permitting Thermal Interface Materials or Integral Heat Spreaders to be attached directly to the chip, thereby maximizing potential heat transfer rates.
  • a resin is injected into the cavity under pressure through runner 230 to underfill the gap between the top surface of the chip 110 and the corresponding substrate surface, encapsulating the solder bumps 130 , as well as to form the structure necessary to stiffen the chip/substrate package.
  • the mold is designed such that when properly injected, the resin surrounding the chip 110 will have a thickness close to the height of the chip's bottom surface from the substrate surface. Furthermore, the resin will encapsulate much of the substrate's surface. It is this volume of resin once cured that provides for the necessary rigidity of the completed package.
  • the resin utilized will be an epoxy having high strength and good thermal properties, including resistance to the high temperatures that can be generated by an integrated chip during operation. Additionally, epoxies in the uncured liquid state have relatively low viscosities making them ideal for injection into close quarters such as the space between the chip and substrate surfaces. Other resins may be utilized as appropriate. Potential alternative resins include bismaleimides, polyesters, and thermoplastics.
  • Table 1 lists some of the properties of a desirable epoxy formulation.
  • CTE coefficient of thermal expansion
  • the difference in the coefficient of thermal expansion (CTE) between virgin unfilled epoxy and either a silicon chip or a reinforced plastic substrate will be significant.
  • CTE coefficient of thermal expansion
  • too much filler could cause the viscosity of the epoxy formulation to increase to a point where it is resistant to flow in the gap between the top of the chip 110 and the corresponding surface of the substrate 120 .
  • the filler has a higher modulus than the virgin epoxy, it acts to increase the stiffness of the cured epoxy formulation which results in greater rigidity for the resulting chip package.
  • the fillers may be microspheres or microballoons comprised of silica or glass.
  • microspheres or balloons may be made from other materials.
  • Microspheres and microballoons typically range in diameters from 30-200 microns although larger and smaller sizes are available, and are generally spherical or nearly spherical in shape. Microballoons are typically hollow, whereas, microspheres are typically solid. Either filler is commonly available from a number of suppliers.
  • an epoxy formulation that cures relatively quickly at an elevated temperature so that chip packages can be fabricated at production rates, but that has a relatively long pot life at room temperature or even slightly elevated temperatures so that the mixed epoxy and catalyst does not cure in the supply lines before being injected into the mold.
  • the resin may have a cure profile of approximately 120 seconds at 165C.
  • different cure profiles may be specified that provide suitable results.
  • certain thermoplastic resins may be utilized in the molding operation that do not have a cure temperature but rather melt at an elevated temperature and solidify when cooled.
  • the molding process would proceed, according to one embodiment, as generally described infra.
  • the mold is either heated to 165 degrees Celsius with the incomplete chip package contained therein, or the mold is maintained at 165 degrees Celsius and the incomplete package is inserted therein.
  • the epoxy resin is injected through runner 230 into the mold at a pressure of around 1-5 Mpa.
  • the resin may be preheated to an intermediate temperature to lower the viscosity of the resin and facilitate the resin transfer molding process.
  • the mold is held at 165 degrees Celsius for at least 120 seconds to fully cool the epoxy.
  • the mold is separated and the packaged chip, as depicted in FIG.
  • the molded flip chip package will be removed while the mold is hot so that the mold may immediately be refused to fabricate another package; however it is conceivable that the mold may be permitted to cool before removing the molded flip chip package. Finally, the excess solidified epoxy 255 from within the runner cavity is removed, resulting in a completed flip chip package.
  • the resin upon curing forms a monolithic structure 250 which is adhesively bonded to the chip and the substrate.
  • This structure 250 fills the gap between the top surface of the chip and the surface of the substrate, effectively encapsulating each of the solder bumps that electrically couple the chip 110 and substrate 120 together.
  • the monolithic structure 250 encapsulates most of the side surfaces of the chip 110 and most of the surface of the substrate, providing the necessary volume to provide sufficient rigidity to the resulting flip chip package.

Abstract

A method for producing a molded flip chip package is described. The incomplete flip chip package comprising a thin substrate and a silicon chip is placed in a mold. A resin, such as an epoxy, is injected into the mold filling the gap between the surface of the flip chip and the adjacent substrate. Additionally, a stiffening structure is formed to increase the overall rigidity of the thin substrate specifically and the package as a whole.

Description

    CROSS-REFERENCE TO RELATED APPLICAITONS
  • This application is a divisional of U.S. patent application Ser. No. 09/741,535 filed Dec. 19, 2000 and assigned to the assignee of the present application.[0001]
    • COPYRIGHT NOTICE
  • Contained herein is material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction of the patent disclosure by any person as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all rights to the copyright whatsoever. [0002]
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0003]
  • The invention relates generally to the field of integrated circuit packaging. More particularly, the invention relates to an epoxy package that is formed in a single molding operation. [0004]
  • 2. Description of the Related Art [0005]
  • Traditionally, semiconductor chips have been electrically coupled to electrical traces on a substrate via wire interconnects that are soldered on one end to the top active area of the chip and soldered to trace pads on the substrate that surround the chip on the other end. These types of interconnects are not particularly efficient, requiring space for both the surface area of the chip and a perimeter region for the trace pads, resulting in larger chip packages. To more efficiently utilize the substrate surface and facilitate smaller chip packages, the flip chip interconnection process was developed. Essentially, the active surface of the semiconductor chip is flipped over to face the substrate and the chip is soldered directly to trace pads located adjacent to the active surface. The result is a more compact and space-efficient package. [0006]
  • One of the most successful and effective methods of electrically connecting a flipped chip utilizes controlled-collapse chip connection technology (the C4 process developed by Intel Corporation of Santa Clara Calif.). First, solder bumps are applied to pads on the active side of the chip, the substrate or both. Next, the solder bumps are melted and permitted to flow, ensuring that the bumps are fully wetted to the corresponding pads on the chip or substrate. A tacky flux is typically applied to one or both of the surfaces to be joined. The flux-bearing surfaces of the chip and substrate are then placed in contact with each other in general alignment. A reflow is performed by heating the chip and substrate package to or above the solder's melting point. The solder on the chip and the substrate combine and the surface tension of the molten solder causes the corresponding pads to self-align with each other. The joined package is then cooled to solidify the solder. The resulting height of the solder interconnects is determined based on a balance between the surface tension of the molten solder columns and the weight of the chip. Any flux or flux residue is removed from the chip and substrate combination in a defluxing operation. Finally, an epoxy underfill is applied between the bottom surface of the chip and the top surface of the substrate, surrounding and supporting the solder columns. The reliability and fatigue resistance of the chip substrate solder connection is increased significantly. The underfill acts to carry a significant portion of the thermal loads induced by coefficient of thermal expansion (CTE) differences between the chip and substrate, rather than having all the thermal load transferred through the solder columns. [0007]
  • It is desirable in many integrated circuit applications to utilize as thin a substrate or film as possible to maximize the electrical performance of the resulting packaged chip. Typically, thin substrates or films are comprised of a polymeric material and are 0.05 to 0.5 mm thick. A thin substrate's shorter vias help reduce loop inductance within the substrate. Unfortunately, these thin substrates are very flexible making it difficult to attach solder balls or pins thereto. Furthermore, in unreinforced form they are susceptible to damage during installation and removal operations. The current practice is to bond rigid blocks of a suitable material to the periphery of the substrate to stiffen the entire package. The additional operation of bonding the rigid blocks to the thin substrate significantly increases the cost of the thin substrate package compared to a comparable package with a thicker substrate. [0008]
  • A typical prior art chip package utilizing a thin substrate is illustrated in FIG. 1. A [0009] silicon chip 110 is electrically coupled and joined to a thin substrate 120 by reflowed solder bumps 130. The chip package may also include various passive components 140, such as resistors and capacitors, also electrically coupled to the substrate 120. An epoxy underfill 160 supplements the solder bump joint 130 between the chip 110 and the thin substrate 120. A solder 145 may also be present around each of the passive components. Finally, stiffening blocks 150 comprising a suitable polymeric or ceramic or metal material are attached to the general periphery of the thin substrate 120 with an adhesive 155 to increase the overall rigidity of the package. Although not shown, the thin substrate may have attached to its backside a ball grid array (BGA) or pin grid array (PGA) to facilitate attachment of the chip package with a circuit board.
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: [0010]
  • FIG. 1 is an illustration of a prior art package wherein a thin substrate is utilized. [0011]
  • FIGS. 2[0012] a-f are illustrations of a chip package after various operations have been performed including the finished chip package as shown in FIG. 2f according to one embodiment.
  • FIG. 3 is a flow chart describing a method of fabricating a chip package according to one embodiment. [0013]
    • DETAILED DESCRIPTION OF THE INVENTION
  • A molded chip package and a method for fabricating the molded chip package are described. In described embodiments, a single molding process is utilized to both underfill the silicon chip and provide structure to increase the rigidity of a chip package. Therefore, the number of operations to fabricate a chip package utilizing a thin substrate is decreased. [0014]
  • FIGS. 2[0015] a-2 f illustrate a chip package after various operations according to a one embodiment have been performed. FIG. 3 is a flow chart listing the various operations that are performed in molding the chip package. In block 310, an incomplete chip package in which a chip and a substrate have been joined using a flip chip process, such as illustrated in FIG. 2a, is placed in a bottom mold half 210. The mold comprising both the bottom half 210 and the top half 220 may be comprised of any suitable material including various metals, plastics, ceramics and composites. The mold should have sufficient rigidity to retain its form while an encapsulating resin is injected into the mold under pressure. The bottom mold half 210 may be coated with a release agent or it may be covered in part with a release film. FIG. 2b illustrates a chip/substrate package placed in the bottom mold half 210.
  • In [0016] block 315, the top mold half 220 is placed over the chip/substrate package as shown in FIG. 2c. A runner 230 is formed at the intersection of both mold halves through which a resin may be injected. Very small air vents are also present in the mold, generally opposite the runner so that the displaced air within the mold can escape when displaced by injected resin. A release film 240 may be utilized as a barrier between the mold cavity and the interior mold surfaces of the top mold half 220. Typical release films comprise fluorocarbon-based polymers and are typically 0.5 to 5 mils thick. Alternatively, a release agent could be applied to the inner surface of the upper mold half 220. Release agents are typically comprised of fluorocarbon polymers held in a liquid suspension that may be wiped onto a mold surface. The fluorocarbon polymers may include reactive molecules that cross-link during a curing operation to create a continuous film on the mold surface.
  • According to one embodiment, the bottom surface of the [0017] chip 110 butts directly up against the mold surface of the top mold half 220 except for any applicable intervening layer of release film 240. This configuration ensures that the resin will not encapsulate the bottom surface of the chip 110 during molding, permitting Thermal Interface Materials or Integral Heat Spreaders to be attached directly to the chip, thereby maximizing potential heat transfer rates.
  • Next, in [0018] block 320 as shown in FIG. 2d, a resin is injected into the cavity under pressure through runner 230 to underfill the gap between the top surface of the chip 110 and the corresponding substrate surface, encapsulating the solder bumps 130, as well as to form the structure necessary to stiffen the chip/substrate package. Typically, the mold is designed such that when properly injected, the resin surrounding the chip 110 will have a thickness close to the height of the chip's bottom surface from the substrate surface. Furthermore, the resin will encapsulate much of the substrate's surface. It is this volume of resin once cured that provides for the necessary rigidity of the completed package.
  • Typically, the resin utilized will be an epoxy having high strength and good thermal properties, including resistance to the high temperatures that can be generated by an integrated chip during operation. Additionally, epoxies in the uncured liquid state have relatively low viscosities making them ideal for injection into close quarters such as the space between the chip and substrate surfaces. Other resins may be utilized as appropriate. Potential alternative resins include bismaleimides, polyesters, and thermoplastics. [0019]
  • Table 1 lists some of the properties of a desirable epoxy formulation. In general, the difference in the coefficient of thermal expansion (CTE) between virgin unfilled epoxy and either a silicon chip or a reinforced plastic substrate will be significant. Given the wide range of operating temperatures that a flip chip package is likely to experience, it is desirable to tailor the CTE's of the joined materials to be as close as possible, thereby minimizing any induced thermal stresses. Conversely, too much filler could cause the viscosity of the epoxy formulation to increase to a point where it is resistant to flow in the gap between the top of the [0020] chip 110 and the corresponding surface of the substrate 120. Additionally, if the filler has a higher modulus than the virgin epoxy, it acts to increase the stiffness of the cured epoxy formulation which results in greater rigidity for the resulting chip package.
  • The fillers may be microspheres or microballoons comprised of silica or glass. In certain embodiments, microspheres or balloons may be made from other materials. Microspheres and microballoons typically range in diameters from 30-200 microns although larger and smaller sizes are available, and are generally spherical or nearly spherical in shape. Microballoons are typically hollow, whereas, microspheres are typically solid. Either filler is commonly available from a number of suppliers. [0021]
    TABLE 1
    Filler material Silica
    Filler shape All Spherical
    Filler content   80 wt %
    Mean particle size   4 um
    Maximum particle size   12 um
    Curing condition  165 C./120 sec
    Spiral flow  180 cm at 165 C./120 sec, 6.9 N/mm2
    Gelation time   30 sec at 165 C.
    Hot hardness   85 at 165 C./120 sec
    Melt viscosity
      10 Pa*s at 165 C.
    Glass transition temperature  145 deg C.
    CTE below Tg   14 ppm
    CTE above Tg   56 ppm
    Specific gravity   1.88 at 25 C.
    Thermal conductivity   0.63 W/m*C
    Flexural modulus 13700 N/mm2 at 25 C.
    Flexural strength  120 N/mm2 at 25 C.
    Volume resistivity   1.00E + 14 ohm*m 25 C.
    Water absorption   0.5%
  • It is also desirable to have an epoxy formulation that cures relatively quickly at an elevated temperature so that chip packages can be fabricated at production rates, but that has a relatively long pot life at room temperature or even slightly elevated temperatures so that the mixed epoxy and catalyst does not cure in the supply lines before being injected into the mold. The resin may have a cure profile of approximately 120 seconds at 165C. Depending on the properties of an alternative resin formulation, different cure profiles may be specified that provide suitable results. It is also contemplated that certain thermoplastic resins may be utilized in the molding operation that do not have a cure temperature but rather melt at an elevated temperature and solidify when cooled. [0022]
  • Utilizing an epoxy resin of the type and formulation specified in table 1, the molding process would proceed, according to one embodiment, as generally described infra. First, the mold is either heated to 165 degrees Celsius with the incomplete chip package contained therein, or the mold is maintained at 165 degrees Celsius and the incomplete package is inserted therein. Next, the epoxy resin is injected through [0023] runner 230 into the mold at a pressure of around 1-5 Mpa. The resin may be preheated to an intermediate temperature to lower the viscosity of the resin and facilitate the resin transfer molding process. Once the proper amount of epoxy is injected into the mold cavity, the mold is held at 165 degrees Celsius for at least 120 seconds to fully cool the epoxy. After cure, the mold is separated and the packaged chip, as depicted in FIG. 2e, is removed. Typically, the molded flip chip package will be removed while the mold is hot so that the mold may immediately be refused to fabricate another package; however it is conceivable that the mold may be permitted to cool before removing the molded flip chip package. Finally, the excess solidified epoxy 255 from within the runner cavity is removed, resulting in a completed flip chip package.
  • The resin upon curing forms a [0024] monolithic structure 250 which is adhesively bonded to the chip and the substrate. This structure 250 fills the gap between the top surface of the chip and the surface of the substrate, effectively encapsulating each of the solder bumps that electrically couple the chip 110 and substrate 120 together. Furthermore, the monolithic structure 250 encapsulates most of the side surfaces of the chip 110 and most of the surface of the substrate, providing the necessary volume to provide sufficient rigidity to the resulting flip chip package.
  • In the foregoing description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of the present invention. The invention is, however, not limited to the described embodiments alone. In this vein, the detailed description provided herein is not intended to limit the scope of the invention as claimed. To the contrary, embodiments of the claims have been contemplated that encompass the full breadth of the claim language as would be obvious to one of ordinary skill in the art. Accordingly, the present invention may be practiced without some of the specific detail provided supra. [0025]

Claims (13)

What is claimed is:
1. A flip chip package comprising:
a chip, the chip comprising a top surface, a bottom surface and one or more side surfaces disposed between the top and bottom surfaces;
a substrate, the substrate comprising an upper surface;
a plurality of reflowed solder bumps, the reflowed solder bumps electrically coupling the top surface with an adjacent portion of the upper surface; and
a monolithic element comprising solidified resin, the monolithic element encapsulating and adhesively bonded to (i) substantially all of the one or more side surfaces, (ii) a substantial portion of the upper surface, and (iii) the plurality of reflowed solder bumps located in a gap between the top surface and the upper surface.
2. The flip chip package of claim 1, wherein the solidified resin does not encapsulate the bottom surface.
3. The flip chip package of claim 2, wherein the resin further comprises a filler material.
4. The flip chip package of claim 3, wherein the filler material comprises silica micro spheres.
5. The flip chip package of claim 1, wherein the resin encapsulates substantially all of the one or more side surfaces.
6. The flip chip package of claim 5, wherein the resin does not encapsulate the bottom surface.
7. The flip chip package of the claim 1, wherein the solidified resin comprises an epoxy.
8. The flip chip package of claim 1, wherein the substrate is a thin substrate.
9. The flip chip package of claim 1, wherein the substrate is comprised of a polymeric material.
10. The flip chip package of claim 8, wherein the substrate is approximately 0.05 mm to 0.5 mm thick.
11. The flip chip package of claim 1, further comprising at least one passive component electrically coupled with the substrate.
12. The flip chip package of claim 11, wherein the solidified resin fills a gap between a first surface of the at least one passive component and an adjacent surface of the substrate.
13. The flip chip package of claim 11, wherein the solidified resin fully encapsulates the at least one passive component.
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020110956A1 (en) * 2000-12-19 2002-08-15 Takashi Kumamoto Chip lead frames
US20030168731A1 (en) * 2002-03-11 2003-09-11 Matayabas James Christopher Thermal interface material and method of fabricating the same
US20060292756A1 (en) * 2005-06-24 2006-12-28 Cardiac Pacemakers, Inc. Flip chip die assembly using thin flexible substrates
US20080284047A1 (en) * 2007-05-15 2008-11-20 Eric Tosaya Chip Package with Stiffener Ring
US20090200659A1 (en) * 2008-02-11 2009-08-13 Eric Tosaya Chip Package with Channel Stiffener Frame
US20090236730A1 (en) * 2008-03-19 2009-09-24 Roden Topacio Die substrate with reinforcement structure
US20100052188A1 (en) * 2008-08-26 2010-03-04 Mohammad Khan Semiconductor Chip with Solder Joint Protection Ring
US20100276799A1 (en) * 2009-05-04 2010-11-04 Heng Stephen F Semiconductor Chip Package with Stiffener Frame and Configured Lid
US20110100692A1 (en) * 2009-11-02 2011-05-05 Roden Topacio Circuit Board with Variable Topography Solder Interconnects
US8232138B2 (en) 2010-04-14 2012-07-31 Advanced Micro Devices, Inc. Circuit board with notched stiffener frame
US9867282B2 (en) 2013-08-16 2018-01-09 Ati Technologies Ulc Circuit board with corner hollows

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7078109B2 (en) * 2000-02-25 2006-07-18 Thermagon Inc. Heat spreading thermal interface structure
FR2820240B1 (en) * 2001-01-26 2004-07-16 St Microelectronics Sa CHIP SUPPORT SUBSTRATE WITH INTEGRATED CIRCUITS SUITABLE FOR PLACEMENT IN A MOLD
JP3839323B2 (en) * 2001-04-06 2006-11-01 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
DE10250541B9 (en) * 2002-10-29 2004-09-16 Infineon Technologies Ag Electronic component with underfill materials made of thermoplastics and process for its production
US20040119151A1 (en) * 2002-12-20 2004-06-24 Intel Corporation Pre-applied underfill
US20040212080A1 (en) * 2003-04-22 2004-10-28 Kai-Chi Chen [chip package structure and process for fabricating the same]
US20050093181A1 (en) * 2003-11-04 2005-05-05 Brandenburg Scott D. Heat sinkable package
US7495344B2 (en) * 2004-03-18 2009-02-24 Sanyo Electric Co., Ltd. Semiconductor apparatus
SG145547A1 (en) * 2004-07-23 2008-09-29 Micron Technology Inc Microelectronic component assemblies with recessed wire bonds and methods of making same
US7445141B2 (en) * 2004-09-22 2008-11-04 International Business Machines Corporation Solder interconnection array with optimal mechanical integrity
TW200612345A (en) * 2004-10-07 2006-04-16 Advanced Flash Memory Card Technology Co Ltd Structure of memory card and producing method thereof
JP2006269486A (en) * 2005-03-22 2006-10-05 Renesas Technology Corp Method for manufacturing semiconductor apparatus
KR20080021703A (en) * 2005-06-29 2008-03-07 코닌클리케 필립스 일렉트로닉스 엔.브이. Method of manufacturing an assembly and assembly
DE112005003634T5 (en) * 2005-08-04 2008-06-12 Infineon Technologies Ag An integrated circuit device and method for forming an integrated circuit device
TWI324378B (en) * 2005-10-21 2010-05-01 Freescale Semiconductor Inc Method of making semiconductor package with reduced moisture sensitivity
TWI303870B (en) * 2005-12-30 2008-12-01 Advanced Semiconductor Eng Structure and mtehod for packaging a chip
DE102006022748B4 (en) * 2006-05-12 2019-01-17 Infineon Technologies Ag Semiconductor device with surface mount devices and method of making the same
US7682874B2 (en) * 2006-07-10 2010-03-23 Shanghai Kaihong Technology Co., Ltd. Chip scale package (CSP) assembly apparatus and method
US20080157300A1 (en) * 2006-12-27 2008-07-03 Shih-Fang Chuang Thermally Enhanced IC Package and Method
US8273603B2 (en) * 2008-04-04 2012-09-25 The Charles Stark Draper Laboratory, Inc. Interposers, electronic modules, and methods for forming the same
US8017451B2 (en) 2008-04-04 2011-09-13 The Charles Stark Draper Laboratory, Inc. Electronic modules and methods for forming the same
US8541263B1 (en) * 2008-08-22 2013-09-24 Altera Corporation Thermoset molding for on-package decoupling in flip chips
US20100209670A1 (en) * 2009-02-17 2010-08-19 Nitto Denko Corporation Sheet for photosemiconductor encapsulation
US8273607B2 (en) 2010-06-18 2012-09-25 Stats Chippac Ltd. Integrated circuit packaging system with encapsulation and underfill and method of manufacture thereof
US20120098114A1 (en) * 2010-10-21 2012-04-26 Nokia Corporation Device with mold cap and method thereof
US8293572B2 (en) * 2011-01-20 2012-10-23 ADL Engineering Inc. Injection molding system and method of chip package
US9190297B2 (en) 2011-08-11 2015-11-17 Stats Chippac, Ltd. Semiconductor device and method of forming a stackable semiconductor package with vertically-oriented discrete electrical devices as interconnect structures
US8859342B2 (en) 2011-12-14 2014-10-14 Stats Chippac Ltd. Integrated circuit packaging system with substrate mold gate and method of manufacture thereof
US8962392B2 (en) * 2012-03-13 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill curing method using carrier
US10128175B2 (en) * 2013-01-29 2018-11-13 Taiwan Semiconductor Manufacturing Company Packaging methods and packaged semiconductor devices
US9196575B1 (en) 2013-02-04 2015-11-24 Altera Corporation Integrated circuit package with cavity in substrate
KR102084542B1 (en) 2013-08-14 2020-03-04 삼성전자주식회사 Semiconductor package
US9793242B2 (en) * 2013-12-30 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with die stack including exposed molding underfill
KR102253552B1 (en) 2014-03-28 2021-05-18 인텔 코포레이션 Anchored interconnect
US9515011B2 (en) 2014-05-28 2016-12-06 Cree, Inc. Over-mold plastic packaged wide band-gap power transistors and MMICS
US9641163B2 (en) 2014-05-28 2017-05-02 Cree, Inc. Bandwidth limiting methods for GaN power transistors
US9472480B2 (en) * 2014-05-28 2016-10-18 Cree, Inc. Over-mold packaging for wide band-gap semiconductor devices
US9704767B1 (en) 2015-12-23 2017-07-11 Intel Corporation Mold compound with reinforced fibers
US20200006207A1 (en) * 2017-02-17 2020-01-02 Sony Semiconductor Solutions Corporation Semiconductor device, chip-shaped semiconductor element, electronic device provided with semiconductor device, and method of manufacturing semiconductor device
US10804217B2 (en) 2018-08-10 2020-10-13 STATS ChipPAC Pte. Ltd. EMI shielding for flip chip package with exposed die backside
US11355452B2 (en) 2018-08-10 2022-06-07 STATS ChipPAC Pte. Ltd. EMI shielding for flip chip package with exposed die backside
US10950519B2 (en) 2019-05-31 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
DE102022108571A1 (en) * 2022-04-08 2023-10-12 Ams-Osram International Gmbh COMPOSITION, METHOD FOR CONNECTING A SUPPORT AND AN ELECTRONIC COMPONENT AND ELECTRONIC COMPONENT

Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5196917A (en) * 1989-08-22 1993-03-23 Mitsubishi Denki Kabushiki Kaisha Carrier tape
US5450283A (en) * 1992-11-03 1995-09-12 Motorola, Inc. Thermally enhanced semiconductor device having exposed backside and method for making the same
US5542171A (en) * 1991-10-04 1996-08-06 Motorola, Inc. Method of selectively releasing plastic molding material from a surface
US5620928A (en) * 1995-05-11 1997-04-15 National Semiconductor Corporation Ultra thin ball grid array using a flex tape or printed wiring board substrate and method
US5635671A (en) * 1994-03-16 1997-06-03 Amkor Electronics, Inc. Mold runner removal from a substrate-based packaged electronic device
US5656549A (en) * 1996-08-19 1997-08-12 Motorola, Inc. Method of packaging a semiconductor device
US5780933A (en) * 1995-05-12 1998-07-14 Kabushiki Kaisha Toshiba Substrate for semiconductor device and semiconductor device using the same
US5784261A (en) * 1995-02-03 1998-07-21 Plessey Semiconductors Limited Microchip module assemblies
US5895229A (en) * 1997-05-19 1999-04-20 Motorola, Inc. Microelectronic package including a polymer encapsulated die, and method for forming same
US5969427A (en) * 1998-02-05 1999-10-19 Micron Technology, Inc. Use of an oxide surface to facilitate gate break on a carrier substrate for a semiconductor device
US5981312A (en) * 1997-06-27 1999-11-09 International Business Machines Corporation Method for injection molded flip chip encapsulation
US5981314A (en) * 1996-10-31 1999-11-09 Amkor Technology, Inc. Near chip size integrated circuit package
US5998243A (en) * 1997-10-15 1999-12-07 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device and apparatus for resin-encapsulating
US6017755A (en) * 1996-08-22 2000-01-25 Hsc Research & Development Limited MADR2 tumour suppressor gene
US6049122A (en) * 1997-10-16 2000-04-11 Fujitsu Limited Flip chip mounting substrate with resin filled between substrate and semiconductor chip
US6048483A (en) * 1996-07-23 2000-04-11 Apic Yamada Corporation Resin sealing method for chip-size packages
US6081997A (en) * 1997-08-14 2000-07-04 Lsi Logic Corporation System and method for packaging an integrated circuit using encapsulant injection
US6083775A (en) * 1998-02-07 2000-07-04 Siliconware Precision Industries Co., Ltd. Method of encapsulating a chip
US6187243B1 (en) * 1997-07-11 2001-02-13 Apic Yamada Corporation Method of resin molding
US6344162B1 (en) * 1998-07-10 2002-02-05 Apic Yamada Corporation Method of manufacturing semiconductor devices and resin molding machine
US6373125B1 (en) * 2000-02-23 2002-04-16 International Business Machines Corporation Chip scale package with direct attachment of chip to lead frame
US6413801B1 (en) * 2000-05-02 2002-07-02 Advanced Semiconductor Engineering, Inc. Method of molding semiconductor device and molding die for use therein
US6432751B1 (en) * 1997-04-11 2002-08-13 Matsushita Electric Industrial Co., Ltd. Resin mold electric part and producing method therefor
US6498054B1 (en) * 2000-06-02 2002-12-24 Siliconware Precision Industries Co., Ltd. Method of underfilling a flip-chip semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208756A (en) 1983-05-12 1984-11-27 Sony Corp Manufacture of semiconductor device package
JP3400877B2 (en) * 1994-12-14 2003-04-28 三菱電機株式会社 Semiconductor device and manufacturing method thereof
GB2297652B (en) 1995-02-03 1999-03-31 Plessey Semiconductors Ltd Microchip module assemblies
US6038136A (en) * 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
JPH11195742A (en) 1998-01-05 1999-07-21 Matsushita Electron Corp Semiconductor device, manufacture thereof, and led frame therefor
JP3436159B2 (en) 1998-11-11 2003-08-11 松下電器産業株式会社 Method for manufacturing resin-encapsulated semiconductor device
JP2000294692A (en) * 1999-04-06 2000-10-20 Hitachi Ltd Resin-sealing type electronic device and manufacture of the same, ignition coil for internal combustion engine using the same device

Patent Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5196917A (en) * 1989-08-22 1993-03-23 Mitsubishi Denki Kabushiki Kaisha Carrier tape
US5542171A (en) * 1991-10-04 1996-08-06 Motorola, Inc. Method of selectively releasing plastic molding material from a surface
US5450283A (en) * 1992-11-03 1995-09-12 Motorola, Inc. Thermally enhanced semiconductor device having exposed backside and method for making the same
US5635671A (en) * 1994-03-16 1997-06-03 Amkor Electronics, Inc. Mold runner removal from a substrate-based packaged electronic device
US5784261A (en) * 1995-02-03 1998-07-21 Plessey Semiconductors Limited Microchip module assemblies
US5620928A (en) * 1995-05-11 1997-04-15 National Semiconductor Corporation Ultra thin ball grid array using a flex tape or printed wiring board substrate and method
US5780933A (en) * 1995-05-12 1998-07-14 Kabushiki Kaisha Toshiba Substrate for semiconductor device and semiconductor device using the same
US6048483A (en) * 1996-07-23 2000-04-11 Apic Yamada Corporation Resin sealing method for chip-size packages
US5656549A (en) * 1996-08-19 1997-08-12 Motorola, Inc. Method of packaging a semiconductor device
US6017755A (en) * 1996-08-22 2000-01-25 Hsc Research & Development Limited MADR2 tumour suppressor gene
US5981314A (en) * 1996-10-31 1999-11-09 Amkor Technology, Inc. Near chip size integrated circuit package
US6432751B1 (en) * 1997-04-11 2002-08-13 Matsushita Electric Industrial Co., Ltd. Resin mold electric part and producing method therefor
US5895229A (en) * 1997-05-19 1999-04-20 Motorola, Inc. Microelectronic package including a polymer encapsulated die, and method for forming same
US5981312A (en) * 1997-06-27 1999-11-09 International Business Machines Corporation Method for injection molded flip chip encapsulation
US6187243B1 (en) * 1997-07-11 2001-02-13 Apic Yamada Corporation Method of resin molding
US6081997A (en) * 1997-08-14 2000-07-04 Lsi Logic Corporation System and method for packaging an integrated circuit using encapsulant injection
US5998243A (en) * 1997-10-15 1999-12-07 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device and apparatus for resin-encapsulating
US6049122A (en) * 1997-10-16 2000-04-11 Fujitsu Limited Flip chip mounting substrate with resin filled between substrate and semiconductor chip
US5969427A (en) * 1998-02-05 1999-10-19 Micron Technology, Inc. Use of an oxide surface to facilitate gate break on a carrier substrate for a semiconductor device
US6083775A (en) * 1998-02-07 2000-07-04 Siliconware Precision Industries Co., Ltd. Method of encapsulating a chip
US6344162B1 (en) * 1998-07-10 2002-02-05 Apic Yamada Corporation Method of manufacturing semiconductor devices and resin molding machine
US6373125B1 (en) * 2000-02-23 2002-04-16 International Business Machines Corporation Chip scale package with direct attachment of chip to lead frame
US6413801B1 (en) * 2000-05-02 2002-07-02 Advanced Semiconductor Engineering, Inc. Method of molding semiconductor device and molding die for use therein
US6498054B1 (en) * 2000-06-02 2002-12-24 Siliconware Precision Industries Co., Ltd. Method of underfilling a flip-chip semiconductor device

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020110956A1 (en) * 2000-12-19 2002-08-15 Takashi Kumamoto Chip lead frames
US20030168731A1 (en) * 2002-03-11 2003-09-11 Matayabas James Christopher Thermal interface material and method of fabricating the same
US7497911B2 (en) 2005-06-24 2009-03-03 Cardiac Pacemakers, Inc. Flip chip die assembly using thin flexible substrates
US20060290007A1 (en) * 2005-06-24 2006-12-28 Cardiac Pacemakers, Inc. Flip Chip Die Assembly Using Thin Flexible Substrates
US7226821B2 (en) 2005-06-24 2007-06-05 Cardiac Pacemakers, Inc. Flip chip die assembly using thin flexible substrates
US20060292756A1 (en) * 2005-06-24 2006-12-28 Cardiac Pacemakers, Inc. Flip chip die assembly using thin flexible substrates
US20080284047A1 (en) * 2007-05-15 2008-11-20 Eric Tosaya Chip Package with Stiffener Ring
US20090200659A1 (en) * 2008-02-11 2009-08-13 Eric Tosaya Chip Package with Channel Stiffener Frame
US8008133B2 (en) 2008-02-11 2011-08-30 Globalfoundries Inc. Chip package with channel stiffener frame
US8405187B2 (en) 2008-02-11 2013-03-26 Globalfoundries Inc. Chip package with channel stiffener frame
US8313984B2 (en) 2008-03-19 2012-11-20 Ati Technologies Ulc Die substrate with reinforcement structure
US20090236730A1 (en) * 2008-03-19 2009-09-24 Roden Topacio Die substrate with reinforcement structure
US8927344B2 (en) 2008-03-19 2015-01-06 Ati Technologies Ulc Die substrate with reinforcement structure
US20100052188A1 (en) * 2008-08-26 2010-03-04 Mohammad Khan Semiconductor Chip with Solder Joint Protection Ring
US7923850B2 (en) 2008-08-26 2011-04-12 Advanced Micro Devices, Inc. Semiconductor chip with solder joint protection ring
US20100276799A1 (en) * 2009-05-04 2010-11-04 Heng Stephen F Semiconductor Chip Package with Stiffener Frame and Configured Lid
US8216887B2 (en) 2009-05-04 2012-07-10 Advanced Micro Devices, Inc. Semiconductor chip package with stiffener frame and configured lid
US20110100692A1 (en) * 2009-11-02 2011-05-05 Roden Topacio Circuit Board with Variable Topography Solder Interconnects
US8232138B2 (en) 2010-04-14 2012-07-31 Advanced Micro Devices, Inc. Circuit board with notched stiffener frame
US9867282B2 (en) 2013-08-16 2018-01-09 Ati Technologies Ulc Circuit board with corner hollows

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US6632704B2 (en) 2003-10-14
US20020109241A1 (en) 2002-08-15
US20040053443A1 (en) 2004-03-18

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