US20020186554A1 - Method for manufacturing a scalable high frequency integrated circuit package - Google Patents
Method for manufacturing a scalable high frequency integrated circuit package Download PDFInfo
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- US20020186554A1 US20020186554A1 US10/217,588 US21758802A US2002186554A1 US 20020186554 A1 US20020186554 A1 US 20020186554A1 US 21758802 A US21758802 A US 21758802A US 2002186554 A1 US2002186554 A1 US 2002186554A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Definitions
- the present invention relates generally to information processing systems and more particularly to a methodology and implementation for signal transmission in an integrated circuit carrier package.
- a plane of signal lines is defined on a SIG plane that is positioned or “sandwiched” between a GND plane and a voltage VDD plane.
- the semiconductor chip sits on top at the center of the package.
- the signal lines radiate outwardly from the chip area and connect to the card area below the carrier “sandwich” which is made up of the three reference planes.
- De-coupling capacitors on the chip and the chip carrier between VDD and GND supply the electrical charge current at the low source inductance needed to drive fast transitions into the signal lines at the chip source end. While this construction has been satisfactory in the past, increasing operating frequencies of systems and chips has created problems with regard to signal isolation and noise immunity.
- a method and implementing system are provided in which a tri-plate structure is arranged to include three substrate layers surrounding an integrated circuit chip which is mounted thereon.
- the tri-plate structure includes a middle or signal layer, a first outer layer or top layer, and a second outer layer or bottom layer.
- the first and second outer layers are positioned on each side of the signal layer.
- the three layers are arranged on electrically insulative material and the three layers are sandwiched together to form a chip carrier.
- the chip is mounted on the middle layer or signal (SIG) layer and extends through an opening in the top layer.
- the middle signal layer includes bundles or groups of printed circuit conductors or lines to carry signals between the chip and the edges of the carrier device.
- the first outer layer includes electrically isolated and separate conducting areas or segments which are held at different system potentials, for example at ground (GND) and VDD power potential levels.
- the separate conducting areas on the top layer are separated by air gaps or by insulative material to provide adequate electrical isolation.
- the separate areas are arranged on the first outer layer relative to the signal conductors in the middle layer such that signal lines from the chip to the outer edges of the chip carrier in the middle layer are positioned under areas of ground potential in the first outer layer and above the grounded second outer layer which is positioned below the signal layer in the carrier device.
- each group of signal conductors in the middle layer between the chip and the outer edges of the carrier have a ground potential area or segment above each signal conductor group and also a ground potential layer below each signal conductor group.
- the tri-plate structure thus formed provides system electromagnetic radiation isolation and enhanced noise isolation and signal integrity.
- ground areas in the top layer are connected to the bottom ground potential layer through vias which pass through the middle layer. Also, vias are used to connect de-coupling capacitors between VDD areas in the top layer and the ground potential bottom layer.
- FIG. 1 is a schematic diagram of a prior art arrangement of reference voltage planes in a chip carrier
- FIG. 2 is a schematic diagram of an exemplary carrier design showing a planar layout with separated areas for different potentials in the same plane in accordance with the present invention
- FIG. 3 is an illustration showing another exemplary carrier design showing a planar layout with separated areas for different potentials in the same plane in accordance with the present invention
- FIG. 4 is a perspective view of the chip carrier arrangement shown in FIG. 2;
- FIG. 5 is an illustration showing details of the middle layer of the tri-plate chip carrier package illustrated in FIG. 4.
- a typical prior art arrangement of reference planes in a chip carrier package includes a SIG plane 103 positioned between a VDD reference plane 101 and a GND reference plane 105 .
- the Sig plane 103 includes signal lines for conducting signals between drivers and receivers which are included within an integrated circuit or chip mounted on the carrier and also to receivers mounted on other carriers in an electronic system.
- the power plane is maintained at a reference VDD power potential.
- a chip carrier includes three substrate layers 201 , 203 , and 205 .
- the top layer 201 is divided into separate areas for connections to VDD and GND potentials.
- the VDD areas or segments are joined together to provide a continuous conducting surface at VDD in the example.
- the GND areas or segments are separate and electrically isolated from the VDD areas.
- An integrated circuit or chip (FIG. 4) is centrally mounted on the middle layer 203 and extends through an opening 207 the top layer 201 .
- the middle or signal layer 203 is sandwiched between the first and second layers 201 and 205 , respectively.
- the middle or signal layer 203 is arranged to have multiple high frequency signal conductors thereon (FIG. 5) separated by insulation material.
- the arrangement of the SIG layer 203 between the first and second layers as shown provides enhanced signal isolation and noise immunity.
- Logic signals which are generated by a chip mounted on the chip carrier are connected to various conductors in the SIG layer for transmission to other chips or other parts of the chip.
- signals are carried on the SIG plane between the separate GND areas in the top and bottom layers, the signals are effectively isolated by the GND sections over and below the signal lines carrying the signals in the SIG plane.
- signal isolation by signal transmission through signal lines sandwiched between and isolated by GND potential layers is achieved at the chip carrier level as illustrated.
- VDD/GND patterns on the carrier planes is available for carrier plane construction in accordance with the present invention. So long as one or more of the signal lines in the SIG plane are overlapped at the top and bottom of the SIG plane by GND layers or patches, signal isolation can be achieved.
- FIG. 3 A second of many possible patterns for VDD/GND layouts on the outer layers of a chip carrier is illustrated in FIG. 3.
- top and bottom substrate layers 301 and 305 are illustrated with a SIG layer 303 sandwiched in-between the outer layers 301 and 305 .
- the carrier is arranged to have a chip mounted on the middle substrate layer 303 which extends through an opening 307 in the top layer 301 .
- FIG. 3 there are only two GND areas on the surface of the top layer 301 rather than four GND areas as shown in FIG. 2. However, in FIG. 3 the GND areas are larger and more contiguous thereby providing a greater area for isolation of the signals being transmitted on the SIG plane 303 .
- FIG. 3 As with FIG.
- the layout on the bottom layer 305 is a continuous surface held at ground.
- the design of the layout on the top and bottom layers can be modified to best accommodate and isolate different chips since the signals and terminals may be positioned differently on different chips and the GND sections on the outer layers can be customized to match the layout of the SIG lines connected to specific chips.
- a tri-plate structure is arranged to include three substrate layers 401 , 403 and 405 surrounding an integrated circuit chip 415 which is mounted thereon.
- the tri-plate structure includes a top or first layer 401 , a middle or second layer 403 and a bottom or third layer 405 .
- each layer is arranged on electrically insulative substrate material such as FR4 material which is known in the art and typically used for circuit boards, although other insulative materials may also be used.
- the three substrate layers 401 , 403 and 405 are sandwiched together to form a chip carrier.
- the chip 415 is mounted on the middle substrate layer or signal (SIG) layer 403 and extends through an opening in the top layer 401 .
- the middle signal layer 403 includes bundles or groups of printed circuit wiring or lines (FIG. 5) to carry signals between the chip 415 and the edges of the carrier device.
- the top or reference potential layer 401 includes electrically isolated and separate conducting areas or segments which are held at different system potentials. For example, segments 417 , 419 , 421 and 423 are held at ground (GND) potential, and segments 407 , 409 , 411 and 413 , which are joined together to form a single electrical node, are held at VDD power potential level.
- the separate conducting areas on the top layer 401 are separated by air gaps, e.g.
- each group of signal conductors in the middle layer 403 between the chip and the outer edges of the carrier have a ground potential area or segment, e.g.
- ground areas in the top layer 401 are connected to the bottom ground potential layer 405 through vias, e.g. 425 , 427 , which pass through the middle layer 403 . Also, vias such as via 429 are used to connect de-coupling capacitors 431 between VDD areas 411 in the top layer 401 and the ground potential bottom layer 405 .
- FIG. 5 a more detailed showing of the middle layer 403 is presented.
- layer 403 is positioned between the top layer 401 and the bottom layer 405 .
- the SIG or middle layer 403 includes groups of signal conductors, such as 501 , 503 , 505 , 507 and 509 , which are positioned between areas in the top layer 401 and bottom layer 405 which are held at ground potential such that each group of signal conductors such as 509 is sandwiched between ground potential areas, for example areas 404 and 406 , in extending from the chip 415 to the outer edges of the chip carrier.
- the signals that radiate outwardly under the patches of GND are launched into true GND-SIG-GND tri-plate carrier construction.
- the desirable GND-GND reference integrity of the tri-plate condition can be maintained in the carrier package to the card upon which the carrier is mounted, and continued all the way through the total interconnect system of cards, boards, back-planes, unit interconnect cables and network interconnect cables to the corresponding similarly constructed tri-plate package containing a chip with the intended receiver of signals transmitted from the driver on the first chip.
- FIG. 2 embodiment often requires package de-coupling capacitors at the corners of the chip while the FIG. 3 embodiment would accommodate de-coupling capacitors along the top and bottom edges of the chip area, with high speed signals propagating on the GND-SIG-GND tri-plate to the left and to the right of the chip. Slower control signals could operate in the capacitively de-coupled VDD-GND area under the VDD part of the top layer.
- the present invention in addition to providing signal isolation and noise immunity, also provides significant wiring advantages over mixed VDD-GND references since the VDD distribution is now a low frequency system and is no longer coupled along its length to the high frequency signal system. This allows single-ended transmissions to scale to higher frequencies. This doubles the number of signal lines in those frequency ranges where differential transmission has been required to counteract the effects of electrical noise on the reference planes. Further, the distribution system for VDD no longer needs to be high frequency interleaved with the signal escape system. It can be placed out of the way to the corners or along selected edges of the package. This yields significant advantages in wiring the package and the card underneath the package, as well as the entire interconnect system.
- VDD voltage reference integrity
- the distribution system for VDD no longer needs to be high frequency interleaved with the GND system. This leads to the VDD distribution system being composed of more continuous conductors for lower DC loss.
- signals are launched into true GND-GND reference integrity of the tri-plate structure, and that voltage reference integrity can be maintained from a driver in one chip through the carrier package to the card below the carrier and all the way through the interconnect system of cards, boards, backplanes, unit interconnect cables and network interconnect cables to a corresponding and similarly constructed tri-plate package containing a chip with a target receiver.
Abstract
A method and implementing system are described in which a tri-plate chip carrier is effective to significantly reduce electromagnetic signal radiation and provide enhanced noise immunity. The tri-plate structure includes a ground layer, a middle signal conducting layer upon which an integrated circuit is mounted, and a top reference potential layer. The middle layer includes groups of printed circuit conductors extending from the chip to the outer edges of the carrier. The top layer is arranged to have separate electrically isolated conducting areas for VDD and ground reference potential connections. The conducting areas are arranged such that each group of signal conductors in the middle signal layer has a ground potential area above it and a ground potential area below it to provide enhanced signal isolation and reduced electromagnetic radiation.
Description
- The present invention relates generally to information processing systems and more particularly to a methodology and implementation for signal transmission in an integrated circuit carrier package.
- Subject matter disclosed and not claimed herein is disclosed and claimed in one or more of the following related co-pending applications, which are assigned to the assignee of the present application and included herein by reference:
- Attorney Docket AUS-2000-0250-US1;
- Attorney Docket AUS-2000-0251-US1; and
- Attorney Docket AUS-2000-0252-US1.
- In digital computer assemblies, including integrated circuit (IC) or chip carrier packages, it has become common practice over the years to sandwich a logic signal (SIG) transmission line between two reference planes, i.e. between a power (VDD) reference plane and a power return ground (GND) reference plane, while transmitting the logic signal from a driver circuit to one or more receiver circuits. With regard to a chip carrier in particular, the minimum that a chip package carrier must supply to a chip mounted thereon is one or more power supply voltages (VDD), one or more ground returns (GND), and a sufficient number of signal (SIG) lines. Currently these requirements are furnished by means of sets of separate planes for VDD, SIG and GND connections to the mounted chip. In other words, a plane of signal lines is defined on a SIG plane that is positioned or “sandwiched” between a GND plane and a voltage VDD plane. The semiconductor chip sits on top at the center of the package. The signal lines radiate outwardly from the chip area and connect to the card area below the carrier “sandwich” which is made up of the three reference planes. De-coupling capacitors on the chip and the chip carrier between VDD and GND supply the electrical charge current at the low source inductance needed to drive fast transitions into the signal lines at the chip source end. While this construction has been satisfactory in the past, increasing operating frequencies of systems and chips has created problems with regard to signal isolation and noise immunity.
- Thus there is a need for an improved chip carrier package design which provides greater signal isolation and noise immunity in systems and chips having high operating frequencies.
- A method and implementing system are provided in which a tri-plate structure is arranged to include three substrate layers surrounding an integrated circuit chip which is mounted thereon. In an exemplary embodiment, the tri-plate structure includes a middle or signal layer, a first outer layer or top layer, and a second outer layer or bottom layer. The first and second outer layers are positioned on each side of the signal layer. The three layers are arranged on electrically insulative material and the three layers are sandwiched together to form a chip carrier. The chip is mounted on the middle layer or signal (SIG) layer and extends through an opening in the top layer. The middle signal layer includes bundles or groups of printed circuit conductors or lines to carry signals between the chip and the edges of the carrier device. The first outer layer includes electrically isolated and separate conducting areas or segments which are held at different system potentials, for example at ground (GND) and VDD power potential levels. The separate conducting areas on the top layer are separated by air gaps or by insulative material to provide adequate electrical isolation. The separate areas are arranged on the first outer layer relative to the signal conductors in the middle layer such that signal lines from the chip to the outer edges of the chip carrier in the middle layer are positioned under areas of ground potential in the first outer layer and above the grounded second outer layer which is positioned below the signal layer in the carrier device. Thus, each group of signal conductors in the middle layer between the chip and the outer edges of the carrier have a ground potential area or segment above each signal conductor group and also a ground potential layer below each signal conductor group. The tri-plate structure thus formed provides system electromagnetic radiation isolation and enhanced noise isolation and signal integrity. In the example, ground areas in the top layer are connected to the bottom ground potential layer through vias which pass through the middle layer. Also, vias are used to connect de-coupling capacitors between VDD areas in the top layer and the ground potential bottom layer.
- A better understanding of the present invention can be obtained when the following detailed description is considered in conjunction with the following drawings, in which:
- FIG. 1 is a schematic diagram of a prior art arrangement of reference voltage planes in a chip carrier;
- FIG. 2 is a schematic diagram of an exemplary carrier design showing a planar layout with separated areas for different potentials in the same plane in accordance with the present invention;
- FIG. 3 is an illustration showing another exemplary carrier design showing a planar layout with separated areas for different potentials in the same plane in accordance with the present invention;
- FIG. 4 is a perspective view of the chip carrier arrangement shown in FIG. 2; and
- FIG. 5 is an illustration showing details of the middle layer of the tri-plate chip carrier package illustrated in FIG. 4.
- The various methods discussed herein may be implemented on a chip carrier in any electronic system which includes integrated circuit packages carried on chip carrier packages. As shown in FIG. 1, a typical prior art arrangement of reference planes in a chip carrier package includes a
SIG plane 103 positioned between aVDD reference plane 101 and aGND reference plane 105. The Sigplane 103 includes signal lines for conducting signals between drivers and receivers which are included within an integrated circuit or chip mounted on the carrier and also to receivers mounted on other carriers in an electronic system. The power plane is maintained at a reference VDD power potential. - An exemplary embodiment of the present invention is illustrated in FIG. 2. As shown, a chip carrier includes three
substrate layers top layer 201 is divided into separate areas for connections to VDD and GND potentials. In the example, the VDD areas or segments are joined together to provide a continuous conducting surface at VDD in the example. The GND areas or segments are separate and electrically isolated from the VDD areas. An integrated circuit or chip (FIG. 4) is centrally mounted on themiddle layer 203 and extends through anopening 207 thetop layer 201. The middle orsignal layer 203 is sandwiched between the first andsecond layers signal layer 203 is arranged to have multiple high frequency signal conductors thereon (FIG. 5) separated by insulation material. The arrangement of theSIG layer 203 between the first and second layers as shown provides enhanced signal isolation and noise immunity. Logic signals which are generated by a chip mounted on the chip carrier are connected to various conductors in the SIG layer for transmission to other chips or other parts of the chip. When signals are carried on the SIG plane between the separate GND areas in the top and bottom layers, the signals are effectively isolated by the GND sections over and below the signal lines carrying the signals in the SIG plane. Thus, signal isolation by signal transmission through signal lines sandwiched between and isolated by GND potential layers is achieved at the chip carrier level as illustrated. - An indefinite number of VDD/GND patterns on the carrier planes is available for carrier plane construction in accordance with the present invention. So long as one or more of the signal lines in the SIG plane are overlapped at the top and bottom of the SIG plane by GND layers or patches, signal isolation can be achieved.
- A second of many possible patterns for VDD/GND layouts on the outer layers of a chip carrier is illustrated in FIG. 3. In the FIG. 3 embodiment, top and
bottom substrate layers SIG layer 303 sandwiched in-between theouter layers middle substrate layer 303 which extends through anopening 307 in thetop layer 301. In FIG. 3, there are only two GND areas on the surface of thetop layer 301 rather than four GND areas as shown in FIG. 2. However, in FIG. 3 the GND areas are larger and more contiguous thereby providing a greater area for isolation of the signals being transmitted on theSIG plane 303. As with FIG. 2, the layout on thebottom layer 305 is a continuous surface held at ground. The design of the layout on the top and bottom layers can be modified to best accommodate and isolate different chips since the signals and terminals may be positioned differently on different chips and the GND sections on the outer layers can be customized to match the layout of the SIG lines connected to specific chips. - In FIG. 4, a more detailed exploded view of the chip carrier is presented. As shown, a tri-plate structure is arranged to include three
substrate layers integrated circuit chip 415 which is mounted thereon. In an exemplary embodiment, the tri-plate structure includes a top orfirst layer 401, a middle orsecond layer 403 and a bottom orthird layer 405. In the example, each layer is arranged on electrically insulative substrate material such as FR4 material which is known in the art and typically used for circuit boards, although other insulative materials may also be used. The threesubstrate layers chip 415 is mounted on the middle substrate layer or signal (SIG)layer 403 and extends through an opening in thetop layer 401. Themiddle signal layer 403 includes bundles or groups of printed circuit wiring or lines (FIG. 5) to carry signals between thechip 415 and the edges of the carrier device. The top or referencepotential layer 401 includes electrically isolated and separate conducting areas or segments which are held at different system potentials. For example,segments segments top layer 401 are separated by air gaps, e.g. 433, 435, 437, or by insulative material, to provide adequate electrical isolation between the different segments of electrical potential. The separate areas are arranged on thetop layer 401 relative to the signal conductors in the middle layer (FIG. 5) such that signal lines from thechip 415 to the outer edges of the chip carrier in themiddle layer 403 are positioned under areas of ground potential such as 423 in the top layer, and above the grounded bottom orthird layer 405 in the carrier device. Thus, each group of signal conductors in themiddle layer 403 between the chip and the outer edges of the carrier have a ground potential area or segment, e.g. 417, 419, 421 or 423, above each signal conductor group and also a ground potential layer below each signal conductor group in thebottom layer 405. The tri-plate structure thus formed provides system electromagnetic radiation isolation and enhanced noise isolation and signal integrity. In the example, ground areas in thetop layer 401 are connected to the bottom groundpotential layer 405 through vias, e.g. 425, 427, which pass through themiddle layer 403. Also, vias such as via 429 are used to connectde-coupling capacitors 431 betweenVDD areas 411 in thetop layer 401 and the groundpotential bottom layer 405. - In FIG. 5, a more detailed showing of the
middle layer 403 is presented. As shown,layer 403 is positioned between thetop layer 401 and thebottom layer 405. The SIG ormiddle layer 403 includes groups of signal conductors, such as 501, 503, 505, 507 and 509, which are positioned between areas in thetop layer 401 andbottom layer 405 which are held at ground potential such that each group of signal conductors such as 509 is sandwiched between ground potential areas, forexample areas chip 415 to the outer edges of the chip carrier. - It is noted that the signals that radiate outwardly under the patches of GND are launched into true GND-SIG-GND tri-plate carrier construction. The desirable GND-GND reference integrity of the tri-plate condition can be maintained in the carrier package to the card upon which the carrier is mounted, and continued all the way through the total interconnect system of cards, boards, back-planes, unit interconnect cables and network interconnect cables to the corresponding similarly constructed tri-plate package containing a chip with the intended receiver of signals transmitted from the driver on the first chip.
- It is noted that the FIG. 2 embodiment often requires package de-coupling capacitors at the corners of the chip while the FIG. 3 embodiment would accommodate de-coupling capacitors along the top and bottom edges of the chip area, with high speed signals propagating on the GND-SIG-GND tri-plate to the left and to the right of the chip. Slower control signals could operate in the capacitively de-coupled VDD-GND area under the VDD part of the top layer.
- The present invention, in addition to providing signal isolation and noise immunity, also provides significant wiring advantages over mixed VDD-GND references since the VDD distribution is now a low frequency system and is no longer coupled along its length to the high frequency signal system. This allows single-ended transmissions to scale to higher frequencies. This doubles the number of signal lines in those frequency ranges where differential transmission has been required to counteract the effects of electrical noise on the reference planes. Further, the distribution system for VDD no longer needs to be high frequency interleaved with the signal escape system. It can be placed out of the way to the corners or along selected edges of the package. This yields significant advantages in wiring the package and the card underneath the package, as well as the entire interconnect system. Moreover, the distribution system for VDD no longer needs to be high frequency interleaved with the GND system. This leads to the VDD distribution system being composed of more continuous conductors for lower DC loss. With this construction, signals are launched into true GND-GND reference integrity of the tri-plate structure, and that voltage reference integrity can be maintained from a driver in one chip through the carrier package to the card below the carrier and all the way through the interconnect system of cards, boards, backplanes, unit interconnect cables and network interconnect cables to a corresponding and similarly constructed tri-plate package containing a chip with a target receiver.
- The method and apparatus of the present invention has been described in connection with a preferred embodiment as disclosed herein. Although an embodiment of the present invention has been shown and described in detail herein, along with certain variants thereof, many other varied embodiments that incorporate the teachings of the invention may be easily constructed by those skilled in the art. Accordingly, the present invention is not intended to be limited to the specific form set forth herein, but on the contrary, it is intended to cover such alternatives, modifications, and equivalents, as can be reasonably included within the spirit and scope of the invention.
Claims (22)
1. An integrated circuit package comprising:
a signal substrate layer arranged for having an integrated circuit mounted thereon;
at least one group of signal conductors on said signal substrate layer arranged to be connected between terminals of said integrated circuit and at least one edge of said signal substrate layer;
a first outer substrate layer positioned on a first side of said signal substrate layer; and
a second outer substrate layer positioned on a second side of said signal substrate layer, said first and second outer substrate layers being arranged to have first areas of conducting surfaces thereon connected to a first potential level, said first areas of conducting surfaces being positioned to extend with said group of said signal conductors on at least two sides of said group of said signal conductors.
2. The integrated circuit package as set forth in claim 1 wherein said first potential level is ground potential.
3. The integrated circuit package as set forth in claim 1 and further including:
second areas of conducting surfaces positioned on said first outer substrate layer, said second areas of conducting surface being arranged for connection to a second potential level, said second potential level being different from said first potential level.
4. The integrated circuit package as set forth in claim 1 wherein said second potential level is a power supply potential.
5. The integrated circuit package as set forth in claim 1 wherein said first areas of conducting surfaces are arranged symmetrically on said first outer substrate layer.
6. The integrated circuit package as set forth in claim 1 wherein said first areas of conducting surfaces comprise electrically isolated areas of conductive material on said first outer substrate layer, and said first areas of conducting surfaces are connected to conducting areas on said second outer substrate layer through vias passing through said signal substrate layer.
7. The integrated circuit package as set forth in claim 1 wherein said one group of signal conductors is arranged between said integrated circuit and only one side of said signal substrate layer.
8. The integrated circuit package as set forth in claim 1 wherein said one group of signal conductors is arranged between said integrated circuit and only two sides of said signal substrate layer.
9. The integrated circuit package as set forth in claim 1 wherein said one group of signal conductors is arranged between said integrated circuit and all sides of said signal substrate layer.
10. The integrated circuit package as set forth in claim 3 and further including at least one de-coupling capacitor connected between one of said first areas of conducting surface on said first outer substrate layer and at least one of said second areas of conducting surface on said second outer substrate layer.
11. The integrated circuit package as set forth in claim 10 wherein said first areas of conducting surfaces are connected to first areas of conducting surfaces on said second outer substrate layer through vias passing through said signal substrate layer.
12. A method for packaging groups of printed signal conductors extending from an integrated circuit mounted on a signal substrate layer to at least one edge of said signal substrate layer, said method comprising:
providing a signal substrate layer arranged for having an integrated circuit mounted thereon;
positioning at least one group of signal conductors on said signal substrate layer arranged to be connected between terminals of said integrated circuit and at least one edge of said signal substrate layer;
positioning a first outer substrate layer on a first side of said signal substrate layer; and
positioning a second outer substrate layer on a second side of said signal substrate layer, said first and second outer substrate layers being arranged to have first areas of conducting surfaces thereon connected to a first potential level, said first areas of conducting surfaces being positioned to be extend with said group of said signal conductors on at least two sides of said group of said signal conductors.
13. The method as set forth in claim 12 wherein said first potential level is ground potential.
14. The method as set forth in claim 12 and further including:
providing second areas of conducting surfaces positioned on said first outer substrate layer, said second areas of conducting surface being arranged for connection to a second potential level, said second potential level being different from said first potential level.
15. The method as set forth in claim 12 wherein said second potential level is a power supply potential.
16. The method as set forth in claim 12 and further including arranging said first areas of conducting surfaces symmetrically on said first outer substrate layer.
17. The method as set forth in claim 12 wherein said first areas of conducting surfaces comprise electrically isolated areas of conductive material on said first outer substrate layer, said method further including connecting said first areas of conducting surfaces to conducting areas on said second outer substrate layer through vias passing through said signal substrate layer.
18. The method as set forth in claim 12 wherein said method further includes arranging said one group of signal conductors between said integrated circuit and only one side of said signal substrate layer.
19. The method as set forth in claim 12 wherein said method further includes arranging said signal conductors between said integrated circuit and only two sides of said signal substrate layer.
20. The method as set forth in claim 12 wherein said method further includes arranging said signal conductors between said integrated circuit and all sides of said signal substrate layer.
21. The method as set forth in claim 14 and further including connecting at least one de-coupling capacitor between one of said first areas of conducting surface on said first outer substrate layer and at least one of said second areas of conducting surface on said second outer substrate layer.
22. The method as set forth in claim 21 and further including connecting said first areas of conducting surfaces to first areas of conducting surfaces on said second outer substrate layer through vias passing through said signal substrate layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/217,588 US20020186554A1 (en) | 2000-08-17 | 2002-08-12 | Method for manufacturing a scalable high frequency integrated circuit package |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/640,544 US6495911B1 (en) | 2000-08-17 | 2000-08-17 | Scalable high frequency integrated circuit package |
US10/217,588 US20020186554A1 (en) | 2000-08-17 | 2002-08-12 | Method for manufacturing a scalable high frequency integrated circuit package |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/640,544 Division US6495911B1 (en) | 2000-08-17 | 2000-08-17 | Scalable high frequency integrated circuit package |
Publications (1)
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US20020186554A1 true US20020186554A1 (en) | 2002-12-12 |
Family
ID=24568682
Family Applications (2)
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US09/640,544 Expired - Fee Related US6495911B1 (en) | 2000-08-17 | 2000-08-17 | Scalable high frequency integrated circuit package |
US10/217,588 Abandoned US20020186554A1 (en) | 2000-08-17 | 2002-08-12 | Method for manufacturing a scalable high frequency integrated circuit package |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US09/640,544 Expired - Fee Related US6495911B1 (en) | 2000-08-17 | 2000-08-17 | Scalable high frequency integrated circuit package |
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US (2) | US6495911B1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10122414A1 (en) * | 2001-05-09 | 2002-11-14 | Giesecke & Devrient Gmbh | Through connection of flexible printed circuit boards |
US6937480B2 (en) * | 2001-05-14 | 2005-08-30 | Fuji Xerox Co., Ltd. | Printed wiring board |
US6575766B1 (en) * | 2002-02-26 | 2003-06-10 | Intel Corporation | Laminated socket contacts |
US6713853B1 (en) * | 2002-07-23 | 2004-03-30 | Applied Micro Circuits Corporation | Electronic package with offset reference plane cutout |
US6979208B2 (en) | 2002-12-19 | 2005-12-27 | Intel Corporation | Laminated socket contacts |
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US4498122A (en) * | 1982-12-29 | 1985-02-05 | At&T Bell Laboratories | High-speed, high pin-out LSI chip package |
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US5519176A (en) * | 1993-04-05 | 1996-05-21 | Sony Corporation | Substrate and ceramic package |
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US6373717B1 (en) * | 1999-07-02 | 2002-04-16 | International Business Machines Corporation | Electronic package with high density interconnect layer |
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Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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FR2747235B1 (en) * | 1996-04-03 | 1998-07-10 | Bull Sa | INTEGRATED CIRCUIT BOX |
TW410446B (en) * | 1999-01-21 | 2000-11-01 | Siliconware Precision Industries Co Ltd | BGA semiconductor package |
-
2000
- 2000-08-17 US US09/640,544 patent/US6495911B1/en not_active Expired - Fee Related
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2002
- 2002-08-12 US US10/217,588 patent/US20020186554A1/en not_active Abandoned
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US4551747A (en) * | 1982-10-05 | 1985-11-05 | Mayo Foundation | Leadless chip carrier apparatus providing for a transmission line environment and improved heat dissipation |
US4498122A (en) * | 1982-12-29 | 1985-02-05 | At&T Bell Laboratories | High-speed, high pin-out LSI chip package |
US4513355A (en) * | 1983-06-15 | 1985-04-23 | Motorola, Inc. | Metallization and bonding means and method for VLSI packages |
US5288949A (en) * | 1992-02-03 | 1994-02-22 | Ncr Corporation | Connection system for integrated circuits which reduces cross-talk |
US5639385A (en) * | 1992-06-04 | 1997-06-17 | Lsi Logic Corporation | Method of fabricating a wafer probe card for testing an integrated circuit die |
US5519176A (en) * | 1993-04-05 | 1996-05-21 | Sony Corporation | Substrate and ceramic package |
US5825628A (en) * | 1996-10-03 | 1998-10-20 | International Business Machines Corporation | Electronic package with enhanced pad design |
US6483714B1 (en) * | 1999-02-24 | 2002-11-19 | Kyocera Corporation | Multilayered wiring board |
US6373717B1 (en) * | 1999-07-02 | 2002-04-16 | International Business Machines Corporation | Electronic package with high density interconnect layer |
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US6495911B1 (en) | 2002-12-17 |
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Legal Events
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STCB | Information on status: application discontinuation |
Free format text: EXPRESSLY ABANDONED -- DURING EXAMINATION |