US20020196611A1 - Reliable card detection in a cpci system - Google Patents
Reliable card detection in a cpci system Download PDFInfo
- Publication number
- US20020196611A1 US20020196611A1 US09/887,807 US88780701A US2002196611A1 US 20020196611 A1 US20020196611 A1 US 20020196611A1 US 88780701 A US88780701 A US 88780701A US 2002196611 A1 US2002196611 A1 US 2002196611A1
- Authority
- US
- United States
- Prior art keywords
- connector
- pins
- front card
- pin
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
Definitions
- the present invention relates to Compact Peripheral Component Interconnect (“CPCI”) computer systems. More particularly, the present invention relates to providing reliable card detection in a CPCI system.
- CPCI Compact Peripheral Component Interconnect
- CPCI is a high performance industrial bus based on the standard PCI electrical specification in rugged 3U or 6U Eurocard packaging. CPCI is intended for application in telecommunications, computer telephony, real-time machine control, industrial automation, real-time data acquisition, instrumentation, military systems or any other application requiring high speed computing, modular and robust packaging design, and long term manufacturer support. Because of its extremely high speed and bandwidth, the CPCI bus is particularly well suited for many high-speed data communication applications such as servers, routers, converters, and switches.
- CPCI Compared to standard desktop PCI, CPCI supports twice as many PCI slots (8 versus 4) and offers a packaging scheme that is much better suited for use in industrial applications.
- Conventional CPCI cards are designed for front loading and removal from a card cage. The cards are firmly held in position by their connector, card guides on both sides, and a faceplate that solidly screws into the card cage. Cards are mounted vertically allowing for natural or forced air convection for cooling. Also, the pin-and-socket connector of the CPCI card is significantly more reliable and has better shock and vibration characteristics than the card edge connector of the standard PCI cards.
- Conventional CPCI defines a backplane environment that is limited to eight slots. More specifically, the bus segment of the conventional CPCI system is limited to eight slots, which includes a system slot and peripheral slots. The system slot provides the arbitration, configuration, and interrupt processing for up to seven peripheral slots.
- Hot swappability is the ability to unplug and plug a card while the system remains on. In other words, hot swappability is the ability to exchange cards while the system is running so that there is no need to reboot the system.
- the CPCI Hot Swap/HA specification defines, among other things, that the connector-pin P 1 -D 15 (in the backplane) and connector-pin J 1 -D 15 (in the front card) be designated as a BD_SELECT# line.
- the BD_SELECT# line is used to detect the insertion of a hot swappable front card into a slot of the backplane, and to allow the powering-up/down of the card by the hot swap controller.
- the specification further defines the dynamic interface protocol between the system's hot swap controller and the card through this line.
- the hot swap controller in the conventional system would not know of the insertion of the non-compliant front card.
- the conventional hot swap controller cannot detect the presence of non-hot swappable front cards so that an accurate hardware configuration would not be known to the operating system if non-hot swappable front cards were present.
- the present invention relates to providing a CPCI system that is adapted to reliably detect the presence of all front cards, whether hot swappable or not.
- the reliable detection of all front cards provides the operating system with a more accurate view of the hardware configuration.
- the present invention has a line that is used to detect the presence of a front card.
- the line is connected to a connector-pin in a connector of a slot.
- the line is also connected to a pull-up resistor so that when a front card is not inserted in the slot, the line has a high value.
- the connector-pin mates with a corresponding connector-pin in the front card.
- the corresponding connector-pin is connected to a ground layer of the front card so that the line becomes grounded.
- the voltage level on the line is input to a register that outputs a high or low to a circuit for detecting the presence of a front card.
- the circuit may be a hot swap controller, a CPU or a status indicator. Accordingly, depending on the output of the register, the circuit determines whether a front card is present in the particular slot.
- An embodiment of the invention includes a computer system including a circuit board, with the system comprising a slot coupled to a front side of the circuit board.
- a plurality of connectors is affixed to the circuit board in alignment with the slot, with the plurality of connectors including a first connector.
- a plurality of connector-pins are extended in a direction substantially perpendicular to and away from the circuit board, and has a column and row arrangement within the connectors.
- the first connector includes first and second connector-pins.
- a register having an input line and an output line is provided, with the input line connected to a voltage source through a pull-up resistor, and the first connector-pin connected to the input line of the register.
- a circuit having an input terminal is connected to the first connector-pin through the register, with the register connected to the input terminal of the circuit via the output line of the register, wherein depending on a voltage level of the first connector-pin, the register transmits one of a high and low signal to the input terminal of the circuit whereby the circuit detects a presence of a front card in the slot based on said one of a high and low signal.
- Another embodiment of the invention includes a circuit board having a front side, with the circuit board comprising a plurality of slots coupled to the front side of the circuit board.
- a plurality of connectors is disposed within each of the plurality of slots and including a first connector in each of the slots, with the respective first connectors of the slots including a first connector-pin and a second connector-pin.
- a plurality of connector-pins is disposed in an arrangement of a plurality of columns and rows in each of the connectors, with the plurality of columns including first and second columns. The connector-pins in the first and second columns are connected to a ground layer of the circuit board, except for the first connector-pins in the first connectors.
- An input/output device has a plurality of input lines and output lines, each of the input lines are connected to a voltage source through a pull-up resistor, and the first connector-pins in each of the slots are connected to the input/output device via the respective input lines.
- a circuit has a plurality of input terminals and is connected to the first connector-pins through the input/output device. The input terminals of the circuit are connected to the output lines of the input/output device, wherein depending on voltage levels of the respective first connector-pins, the input/output device transmits respective signals to the corresponding input terminals of the circuit whereby the circuit detects a presence of a front card in corresponding ones of the slots depending on the respective signals.
- FIG. 1 is a perspective view of a conventional CPCI chassis system
- FIG. 2 shows the form factor that is defined for the CPCI daughter card
- FIG. 3 is a front view of a conventional 3U backplane having eight slots with two connectors each;
- FIG. 4( a ) shows a front view of a conventional CPCI backplane in the 6U form factor
- FIG. 4( b ) shows a back view of a conventional CPCI backplane in the 6U form factor
- FIG. 5 shows a side view of the conventional backplane of FIGS. 4 ( a ) and 4 ( b );
- FIG. 6( a ) shows a front view of a conventional pin out arrangement of the connectors of a slot
- FIG. 6( b ) shows a back view of a conventional pin out arrangement of connectors of a slot
- FIG. 7( a ) shows a conventional hot swappable CPCI system for detecting the presence of a hot swappable front card
- FIG. 7( b ) shows a conventional hot swappable CPCI system for illustrating that the system cannot detect the presence of a non-hot swappable front card
- FIG. 8( a ) shows a front view of the pin out arrangement of the connectors of a slot according to an embodiment of the invention
- FIG. 8( b ) shows a modification of the pin out arrangement of FIG. 8( a ) according to another embodiment of the invention
- FIG. 9( a ) shows a front card having a pin out arrangement corresponding to the pin out arrangement shown in FIG. 8( a );
- FIG. 9( b ) shows a front card having a pin out arrangement corresponding to the pin out arrangement shown in FIG. 8( b );
- FIG. 10( a ) shows a hot swappable CPCI system for detecting a non-hot swappable front card according to an embodiment of the invention
- FIG. 10( b ) shows a non-hot swappable CPCI system for detecting a non-hot swappable front card according to an embodiment of the invention
- FIG. 10( c ) shows a non-hot swappable CPCI system for detecting a non-hot swappable front card according to another embodiment of the invention
- FIG. 11 shows a hot swappable CPCI system including a CPU and a status indicator according to an embodiment of the invention
- FIG. 12 shows a plurality of slots having respective BD_DETECT# pins connected to respective inputs of a register for detecting the presence of front cards according to an embodiment of the invention.
- FIG. 13 shows a side view of a register in the form of a front card according to an embodiment of the invention.
- the present invention relates to a CPCI system that reliably detects the presence of front cards that are inserted in the add-on slots.
- a conventional CPCI system that supports hot swappability of the front cards, the insertion and presence of non-hot swappable front cards are not detectable. Accordingly, there is a need for a CPCI system that can detect the presence of all front cards that are inserted in the add-on slots, whether hot swappable or not. This would allow the operating system to have a more accurate and complete view of the hardware configuration.
- FIG. 1 there is shown a perspective view of a conventional CPCI chassis system.
- the chassis system 100 includes a CPCI circuit board referred to in the conventional CPCI system as a passive backplane 102 since the circuit board is located at the back of the chassis 100 and add-on cards (front cards) can only be inserted from the front of the chassis 100 .
- On the front side of the backplane 102 are slots provided with connectors 104 .
- a 6U daughter card 108 is inserted into one of the slots and mates with a corresponding one of the connectors 104 .
- card guides 110 are provided.
- This conventional chassis system 100 provides front removable daughter cards and unobstructed cooling across the entire set of daughter cards 108 .
- the daughter card 200 has a front plate interface 202 and ejector/injector handles 204 .
- the front plate interface 202 is consistent with Eurocard packaging and is compliant with IEEE 1101.1 or IEEE 1101.10.
- the ejector/injector handles should also be compliant with IEEE 1101.1.
- One ejector/injector handle 204 is used for 3U daughter cards, and two ejector/injector handles 204 are used for 6U daughter cards.
- the connectors 104 a - 104 e of the daughter card 200 are numbered starting from the bottom connector 104 a, and both 3U and 6U daughter card sizes are defined, as described below.
- the dimensions of the 3U form factor are approximately 160.00 mm by approximately 100.00 mm, and the dimensions of the 6U form factor are approximately 160.00 mm by approximately 233.35 mm.
- the 3U form factor includes two 2 mm connectors 104 a - 104 b, which is the minimum number of connectors that are required to accommodate a full 64 bit CPCI bus. Specifically, the 104 a connectors are reserved to carry the signals required to support the 32-bit PCI bus, hence no other signals may be carried in any of the pins of this connector.
- the 104 a connectors may have a reserved key area that can be provided with a connector “key”, which is a pluggable plastic piece that comes in different shapes and sizes, so that the add-on card can only mate with an appropriately keyed slot.
- the 104 b connectors are defined to facilitate 64 bit transfers or for rear panel I/O in the 3U form factor.
- the 104 c - 104 e connectors are available for 6U systems as shown in FIG. 1.
- the 6U form factor includes the two connectors 104 a - 104 b of the 3U form factor, and three additional 2 mm connectors 104 c - 104 e.
- the 3U form factor includes connectors 104 a - 104 b
- the 6U form factor includes connectors 104 a - 104 e.
- the three additional connectors 104 c - 104 e of the 6U form factor can be used for secondary buses (i.e., Signal Computing System Architecture (SCSA) or MultiVendor Integration Protocol (MVIP) telephony buses), bridges to other buses (i.e., Virtual Machine Environment (VME) or Small Computer System Interface (SCSI)), or for user specific applications.
- SCSA Signal Computing System Architecture
- MVIP MultiVendor Integration Protocol
- VME Virtual Machine Environment
- SCSI Small Computer System Interface
- the CPCI specification defines the locations for all the connectors 104 a - 104 e, but only the signal-pin assignments for the CPCI bus portion 104 a and 104 b are defined.
- the remaining connectors are the subjects of additional specification efforts, or can be user defined for specific applications, as described above.
- a CPCI system is composed of one or more CPCI bus segments, where each bus segment includes up to eight CPCI card slots.
- Each CPCI bus segment consists of one system slot 302 , and up to seven peripheral slots 304 a - 304 g.
- the CPCI daughter card for the system slot 302 provides arbitration, clock distribution, and reset functions for the CPCI peripheral cards on the bus segment.
- the peripheral slots 304 a - 304 g may contain simple cards, intelligent slaves or PCI bus masters.
- the connectors 308 a, 308 b have connector-pins 306 that project in a direction perpendicular to the backplane 300 , and are designed to mate with the front side “active” daughter cards (“front cards”), and “pass-through” its relevant interconnect signals to mate with the rear side “passive” input/output (I/O) card(s) (“rear transition cards”).
- front cards front cards
- rear transition cards rear side “passive” input/output (I/O) card(s)
- the connector-pins 306 allow the interconnected signals to pass-through from the front cards to the rear transition cards.
- FIGS. 4 ( a ) and 4 ( b ) there are shown a front and back view of a conventional CPCI backplane in the 6U form factor, respectively.
- four slots 402 a - 402 d are provided on the front side 400 a of the backplane 400 .
- FIG. 4( b ) four slots 406 a - 406 d are provided on the back side 400 b of the backplane 400 . Note that in both FIGS. 4 ( a ) and 4 ( b ) only four slots are provided instead of eight slots as in FIG. 3.
- each of the slots 402 a - 402 d on the front side 400 a has five connectors 404 a - 404 e while each of the slots 406 a - 406 d on the back side 400 b has only four connectors 408 b - 408 e.
- the 404 a connectors are provided for 32 bit PCI and connector keying. Thus, they do not have I/O connectors to their rear.
- the front cards that are inserted in the front side slots 402 a - 402 d only transmit signals to the rear transition cards that are inserted in the back side slots 406 a - 406 d through front side connectors 404 b - 404 e.
- FIG. 5 there is shown a side view of the conventional backplane of FIGS. 4 ( a ) and 4 ( b ).
- slot 402 d on the front side 400 a and slot 406 d on the back side 400 b are arranged to be substantially aligned so as to be back to back.
- slot 402 c on the front side 400 a and slot 406 c on the backside 400 b are arranged to be substantially aligned, and so on.
- the front side connectors 404 b - 404 e are arranged back-to-back with the back side connectors 408 b - 408 e.
- the front side connector 404 a does not have a corresponding back side connector. It is important to note that the system slot 402 a is adapted to receive the CPU front card, and the signals from the system slot 402 a are then transmitted to corresponding connector-pins of the peripheral slots 402 b - 402 d.
- the conventional CPCI system can have expanded I/O functionality by adding peripheral front cards in the peripheral slots 402 b - 402 d.
- FIGS. 6 ( a ) and 6 ( b ) illustrate a conventional pin out arrangement of the connectors in a CPCI system.
- FIG. 6( a ) shows a front view of a conventional pin out arrangement of the connectors of a slot.
- FIG. 6( a ) there are shown connectors 404 a - 404 e of slot 402 d.
- the connector-pins are arranged in a column and row configuration.
- Each of the connectors 404 a - 404 e have seven columns of pins, which are designated as Z, A, B, C, D, E, and F going from left to right.
- Each of the connectors 404 a - 404 e also has twenty-two rows of connector-pins.
- FIG. 6( b ) shows a back view of a conventional pin out arrangement of the connectors of a slot.
- connectors 408 b - 408 e of slot 406 d there are shown connectors 408 b - 408 e of slot 406 d.
- the back view shows only four connectors instead of five. This is because, as shown in FIGS. 4 ( a ) and 4 ( b ), the front side of the backplane has five connectors while the back side of the backplane has four connectors.
- the column arrangement of the connector-pins is designated as F, E, D, C, B, A, and Z going from left to right.
- connector-pins of slots 402 d and 406 d are straight-pass through pins, and so the column designations are mirror images with respect to each other.
- the connector-pin located at column A, row 2 of connector 404 b is the same connector-pin located at column A, row 2 of connector 408 b.
- connector-pins located at columns F and Z in FIG. 6( b ) are connected to a ground layer GND in the backplane.
- connector-pins of columns A, B, C, D, and E are connected to various signals, as in FIG. 6( a ).
- the Hot Swap/HA Specification defines the connector-pin located at column D, row 15 of connector 404 ( a ) to be a BD_SELECT# pin.
- Other relevant connector-pins of connector 404 a include a BD_HEALTHY# pin, which is located at column B, row 4 , and a BD_RESET# pin, which is located at column C, row 5 .
- the significance of these connector-pins in the Hot Swap/HA specification is discussed in more detail with reference to FIGS. 7 ( a ) and 7 ( b ) below.
- FIG. 7( a ) shows a conventional hot swappable CPCI system for detecting the presence of a hot swappable front card.
- a CPCI backplane 702 has a connector 404 a in one of its slots, and a hot swap controller 704 coupled to the 10 backplane 702 .
- the connector 404 a has the BD_SELECT# 706 a, BD_HEALTHY# 708 a, and BD_RESET# 710 a connector-pins, which are of male-type, connected to the hot swap controller 704 .
- the BD_SELECT# line 716 is connected to a “weak-pull-down” resistor 714 that is connected to a ground layer 718 in the backplane 702 .
- a front card 200 b has corresponding BD SELECT# 706 b, BD_HEALTHY# 708 b, and BD_RESET# 710 b connector-pins, which are of female-type, with the BD_SELECT# pin 706 b being connected to a voltage source Vcc through a pull-up resistor 712 .
- the BD_SELECT# line 716 is defined to provide a signal to the hot swap controller 704 such that the controller 704 knows whether a hot swappable front card 200 b has been inserted in a particular slot.
- the hot swap controller 704 performs the powering up/down of the hot swappable front card 200 b using this line 716 .
- the BD_HEALTHY# pin 708 b is connected to an internal power supply 724 b in the front card 200 b such that the BD_HEALTHY# line 720 indicates to the hot swap controller 704 whether or not the board is defective.
- the BD_RESET# line 722 is used by the hot swap controller 704 to reset a front card 200 b so that it remains in a back up mode. All of the above described functions of the BD_SELECT#, BD_HEALTHY#, and BD_RESET# lines are described in more detail below.
- the hot swappable front card 200 b is inserted into a slot of backplane 702 such that the connectors 404 a and 104 a mate
- the BD_SELECT# pin 706 a is pulled up to the voltage level of the BD_SELECT# pin 706 b.
- This pull-up on the BD_SELECT# pin 706 a is detected by the hot swap controller 704 such that the hot swap controller 704 senses that a hot swappable front card 200 b has been inserted in the particular slot.
- the hot swap controller 704 then drives the BD_SELECT# line 716 low so as to allow the front card 200 b to power up.
- the hot swap controller 704 examines the BD_HEALTHY# line 720 to determine if the inserted front card 200 b is healthy. This determination is made by sensing the voltage level from the internal power supply 724 b. The hot swap controller 704 then uses the BD_RESET# line 722 to release the front card 200 b from the reset mode to connect to the system. Alternatively, if the front card 200 b is a back up board, then the BD_RESET# line 722 is used to maintain the front card 200 b in the reset mode until backup is needed from the particular front card 200 b.
- FIG. 7 ( b ) shows a conventional hot swappable CPCI system for illustrating that the system cannot detect the insertion of a non-hot swappable front card.
- a non-hot swappable front card 200 c has corresponding BD_SELECT# 706 c, BD_HEALTHY# 708 c, and BD_RESET# 710 c connector-pins, which are of female-type, with the BD_SELECT# pin 706 c in the non-hot swappable front card 200 c not connected to a pull-up resistor, but connected instead to a ground layer 726 in the front card 200 c.
- the BD_HEALTHY# pin 708 c is again connected to an internal power supply 724 c in the front card 200 c such that the BD HEALTHY# line 720 indicates to the hot swap controller 704 whether or not the board is defective.
- the BD_SELECT# pin 706 a becomes grounded.
- the hot swap controller 704 senses that the BD_SELECT# pin 706 a is at ground potential and so does not know that a non-hot swappable front card 200 c has been inserted in the particular slot of backplane 702 .
- the BD_SELECT# line 716 is already connected to the “weak-pull-down” resistor 714 and cannot distinguish between the ground potential and the weak-pull-down on the resistor 714 .
- the weak-pull-down on the resistor 714 typically involves a high value resistor that is connected to a ground layer 718 such that the hot swap controller 704 senses the logic level/voltage potential to be a “low”. Accordingly, the hot swap controller 704 is not able to distinguish between the low level and the ground potential.
- the ground layer 718 of the backplane 702 is at the same potential as the ground layer 726 of the front card 200 c when the front card 200 c is inserted in a slot of backplane 702 .
- the hot swap controller 704 in conventional CPCI systems cannot detect the insertion of a non-hot swappable front card 200 c in a particular slot.
- the present invention reliably detects the presence of all cards, 200 b, 200 c, whether hot swappable or not.
- FIG. 8( a ) shows a front view of the pin out arrangement of the connectors of a CPCI system according to an embodiment of the invention.
- connectors 404 a - 404 e of slot 402 d there are shown connectors 404 a - 404 e of slot 402 d.
- the connector-pins are arranged in a column and row configuration.
- Each of the connectors 404 a - 404 e have seven columns of pins, which are designated as Z, A, B, C, D, E, and F going from left to right.
- the connectors 404 a - 404 e each also have twenty-two rows.
- the connector-pins having XXX or YYY as the defined signals do not mean that those pins share the same signals, respectively. Instead, the XXX or YYY designations are provided to show that these connector-pins are connected to various CPCI signals that are not particularly relevant to the present invention, and thus are not specifically shown in FIG. 8( a ). Note that the other slots 402 a - 402 c have a similar pin out arrangement as shown in slot 402 d of FIG. 8( a ).
- FIG. 8( b ) shows a modification of the pin out arrangement of FIG. 8( a ) according to another embodiment of the invention.
- the arrangement of the connector-pins are exactly the same as the arrangement shown in FIG. 8( a ), except for the key area located in connector 404 a.
- the 404 a connectors may have an optional key area that is provided with a connector “key”, which is a pluggable plastic piece that comes in different shapes and sizes, so that only an appropriately keyed front card can mate with a particular slot.
- FIG. 9( a ) shows a front card having a pin out arrangement corresponding to the pin out arrangement shown in FIG. 8( a ).
- the pin out arrangement of the front card 200 is essentially a mirror image of the pin out arrangement shown in FIG. 8( a ), except that the connector-pin located at column F, row 1 , of connector 104 a is connected to a ground layer in the front card.
- FIG. 9( b ) shows a front card having a pin out arrangement corresponding to the pin out arrangement of FIG. 8( b ). This arrangement is the same as the arrangement shown in FIG. 9( a ), except for the addition of the key area.
- FIG. 10 ( a ) shows a hot swappable CPCI system for detecting a non-hot swappable front card according to an embodiment of the invention.
- a CPCI backplane 1002 has a hot swap controller 1004 , a register 1006 , a pull-up resistor 1008 connected to a voltage source Vcc, and a connector 1010 in one of its slots.
- the connector 1010 has the BD_SELECT# 1014 a, BD_HEALTHY# 1016 a, and BD_RESET# 1018 a connector-pins, which are of male-type, connected to the hot swap controller 1004 .
- the BD_DETECT# pin 1012 a which is of male-type, is connected to the register 1006 via the D input line 1038 .
- the register 1006 has its D input line 1038 connected to a voltage source Vcc through the pull-up resistor 1008 , and the Q output line 1040 of the register 1006 is connected to the hot swap controller 1004 .
- a front card 1020 has a connector 1022 with corresponding BD_DETECT# 1012 b, BD_SELECT# 1014 b, BD_HEALTHY# 1016 b, and BD_RESET# 1018 b connector-pins, which are of female-type. Both the BD_DETECT# 1012 b and BD_SELECT# 1016 b pins are connected to a ground layer 1024 in the front card 1020 . Note that the BD_SELECT# pin 1016 b is connected to the ground layer 1024 since the front card 1020 is not a hot swappable card.
- the Q output when the D input to the register 1006 is high, which occurs when a front card 1020 is not present in the particular slot, then the Q output is high. When the D input of the register 1006 is low or ground, then the Q output is low.
- the hot swap controller 1004 detects the insertion of a front card when the Q output is low. For example, when the non-hot swappable front card 1020 is inserted into a slot of backplane 1002 such that the connectors 1010 and 1022 mate during a power-off state of the system, then when the CPCI system is turned on, the D input line 1038 is pulled-down to a ground potential since the BD_DETECT# pin 1012 b in the front card 1020 is connected to the ground layer 1024 . This pull-down on the voltage level of the D input line 1038 is input to the register 1006 .
- the hot swap controller detects that the Q output line 1040 of the register 1006 is low, and senses that a front card has been inserted in that particular slot. Accordingly, in the present invention, the hot swap controller 1004 is able to detect the insertion of the non-hot swappable front card. Note that the present invention detects the presence of non-hot swappable cards during the initial power-up since the non-hot swappable cards cannot be inserted unless the system is in an off state.
- the hot swap controller is able to distinguish between the presence of a hot swappable card and a non-hot swappable card. This is because if the BD_SELECT line 1032 is high, then the hot swap controller 1004 knows that a hot swappable card has been inserted. If the BD_SELECT# line 1032 is low and the Q output line 1040 from the register 1006 is low, then the hot swap controller 1004 senses that a non-hot swappable card is present.
- a CPU card may include a stand-alone hot swap controller in the backplane. Further, the hot swap controller shares this information with the operating system of the CPU (not shown) so that a more accurate hardware configuration is known to the operating system.
- FIG. 10( b ) shows a non-hot swappable CPCI system for detecting a non-hot swappable front card according to an embodiment of the invention.
- a CPU 1042 receives the Q output signal from the register 1006 . Similar to the hot swap controller 1004 of FIG. 10( a ), a low on the Q output line 1040 indicates to the CPU 1042 the insertion of a front card 1020 while a high on the Q output line 1040 represents that the particular slot is empty.
- the CPU receives the Q output signal so that the operating system has a more accurate view of the hardware configuration in the system.
- FIG. 10( c ) shows a non-hot swappable CPCI system for detecting a non-hot swappable front card according to another embodiment of the invention.
- a status indicator 1044 receives the Q output signal from the register 1006 . Similar to the embodiments of FIG. 10( a ) and 10 ( b ), a low on the Q output line 1040 indicates the insertion of a front card 1020 while a high on the Q output line 1040 represents that the particular slot is empty.
- the status indicator 1044 receives this information and provides the status of the slots of the system to a user.
- the status indicator 1044 is a front panel LED light indicator having corresponding light indicators to light when a board is present in the system.
- FIG. 11 shows a hot swappable CPCI system including a CPU and status indicator according to an embodiment of the invention.
- the backplane 1002 includes the hot swap controller 1004 , the CPU 1042 and the status indicator 1044 .
- the register 1006 acts as a buffer such that the signal that is input to its D input is stored for use by the hot swap controller, CPU and status indicator.
- a low on the Q output line 1040 indicates the presence of a front card in the particular slot while a high on the Q output line 1040 indicates the absence of a front card in the particular slot.
- the signal from the Q output line 1040 is used by the hot swap controller, CPU and the status indicator in the manner described above with respect to FIGS. 10 ( a )- 10 ( c ), respectively.
- FIG. 12 shows a plurality of slots having respective BD_DETECT# pins connected to respective inputs of a register for detecting the presence of front cards according to an embodiment of the invention.
- slots 1201 a, 1201 b each have the connector 404 a on a backplane 1200 .
- the connector-pins designated as 1202 a, 1202 b are the BD_DETECT# pins.
- Signal trace lines 1204 a, 1204 b connect the pins 1202 a, 1202 b to the D inputs of the register 1006 , respectively.
- the register 1006 has corresponding Q output lines 1206 a, 1206 b, that transmit the output signals to the hot swap controller 1004 , CPU 1042 , and status indicator 1044 . Note that in the present embodiment, only two signal lines 1204 a, 1204 b are input to the register 1006 since only two slots 402 a, 402 d are shown. However, if more or less slots are provided on the backplane 1200 , then an equal number of signal lines should be provided as inputs to the register 1006 and outputs from the register 1006 to the hot swap controller, CPU and status indicator. Further, in the embodiment of FIG. 12, the register 1006 is disposed on an area of the backplane 1200 .
- the register 1006 may be provided as a front card that is inserted in a slot of the backplane.
- FIG. 13 shows a side view of a register in the form of a front card 1300 inserted in a slot 1302 of the backplane 1304 .
Abstract
Description
- 1. Field of the Invention
- The present invention relates to Compact Peripheral Component Interconnect (“CPCI”) computer systems. More particularly, the present invention relates to providing reliable card detection in a CPCI system.
- 2. Description of Related Art
- CPCI is a high performance industrial bus based on the standard PCI electrical specification in rugged 3U or 6U Eurocard packaging. CPCI is intended for application in telecommunications, computer telephony, real-time machine control, industrial automation, real-time data acquisition, instrumentation, military systems or any other application requiring high speed computing, modular and robust packaging design, and long term manufacturer support. Because of its extremely high speed and bandwidth, the CPCI bus is particularly well suited for many high-speed data communication applications such as servers, routers, converters, and switches.
- Compared to standard desktop PCI, CPCI supports twice as many PCI slots (8 versus 4) and offers a packaging scheme that is much better suited for use in industrial applications. Conventional CPCI cards are designed for front loading and removal from a card cage. The cards are firmly held in position by their connector, card guides on both sides, and a faceplate that solidly screws into the card cage. Cards are mounted vertically allowing for natural or forced air convection for cooling. Also, the pin-and-socket connector of the CPCI card is significantly more reliable and has better shock and vibration characteristics than the card edge connector of the standard PCI cards.
- Conventional CPCI defines a backplane environment that is limited to eight slots. More specifically, the bus segment of the conventional CPCI system is limited to eight slots, which includes a system slot and peripheral slots. The system slot provides the arbitration, configuration, and interrupt processing for up to seven peripheral slots.
- The newest trend in CPCI systems is to support hot swappable front cards. Hot swappability is the ability to unplug and plug a card while the system remains on. In other words, hot swappability is the ability to exchange cards while the system is running so that there is no need to reboot the system. The CPCI Hot Swap/HA specification defines, among other things, that the connector-pin P1-D15 (in the backplane) and connector-pin J1-D15 (in the front card) be designated as a BD_SELECT# line. The BD_SELECT# line is used to detect the insertion of a hot swappable front card into a slot of the backplane, and to allow the powering-up/down of the card by the hot swap controller. The specification further defines the dynamic interface protocol between the system's hot swap controller and the card through this line. However, if a non-hot swappable front card, which is non-compliant to the Hot Swap/HA Specification, is inserted in a slot of the backplane, the hot swap controller in the conventional system would not know of the insertion of the non-compliant front card. In other words, the conventional hot swap controller cannot detect the presence of non-hot swappable front cards so that an accurate hardware configuration would not be known to the operating system if non-hot swappable front cards were present.
- Accordingly, it would be advantageous to provide a CPCI system that can reliably detect the insertion of all front cards, whether hot swappable or not.
- The present invention relates to providing a CPCI system that is adapted to reliably detect the presence of all front cards, whether hot swappable or not. The reliable detection of all front cards provides the operating system with a more accurate view of the hardware configuration.
- The present invention has a line that is used to detect the presence of a front card. The line is connected to a connector-pin in a connector of a slot. The line is also connected to a pull-up resistor so that when a front card is not inserted in the slot, the line has a high value. When a front card is inserted in the slot, the connector-pin mates with a corresponding connector-pin in the front card. Note that the corresponding connector-pin is connected to a ground layer of the front card so that the line becomes grounded. The voltage level on the line is input to a register that outputs a high or low to a circuit for detecting the presence of a front card. The circuit may be a hot swap controller, a CPU or a status indicator. Accordingly, depending on the output of the register, the circuit determines whether a front card is present in the particular slot.
- An embodiment of the invention includes a computer system including a circuit board, with the system comprising a slot coupled to a front side of the circuit board. A plurality of connectors is affixed to the circuit board in alignment with the slot, with the plurality of connectors including a first connector. A plurality of connector-pins are extended in a direction substantially perpendicular to and away from the circuit board, and has a column and row arrangement within the connectors. The first connector includes first and second connector-pins. A register having an input line and an output line is provided, with the input line connected to a voltage source through a pull-up resistor, and the first connector-pin connected to the input line of the register. A circuit having an input terminal is connected to the first connector-pin through the register, with the register connected to the input terminal of the circuit via the output line of the register, wherein depending on a voltage level of the first connector-pin, the register transmits one of a high and low signal to the input terminal of the circuit whereby the circuit detects a presence of a front card in the slot based on said one of a high and low signal.
- Another embodiment of the invention includes a circuit board having a front side, with the circuit board comprising a plurality of slots coupled to the front side of the circuit board. A plurality of connectors is disposed within each of the plurality of slots and including a first connector in each of the slots, with the respective first connectors of the slots including a first connector-pin and a second connector-pin. A plurality of connector-pins is disposed in an arrangement of a plurality of columns and rows in each of the connectors, with the plurality of columns including first and second columns. The connector-pins in the first and second columns are connected to a ground layer of the circuit board, except for the first connector-pins in the first connectors. An input/output device has a plurality of input lines and output lines, each of the input lines are connected to a voltage source through a pull-up resistor, and the first connector-pins in each of the slots are connected to the input/output device via the respective input lines. A circuit has a plurality of input terminals and is connected to the first connector-pins through the input/output device. The input terminals of the circuit are connected to the output lines of the input/output device, wherein depending on voltage levels of the respective first connector-pins, the input/output device transmits respective signals to the corresponding input terminals of the circuit whereby the circuit detects a presence of a front card in corresponding ones of the slots depending on the respective signals.
- A more complete understanding of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages and objects thereof, by a consideration of the following detailed description of the embodiment. Reference will be made to the appended sheets of drawings, which will first be described briefly.
- FIG. 1 is a perspective view of a conventional CPCI chassis system;
- FIG. 2 shows the form factor that is defined for the CPCI daughter card;
- FIG. 3 is a front view of a conventional 3U backplane having eight slots with two connectors each;
- FIG. 4(a) shows a front view of a conventional CPCI backplane in the 6U form factor;
- FIG. 4(b) shows a back view of a conventional CPCI backplane in the 6U form factor;
- FIG. 5 shows a side view of the conventional backplane of FIGS.4(a) and 4(b);
- FIG. 6(a) shows a front view of a conventional pin out arrangement of the connectors of a slot;
- FIG. 6(b) shows a back view of a conventional pin out arrangement of connectors of a slot;
- FIG. 7(a) shows a conventional hot swappable CPCI system for detecting the presence of a hot swappable front card;
- FIG. 7(b) shows a conventional hot swappable CPCI system for illustrating that the system cannot detect the presence of a non-hot swappable front card;
- FIG. 8(a) shows a front view of the pin out arrangement of the connectors of a slot according to an embodiment of the invention;
- FIG. 8(b) shows a modification of the pin out arrangement of FIG. 8(a) according to another embodiment of the invention;
- FIG. 9(a) shows a front card having a pin out arrangement corresponding to the pin out arrangement shown in FIG. 8(a);
- FIG. 9(b) shows a front card having a pin out arrangement corresponding to the pin out arrangement shown in FIG. 8(b);
- FIG. 10(a) shows a hot swappable CPCI system for detecting a non-hot swappable front card according to an embodiment of the invention;
- FIG. 10(b) shows a non-hot swappable CPCI system for detecting a non-hot swappable front card according to an embodiment of the invention;
- FIG. 10(c) shows a non-hot swappable CPCI system for detecting a non-hot swappable front card according to another embodiment of the invention;
- FIG. 11 shows a hot swappable CPCI system including a CPU and a status indicator according to an embodiment of the invention;
- FIG. 12 shows a plurality of slots having respective BD_DETECT# pins connected to respective inputs of a register for detecting the presence of front cards according to an embodiment of the invention; and
- FIG. 13 shows a side view of a register in the form of a front card according to an embodiment of the invention.
- The present invention relates to a CPCI system that reliably detects the presence of front cards that are inserted in the add-on slots. In a conventional CPCI system that supports hot swappability of the front cards, the insertion and presence of non-hot swappable front cards are not detectable. Accordingly, there is a need for a CPCI system that can detect the presence of all front cards that are inserted in the add-on slots, whether hot swappable or not. This would allow the operating system to have a more accurate and complete view of the hardware configuration.
- Referring to FIG. 1, there is shown a perspective view of a conventional CPCI chassis system. The
chassis system 100 includes a CPCI circuit board referred to in the conventional CPCI system as apassive backplane 102 since the circuit board is located at the back of thechassis 100 and add-on cards (front cards) can only be inserted from the front of thechassis 100. On the front side of thebackplane 102 are slots provided withconnectors 104. In theconventional chassis system 100 that is shown, a6U daughter card 108 is inserted into one of the slots and mates with a corresponding one of theconnectors 104. For proper insertion of thedaughter cards 108 into the slots, card guides 110 are provided. Thisconventional chassis system 100 provides front removable daughter cards and unobstructed cooling across the entire set ofdaughter cards 108. - Referring to FIG. 2, there is shown the form factor defined for the CPCI daughter card, which is based on the Eurocard industry standard. As shown in FIG. 2, the
daughter card 200 has afront plate interface 202 and ejector/injector handles 204. Thefront plate interface 202 is consistent with Eurocard packaging and is compliant with IEEE 1101.1 or IEEE 1101.10. The ejector/injector handles should also be compliant with IEEE 1101.1. One ejector/injector handle 204 is used for 3U daughter cards, and two ejector/injector handles 204 are used for 6U daughter cards. Theconnectors 104 a-104 e of thedaughter card 200 are numbered starting from thebottom connector 104 a, and both 3U and 6U daughter card sizes are defined, as described below. - The dimensions of the 3U form factor are approximately 160.00 mm by approximately 100.00 mm, and the dimensions of the 6U form factor are approximately 160.00 mm by approximately 233.35 mm. The 3U form factor includes two 2
mm connectors 104 a-104 b, which is the minimum number of connectors that are required to accommodate a full 64 bit CPCI bus. Specifically, the 104 a connectors are reserved to carry the signals required to support the 32-bit PCI bus, hence no other signals may be carried in any of the pins of this connector. Optionally, the 104 a connectors may have a reserved key area that can be provided with a connector “key”, which is a pluggable plastic piece that comes in different shapes and sizes, so that the add-on card can only mate with an appropriately keyed slot. The 104 b connectors are defined to facilitate 64 bit transfers or for rear panel I/O in the 3U form factor. The 104 c-104 e connectors are available for 6U systems as shown in FIG. 1. The 6U form factor includes the twoconnectors 104 a-104 b of the 3U form factor, and three additional 2mm connectors 104 c-104 e. In other words, the 3U form factor includesconnectors 104 a-104 b, and the 6U form factor includesconnectors 104 a-104 e. The threeadditional connectors 104 c-104 e of the 6U form factor can be used for secondary buses (i.e., Signal Computing System Architecture (SCSA) or MultiVendor Integration Protocol (MVIP) telephony buses), bridges to other buses (i.e., Virtual Machine Environment (VME) or Small Computer System Interface (SCSI)), or for user specific applications. Note that the CPCI specification defines the locations for all theconnectors 104 a-104 e, but only the signal-pin assignments for theCPCI bus portion - Referring to FIG. 3, there is shown a front view of a conventional 3U backplane having eight slots with two connectors each. A CPCI system is composed of one or more CPCI bus segments, where each bus segment includes up to eight CPCI card slots. Each CPCI bus segment consists of one
system slot 302, and up to seven peripheral slots 304 a-304 g. The CPCI daughter card for thesystem slot 302 provides arbitration, clock distribution, and reset functions for the CPCI peripheral cards on the bus segment. The peripheral slots 304 a-304 g may contain simple cards, intelligent slaves or PCI bus masters. - The
connectors pins 306 that project in a direction perpendicular to thebackplane 300, and are designed to mate with the front side “active” daughter cards (“front cards”), and “pass-through” its relevant interconnect signals to mate with the rear side “passive” input/output (I/O) card(s) (“rear transition cards”). In other words, in the conventional CPCI system, the connector-pins 306 allow the interconnected signals to pass-through from the front cards to the rear transition cards. - Referring to FIGS.4(a) and 4(b), there are shown a front and back view of a conventional CPCI backplane in the 6U form factor, respectively. In FIG. 4(a), four slots 402 a-402 d are provided on the
front side 400 a of thebackplane 400. In FIG. 4(b), four slots 406 a-406 d are provided on theback side 400 b of thebackplane 400. Note that in both FIGS. 4(a) and 4(b) only four slots are provided instead of eight slots as in FIG. 3. Further, it is important to note that each of the slots 402 a-402 d on thefront side 400 a has five connectors 404 a-404 e while each of the slots 406 a-406 d on theback side 400 b has only fourconnectors 408 b-408 e. This is because, as in the 3U form factor of the conventional CPCI system, the 404 a connectors are provided for 32 bit PCI and connector keying. Thus, they do not have I/O connectors to their rear. Accordingly, the front cards that are inserted in the front side slots 402 a-402 d only transmit signals to the rear transition cards that are inserted in the back side slots 406 a-406 d throughfront side connectors 404 b-404 e. - Referring to FIG. 5, there is shown a side view of the conventional backplane of FIGS.4(a) and 4(b). As shown in FIG. 5, slot 402 d on the
front side 400 a andslot 406 d on theback side 400 b are arranged to be substantially aligned so as to be back to back. Further,slot 402 c on thefront side 400 a andslot 406 c on thebackside 400 b are arranged to be substantially aligned, and so on. Accordingly, thefront side connectors 404 b-404 e are arranged back-to-back with theback side connectors 408 b-408 e. Note that thefront side connector 404 a does not have a corresponding back side connector. It is important to note that thesystem slot 402 a is adapted to receive the CPU front card, and the signals from thesystem slot 402 a are then transmitted to corresponding connector-pins of theperipheral slots 402 b-402 d. Thus, the conventional CPCI system can have expanded I/O functionality by adding peripheral front cards in theperipheral slots 402 b-402 d. - FIGS.6(a) and 6(b) illustrate a conventional pin out arrangement of the connectors in a CPCI system. Specifically, FIG. 6(a) shows a front view of a conventional pin out arrangement of the connectors of a slot. Referring to FIG. 6(a), there are shown connectors 404 a-404 e of
slot 402 d. The connector-pins are arranged in a column and row configuration. Each of the connectors 404 a-404 e have seven columns of pins, which are designated as Z, A, B, C, D, E, and F going from left to right. Each of the connectors 404 a-404 e also has twenty-two rows of connector-pins. - As shown in FIG. 6(a), all of the connector-pins in the Z and F columns are connected to a ground layer GND in the backplane. The connector-pins of the other columns A, B, C, D, and E are connected to various other CPCI signals including ground. Note that in FIG. 6(a), the connector-pins having XXX or YYY designations do not mean that those pins share the same signals, respectively. Instead, the XXX or YYY designations are provided to show that these connector-pins are defined to carry various CPCI signals that are not particularly relevant to the present invention, and thus are not specifically shown in FIG. 6(a). Note that the other slots 402 a-402 c have a similar pin out arrangement as shown in
slot 402 d of FIG. 6(a). - FIG. 6(b) shows a back view of a conventional pin out arrangement of the connectors of a slot. Referring to FIG. 6(b), there are shown
connectors 408 b-408 e ofslot 406 d. Note that the back view shows only four connectors instead of five. This is because, as shown in FIGS. 4(a) and 4(b), the front side of the backplane has five connectors while the back side of the backplane has four connectors. Further, the column arrangement of the connector-pins is designated as F, E, D, C, B, A, and Z going from left to right. This is because the connector-pins ofslots row 2 ofconnector 404 b is the same connector-pin located at column A,row 2 ofconnector 408 b. Also, similar to FIG. 6(a), connector-pins located at columns F and Z in FIG. 6(b) are connected to a ground layer GND in the backplane. Likewise, connector-pins of columns A, B, C, D, and E are connected to various signals, as in FIG. 6(a). - More specifically, the Hot Swap/HA Specification defines the connector-pin located at column D,
row 15 of connector 404(a) to be a BD_SELECT# pin. Other relevant connector-pins ofconnector 404 a include a BD_HEALTHY# pin, which is located at column B,row 4, and a BD_RESET# pin, which is located at column C,row 5. The significance of these connector-pins in the Hot Swap/HA specification is discussed in more detail with reference to FIGS. 7(a) and 7(b) below. - FIG. 7(a) shows a conventional hot swappable CPCI system for detecting the presence of a hot swappable front card. Referring to FIG. 7(a), a
CPCI backplane 702 has aconnector 404 a in one of its slots, and ahot swap controller 704 coupled to the 10backplane 702. Theconnector 404 a has the BD_SELECT# 706 a, BD_HEALTHY# 708 a, and BD_RESET# 710 a connector-pins, which are of male-type, connected to thehot swap controller 704. Note that theBD_SELECT# line 716 is connected to a “weak-pull-down”resistor 714 that is connected to aground layer 718 in thebackplane 702. Afront card 200 b has correspondingBD SELECT# 706 b,BD_HEALTHY# 708 b, andBD_RESET# 710 b connector-pins, which are of female-type, with theBD_SELECT# pin 706 b being connected to a voltage source Vcc through a pull-upresistor 712. TheBD_SELECT# line 716 is defined to provide a signal to thehot swap controller 704 such that thecontroller 704 knows whether a hot swappablefront card 200 b has been inserted in a particular slot. Further, thehot swap controller 704 performs the powering up/down of the hot swappablefront card 200 b using thisline 716. TheBD_HEALTHY# pin 708 b is connected to aninternal power supply 724 b in thefront card 200 b such that theBD_HEALTHY# line 720 indicates to thehot swap controller 704 whether or not the board is defective. TheBD_RESET# line 722 is used by thehot swap controller 704 to reset afront card 200 b so that it remains in a back up mode. All of the above described functions of the BD_SELECT#, BD_HEALTHY#, and BD_RESET# lines are described in more detail below. - Specifically, when the hot swappable
front card 200 b is inserted into a slot ofbackplane 702 such that theconnectors BD_SELECT# pin 706 a is pulled up to the voltage level of theBD_SELECT# pin 706 b. This pull-up on theBD_SELECT# pin 706 a is detected by thehot swap controller 704 such that thehot swap controller 704 senses that a hot swappablefront card 200 b has been inserted in the particular slot. Thehot swap controller 704 then drives theBD_SELECT# line 716 low so as to allow thefront card 200 b to power up. Then, thehot swap controller 704 examines theBD_HEALTHY# line 720 to determine if the insertedfront card 200 b is healthy. This determination is made by sensing the voltage level from theinternal power supply 724 b. Thehot swap controller 704 then uses theBD_RESET# line 722 to release thefront card 200 b from the reset mode to connect to the system. Alternatively, if thefront card 200 b is a back up board, then theBD_RESET# line 722 is used to maintain thefront card 200 b in the reset mode until backup is needed from theparticular front card 200 b. - FIG. 7 (b) shows a conventional hot swappable CPCI system for illustrating that the system cannot detect the insertion of a non-hot swappable front card. Referring to FIG. 7 (b), note that a non-hot swappable
front card 200 c has correspondingBD_SELECT# 706 c,BD_HEALTHY# 708 c, and BD_RESET# 710 c connector-pins, which are of female-type, with theBD_SELECT# pin 706c in the non-hot swappablefront card 200 c not connected to a pull-up resistor, but connected instead to aground layer 726 in thefront card 200 c. It should also be appreciated that theBD_HEALTHY# pin 708 c is again connected to aninternal power supply 724 c in thefront card 200 c such that the BDHEALTHY# line 720 indicates to thehot swap controller 704 whether or not the board is defective. When the non-hot swappablefront card 200 c is inserted in a slot of thebackplane 702 so that theconnectors BD_SELECT# pin 706 a becomes grounded. Thehot swap controller 704 senses that theBD_SELECT# pin 706 a is at ground potential and so does not know that a non-hot swappablefront card 200 c has been inserted in the particular slot ofbackplane 702. This is because theBD_SELECT# line 716 is already connected to the “weak-pull-down”resistor 714 and cannot distinguish between the ground potential and the weak-pull-down on theresistor 714. The weak-pull-down on theresistor 714 typically involves a high value resistor that is connected to aground layer 718 such that thehot swap controller 704 senses the logic level/voltage potential to be a “low”. Accordingly, thehot swap controller 704 is not able to distinguish between the low level and the ground potential. Note that theground layer 718 of thebackplane 702 is at the same potential as theground layer 726 of thefront card 200 c when thefront card 200 c is inserted in a slot ofbackplane 702. This is because the grounded connector-pins of thebackplane 702 mate with the grounded connector-pins of thefront card 200 c so that they share a common ground. As described above, thehot swap controller 704 in conventional CPCI systems cannot detect the insertion of a non-hot swappablefront card 200 c in a particular slot. In contrast, the present invention reliably detects the presence of all cards, 200 b, 200 c, whether hot swappable or not. - FIG. 8(a) shows a front view of the pin out arrangement of the connectors of a CPCI system according to an embodiment of the invention. Referring to FIG. 8(a), there are shown connectors 404 a-404 e of
slot 402 d. The connector-pins are arranged in a column and row configuration. Each of the connectors 404 a-404 e have seven columns of pins, which are designated as Z, A, B, C, D, E, and F going from left to right. The connectors 404 a-404 e each also have twenty-two rows. - As shown in FIG. 8(a), all of the connector-pins in column Z and all of the connector-pins in column F, except for one, are connected to a ground layer GND in the backplane. Specifically, the connector-pin located in column F,
row 1 ofconnector 404 a of FIG. 8(a) is designated as a BD_DETECT# pin, and is used to detect the insertion of a front card, whether hot swappable or not. The connector-pins of the other columns A, B, C, D, and E are defined for various CPCI signals. Note that in FIG. 8(a) as in FIG. 6(a), the connector-pins having XXX or YYY as the defined signals do not mean that those pins share the same signals, respectively. Instead, the XXX or YYY designations are provided to show that these connector-pins are connected to various CPCI signals that are not particularly relevant to the present invention, and thus are not specifically shown in FIG. 8(a). Note that the other slots 402 a-402 c have a similar pin out arrangement as shown inslot 402 d of FIG. 8(a). - FIG. 8(b) shows a modification of the pin out arrangement of FIG. 8(a) according to another embodiment of the invention. Referring to FIG. 8(b), the arrangement of the connector-pins are exactly the same as the arrangement shown in FIG. 8(a), except for the key area located in
connector 404 a. As illustrated in FIG. 8(b), the 404 a connectors may have an optional key area that is provided with a connector “key”, which is a pluggable plastic piece that comes in different shapes and sizes, so that only an appropriately keyed front card can mate with a particular slot. - FIG. 9(a) shows a front card having a pin out arrangement corresponding to the pin out arrangement shown in FIG. 8(a). The pin out arrangement of the
front card 200 is essentially a mirror image of the pin out arrangement shown in FIG. 8(a), except that the connector-pin located at column F,row 1, ofconnector 104 a is connected to a ground layer in the front card. FIG. 9(b) shows a front card having a pin out arrangement corresponding to the pin out arrangement of FIG. 8(b). This arrangement is the same as the arrangement shown in FIG. 9(a), except for the addition of the key area. - FIG. 10 (a) shows a hot swappable CPCI system for detecting a non-hot swappable front card according to an embodiment of the invention. Referring to FIG. 10(a), a
CPCI backplane 1002 has ahot swap controller 1004, aregister 1006, a pull-upresistor 1008 connected to a voltage source Vcc, and aconnector 1010 in one of its slots. Theconnector 1010 has the BD_SELECT# 1014 a, BD_HEALTHY# 1016 a, and BD_RESET# 1018 a connector-pins, which are of male-type, connected to thehot swap controller 1004. TheBD_DETECT# pin 1012 a, which is of male-type, is connected to theregister 1006 via theD input line 1038. Theregister 1006 has itsD input line 1038 connected to a voltage source Vcc through the pull-upresistor 1008, and theQ output line 1040 of theregister 1006 is connected to thehot swap controller 1004. - A
front card 1020 has aconnector 1022 with correspondingBD_DETECT# 1012 b,BD_SELECT# 1014 b,BD_HEALTHY# 1016 b, andBD_RESET# 1018 b connector-pins, which are of female-type. Both theBD_DETECT# 1012 b andBD_SELECT# 1016 b pins are connected to aground layer 1024 in thefront card 1020. Note that theBD_SELECT# pin 1016 b is connected to theground layer 1024 since thefront card 1020 is not a hot swappable card. - In the present embodiment, when the D input to the
register 1006 is high, which occurs when afront card 1020 is not present in the particular slot, then the Q output is high. When the D input of theregister 1006 is low or ground, then the Q output is low. - Accordingly, the
hot swap controller 1004 detects the insertion of a front card when the Q output is low. For example, when the non-hotswappable front card 1020 is inserted into a slot ofbackplane 1002 such that theconnectors D input line 1038 is pulled-down to a ground potential since theBD_DETECT# pin 1012 b in thefront card 1020 is connected to theground layer 1024. This pull-down on the voltage level of theD input line 1038 is input to theregister 1006. The hot swap controller then detects that theQ output line 1040 of theregister 1006 is low, and senses that a front card has been inserted in that particular slot. Accordingly, in the present invention, thehot swap controller 1004 is able to detect the insertion of the non-hot swappable front card. Note that the present invention detects the presence of non-hot swappable cards during the initial power-up since the non-hot swappable cards cannot be inserted unless the system is in an off state. - In another aspect of the invention, the hot swap controller is able to distinguish between the presence of a hot swappable card and a non-hot swappable card. This is because if the
BD_SELECT line 1032 is high, then thehot swap controller 1004 knows that a hot swappable card has been inserted. If theBD_SELECT# line 1032 is low and theQ output line 1040 from theregister 1006 is low, then thehot swap controller 1004 senses that a non-hot swappable card is present. Note that in the embodiment of FIG. 10(a), a CPU card (not shown) may include a stand-alone hot swap controller in the backplane. Further, the hot swap controller shares this information with the operating system of the CPU (not shown) so that a more accurate hardware configuration is known to the operating system. - FIG. 10(b) shows a non-hot swappable CPCI system for detecting a non-hot swappable front card according to an embodiment of the invention. Referring to FIG. 10(b), instead of hot swap controller, a
CPU 1042 receives the Q output signal from theregister 1006. Similar to thehot swap controller 1004 of FIG. 10(a), a low on theQ output line 1040 indicates to theCPU 1042 the insertion of afront card 1020 while a high on theQ output line 1040 represents that the particular slot is empty. In the present embodiment, the CPU receives the Q output signal so that the operating system has a more accurate view of the hardware configuration in the system. - FIG. 10(c) shows a non-hot swappable CPCI system for detecting a non-hot swappable front card according to another embodiment of the invention. Referring to FIG. 10(c), instead of a CPU, a
status indicator 1044 receives the Q output signal from theregister 1006. Similar to the embodiments of FIG. 10(a) and 10(b), a low on theQ output line 1040 indicates the insertion of afront card 1020 while a high on theQ output line 1040 represents that the particular slot is empty. Thestatus indicator 1044 receives this information and provides the status of the slots of the system to a user. Typically, thestatus indicator 1044 is a front panel LED light indicator having corresponding light indicators to light when a board is present in the system. - FIG. 11 shows a hot swappable CPCI system including a CPU and status indicator according to an embodiment of the invention. Referring to FIG. 11, the
backplane 1002 includes thehot swap controller 1004, theCPU 1042 and thestatus indicator 1044. Theregister 1006 acts as a buffer such that the signal that is input to its D input is stored for use by the hot swap controller, CPU and status indicator. As described above, a low on theQ output line 1040 indicates the presence of a front card in the particular slot while a high on theQ output line 1040 indicates the absence of a front card in the particular slot. The signal from theQ output line 1040 is used by the hot swap controller, CPU and the status indicator in the manner described above with respect to FIGS. 10(a)-10(c), respectively. - FIG. 12 shows a plurality of slots having respective BD_DETECT# pins connected to respective inputs of a register for detecting the presence of front cards according to an embodiment of the invention. Referring to FIG. 12,
slots connector 404 a on a backplane 1200. The connector-pins designated as 1202 a, 1202 b are the BD_DETECT# pins.Signal trace lines pins register 1006, respectively. Theregister 1006 has correspondingQ output lines hot swap controller 1004,CPU 1042, andstatus indicator 1044. Note that in the present embodiment, only twosignal lines register 1006 since only twoslots register 1006 and outputs from theregister 1006 to the hot swap controller, CPU and status indicator. Further, in the embodiment of FIG. 12, theregister 1006 is disposed on an area of the backplane 1200. However, theregister 1006 may be provided as a front card that is inserted in a slot of the backplane. For example, FIG. 13 shows a side view of a register in the form of afront card 1300 inserted in aslot 1302 of thebackplane 1304. - Having thus described embodiments of the present invention, it should be apparent to those skilled in the art that certain advantages of the within system have been achieved. It should also be appreciated that various modifications, adaptations, and alternative embodiments thereof may be made within the scope and spirit of the present invention. For example, a reliable card detection system in a CPCI system has been illustrated, but it should be apparent that the inventive concepts described above would be equally applicable to other types of busses and computer systems, whether hot swappable or not. The invention is further defined by the following claims.
Claims (18)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/887,807 US6501660B1 (en) | 2001-06-22 | 2001-06-22 | Reliable card detection in a CPCI system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/887,807 US6501660B1 (en) | 2001-06-22 | 2001-06-22 | Reliable card detection in a CPCI system |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020196611A1 true US20020196611A1 (en) | 2002-12-26 |
US6501660B1 US6501660B1 (en) | 2002-12-31 |
Family
ID=25391903
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/887,807 Expired - Lifetime US6501660B1 (en) | 2001-06-22 | 2001-06-22 | Reliable card detection in a CPCI system |
Country Status (1)
Country | Link |
---|---|
US (1) | US6501660B1 (en) |
Cited By (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010045363A2 (en) * | 2008-10-16 | 2010-04-22 | Silicon Image, Inc. | Discovery of connections utilizing a control bus |
CN103810079A (en) * | 2012-11-13 | 2014-05-21 | 联想(北京)有限公司 | Cue circuit and electronic equipment |
WO2014075268A1 (en) * | 2012-11-15 | 2014-05-22 | Abb Technology Ltd | Module supporting hot plug, backplane, system and method for determining connection thereof |
US20160026606A1 (en) * | 2011-10-31 | 2016-01-28 | Iii Holdings 2, Llc | Node card management in a modular and large scalable server system |
US9680770B2 (en) | 2009-10-30 | 2017-06-13 | Iii Holdings 2, Llc | System and method for using a multi-protocol fabric module across a distributed server interconnect fabric |
US9749326B2 (en) | 2009-10-30 | 2017-08-29 | Iii Holdings 2, Llc | System and method for data center security enhancements leveraging server SOCs or server fabrics |
US9866477B2 (en) | 2009-10-30 | 2018-01-09 | Iii Holdings 2, Llc | System and method for high-performance, low-power data center interconnect fabric |
US9876735B2 (en) | 2009-10-30 | 2018-01-23 | Iii Holdings 2, Llc | Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect |
US9929976B2 (en) | 2009-10-30 | 2018-03-27 | Iii Holdings 2, Llc | System and method for data center security enhancements leveraging managed server SOCs |
US20180098415A1 (en) * | 2016-09-30 | 2018-04-05 | Asustek Computer Inc. | Electronic assemblies and method for manufacturing the same |
US9977763B2 (en) | 2009-10-30 | 2018-05-22 | Iii Holdings 2, Llc | Network proxy for high-performance, low-power data center interconnect fabric |
US10021806B2 (en) | 2011-10-28 | 2018-07-10 | Iii Holdings 2, Llc | System and method for flexible storage and networking provisioning in large scalable processor installations |
US10140245B2 (en) | 2009-10-30 | 2018-11-27 | Iii Holdings 2, Llc | Memcached server functionality in a cluster of data processing nodes |
US10153603B1 (en) | 2016-06-22 | 2018-12-11 | EMC IP Holding Company LLC | Adapter system |
US10235322B1 (en) * | 2016-06-22 | 2019-03-19 | EMC IP Holding Company LLC | Hot-swappable adapter system for non-hot-swappable expansion cards |
US10877695B2 (en) | 2009-10-30 | 2020-12-29 | Iii Holdings 2, Llc | Memcached server functionality in a cluster of data processing nodes |
US11467883B2 (en) | 2004-03-13 | 2022-10-11 | Iii Holdings 12, Llc | Co-allocating a reservation spanning different compute resources types |
US11496415B2 (en) | 2005-04-07 | 2022-11-08 | Iii Holdings 12, Llc | On-demand access to compute resources |
US11494235B2 (en) | 2004-11-08 | 2022-11-08 | Iii Holdings 12, Llc | System and method of providing system jobs within a compute environment |
US11522952B2 (en) | 2007-09-24 | 2022-12-06 | The Research Foundation For The State University Of New York | Automatic clustering for self-organizing grids |
US11630704B2 (en) | 2004-08-20 | 2023-04-18 | Iii Holdings 12, Llc | System and method for a workload management and scheduling module to manage access to a compute environment according to local and non-local user identity information |
US11650857B2 (en) | 2006-03-16 | 2023-05-16 | Iii Holdings 12, Llc | System and method for managing a hybrid computer environment |
US11652706B2 (en) | 2004-06-18 | 2023-05-16 | Iii Holdings 12, Llc | System and method for providing dynamic provisioning within a compute environment |
US11658916B2 (en) | 2005-03-16 | 2023-05-23 | Iii Holdings 12, Llc | Simple integration of an on-demand compute environment |
US11720290B2 (en) | 2009-10-30 | 2023-08-08 | Iii Holdings 2, Llc | Memcached server functionality in a cluster of data processing nodes |
US11960937B2 (en) | 2022-03-17 | 2024-04-16 | Iii Holdings 12, Llc | System and method for an optimizing reservation in time of compute resources based on prioritization function and reservation policy parameter |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100414943B1 (en) * | 2001-12-28 | 2004-01-16 | 엘지전자 주식회사 | Apparatus and Method for Distribution Clock in Multiple Processing System based on Compact Peripheral Component Interconnect |
JP2003323446A (en) * | 2002-03-01 | 2003-11-14 | Inventio Ag | Procedure, system and computer program product for representation of multimedia content in elevator installation |
US7533210B2 (en) * | 2002-10-24 | 2009-05-12 | Sun Microsystems, Inc. | Virtual communication interfaces for a micro-controller |
US7080264B2 (en) * | 2002-12-11 | 2006-07-18 | Sun Microsystems, Inc. | Methods and apparatus for providing microprocessor firmware control of power sequencing on a CPCI card |
US7304855B1 (en) * | 2003-03-03 | 2007-12-04 | Storage Technology Corporation | Canister-based storage system |
US7030771B2 (en) * | 2003-03-12 | 2006-04-18 | Sun Microsystems, Inc. | System and method to provide hot-swap status indication in a computer system having redundant power supplies |
US6993614B2 (en) * | 2003-08-26 | 2006-01-31 | Sun Microsystems, Inc. | Management methods and apparatus that are independent of operating systems |
CN104639211A (en) * | 2013-11-08 | 2015-05-20 | 华为技术有限公司 | Connector detection method, device and system |
US11132322B2 (en) * | 2018-03-15 | 2021-09-28 | Hewlett. Packard Enterprise Development LP | Determining a quantity of hot swap controllers |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07271711A (en) * | 1994-03-28 | 1995-10-20 | Toshiba Corp | Computer system |
US5636347A (en) * | 1994-09-27 | 1997-06-03 | Intel Corporation | Computer card insertion detection circuit |
US5568610A (en) * | 1995-05-15 | 1996-10-22 | Dell Usa, L.P. | Method and apparatus for detecting the insertion or removal of expansion cards using capacitive sensing |
US5974489A (en) * | 1996-12-18 | 1999-10-26 | Sun Micro Systems | Computer bus expansion |
US6125417A (en) * | 1997-11-14 | 2000-09-26 | International Business Machines Corporation | Hot plug of adapters using optical switches |
US6185645B1 (en) * | 1998-06-08 | 2001-02-06 | Micron Electronics, Inc. | Method for removing power and signals from an inadvertently swapped bus card |
-
2001
- 2001-06-22 US US09/887,807 patent/US6501660B1/en not_active Expired - Lifetime
Cited By (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11467883B2 (en) | 2004-03-13 | 2022-10-11 | Iii Holdings 12, Llc | Co-allocating a reservation spanning different compute resources types |
US11652706B2 (en) | 2004-06-18 | 2023-05-16 | Iii Holdings 12, Llc | System and method for providing dynamic provisioning within a compute environment |
US11630704B2 (en) | 2004-08-20 | 2023-04-18 | Iii Holdings 12, Llc | System and method for a workload management and scheduling module to manage access to a compute environment according to local and non-local user identity information |
US11537434B2 (en) | 2004-11-08 | 2022-12-27 | Iii Holdings 12, Llc | System and method of providing system jobs within a compute environment |
US11886915B2 (en) | 2004-11-08 | 2024-01-30 | Iii Holdings 12, Llc | System and method of providing system jobs within a compute environment |
US11861404B2 (en) | 2004-11-08 | 2024-01-02 | Iii Holdings 12, Llc | System and method of providing system jobs within a compute environment |
US11494235B2 (en) | 2004-11-08 | 2022-11-08 | Iii Holdings 12, Llc | System and method of providing system jobs within a compute environment |
US11762694B2 (en) | 2004-11-08 | 2023-09-19 | Iii Holdings 12, Llc | System and method of providing system jobs within a compute environment |
US11537435B2 (en) | 2004-11-08 | 2022-12-27 | Iii Holdings 12, Llc | System and method of providing system jobs within a compute environment |
US11709709B2 (en) | 2004-11-08 | 2023-07-25 | Iii Holdings 12, Llc | System and method of providing system jobs within a compute environment |
US11656907B2 (en) | 2004-11-08 | 2023-05-23 | Iii Holdings 12, Llc | System and method of providing system jobs within a compute environment |
US11658916B2 (en) | 2005-03-16 | 2023-05-23 | Iii Holdings 12, Llc | Simple integration of an on-demand compute environment |
US11533274B2 (en) | 2005-04-07 | 2022-12-20 | Iii Holdings 12, Llc | On-demand access to compute resources |
US11765101B2 (en) | 2005-04-07 | 2023-09-19 | Iii Holdings 12, Llc | On-demand access to compute resources |
US11522811B2 (en) | 2005-04-07 | 2022-12-06 | Iii Holdings 12, Llc | On-demand access to compute resources |
US11831564B2 (en) | 2005-04-07 | 2023-11-28 | Iii Holdings 12, Llc | On-demand access to compute resources |
US11496415B2 (en) | 2005-04-07 | 2022-11-08 | Iii Holdings 12, Llc | On-demand access to compute resources |
US11650857B2 (en) | 2006-03-16 | 2023-05-16 | Iii Holdings 12, Llc | System and method for managing a hybrid computer environment |
US11522952B2 (en) | 2007-09-24 | 2022-12-06 | The Research Foundation For The State University Of New York | Automatic clustering for self-organizing grids |
WO2010045363A2 (en) * | 2008-10-16 | 2010-04-22 | Silicon Image, Inc. | Discovery of connections utilizing a control bus |
CN102203755A (en) * | 2008-10-16 | 2011-09-28 | 晶像股份有限公司 | Discovery of connections utilizing a control bus |
WO2010045363A3 (en) * | 2008-10-16 | 2010-06-10 | Silicon Image, Inc. | Discovery of connections utilizing a control bus |
US20100100200A1 (en) * | 2008-10-16 | 2010-04-22 | Jason Seung-Min Kim | Discovery of connections utilizing a control bus |
US8275914B2 (en) | 2008-10-16 | 2012-09-25 | Silicon Image, Inc. | Discovery of connections utilizing a control bus |
US9866477B2 (en) | 2009-10-30 | 2018-01-09 | Iii Holdings 2, Llc | System and method for high-performance, low-power data center interconnect fabric |
US9929976B2 (en) | 2009-10-30 | 2018-03-27 | Iii Holdings 2, Llc | System and method for data center security enhancements leveraging managed server SOCs |
US9680770B2 (en) | 2009-10-30 | 2017-06-13 | Iii Holdings 2, Llc | System and method for using a multi-protocol fabric module across a distributed server interconnect fabric |
US11720290B2 (en) | 2009-10-30 | 2023-08-08 | Iii Holdings 2, Llc | Memcached server functionality in a cluster of data processing nodes |
US10140245B2 (en) | 2009-10-30 | 2018-11-27 | Iii Holdings 2, Llc | Memcached server functionality in a cluster of data processing nodes |
US10135731B2 (en) | 2009-10-30 | 2018-11-20 | Iii Holdings 2, Llc | Remote memory access functionality in a cluster of data processing nodes |
US9749326B2 (en) | 2009-10-30 | 2017-08-29 | Iii Holdings 2, Llc | System and method for data center security enhancements leveraging server SOCs or server fabrics |
US11526304B2 (en) | 2009-10-30 | 2022-12-13 | Iii Holdings 2, Llc | Memcached server functionality in a cluster of data processing nodes |
US10050970B2 (en) | 2009-10-30 | 2018-08-14 | Iii Holdings 2, Llc | System and method for data center security enhancements leveraging server SOCs or server fabrics |
US9977763B2 (en) | 2009-10-30 | 2018-05-22 | Iii Holdings 2, Llc | Network proxy for high-performance, low-power data center interconnect fabric |
US10877695B2 (en) | 2009-10-30 | 2020-12-29 | Iii Holdings 2, Llc | Memcached server functionality in a cluster of data processing nodes |
US9876735B2 (en) | 2009-10-30 | 2018-01-23 | Iii Holdings 2, Llc | Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect |
US10021806B2 (en) | 2011-10-28 | 2018-07-10 | Iii Holdings 2, Llc | System and method for flexible storage and networking provisioning in large scalable processor installations |
US9965442B2 (en) * | 2011-10-31 | 2018-05-08 | Iii Holdings 2, Llc | Node card management in a modular and large scalable server system |
US9792249B2 (en) | 2011-10-31 | 2017-10-17 | Iii Holdings 2, Llc | Node card utilizing a same connector to communicate pluralities of signals |
US20160026606A1 (en) * | 2011-10-31 | 2016-01-28 | Iii Holdings 2, Llc | Node card management in a modular and large scalable server system |
CN103810079A (en) * | 2012-11-13 | 2014-05-21 | 联想(北京)有限公司 | Cue circuit and electronic equipment |
CN104813300A (en) * | 2012-11-15 | 2015-07-29 | Abb技术有限公司 | Module supporting hot plug, backplane, system and method for determining connection thereof |
WO2014075268A1 (en) * | 2012-11-15 | 2014-05-22 | Abb Technology Ltd | Module supporting hot plug, backplane, system and method for determining connection thereof |
US10153603B1 (en) | 2016-06-22 | 2018-12-11 | EMC IP Holding Company LLC | Adapter system |
US10235322B1 (en) * | 2016-06-22 | 2019-03-19 | EMC IP Holding Company LLC | Hot-swappable adapter system for non-hot-swappable expansion cards |
US20180098415A1 (en) * | 2016-09-30 | 2018-04-05 | Asustek Computer Inc. | Electronic assemblies and method for manufacturing the same |
US10057975B2 (en) * | 2016-09-30 | 2018-08-21 | Asustek Computer Inc. | Electronic assemblies and method for manufacturing the same |
US11960937B2 (en) | 2022-03-17 | 2024-04-16 | Iii Holdings 12, Llc | System and method for an optimizing reservation in time of compute resources based on prioritization function and reservation policy parameter |
Also Published As
Publication number | Publication date |
---|---|
US6501660B1 (en) | 2002-12-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6501660B1 (en) | Reliable card detection in a CPCI system | |
US6677687B2 (en) | System for distributing power in CPCI computer architecture | |
US20030140190A1 (en) | Auto-SCSI termination enable in a CPCI hot swap system | |
US7103704B2 (en) | Exporting 12C controller interfaces for 12C slave devices using IPMI micro-controller | |
US6646868B2 (en) | Computer bus rack having an increased density of card slots | |
US6629181B1 (en) | Incremental bus structure for modular electronic equipment | |
US20060140211A1 (en) | Blade server system with a management bus and method for managing the same | |
US5995376A (en) | Chassis which includes configurable slot 0 locations | |
US7533210B2 (en) | Virtual communication interfaces for a micro-controller | |
US6735660B1 (en) | Sideband signal transmission between host and input/output adapter | |
EP1376375A2 (en) | Computer system and method of communicating | |
US20060090025A1 (en) | 9U payload module configurations | |
US7188205B2 (en) | Mapping of hot-swap states to plug-in unit states | |
EP1413945A2 (en) | System and method for providing a persistent power mask | |
US20030235042A1 (en) | Carrier card and method | |
US7000053B2 (en) | Computer system having a hot swappable hot swap controller | |
US6976113B2 (en) | Supporting non-hotswap 64-bit CPCI cards in a HA system | |
US6418026B1 (en) | Bus rack for accommodating plural stand-alone computers | |
US20040246982A1 (en) | Methods and apparatus for configuring a packet switching (PS) backplane to support various configurations | |
US6836811B2 (en) | Front access only CPCI computer system | |
US6662255B1 (en) | System for housing CompactPCI adapters in a non-CompactPCI frame | |
US7080264B2 (en) | Methods and apparatus for providing microprocessor firmware control of power sequencing on a CPCI card | |
US7254039B2 (en) | 3U payload module configurations | |
EP1415234B1 (en) | High density severlets utilizing high speed data bus | |
US20060062227A1 (en) | Switched fabric payload module having an embedded central switching resource |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SUN MICROSYSTEMS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HO, RAYMOND K.;JOCHIONG, VICTOR E.;REEL/FRAME:011938/0693 Effective date: 20010619 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: ORACLE AMERICA, INC., CALIFORNIA Free format text: MERGER AND CHANGE OF NAME;ASSIGNORS:ORACLE USA, INC.;SUN MICROSYSTEMS, INC.;ORACLE AMERICA, INC.;REEL/FRAME:037278/0670 Effective date: 20100212 |