US20030057473A1 - Nonvolatile semiconductor memory device - Google Patents
Nonvolatile semiconductor memory device Download PDFInfo
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- US20030057473A1 US20030057473A1 US09/558,585 US55858500A US2003057473A1 US 20030057473 A1 US20030057473 A1 US 20030057473A1 US 55858500 A US55858500 A US 55858500A US 2003057473 A1 US2003057473 A1 US 2003057473A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 53
- 229920005591 polysilicon Polymers 0.000 claims abstract description 53
- 238000005530 etching Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 31
- 238000004519 manufacturing process Methods 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims 2
- 230000001590 oxidative effect Effects 0.000 claims 2
- 239000010410 layer Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
In a memory cell, a gate oxide film is formed on a surface of semiconductor substrate and a first floating gate is formed on the gate oxide film. An insulating film is formed on a first floating gate and a second floating gate is formed on the insulating film. The first and second floating gates constitute a floating gate in the memory cell. An insulating film between the first floating gate and the second floating gate acts as an etching stopper when a polysilicon constituting the second floating gate is etched.
Description
- This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-119848, filed Apr. 27, 1999, the entire contents of which are incorporated herein by reference.
- The present invention relates to a nonvolatile semiconductor memory device of a two-layered gate structure, such as a flash EEPROM and a method for manufacturing the same.
- In recent years, a NAND cell type EEPROM has been proposed as one of electrically erasable semiconductor memory devices. This NAND cell type EEPROM is of such a type that a plurality of memory cells are provided with their source and drain shared by adjacent ones in a series-connected manner and each cell connected as one unit to a corresponding bit line. The respective memory cell constitutes a two-layered gate structure with a floating gate (charge storage layer) and control gate stacked with an insulating film therebetween.
- In this type of nonvolatile semiconductor memory device, a shallow trench isolation (STI) is adopted, as an element isolation area, in place of a LOCOS (Local oxidation of silicon). In the case where a nonvolatile semiconductor memory device using such an STI is manufactured, a process for forming a floating gate is used before forming a trench.
- FIGS. 7 and 8 show a conventional nonvolatile semiconductor memory device using a process for forming a floating gate in advance.
- In FIGS. 7 and 8, a
gate oxide film 102 and plurality offloating gates 103 of, for example, polysilicon are formed over a surface of asemiconductor substrate 101. A buriedinsulating film 104 of, for example, a silicon oxide film constituting an STI area is formed in asemiconductor substrate 101 at an area situated between those floatinggates 103. For example, an ONOfilm 105 is formed as a composite insulating film on the respectivefloating gate 103. Acontrol gate 106 of, for example, polysilicon is formed on the ONOfilm 105. Amask material 107 of, for example, silicon nitride film is formed on thecontrol gate 106. Themask material 107 is used as a mask when thecontrol gate 106 and floatinggate 103 are etched. - As shown in FIG. 7, the
floating gate 103 is comprised of a first floating gate 103 a and second floatinggate 103 b formed on the first floating gate 103 a. The buriedinsulating film 104 is formed after the formation of the first floating gate 103 a but before the formation of the second floatinggate 103 b. - That is, the
gate oxide film 102, first floating gate 103 a of, for example, polysilicon and mask material (not shown) of, for example, a silicon nitride film are sequentially formed over the surface of asemiconductor substrate 101. The mask material is subjected to a patterning process. With the patterned mask material used as a mask, the first floating gate 103 a,gate oxide film 102 andsemiconductor substrate 101 are dry etched, for example, are reactive ion etched (RIE) to provide a plurality oftrenches 108. - Then, a silicon oxide film is deposited, by a chemical vapor deposition (CVD) method, on a whole surface and, by doing so, the trench is buried with the silicon oxide film. Thereafter, with the mask material used as a stopper, the silicon oxide film is planarized by a chemical mechanical polishing (CMP) method to provide the buried
insulating film 104. Then the second floatinggate 103 b is formed on the first floating gate 103 a. - In the case where the floating gate is initially formed as set out above, the
floating gate 103 is comprised of the first floating gate 103 a and second floatinggate 103 b and hence is made thicker. As shown in FIG. 8, therefore, when thefloating gate 103 is etched back to thegate oxide film 102 with themask material 107 andcontrol gate 106 as a mask, the aspect ratio becomes greater. It is, therefore, difficult to set a selection ratio between the polysilicon as thefloating gate 103 and the gate oxide film optimal. In the case where, for example, the selection ratio is set greater, the polysilicon is less likely to be etched. This provides a possibility of the polysilicon remaining. In the case where, on the other hand, the selection ratio is set smaller, etching is not stopped to thegate oxide film 102 and reaches thesemiconductor substrate 101, thus presenting a problem. - The present invention solves the above-mentioned task and the object of the present invention is to provide a nonvolatile semiconductor memory device and method for manufacturing the same which, when a floating gate is etched, ensures easier etching control.
- The object of the present invention is achieved by the following device.
- A nonvolatile semiconductor memory device comprises a floating gate formed over a semiconductor substrate with a gate insulating film formed therebetween, a control gate insulated from the floating gate and source/drain regions formed in the semiconductor substrate at those areas situated on both sides of the floating gate and an insulating film provided inside the floating gate.
- Further, the object of the present invention is achieved by the following device.
- A nonvolatile semiconductor memory device comprises a first conductive film formed over a semiconductor substrate with a gate insulating film formed therebetween, a first insulating film formed on the first conductive film, a second conductive film formed on the first insulating film, the second conductive film and first conducive film constituting a floating gate, a second insulating film formed on the second conductive film, a third conductive film formed on the second insulating film and constituting a control gate, and source/drain regions formed in the semiconductor substrate at those areas situated on both sides of the floating gate.
- Further, the object of the present invention is achieved by the following method.
- A method for manufacturing a nonvolatile semiconductor memory device comprises the steps of forming a first polysilicon film over a semiconductor substrate with a gate insulting film formed therebetween, forming a first insulating film on the first polysilicon film, forming a second polysilicon film on the first insulating film, forming a second insulating film on the second polysilicon film, forming a third polysilicon film on the second insulating film, forming a mask material on the third polysilicon film, a first etching process for etching the third polysilicon film by using mask material as a mask, the first etching process forming a control gate, a second etching process for etching the second polysilicon film to the first insulating film by using mask material as a mask, the second etching process forming a first floating gate, and a third etching process for etching the first polysilicon film to the gate insulating film by using mask material as a mask, the third etching process forming a second floating gate.
- According to the present invention, the gate insulating film is provided inside the floating gate and, by using this insulating film as an etching stopper, the etching control can be easily effected when the polysilicon constituting the floating gate is etched.
- Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
- The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
- FIG. 1 shows a perspective view showing an embodiment of the present invention;
- FIGS. 2A to2C are cross-sectional views sequentially showing the manufacturing steps of the embodiment in FIG. 1;
- FIGS. 3A to3C are cross-sectional views sequentially showing the manufacturing steps following the manufacturing step of FIG. 2C;
- FIG. 4 is a perspective view showing the manufacturing step following the manufacturing step of FIG. 3C;
- FIG. 5 is a perspective view showing the manufacturing step following the manufacturing step of FIG. 4;
- FIG. 6 is a perspective view showing the manufacturing step following the manufacturing step of FIG. 5;
- FIG. 7 is a cross-sectional view showing a conventional nonvolatile semiconductor memory device; and
- FIG. 8 is a perspective view showing the manufacturing step following the manufacturing step of FIG. 7.
- The embodiment of the present invention will be explained below with reference to the accompanying drawing.
- FIG. 1 shows a nonvolatile semiconductor memory device of the present invention and shows the case where the present invention is applied to a NAND type flash EEPROM for initially forming a gate. In FIG. 1, one NAND cell comprises a plurality of memory cells MC connected in a series array. Each NAND cell is separated by an STI area comprised of a buried
insulating film 24 formed in asemiconductor substrate 11 of, for example, a P type. - In the respective memory cell MC, a
gate oxide film 12 is formed on a surface of thesemiconductor substrate 11. A first floating gate 13 a of, for example, polysilicon is formed on thegate oxide film 12 to provide a floating gate FG. Aninsulating film 14 constituting the feature of the present invention is formed on a first floating gate 13 a. Thisinsulating film 14 is comprised of, for example, a silicon oxide film. A second floatinggate 13 b of, for example, polysilicon is formed on theinsulating film 14 to provide a floating gate FG. And anONO film 15 for example is formed as a composite insulating film on the second floatinggate 13 b and acontrol gate 16 of, for example, polysilicon is formed on thefilm 15 and amask material 17 of, for example, a silicon nitride film is formed on thecontrol gate 16. Themask material 17,control gate 16 and first and second floatinggates 13 a and 13 b are covered with thesilicon nitride film 18 to provide a gate structure GS. - n-Type diffusion layers19 are formed as source and drain regions in the
semiconductor substrate 11 at those areas situated between the gate structures GS. one memory cell MC is formed by the diffusion layers 19 and gate structure GS. The respective memory cells MC are series-connected with the diffusion layers 19 shared by those adjacent ones. These memory cells MC are covered with aninterlayer insulating film 20 of, for example, BPSG and aninterconnect line 21 of, for example, tungsten is formed at the interinterlayer insulating film 20. - FIGS.2 to 6 show the process for manufacturing a nonvolatile semiconductor memory device shown in FIG. 1 and the same reference numerals are employed to designate parts or elements corresponding to those shown in FIG. 1.
- First, as shown in FIG. 2A, a
gate oxide film 12, first floating gate 13 a of, for example, polysilicon andmask material 22 of, for example, silicon nitride film are sequentially formed over the surface of asemiconductor substrate 11. Then, themask material 22 is subjected to a patterning process. With the patternedmask material 22 used as a mask, the first floating gate 13 a,gate oxide film 12 andsemiconductor substrate 11 are etched by, for example, an RIE etching method to provide a plurality oftrenches 23. - Then, as shown in FIG. 2B, a buried insulating
film 24 of, for example, a silicon oxide film is deposited on a whole surface by, for example, a CVD (chemical vapor deposition) method and thetrench 23 is buried with the insulatingfilm 24. As the buried insulatingfilm 24 use can be made of, for example, TEOS (tetra-ethylortho-silicate) film, HDP (high density plasma decomposition) film, etc. Thereafter, with the mask material 2 used as a stopper, thesilicon oxide film 24 is planarized by a CMP (chemical mechanical polishing) method. - Then, as shown in FIG. 2C, by dry or wet etching the surface of the
silicon oxide film 24 in thetrench 23 is made somewhat lower than the surface of themask material 22. By doing so, a step difference between the surface of the first floating gate 13 a and the surface of the buried insulatingfilm 24 is decreased and themask material 22 is eliminated. - Then, as shown in FIG. 3A, an insulating
film 14 is formed on the surface of the first floating gate 13 a. This insulatingfilm 14 is formed in an oxidation atmosphere, for example, by exposing the substrate structure to an oxidation-filled atmosphere in a furnace or can be formed by depositing a silicon oxide film or silicon nitride film on the first floating gate 13 a with the use of, for example, an LPCVD (low pressure CVD). - It is necessary that the insulating
film 14 be made to have some thickness to allow it to act as a stopper in an etching process to be done on a second floating gate as will be described later. In order to suppress a lowering in a coupling ratio of the floating gate, the thickness of the insulatingfilm 14 is preferably made as small as possible. Therefore, the thickness of the insulatingfilm 14 is set in a range of, for example, above about 10 angstrom but below about 50 angstrom and the optimal value is, for example, about 25 to 35 angstrom. The film thickness is substantially the same as in the case of a silicon oxide film or silicon nitride film. - Then, as shown in FIG. 3B, a second floating
gate 13 b of, for example, polysilicon is formed on a whole surface of the insulatingfilm 14. - Then, as shown in FIG. 3C, the second floating
gate 13 b is patterned by the dry etching to form aslit 26 over the upper surface of the buried insulatingfilm 24. Then, for example, anONO film 15 as a composite insulating film, control gate (CG) 16 of, for example, polysilicon and mask material of, for example, a silicon nitride film are sequentially formed on a whole surface including the second floatinggate 13 b. - Then, as shown in FIG. 4, the
mask material 17 is patterned by, for example, the dry etching. With the use of the patternedmask material 17, the polysilicon of thecontrol gate 16 andONO film 15 are etched by, for example, the RIE etching. - Then, as shown in FIG. 5, the polysilicon constituting the second floating
gate 13 b is etched by, for example, the RIE etching method under a condition of a greater selection ratio to theinsulting film 14. For this reason, it is possible to prevent the polysilicon remaining between those second floatinggates 13 b. Thereafter, the insulatingfilm 14 is removed by the dry or wet etching. - Then, as shown in FIG. 6, the polysilicon constituting the first floating gate13 a is etched by, for example, the RIE etching method under a condition of a greater selection ratio to the
gate oxide film 12. For this reason, it is possible to prevent the polysilicon remaining between the first floating gates 13 a. Further, the etching processing is stopped with thegate insulation film 12 and, therefore, thesubstrate 11 can be prevented from being etched. - Thereafter, as shown in FIG. 1, the
mask material 17,control gate 16 and first and second floatinggates 13 a and 13 b are covered with asilicon nitride film 18 and a gate structure GS is formed and n-type diffusion layers 19 acting as source and drain regions are formed in thesemiconductor substrate 11 at those areas situated between the respective gate structures GS. The diffusion layers 19 and gate structure GS provide one memory cell MC. Those memory cells MC is covered with aninterlayer insulating film 20 of, for example, BPSG. Aninterconnect line 21 of, for example, tungsten and contact holes, not shown, are formed at theinterlayer insulating film 20 to provide a NAND type flash EPROM. - According to the above-mentioned embodiment, the insulating
film 14 is formed on the first floating gate 13 a and the second floatinggate 13 b is formed on the insulatingfilm 14, and the second and first floatinggates 13 b and 13 a are etched by two separate steps. Therefore, the aspect ratio at the respective etching processing can be made smaller than in the conventional method and the etching control, that is, the setting of the etching condition, becomes easier. When, therefore, the polysilicon constituting the second floatinggate 13 b is etched, it is done under a condition of a greater selection ratio to the insulatingfilm 14 and it is possible to prevent the polysilicon remaining between those second floatinggates 13 b. Further, when the polysilicon constituting the first floating gate 13 a is etched, it is done under a condition of a greater selection ratio to thegate oxide film 12. For this reason, it is possible to prevent the polysilicon remaining between those first floating gates 13 a and the etching processing can be stopped down to thegate oxide film 12, so that the etching of thesubstrate 11 can be prevented. - As set out above, by providing the insulating
film 14 between the first and second floatinggates 13 a and 13 b, the coupling ratio is lowered, thus presenting a problem. A voltage Vfg on the floating gate FG is represented by the following equation: - Vfg=(Cono/(Cono+Cox)+Cox×Cono/Cf)Vcg
- where
- Cono: a capacitance of the
ONO film 15 - Cox: a capacitance of the
gate oxide film 12 - Cf: a capacitance of the insulating
film 14 - Vcg: a voltage on the
control gate 16. - As evident from the above, if the capacitance cf of the insulating
film 14 is set to be greater, then it is possible to decrease an adverse effect resulting from the insulatingfilm 14. For this reason, it is possible to suppress a lowering in coupling ratio by making the thickness of the insulatingfilm 14 smaller or making the permittivity greater. A practical example of the film thickness of the insulatingfilm 14 is as set out above. - Although, the above-mentioned embodiment has been explained as being applied to the NAND cell type EEPROM, the present invention is not restricted thereto and can also be applied to a NOR type EEPROM.
- Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Claims (19)
1. A nonvolatile semiconductor memory device comprising:
a memory cell having a floating gate formed over a semiconductor substrate with a gate insulating film formed therebetween and a control gate insulated from the floating gate and source/drain regions formed in the semiconductor substrate at those areas situated on both sides of the floating gate; and
an insulating film provided inside the floating gate.
2. A device according to claim 1 , wherein the insulating film is comprised of one of a silicon oxide film and silicon nitride film.
3. A device according to claim 2 , wherein the insulating film is in a range of above about 10 angstrom but below about 50 angstrom.
4. A nonvolatile semiconductor memory device comprising:
a first conductive film formed over a semiconductor substrate with a gate insulating film formed therebetween;
a first insulating film formed on the first conductive film;
a second conductive film formed on the first insulating film, the second conductive film and first conductive film constituting a floating gate;
a second insulating film formed on the second conductive film;
a third conductive film formed on the second insulating film and constituting a control gate; and
source/drain regions formed in the semiconductor substrate at those areas situated on both sides of the floating gate.
5. A device according to claim 4 , wherein the first insulating film is comprised of one of a silicon oxide film and silicon nitride film.
6. A device according to claim 5 , wherein the first insulating film is in a range of above about 10 angstrom but below about 50 angstrom.
7. A method for manufacturing a nonvolatile semiconductor memory device comprising the steps of:
forming a first polysilicon film over a semiconductor substrate with a gate insulating film formed therebetween;
forming a first insulating film on the first polysilicon film;
forming a second polysilicon film on the first insulating film;
forming a second insulating film on the second polysilicon film;
forming a third polysilicon film on the second insulating film;
forming a mask material on the third polysilicon film;
a first etching process for etching the third polysilicon film by using mask material as a mask, the first etching process forming a control gate;
a second etching process for etching the second polysilicon film to the first insulating film by using mask material as a mask, the second etching process forming a first floating gate; and
a third etching process for etching the first polysilicon film to the gate insulating film by using mask material as a mask, the third etching process forming a second floating gate.
8. A method according to claim 7 , wherein the first insulating film is formed by one of oxidizing the first polysilicon and depositing an insulating material.
9. A method according to claim 7 , wherein the second etching step has a greeter selection ratio to the first insulating film.
10. A method according to claim 9 , wherein the first insulating film is comprised of one of a silicon oxide film and silicon nitride film.
11. A method according to claim 10 , wherein the first insulating film is in a range of above about 10 angstrom but below about 50 angstrom.
12. A method for manufacturing a nonvolatile semiconductor memory device, comprising the steps of:
sequentially forming a gate insulating film, first polysilicon film and first insulating film over a semiconductor substrate;
forming a trench in the semiconductor substrate through a gate insulating film, first polysilicon film and first insulating film;
depositing a second insulating film over a whole surface to bury the trench with the second insulating film;
removing the second insulating film by etching to allow the second insulating film to remain in the trench at a height level lower than the surface of the first insulating film;
removing the first insulating film;
forming a third insulating film on the first polysilicon film;
forming a second polysilicon film on the third insulating film;
forming a fourth insulating film on the second polysilicon film;
forming a third polysilicon film on the fourth insulating film;
forming a mask material on the third polysilicon film;
a first etching process for etching the third polysilicon film by using mask material as a mask, the first etching process forming a control gate;
a second etching process for etching the second polysilicon film to the third insulating film by using mask material as a mask, the second etching process forming a first floating gate; and
a third etching process for etching the first polysilicon film to the gate insulating film by using mask material as a mask, the third etching process forming a second floating gate.
13. A method according to claim 12 , wherein the third insulating film is formed by one of oxidizing the first polysilicon film and depositing an insulating material.
14. A method according to claim 12 , wherein the second etching step has a greater selection ratio to the third insulating film.
15. A method according to claim 14 , wherein the third insulating film is comprised of one of a silicon oxide film and silicon nitride film.
16. A method according to claim 15 , wherein the third insulating film is in a range of above about 10 angstrom but below about 50 angstrom.
17. A nonvolatile semiconductor memory device comprising:
a plurality of first conductive films formed over a semiconductor substrate with a gate insulating film formed therebetween;
a trench formed between those adjacent first insulating films and in the semiconductor substrate;
a first insulating film for element isolation which is provided on the trench;
a second insulating film formed on the first conductive film;
a second conductive film formed on the second insulating film and, together with the first conductive film, constituting a floating gate;
a third insulating film formed on the second conductive film;
a third conductive film formed on the third insulating film and constituting a control gate; and
source/drain regions formed in the semiconductor substrate at those areas situated on both sides of the floating gate.
18. A device according to claim 17 , wherein the second insulating film is comprised of one of a silicon oxide film and silicon nitride film.
19. A device according to claim 18 , wherein the second insulating film is in a range of above about 10 angstrom but below about 50 angstrom.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US10/412,365 US6943074B2 (en) | 1999-04-27 | 2003-04-14 | Nonvolatile semiconductor memory device having a two-layer gate structure and method for manufacturing the same |
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JP11-119848 | 1999-04-27 | ||
JP11119848A JP2000311956A (en) | 1999-04-27 | 1999-04-27 | Nonvolatile semiconductor memory device and manufacture thereof |
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US09/558,585 Abandoned US20030057473A1 (en) | 1999-04-27 | 2000-04-26 | Nonvolatile semiconductor memory device |
US10/412,365 Expired - Fee Related US6943074B2 (en) | 1999-04-27 | 2003-04-14 | Nonvolatile semiconductor memory device having a two-layer gate structure and method for manufacturing the same |
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JP (1) | JP2000311956A (en) |
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CN (1) | CN1154190C (en) |
TW (1) | TW452983B (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
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US20050047261A1 (en) * | 2003-08-28 | 2005-03-03 | Naoki Kai | Nonvolatile semiconductor memory device having trench-type isolation region, and method of fabricating the same |
WO2006036334A2 (en) * | 2004-09-17 | 2006-04-06 | Freescale Semiconductor, Inc. | Programming and erasing structure for a floating gate memory cell and method of making |
US20070047303A1 (en) * | 2005-08-25 | 2007-03-01 | Jun-Seuck Kim | Electrically erasable programmable read-only memory cell transistor and related method |
US20080090352A1 (en) * | 2006-10-16 | 2008-04-17 | Sang-Kyoung Lee | Nonvolatile memory device and method of manufacturing the same |
US7888204B2 (en) | 2007-08-16 | 2011-02-15 | Samsung Electronics Co., Ltd. | Method of forming nonvolatile memory device having floating gate and related device |
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US20080090352A1 (en) * | 2006-10-16 | 2008-04-17 | Sang-Kyoung Lee | Nonvolatile memory device and method of manufacturing the same |
US7579237B2 (en) | 2006-10-16 | 2009-08-25 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of manufacturing the same |
US7888204B2 (en) | 2007-08-16 | 2011-02-15 | Samsung Electronics Co., Ltd. | Method of forming nonvolatile memory device having floating gate and related device |
US20110101437A1 (en) * | 2007-08-16 | 2011-05-05 | Samsung Electronics Co., Ltd. | Method of forming nonvolatile memory device having floating gate and related device |
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CN110854121A (en) * | 2019-11-27 | 2020-02-28 | 上海华力微电子有限公司 | Semiconductor manufacturing method |
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KR20010014833A (en) | 2001-02-26 |
CN1154190C (en) | 2004-06-16 |
US20030209753A1 (en) | 2003-11-13 |
KR100373472B1 (en) | 2003-02-25 |
CN1271963A (en) | 2000-11-01 |
TW452983B (en) | 2001-09-01 |
JP2000311956A (en) | 2000-11-07 |
US6943074B2 (en) | 2005-09-13 |
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