US20030091139A1 - System and method for adjusting phase offsets - Google Patents
System and method for adjusting phase offsets Download PDFInfo
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- US20030091139A1 US20030091139A1 US10/328,119 US32811902A US2003091139A1 US 20030091139 A1 US20030091139 A1 US 20030091139A1 US 32811902 A US32811902 A US 32811902A US 2003091139 A1 US2003091139 A1 US 2003091139A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
- H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration
- H03K3/356043—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00195—Layout of the delay element using FET's
- H03K2005/00208—Layout of the delay element using FET's using differential stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
- This application is a continuation-in-part of U.S. patent application Ser. No. 09/955,693 entitled “Linear Phase Detector for High-Speed Clock and Data Recovery” and filed on Sep. 18, 2001.
- The above-referenced United States patent application is hereby incorporated herein by reference in its entirety.
- High-speed data communication relies heavily on clock and data recovery (CDR) circuits. CDR circuits extract clock information from an incoming data signal (e.g., an incoming data stream) and employ the extracted clock signal to regenerate the data signal, thereby reducing noise from the original data signal and preventing noise accumulation along the communication lines.
- A CDR circuit employs a full-rate phase-lock loop. When the loop is locked, the CDR circuit should generate a clock signal with the exact frequency of the incoming data signal and fix the phase relationship between the generated clock signal and the incoming data signal. In a conventional phase detector, the conventional lock position is such that the latching clock edge is at the center between the data transitions.
- However, optimal data regeneration does not always occur at the conventional lock position of a conventional phase detector. For example, different asymmetries and jitter may occur in the data signal, especially if the data signal is propagating long distances. In addition, the data signal may be further degraded due to the severe dispersion and distortion that may occur in the particular communications medium (e.g., fiber, wire, cable, air, etc.).
- Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
- Aspects of the present invention may be found in, for example, systems and methods that adjust phase offsets. In one embodiment, the present invention may provide a phase detector. The phase detector may include, for example, a delay block coupled to a first exclusive OR (XOR) gate via a first delay element; a first sequential device coupled the first XOR gate via a second delay element; a second sequential device coupled to the first sequential device and coupled to a second XOR gate via a third delay element; and a third sequential device coupled to the second sequential device and coupled to the second XOR gate via a fourth delay element.
- In another embodiment, the present invention may provide a system that adjusts a locked phase offset between a data signal and a clock signal. The system may include, for example, a phase detector in which one or more data paths used in generating an error signal or a reference signal comprise a respective delay element; a loop filter coupled to the phase detector; and a voltage controlled oscillator coupled to the loop filter and an output of the voltage controlled oscillator coupled to an input of the phase detector.
- In yet another embodiment, the present invention may provide a method that adjusts a locked phase offset between a data signal and a clock signal. The method may comprise, for example, adjusting a time delay in a respective delay element disposed in each data path of a phase detector.
- In yet another embodiment, the present invention may provide a method that adjusts a locked phase offset between a data signal and a clock signal. The method may comprise, for example, adjusting a first time delay in a first data path of a phase detector; and adjusting a second time delay in a second data path of the phase detector
- These and other features and advantages of the present invention may be appreciated from a review of the following detailed description of the present invention, along with the accompanying figures in which like reference numerals refer to like parts throughout.
- FIG. 1 shows an embodiment of an optical receiver according to the present invention.
- FIG. 2 shows an embodiment of a clock and data recovery (CDR) circuit according to the present invention.
- FIG. 3 shows a diagram illustrating an embodiment of a phase detector according to the present invention.
- FIG. 4 shows a diagram illustrating an embodiment of a phase detector according to the present invention.
- FIG. 5 shows a diagram illustrating an embodiment of a delay element according to the present invention.
- Some aspects of the present invention may relate to systems and methods that adjust phase offsets, for example, in phase locked loops. Some embodiments according to the present invention may find application in use with, for example, phase detectors or clock and data recovery circuits.
- FIG. 1 shows an embodiment of an optical receiver according to the present invention. Although illustrated with respect to an optical receiver, the present invention need not be so limited. The optical receiver100 may include, for example, a
photodiode 110, afirst resistor 120, a pre-amplifier 130, anamplifier 140, a DCoffset correction circuit 150, asecond resistor 160, a clock and data recovery (CDR)circuit 170 and a link and data detect (LDD)circuit 180. TheCDR circuit 170 may include, for example, twooutputs first output 190 may provide, for example, a data signal; and thesecond output 200 may provide, for example, a clock signal. TheLDD circuit 180 may include, for example, twooutputs first output 210 may provide, for example, a squelch signal; and thesecond output 220 may provide, for example, a valid link signal. - An
optical data path 230 may be coupled to the optical receiver 100 via thephotodiode 110. Thephotodiode 110 and the first resistor 120 (e.g., a sensing resistor) may be in series and coupled between electrical ground and a voltage source VCC. A node between thephotodiode 110 and thefirst resistor 120 may be coupled to an input of the pre-amplifier 130. An output of the pre-amplifier 130 may be coupled to a first input of theamplifier 140. An output of theamplifier 140 may be coupled to respective inputs of the DCoffset correction circuit 150, the CDR circuit and theLDD circuit 180. The DCoffset correction circuit 150 may be coupled to a second input of theamplifier 140 via asecond resistor 160. TheCDR circuit 170 and theLDD circuit 180 may also be directly coupled to each other. - In operation, an optical data signal may be carried by the
optical data path 230. The optical data signal may be received by thephotodiode 110 which may generate a current as a function of the received optical data signal. The generated current may result in a particular voltage across thefirst resistor 120. The voltage may be amplified by the pre-amplifier 130 andamplifier 140. Offsets in the amplified voltage may be, for example, reduced by the DCoffset correction circuit 150 which may provide a feedback loop back to theamplifier 140 via thesecond resistor 160. The output of theamplifier 130 may drive theCDR circuit 170 and theLDD circuit 180. TheCDR circuit 170 may extract a clock signal from the amplified data signal and provide the clock signal on thesecond output 200 of theCDR circuit 170. TheCDR circuit 270 may also use the clock signal to retime the data for output on thefirst output 190 of theCDR circuit 170. If theLDD circuit 160 senses either a data or link signal from theamplifier 140, then a valid link signal may be asserted on thefirst output 210 of theLDD circuit 160. If theLDD circuit 160 senses a data signal from theamplifier 140, a receive squelch signal may be deasserted on thesecond output 200. - FIG. 2 shows an embodiment of a CDR circuit according to the present invention. The
CDR circuit 170 may include, for example, adata retimer 240, aphase detector 250, afrequency detector 260, aloop filter 270 and a voltage controlled oscillator (VCO) 280. TheCDR circuit 170 may include, for example, twoinputs first input 290 may provide, for example, a data signal received from theamplifier 140. Thesecond input 300 may provide, for example, a reference clock signal. TheCDR circuit 170 may include, for example, twooutputs first output 190 may provide, for example, a retimed data signal. Thesecond output 200 may provide, for example, a clock signal. Thefirst input 290 of theCDR circuit 170 may be coupled to respective inputs of the data retimer 240 and thephase detector 250. Thesecond input 300 of theCDR circuit 170 may be coupled to an input of thefrequency detector 260. Aloop 350 may provide a feedback loop from anoutput 345 of theVCO 280 to respective inputs of the data retimer 240, thephase detector 250 and thefrequency detector 260. An output of the data retimer 240 may coupled to thefirst output 190 of theCDR circuit 170. Afirst output 310 and asecond output 320 of thephase detector 250 may be coupled to a first input and a second input of theloop filter 270. Thefirst output 310 of thephase detector 250 may provide, for example, an error signal. Thesecond output 320 of thephase detector 250 may provide, for example, a reference signal. Anoutput 330 of thefrequency detector 260 may be coupled to a third input of theloop filter 270. Theloop filter 270 may be coupled to theVCO 280 via anoutput 340. Theoutput 340 may provide, for example, a control signal such as, for example, a control voltage signal or a tuning signal. Theoutput 345 of theVCO 280 may be coupled to thesecond output 200 of theCDR circuit 170 and may be coupled to theloop 350. TheVCO 280 may be coupled to the data retimer 240, thephase detector 250 and thefrequency detector 260 via theloop 350. - Although illustrated as separate components, the present invention also contemplates different levels of integration. For example, the
phase detector 250 may be integrated, at least in part, with thefrequency detector 260. In addition, although many of the signals are illustrated as single-ended signals, the present invention also contemplates that some signals may be represented as differential signals. For example, the reference clock signal provided on thesecond input 300 of theCDR circuit 170 may be a single-ended signal provided on a single line or a differential signal provided on at least two lines. Other examples of signals that may be represented as single-ended signals or differential signals include, for example, the data signal, the error signal and the reference signal. - In operation, a startup of the
CDR circuit 170 may be initiated, for example, by turning on a power supply, receiving a valid link via the receiver 100 or other events or conditions. A reference clock signal (e.g., a system clock signal) may be provided at thesecond input 300 of theCDR circuit 170. The reference clock signal may be, for example, a relatively low-frequency signal generated by a stable oscillation source (e.g., a crystal). Thefrequency detector 260 may compare the reference clock signal with theoutput 345 of theVCO 280, which may be carried via theloop 350 to an input of thefrequency detector 260. In one example, theoutput 345 of theVCO 280 may be divided down in frequency by, for example, a divider before being compared in thefrequency detector 260 with the reference clock signal (e.g., a low-frequency system clock). The signal comparison may include, for example, calculating a difference signal. Thefrequency detector 260 may provide an output signal, which may be a function of the signal comparison. The output signal of thefrequency detector 260 may then be filtered by theloop filter 270. - The
loop filter 270 may provide a control signal (e.g., a voltage control signal for controlling the VCO 280) onoutput 340. The control signal may be used by theVCO 280 to adjust, for example, the frequency of theoutput 345 of theVCO 280 and thus, the output 200 (e.g., a clock signal) of theCDR circuit 170. If the frequency of the signal on theoutput 345 of theVCO 280 is too high, thenloop filter 270 may provide a control signal on theoutput 340 such that theVCO 280 may lower the frequency of its output. If the frequency of the signal on theoutput 345 of theVCO 280 is too low, then theloop filter 270 may provide a control signal on theoutput 340 such that theVCO 280 may increase the frequency of its output. Since theloop 350 may provide theoutput 345 of theVCO 280 to thefrequency detector 260 as a feedback signal, the frequency of theoutput 345 of theVCO 280 may be adjusted with greater precision until, for example, a particular threshold condition is satisfied. - The
phase detector 250 may operate concurrently or sequentially with thefrequency detector 260. In one embodiment, for example, thefrequency detector 230 may first tune theoutput 345 of theVCO 280 to approximately the desired frequency before thephase detector 250 activates. Thephase detector 250 may receive, for example, a data signal at a first input and may receive, for example, theoutput 345 of theVCO 280, via theloop 350, at a second input. The data signal may be carried, for example, on thefirst input 290 of theCDR circuit 170 which may be coupled to the first input of thephase detector 250. In one example, the output of theamplifier 140 may be coupled to theCDR circuit 170 and may provide the data signal to thefirst input 290 of theCDR circuit 170. Thephase detector 250 may adjust the frequency and/or the phase of theoutput 345 of theVCO 280 by comparing the output signal carried by theoutput 345 of theVCO 280 and the data signal. In one embodiment, thephase detector 250 may determine a phase relationship between theVCO 280 output signal and the data signal. For example, thephase detector 250 may compare transitions in the data signal to the rising edges or the falling edges of a clock signal provided byoutput 345 of theVCO 280. Thephase detector 250 may produce an error signal on thefirst output 310 of thephase detector 250 that may be proportional to the phase relationship. Thephase detector 250 may also produce a reference signal on thesecond output 310 of thephase detector 250. The reference signal may be, for example, subtracted from the error signal to generate a correction signal that is independent of the data signal pattern, but is dependent on the phase error. - The
loop filter 270 may then subtract and filter the error signal and the reference signal in generating a control signal (e.g., a voltage signal) on theoutput 340 of theloop filter 270. If the data signal provided by thefirst input 290 and the clock signal provided by theoutput 345 of theVCO 280 do not have the desired phase relationship, then the control signal may be used to correct the phase error. For example, if the data signal comes too soon (i.e., the data signal is advanced in time relative to the clock signal), then thephase detector 250 may increase the error signal (e.g., an error voltage signal) on thesecond output 310 of thephase detector 250. This may result in a change in the control signal on theoutput 340 which may, in turn, increase the frequency of the output signal (i.e., the clock signal) on theoutput 345 of theVCO 280. As the frequency of the clock signal increases, its edges come sooner in time (i.e., the edges advance in time). Thus, for example, the rising edges of the clock come in better alignment with the transitions or other reference points in the data signal. The feedback may insure that the data signal and the clock signal have the desired phase relationship for retiming the data via thedata retimer 240. When the desired phase relationship is reached via the feedback, then the loop may be deemed locked. Thus, theCDR circuit 170 may include one or more phase-locked loops. - The data retimer240 may generate retimed data. The data retimer 240 may receive, for example, the data signal provided by the first input of the
CDR circuit 170 at a first input of the data retimer 240 and may receive, for example, the clock signal provided by theoutput 345 of theVCO 280 at a second input of thedata retimer 240. The data retimer 240 may generate retimed data using, for example, the data signal and the clock signal. The output of the data retimer 240 may be coupled, for example, to thefirst output 190 of the CDR circuit. - FIG. 3 shows a diagram illustrating an embodiment of a phase detector according to the present invention. The
phase detector 250 may include, for example, adelay block 350, a firstsequential device 360, a secondsequential device 370, a thirdsequential device 380, a first exclusive OR (XOR)gate 390 and asecond XOR gate 400. In one embodiment, the first sequential device (FSD) 360 may be, for example, a flip flop; and the second sequential device (SSD) 370 and the third sequential device (TSD) 380 may be, for example, latches. In one example, the flip flop may be a negative-edge triggered device (i.e., the flip flop may change state on the falling edges of the clock signal). The latch may be adapted to pass data when its clock input is high and to latch data when its clock input is low. - A
data input 410 to thephase detector 250 may be coupled to an input of thedelay block 350 and to an input to theFSD 360. Thedata input 410 may be coupled, for example, to a first input of thephase detector 250 which, in turn, may be coupled to thefirst input 290 of theCDR circuit 170. The output of theFSD 360 and the output of thedelay block 350 may be coupled to respective inputs of thefirst XOR gate 390. Theoutput 430 of thefirst XOR gate 390 may provide, for example, an error signal that may be carried by thefirst output 310 of thephase detector 250. The output of theFSD 360 may be coupled to an input of theSSD 370. The output of theSSD 370 may be coupled to an input of theTSD 380. Theclock input 420 may be coupled to theFSD 360, theSSD 370 and theTSD 380 and may provide a clock for each of the sequential devices. In one example, theTSD 380 may use the inverted clock signal as a clock signal. Theclock input 420 may be coupled, for example, to a second input of thephase detector 250 which, in turn, may be coupled to theoutput 345 of theVCO 280 via theloop 350. The output of theSSD 370 and the output of theTSD 380 may be coupled to respective inputs of thesecond XOR gate 400. Theoutput 440 of thesecond XOR gate 400 may provide, for example, a reference signal that may be carried by thesecond output 320 of thephase detector 250. - In operation, a data signal may be provided by the
data input 410 and received by theFSD 360 and thedelay block 350. TheFSD 360 may be, for example, a flip flop. The flip flop may be clocked by a clock signal provided by theclock input 420. The clock signal may have been generated, for example, by theVCO 280. For example, on each falling edge of the clock signal, data in the data signal may be latched by the flip flop and may be held at its output. In one embodiment, the output signal of the flip flop may be the data signal retimed to follow a falling edge of the clock signal. TheSSD 370 and theTSD 380 may be, for example, latches. The output signal of the flip flop may be passed by the latch of theSSD 370 when the clock signal is high or may be latched when the clock signal is low. In one embodiment, the output signal of the latch of theSSD 370 may be the output signal of the flip flop delayed by half a clock cycle. The output signal of the latch of theSSD 370 may be passed by the latch of theTSD 380 when the clock signal is low or may be latched when the clock signal is high. In one embodiment, the output signal of the latch of theTSD 380 may be the output signal of the latch of theSSD 370 delayed by half a clock cycle. - The
delay block 350 may delay the data signal received from thedata input 410 by a particular time delay. In one embodiment, the delay through thedelay block 350 may be approximately equal to the clock-to-output delay of the flip flop of theFSD 360. The clock-to-output delay for a flip flop may be the delay of the output changing in response to a clock edge. Thefirst XOR gate 400 may produce an output signal on theoutput 430 of thefirst XOR gate 400. The output signal of thefirst XOR gate 390 may be a function of the exclusive OR between the output of thedelay block 350 and the output of theflip flop 360. The output signal of thefirst XOR gate 390 may be an error signal. Thesecond XOR gate 400 may produce an output signal on theoutput 440 of thesecond XOR gate 400. The output signal of thesecond XOR gate 390 may be a function of the exclusive OR between the output of the latch of theSSD 370 and the output of the latch of theTSD 380. The output signal of thesecond XOR gate 390 may be a reference signal. - FIG. 4 shows a diagram illustrating an embodiment of a phase detector according to the present invention. The
phase detector 250 may include many of the same components as described above including, for example, theFSD 360, theSSD 370, theTSD 380, thefirst XOR gate 390 and thesecond XOR gate 400. In FIG. 4, thedelay block 350 is illustrated as adelay cell 450. Thephase detector 350 may also include, for example, afirst delay element 460, asecond delay element 470, athird delay element 480 and afourth delay element 490. Thefirst delay element 460 may be disposed between the output of thedelay cell 450 and the first input of thefirst XOR gate 390. Thesecond delay element 470 may be disposed between the output of theFSD 360 and the second input of thefirst XOR gate 390. Thethird delay element 480 may be disposed between the output of theSSD 370 and the first input of thesecond XOR gate 400. Thefourth delay element 490 may be disposed between the output of theTSD 380 and the second input of thesecond XOR gate 400. As illustrated, a delay element has been disposed in each of the four data paths. However, a delay element need not be present in each data path. Eachdelay element - Although illustrated as separate components, the present invention also contemplates various degrees of integration. For example, the
first delay element 460 may be integrated, at least in part, with the delay cell or with thefirst XOR gate 390. Similarly, theother delay elements sequential devices XOR gates - FIG. 5 shows a diagram illustrating an embodiment of a delay element according to the present invention. Delay elements may be realized in any number of conventional manners. In one example, the delay element may include, for example, a
variable capacitor 500. Thevariable capacitor 500 may be disposed between electrical ground and the line to which the delay element may be adding delay. Thevariable capacitor 500 may be formed in any number of conventional manners. In one example, thevariable capacitor 500 may include conventionally configured transistors. - In operation, the
delay elements elements first XOR gate 390; and delayelements second XOR gate 400. By using a delay element for each branch input to theXOR gate 390, a wider range of delay mismatches may be available. However, a delay element need not be present in each branch input to the XOR gates. In one example, a relatively small amount of delay in each of the input branches of the XOR gates may generate a relatively large amount of relative delay between the data signal and the clock signal. In some applications such as, for example, some applications related to high-speed data recovery, introducing small delays in the data signal may help in preserving data integrity. - In some applications, the phase detector may lock the phase relationship between the clock signal and the data signal such that the latching clock edge is at the center between the data transitions. However, the data signal may be severely distorted and dispersed due to, for example, the data signal traveling over very long distances. The data signal may be subject to, for example, an asymmetrical jitter distribution. In such cases, the optimal phase relationship between the clock signal and the data signal may not be with the latching clock edge centered between the data transitions. Thus, through the use of the
delay elements - One or more embodiments according to the present invention may have one or more of the advantages as set forth below.
- By using delay elements to generate a different phase-lock position, the
CDR circuit 170 may not accumulate charge. In one example, when no data is being received or when a long chain of ones or zeroes is being received, the CDR circuit may not accumulate charge. The accumulation of charge may have the potential of pushing the loop out of lock. Compare, e.g., “Method and Apparatus for High Speed Signal Recovery,” U.S. patent application Ser. No. 10/159,788 to Momtaz et al., assigned to the same assignee as the present application and filed on May 30, 2002. The above-referenced application is hereby incorporated by reference in its entirety. - One or more embodiments according to the present invention may generate the desired phase-offset from inside of the phase detector and the amount of phase-offset does not change with the input data pattern.
- One or more embodiments according to the present invention may be used in, for example, linear-type phase detectors, binary-type (e.g., bang-bang type) phase detectors and other types of phase detectors.
- According to one or more embodiments of the present invention, since the delay elements are added on the data path, the delay elements may be effective when there is a transition. Accordingly, the phase detector may only adjust the phase relationship between the clock signal and the data signal when the data signal is changing. Thus, the phase adjustment amount may be independent of the input data pattern.
- While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.
Claims (24)
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US10/328,119 US20030091139A1 (en) | 2001-09-18 | 2002-12-23 | System and method for adjusting phase offsets |
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Application Number | Priority Date | Filing Date | Title |
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US09/955,693 US7092474B2 (en) | 2001-09-18 | 2001-09-18 | Linear phase detector for high-speed clock and data recovery |
US10/328,119 US20030091139A1 (en) | 2001-09-18 | 2002-12-23 | System and method for adjusting phase offsets |
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US09/955,693 Continuation-In-Part US7092474B2 (en) | 2001-09-18 | 2001-09-18 | Linear phase detector for high-speed clock and data recovery |
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US09/955,693 Expired - Fee Related US7092474B2 (en) | 2001-09-18 | 2001-09-18 | Linear phase detector for high-speed clock and data recovery |
US10/328,119 Abandoned US20030091139A1 (en) | 2001-09-18 | 2002-12-23 | System and method for adjusting phase offsets |
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US09/955,693 Expired - Fee Related US7092474B2 (en) | 2001-09-18 | 2001-09-18 | Linear phase detector for high-speed clock and data recovery |
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US (2) | US7092474B2 (en) |
EP (1) | EP1294123B1 (en) |
DE (1) | DE60205997T2 (en) |
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Also Published As
Publication number | Publication date |
---|---|
DE60205997D1 (en) | 2005-10-13 |
DE60205997T2 (en) | 2006-06-22 |
EP1294123A1 (en) | 2003-03-19 |
EP1294123B1 (en) | 2005-09-07 |
US7092474B2 (en) | 2006-08-15 |
US20030053576A1 (en) | 2003-03-20 |
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