US20030116816A1 - Image sensor and manufacturing method thereof - Google Patents
Image sensor and manufacturing method thereof Download PDFInfo
- Publication number
- US20030116816A1 US20030116816A1 US10/318,122 US31812202A US2003116816A1 US 20030116816 A1 US20030116816 A1 US 20030116816A1 US 31812202 A US31812202 A US 31812202A US 2003116816 A1 US2003116816 A1 US 2003116816A1
- Authority
- US
- United States
- Prior art keywords
- image sensor
- layer
- substrate
- electrode
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 239000010409 thin film Substances 0.000 claims abstract description 21
- 229910004613 CdTe Inorganic materials 0.000 claims abstract description 18
- 239000011159 matrix material Substances 0.000 claims abstract description 9
- 229910052738 indium Inorganic materials 0.000 claims description 31
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 31
- 239000010931 gold Substances 0.000 claims description 27
- 230000005855 radiation Effects 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 229920005989 resin Polymers 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 2
- 238000012546 transfer Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- 238000003825 pressing Methods 0.000 description 9
- 238000010438 heat treatment Methods 0.000 description 6
- 239000000470 constituent Substances 0.000 description 5
- 238000003466 welding Methods 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052793 cadmium Inorganic materials 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 229910052500 inorganic mineral Inorganic materials 0.000 description 2
- 239000011707 mineral Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- MARUHZGHZWCEQU-UHFFFAOYSA-N 5-phenyl-2h-tetrazole Chemical compound C1=CC=CC=C1C1=NNN=N1 MARUHZGHZWCEQU-UHFFFAOYSA-N 0.000 description 1
- 229910004611 CdZnTe Inorganic materials 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- MCMSPRNYOJJPIZ-UHFFFAOYSA-N cadmium;mercury;tellurium Chemical compound [Cd]=[Te]=[Hg] MCMSPRNYOJJPIZ-UHFFFAOYSA-N 0.000 description 1
- 230000002301 combined effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000002901 radioactive waste Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000003325 tomography Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14665—Imagers using a photoconductor layer
- H01L27/14676—X-ray, gamma-ray or corpuscular radiation imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
- H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13109—Indium [In] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13609—Indium [In] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Definitions
- the present invention relates to an image sensor, which detects radiation, and to a method of manufacturing image sensors.
- An image sensor which detects radiation such as hard X-rays or ⁇ -rays so as to generate image information, has been used in various technical fields. For example, a radiant field from a certain celestial body is detected, and thereby, it is possible to know the physical status of the celestial body and the spatial structure thereof. Further, X-rays are irradiated to a human body, and then, the transmitted wave is investigated, and thereby, tomography of the human body can be obtained. Besides, the image sensors have also been used in other fields, such as nuclear power (glass solidification check of radioactive waste, radiation monitor, etc.), non-destructive tests (semiconductor tester, etc.) and mineral surveying (mineral resources research).
- nuclear power glass solidification check of radioactive waste, radiation monitor, etc.
- non-destructive tests semiconductor tester, etc.
- mineral surveying mineral resources research
- the image sensor conventionally used for the above fields has the following structure, for example.
- FIG. 1A is a view showing a typical example of the above conventional image sensor 80
- FIG. 1B is a cross-sectional view taken along the B-B direction of FIG. 1A
- the image sensor 80 has a detecting element (Si element or Ge element) 81 , and an amplifying IC 84 . More specifically, the detecting element 81 detects incident radiation so as to generate an electric signal.
- the amplifying IC 84 is arranged on the same plane as the detecting element 81 , and amplifies the electric signal.
- an interconnection line 83 led out of the detecting element 81 is connected to the amplifying IC 84 by wire bonding.
- the image sensor using the Si element detects only X-rays having a low energy from several KeV to tens of KeV; for this reason, the image sensor does not have the sensitivity required for practical use.
- the present invention has been made in view of the above circumstances. Accordingly, it is an object to provide a highly sensitive image sensor, which can readily make an electric connection between each sensor element and an amplifying IC even if it has many sensor elements, and to provide a method of manufacturing the image sensor.
- an image sensor which comprises: a sensor element array having a plurality of sensor elements arrayed in a two-dimensional matrix; an IC substrate laminating the sensor element array and provided with a plurality of ICs for amplifying an electric signal based on radiation incident on any of the plurality of the sensor elements; and a connection layer interposed between the sensor element array and the IC substrate, and electrically connecting each electrode of the sensor elements with each electrode of the ICs.
- connection layer has a plurality of stud bumps formed on the electrode of each IC; and a plurality of thin film layers formed at the distal end of each stud bump and electrically connected with the electrode of each sensor element.
- each of the stud bumps is made of gold; and each of the thin film layers is made of indium.
- connection layer has an insulating layer which buries the stud bumps and the thin film layers.
- connection layer has a plurality of multi-layer bumps formed in a manner that at least two-layer stud bump is laminated on the electrode of each IC, and a plurality of thin film layers formed at the distal end of the multi-layer bump and electrically connected with the electrode of each sensor element.
- each of the multi-layer bumps is made of gold; and each of the thin film layers is made of indium.
- connection layer has an insulating layer which buries the stud bumps and the thin film layers.
- the sensor element is a CdTe element.
- a method of manufacturing an image sensor which comprises: forming a stud bump on each electrode pad of the predetermined number of IC chips provided in a first substrate; carrying out indium plating with respect to a second substrate; transferring the plated indium to the second substrate to the distal end of each stud bump so that a plurality of thin film layers can be formed; connecting each of the thin film layers with the electrode of the sensor element so that a sensor element array having a plurality of sensor elements arrayed like two-dimensional matrix is mounted to each IC of the first substrate by flip chip mounting; and injecting an insulating resin between the first substrate and the sensor element array, and thereafter, hardening the insulating resin.
- each of the stud bumps is made of gold, and each of the thin film layers is made of indium.
- FIG. 1A and FIG. 1B are views to explain a conventional image sensor
- FIG. 2A and FIG. 2B are views to schematically explain the structure of an image sensor 10 ;
- FIG. 3A to FIG. 3C are cross-sectional views taken along the line A-A of the image sensor shown in FIG. 2A;
- FIG. 4A and FIG. 4B are views to schematically explain the structure of an IC substrate included in the image sensor 10 ;
- FIG. 5 is a flowchart schematically showing a method of manufacturing the image sensor 10 ;
- FIG. 6 is a conceptual view to explain indium (In) transfer in step S 2 ;
- FIG. 7 is a schematic view showing an indium (In) layer 131 formed at the distal end of an au stud bump 130 formed in the process of step S 2 ;
- FIG. 8 is a flowchart showing the embodiment of the method of manufacturing the image sensor 10 .
- the image sensor 10 of the embodiment is formed in a manner of mounting a sensor element array on the IC substrate mounted with the amplifying IC according to flip chip mounting (hereinafter, referred to as “FC mounting”) by the stud bump process described later.
- the sensor element array is formed by arranging a plurality of sensor elements made of CdTe (cadmium telluride) in a matrix. The structure of the sensor element array and the IC substrate will be described below with reference to FIG. 1 to FIG. 3.
- FIG. 2A and FIG. 2B are views to schematically explain the structure of the image sensor 10 .
- FIG. 2A is a view showing an upper surface of the image sensor 10 (and an upper surface of the sensor element array 11 ).
- FIG. 2B is an enlarged view showing a portion surrounded by a circle shown in FIG. 2A.
- FIG. 3A is a cross-sectional view taken along the line A-A of the image sensor 10 shown in FIG. 2A.
- the sensor element array 11 has a CdTe element 110 , a first electrode 111 , a second electrode 112 , and an active contact 113 .
- the CdTe element 110 is a compound semiconductor consisting of Cd (cadmium) and Te (tellurium).
- the energy gap of the CdTe element 110 is about 1.47 eV under room temperature.
- the first electrode 111 is arrayed like two-dimensional matrix on the radiation incident side of the CdTe element 110 , and is formed of Pt, for example.
- the second electrode 112 is arrayed on an electric signal fetch side of the CdTe element 110 facing the first electrode 111 via the CdTe element 110 , and is formed of Pt, for example.
- a predetermined voltage for detecting radiation is applied between the first and second electrodes 111 and 112 .
- the sensor element array 11 is formed in the following manner.
- the sensor element is formed in a manner of sandwiching the CdTe element 110 between the first and second Pt electrodes 111 and 112 , and thereafter, in a two-dimensional matrix.
- a depletion layer formed by applying the voltage between the first and second Pt electrodes 111 and 112 , many electrons and holes are generated along the track of radiation. Positive and negative charges are fetched as an electric signal, and thereby, the sensor array element 11 generates image information based on the incident radiation.
- the active contact 113 is formed in the first and second electrodes, and is a pad for flip-chip-mounting the sensor array element 11 on the IC substrate 15 by the stud bump process described later.
- the electric signal detected by each sensor element is inputted to the IC from the active contact 113 via a stud bump described later, thereafter, is subjected to predetermined signal processing such as amplification.
- FIG. 3 is a view to schematically explain the structure of the IC substrate 15 included in the image sensor 10 .
- FIG. 4A is a view showing an upper surface of the IC substrate 15
- FIG. 4B is an enlarged view showing a portion surrounded by a circle shown in FIG. 4A.
- FC pad flip chip bump 150 included in each of plural X-ray resistant ICs (not shown) is arrayed like two-dimensional matrix.
- the position of the FC pad 150 corresponds to that of the above active contact 113 , and FC mounting is carried out based on both positions.
- a stud bump described later is formed on the FC pad 150 .
- FIG. 3B and FIG. 3C are views to explain FC mounting of the image sensor 10 to the IC substrate 15 .
- FIG. 3B is an enlarged view showing part of the connecting layer 13 shown in FIG. 3A.
- the connecting layer 13 has a stud bump 130 , an indium layer 131 formed at the distal end of the stud bump 130 , and an insulating layer 132 .
- the stud bump 130 is formed on the FC pad 150 on each IC substrate 15 , and is made of gold.
- the stud bump 130 is formed in a manner that a projection-shaped bump is laminated on the FC pad 150 in one or two-stage or more.
- the stud bump 130 performs the function of absorbing the current application between the sensor element and the IC, and a connection error in FC mounting described later. Therefore, it is preferable that the material used for the stud bump is a relatively soft metal having excellent conductivity.
- the indium layer (In layer) 131 is a thin film layer, which is formed at the distal end of the stud bump 130 .
- the indium layer 131 is formed into a tapered shape so as to have a predetermined height in the manufacturing stage (see FIG. 7).
- the indium layer 131 is pressed and welded by the second electrode and the active contact 113 , and thus, has a shape shown in FIG. 3C.
- the indium layer 131 performs the function of applying a current between the sensor element and the IC, and providing a predetermined height required for FC mounting described later.
- a solder having a melting point of 100° C. or less is used.
- bismuth may be used in addition to indium.
- the insulating layer 132 is a resin layer formed in underfill, and is formed of an epoxy resin, for example. Further, the insulating layer 132 performs the function of burying the stud bump 130 and the indium layer 131 so that they can be both electrically insulated and reinforced. The insulating layer 132 prevents the thermal stress generated by the difference in thermal expansion coefficient between the sensor element array 11 and the IC substrate 15 from concentrating on the stud bump 130 and the indium layer 131 .
- One of the features of the above image sensor 10 is that the sensor element array 11 and the IC substrate 15 are mounted in the laminated form by the connection layer 13 , in particular, the stud bump 130 and the In layer 131 . More specifically, in the conventional image sensor, the IC and the sensor element arrayed on the same plane are connected by wire bonding; a so-called “two-dimensional mounting mode” has been employed. On the contrary, in the image sensor 10 , the sensor element array 11 is laminated on the IC substrate 15 by the stud bump 130 and the In layer 131 ; a so-called “three-dimensional mounting mode” is employed.
- FIG. 5 is a flowchart schematically showing the method of manufacturing the image sensor 10 .
- the IC substrate 15 having the plurality of ICs arrayed in a predetermined form is prepared.
- a stub bump (hereinafter, referred to as “Au stud bump”) using gold as the base material is molded on each flip chip pad 150 (step S 1 ).
- Au stud bump is formed in plural stages (i.e., the Au stud bump is laminated).
- a stainless substrate is plated with indium (In) so as to form the transfer destination for indium (In) transfer to the distal end of the Au stud bump (step S 1 ′).
- step S 2 Sequentially, the indium (In) is transferred to the distal end of the Au stud bump (step S 2 ).
- the transfer in step S 2 is carried out in the following manner using an FC bonder.
- FIG. 6 is a conceptual view to explain the indium (In) transfer in step S 2 .
- the IC substrate 15 with the Au stud bump 130 provided on the head side of the FC bonder (not shown) is pressed against a stainless substrate 16 plated with In.
- the above pressing operation is carried out under predetermined head temperature control, predetermined head speed and predetermined load control, and further, there is the case where the pressing operation is repeated plural times. After a predetermined pressing time elapses, when the head is pulled up under predetermined head temperature control, predetermined head speed and predetermined load control, the In transfer to the distal end of the Au stud bump 130 is completed.
- FIG. 7 is a view schematically showing the In layer 131 formed at the distal end of the Au stud bump 130 formed in the process of step S 2 .
- the In layer 131 formed in step S 2 has a tapered shape and a predetermined height. Also, the shape of the Au stud bump 130 does not crush as shown in FIG. 3C.
- step S 3 Sequentially, FC mounting of the sensor element array 11 to the IC substrate 15 is carried out (step S 3 ). More specifically, first, flattening is carried out with respect to the In layer 131 formed in step S 2 . This is to prevent an extra pressure from being applied to one point on the second electrode of the sensor element array 11 (in other words, pressure is uniformly applied to each second electrode 112 ). After the above flattening, the pressing/heating by the FC bonder destroys/melts an oxide film on the surface of each In layer 131 so that the In layer 131 can be welded to the corresponding second electrode 112 , and thereby, FC welding is achieved between the sensor element array 11 and the IC substrate 15 .
- the insulating layer 132 is formed (step S 4 ). More specifically, the underfill seals the gap (FC gap) between the sensor element array 11 and the IC substrate 15 , which have been FC-connected in the process of step S 3 . Thereafter, the underfill is heated and hardened for a predetermined time so that the insulating layer 132 can be formed.
- FIG. 8 is a flowchart showing the embodiment of the method of manufacturing the image sensor 10 .
- the IC substrate 15 having the plurality of ICs arranged in a predetermined form is prepared.
- a stub bump (hereinafter, referred to as “Au stud bump”) using gold as the base material is molded on each flip chip pad 150 (step S 1 ).
- the stainless substrate is plated with indium (In) to a thickness of 20 ⁇ m, and thus, the transfer destination for In transfer to the distal end of the Au stud bump is formed (step S 1 ′).
- step S 2 Sequentially, the indium (In) is transferred to the distal end of the Au stud bump (step S 2 ).
- the transfer in step S 2 is carried out in the following manner using an FC bonder.
- the IC substrate with the stud bump 150 is set to the head side of the FC bonder.
- the stainless substrate plated with indium (In) is set to the table side.
- the table temperature is kept at 50° C., for example.
- the head is pressed at loading: 2.64 [kgf], pressing time: 11.0 sec., head temperature: 250° C., and head pull-down speed 0.2 [mm/s], and thereafter, pulled up by the height of 5 mm at the pull-up speed of 0.5 [mm/s] while maintaining the head temperature.
- the In plating layer is left to cool for 40 seconds, and then, the second-pressing is carried out under the following conditions. That is, the head is pressed at loading: 2.64 [kgf], pressing time: 5.0 sec., head temperature: 250° C., and head pull-down speed 0.2 [mm/s], and thereafter, pulled up by the height of 5 mm at the pull-up speed of 0.08 [mm/s] while maintaining the head temperature.
- the In transfer to the distal end of the Au stud bump 130 is then completed.
- FC mounting of the sensor element array 11 to the IC substrate 15 is carried out (step S 3 ).
- step S 2 flattening is carried out with respect to the In layer 131 formed in step S 2 .
- the IC substrate 15 is set to the head side of the FC bonder; on the other hand, the sensor element array 11 is set to the table side.
- the head is pulled down under the following conditions, that is, at loading: 10.00 [kgf], head temperature: 175° C., pressing time: 10.0 sec., and head pull-down speed 0.08 [mm/s]. Thereafter, the head is pressed against the stud bump 130 and the active contact 113 of the In layer 131 under the following conditions.
- the head position is held for 1.0 second while maintaining the head temperature at 175° C. Thereafter, the head is pulled up by the height of 5 mm at the pull-up speed of 0.17 [mm/s] while keeping the head temperature at 175° C., and thereby, the sensor element array 11 and the IC substrate 15 can be FC-welded together.
- the table temperature is kept at 80° C.
- the insulating layer 132 is formed (step S 4 ).
- the sensor element array 11 is heated at a temperature from 60° C. to 80° C., and an epoxy resin is kept at a temperature from 25° C. to 40° C.
- the epoxy resin is injected into the FC gap formed in the process of step S 3 .
- care must be taken to prevent the sensor element array comprising CdTe and the FC welding portion separating.
- the heating temperature of the sensor element array 11 must be set so as not to exceed 80° C. If the temperature exceeds 80° C., the epoxy resin is set faster; as a result, injection is not smoothly achieved.
- the injection processing is carried out for about 3 minutes.
- heating and hardening are carried out under the condition that the heating temperature is 125° C. and the heating time is two hours, and thereby, the insulating layer 132 is formed.
- One of the features of the above manufacturing method is the Au stud bump 130 (plural-stage Au stud bump 130 , as the case may be,) and the In layer 131 having a predetermined height, formed at the distal end of the Au stud bump 130 . More specifically, the height of the In layer 131 further increases in addition to the height of the au stud bump 130 . By doing so, it is possible to obtain a larger pressing width when pressure-welding the sensor element array 11 to the IC substrate 15 in FC welding. Further, the Au stud bump 130 absorbs the error in the height between bumps connected in FC welding. Therefore, according to the manufacturing method, it is possible to readily realize an image sensor having a great number of pixels.
- the image sensor 10 uses the CdTe element, it is possible to provide a high-performance image sensor as compared with the conventional case.
- the stud bump process has been described while giving the image sensor 10 using the CdTe element as one example.
- the stud bump process is applicable to the method of manufacturing the image sensors using the base materials other than CdTe as the sensor element; for example, Si, Ge, CdZnTe or HgCdTe (mercury cadmium telluride).
- the present invention is not limited to the above embodiment, and various modifications may be made without departing from the scope of the general inventive concept in the working stage of the invention.
- Each embodiment may be carried out based on proper combinations as much as possible; in this case, combined effects are obtained.
- the above embodiment includes various-step inventions, and the plurality of constituent requirements disclosed is properly combined, and thereby, various inventions can be extracted. For example, even if some constituent requirements are deleted from all constituent requirements disclosed in the embodiment, it is possible to solve the problem described in the column of the problem that the invention is to solve. When at least one of the effects described in the column of the effects of the invention is obtained, the construction in which the constituent requirements is deleted can be extracted as an invention.
Abstract
Description
- This is a Continuation Application of PCT Application No. PCT/JP02/01919, filed Mar. 1, 2002, which was not published under PCT Article 21(2) in English.
- This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-057346, filed Mar. 1, 2001, the entire contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to an image sensor, which detects radiation, and to a method of manufacturing image sensors.
- 2. Description of the Related Art
- An image sensor, which detects radiation such as hard X-rays or γ-rays so as to generate image information, has been used in various technical fields. For example, a radiant field from a certain celestial body is detected, and thereby, it is possible to know the physical status of the celestial body and the spatial structure thereof. Further, X-rays are irradiated to a human body, and then, the transmitted wave is investigated, and thereby, tomography of the human body can be obtained. Besides, the image sensors have also been used in other fields, such as nuclear power (glass solidification check of radioactive waste, radiation monitor, etc.), non-destructive tests (semiconductor tester, etc.) and mineral surveying (mineral resources research).
- The image sensor conventionally used for the above fields has the following structure, for example.
- FIG. 1A is a view showing a typical example of the above
conventional image sensor 80, and FIG. 1B is a cross-sectional view taken along the B-B direction of FIG. 1A. As shown in FIG. 1A and FIG. 1B, theimage sensor 80 has a detecting element (Si element or Ge element) 81, and an amplifying IC 84. More specifically, the detectingelement 81 detects incident radiation so as to generate an electric signal. The amplifying IC 84 is arranged on the same plane as the detectingelement 81, and amplifies the electric signal. In theimage sensor 80, aninterconnection line 83 led out of the detectingelement 81 is connected to the amplifying IC 84 by wire bonding. - In general, according to the above structure in which the detecting element and the amplifying IC are arranged on the same plane and mutually connected, it is difficult to greatly increase the number of the detecting
elements 81 of the image sensor. The reason is because it is technically difficult to further lead many signal lines out of the peripheral region of the detectingelement 81 by wire bonding. - The image sensor using the Si element detects only X-rays having a low energy from several KeV to tens of KeV; for this reason, the image sensor does not have the sensitivity required for practical use.
- As typified by the CCD, the recent visible sensor technique has been specialized in slowly reading two-dimensional information under the condition that a signal to noise ratio is very good. However, in photons other than the visible light region, environmental noise is high and signals are weak; for this reason, high-speed operation and high-reduction of noise are required as not so compared with the case of detecting the visible light. As a result, there is a need of connecting a read circuit to each one of fine pixels, and the development of a high-speed parallel readable system has been required.
- It has been known that silicon becomes transparent with respect to hard X-rays or γ-rays having a wave-length shorter than soft X-rays. Therefore, in order to obtain the large stopping power, the development of a new CdTe semiconductor must progress quickly.
- The present invention has been made in view of the above circumstances. Accordingly, it is an object to provide a highly sensitive image sensor, which can readily make an electric connection between each sensor element and an amplifying IC even if it has many sensor elements, and to provide a method of manufacturing the image sensor.
- In order to achieve the above object, the present invention has taken the following means.
- According to a first aspect of the present invention, there is provided an image sensor which comprises: a sensor element array having a plurality of sensor elements arrayed in a two-dimensional matrix; an IC substrate laminating the sensor element array and provided with a plurality of ICs for amplifying an electric signal based on radiation incident on any of the plurality of the sensor elements; and a connection layer interposed between the sensor element array and the IC substrate, and electrically connecting each electrode of the sensor elements with each electrode of the ICs.
- According to a second aspect of the present invention, in the image sensor of the first aspect, the connection layer has a plurality of stud bumps formed on the electrode of each IC; and a plurality of thin film layers formed at the distal end of each stud bump and electrically connected with the electrode of each sensor element.
- According to a third aspect of the present invention, in the image sensor of the second aspect, each of the stud bumps is made of gold; and each of the thin film layers is made of indium.
- According to a fourth aspect of the present invention, in the image sensor of the second aspect, the connection layer has an insulating layer which buries the stud bumps and the thin film layers.
- According to a fifth aspect of the present invention, in the image sensor of the first aspect, the connection layer has a plurality of multi-layer bumps formed in a manner that at least two-layer stud bump is laminated on the electrode of each IC, and a plurality of thin film layers formed at the distal end of the multi-layer bump and electrically connected with the electrode of each sensor element.
- According to a sixth aspect of the present invention, in the image sensor of the fifth aspect, each of the multi-layer bumps is made of gold; and each of the thin film layers is made of indium.
- According to a seventh aspect of the present invention, in the image sensor of the fifth aspect, the connection layer has an insulating layer which buries the stud bumps and the thin film layers.
- According to an eighth aspect of the present invention, in the image sensor of the first aspect, the sensor element is a CdTe element.
- According to a ninth aspect of the present invention, there is provided a method of manufacturing an image sensor which comprises: forming a stud bump on each electrode pad of the predetermined number of IC chips provided in a first substrate; carrying out indium plating with respect to a second substrate; transferring the plated indium to the second substrate to the distal end of each stud bump so that a plurality of thin film layers can be formed; connecting each of the thin film layers with the electrode of the sensor element so that a sensor element array having a plurality of sensor elements arrayed like two-dimensional matrix is mounted to each IC of the first substrate by flip chip mounting; and injecting an insulating resin between the first substrate and the sensor element array, and thereafter, hardening the insulating resin.
- According to a tenth aspect of the present invention, in the method of the ninth aspect, each of the stud bumps is made of gold, and each of the thin film layers is made of indium.
- Therefore, according to the above structure, even if the image sensor has many sensor elements, it is possible to provide a high-sensitive image sensor, which can readily make electric connection between each sensor element and amplification IC, and to provide a method of manufacturing the image sensor.
- FIG. 1A and FIG. 1B are views to explain a conventional image sensor;
- FIG. 2A and FIG. 2B are views to schematically explain the structure of an
image sensor 10; - FIG. 3A to FIG. 3C are cross-sectional views taken along the line A-A of the image sensor shown in FIG. 2A;
- FIG. 4A and FIG. 4B are views to schematically explain the structure of an IC substrate included in the
image sensor 10; - FIG. 5 is a flowchart schematically showing a method of manufacturing the
image sensor 10; - FIG. 6 is a conceptual view to explain indium (In) transfer in step S2;
- FIG. 7 is a schematic view showing an indium (In)
layer 131 formed at the distal end of anau stud bump 130 formed in the process of step S2; and - FIG. 8 is a flowchart showing the embodiment of the method of manufacturing the
image sensor 10. - The embodiments of the present invention will be described below with reference to the accompanying drawings. In the following description, the identical reference numerals are given to constituent components having substantially the same function and structure, and the overlapping explanation will be made in only necessary case.
- The
image sensor 10 of the embodiment is formed in a manner of mounting a sensor element array on the IC substrate mounted with the amplifying IC according to flip chip mounting (hereinafter, referred to as “FC mounting”) by the stud bump process described later. The sensor element array is formed by arranging a plurality of sensor elements made of CdTe (cadmium telluride) in a matrix. The structure of the sensor element array and the IC substrate will be described below with reference to FIG. 1 to FIG. 3. - FIG. 2A and FIG. 2B are views to schematically explain the structure of the
image sensor 10. FIG. 2A is a view showing an upper surface of the image sensor 10 (and an upper surface of the sensor element array 11). FIG. 2B is an enlarged view showing a portion surrounded by a circle shown in FIG. 2A. - FIG. 3A is a cross-sectional view taken along the line A-A of the
image sensor 10 shown in FIG. 2A. - As is illustrated in FIG. 2A and FIG. 3A, the
sensor element array 11 has aCdTe element 110, afirst electrode 111, asecond electrode 112, and anactive contact 113. - The
CdTe element 110 is a compound semiconductor consisting of Cd (cadmium) and Te (tellurium). The energy gap of theCdTe element 110 is about 1.47 eV under room temperature. - The
first electrode 111 is arrayed like two-dimensional matrix on the radiation incident side of theCdTe element 110, and is formed of Pt, for example. Thesecond electrode 112 is arrayed on an electric signal fetch side of theCdTe element 110 facing thefirst electrode 111 via theCdTe element 110, and is formed of Pt, for example. A predetermined voltage for detecting radiation is applied between the first andsecond electrodes - More specifically, the
sensor element array 11 is formed in the following manner. The sensor element is formed in a manner of sandwiching theCdTe element 110 between the first andsecond Pt electrodes second Pt electrodes sensor array element 11 generates image information based on the incident radiation. - The
active contact 113 is formed in the first and second electrodes, and is a pad for flip-chip-mounting thesensor array element 11 on theIC substrate 15 by the stud bump process described later. The electric signal detected by each sensor element is inputted to the IC from theactive contact 113 via a stud bump described later, thereafter, is subjected to predetermined signal processing such as amplification. - FIG. 3 is a view to schematically explain the structure of the
IC substrate 15 included in theimage sensor 10. FIG. 4A is a view showing an upper surface of theIC substrate 15, and FIG. 4B is an enlarged view showing a portion surrounded by a circle shown in FIG. 4A. - As shown in FIG. 4A, in the
IC substrate 15, a flip chip bump 150 (hereinafter, referred to as “FC pad”) included in each of plural X-ray resistant ICs (not shown) is arrayed like two-dimensional matrix. The position of theFC pad 150 corresponds to that of the aboveactive contact 113, and FC mounting is carried out based on both positions. A stud bump described later is formed on theFC pad 150. - Next, a connecting
layer 13 formed between theimage sensor 10 and theIC substrate 15 will be described below with reference to FIG. 3B and FIG. 3C. - FIG. 3B and FIG. 3C are views to explain FC mounting of the
image sensor 10 to theIC substrate 15. FIG. 3B is an enlarged view showing part of the connectinglayer 13 shown in FIG. 3A. - As seen from FIG. 3B and FIG. 3C, the connecting
layer 13 has astud bump 130, anindium layer 131 formed at the distal end of thestud bump 130, and an insulatinglayer 132. - The
stud bump 130 is formed on theFC pad 150 on eachIC substrate 15, and is made of gold. Thestud bump 130 is formed in a manner that a projection-shaped bump is laminated on theFC pad 150 in one or two-stage or more. Thestud bump 130 performs the function of absorbing the current application between the sensor element and the IC, and a connection error in FC mounting described later. Therefore, it is preferable that the material used for the stud bump is a relatively soft metal having excellent conductivity. - The indium layer (In layer)131 is a thin film layer, which is formed at the distal end of the
stud bump 130. Theindium layer 131 is formed into a tapered shape so as to have a predetermined height in the manufacturing stage (see FIG. 7). In FC mounting, theindium layer 131 is pressed and welded by the second electrode and theactive contact 113, and thus, has a shape shown in FIG. 3C. Further, theindium layer 131 performs the function of applying a current between the sensor element and the IC, and providing a predetermined height required for FC mounting described later. Since the CdTe element is used in the embodiment, it is preferable that a solder having a melting point of 100° C. or less is used. For example, bismuth may be used in addition to indium. - The insulating
layer 132 is a resin layer formed in underfill, and is formed of an epoxy resin, for example. Further, the insulatinglayer 132 performs the function of burying thestud bump 130 and theindium layer 131 so that they can be both electrically insulated and reinforced. The insulatinglayer 132 prevents the thermal stress generated by the difference in thermal expansion coefficient between thesensor element array 11 and theIC substrate 15 from concentrating on thestud bump 130 and theindium layer 131. - One of the features of the
above image sensor 10 is that thesensor element array 11 and theIC substrate 15 are mounted in the laminated form by theconnection layer 13, in particular, thestud bump 130 and the Inlayer 131. More specifically, in the conventional image sensor, the IC and the sensor element arrayed on the same plane are connected by wire bonding; a so-called “two-dimensional mounting mode” has been employed. On the contrary, in theimage sensor 10, thesensor element array 11 is laminated on theIC substrate 15 by thestud bump 130 and the Inlayer 131; a so-called “three-dimensional mounting mode” is employed. - In the image sensor made employing the above three-dimensional mounting, IC connection is made from the lower portion of each sensor element. Therefore, even if the number of sensor elements increases, it is possible to easily extract signals. As a result, it is possible to generate an image having a great number of pixels as compared with the conventional case. Further, the three-dimensional mounting is employed, and thereby, it is possible to down-size the image sensor.
- (Method of Manufacturing the Image Sensor)
- Next, the method of manufacturing the
image sensor 10 will be described below with reference to FIG. 5. - FIG. 5 is a flowchart schematically showing the method of manufacturing the
image sensor 10. In FIG. 5, first, theIC substrate 15 having the plurality of ICs arrayed in a predetermined form is prepared. A stub bump (hereinafter, referred to as “Au stud bump”) using gold as the base material is molded on each flip chip pad 150 (step S1). As the need arises, there is the case where the au stub bump is formed in plural stages (i.e., the Au stud bump is laminated). - On the other hand, a stainless substrate is plated with indium (In) so as to form the transfer destination for indium (In) transfer to the distal end of the Au stud bump (step S1′).
- Sequentially, the indium (In) is transferred to the distal end of the Au stud bump (step S2). The transfer in step S2 is carried out in the following manner using an FC bonder.
- FIG. 6 is a conceptual view to explain the indium (In) transfer in step S2. As is illustrated in FIG. 6, the
IC substrate 15 with theAu stud bump 130 provided on the head side of the FC bonder (not shown) is pressed against astainless substrate 16 plated with In. The above pressing operation is carried out under predetermined head temperature control, predetermined head speed and predetermined load control, and further, there is the case where the pressing operation is repeated plural times. After a predetermined pressing time elapses, when the head is pulled up under predetermined head temperature control, predetermined head speed and predetermined load control, the In transfer to the distal end of theAu stud bump 130 is completed. - FIG. 7 is a view schematically showing the In
layer 131 formed at the distal end of theAu stud bump 130 formed in the process of step S2. As is illustrated in FIG. 7, the Inlayer 131 formed in step S2 has a tapered shape and a predetermined height. Also, the shape of theAu stud bump 130 does not crush as shown in FIG. 3C. - Sequentially, FC mounting of the
sensor element array 11 to theIC substrate 15 is carried out (step S3). More specifically, first, flattening is carried out with respect to the Inlayer 131 formed in step S2. This is to prevent an extra pressure from being applied to one point on the second electrode of the sensor element array 11 (in other words, pressure is uniformly applied to each second electrode 112). After the above flattening, the pressing/heating by the FC bonder destroys/melts an oxide film on the surface of each Inlayer 131 so that the Inlayer 131 can be welded to the correspondingsecond electrode 112, and thereby, FC welding is achieved between thesensor element array 11 and theIC substrate 15. In this case, no gap is generated between thesecond electrode 112 and the Inlayer 131 by the above press. Therefore, it is possible to prevent oxidation between the In layer and the second electrode in heating (i.e., the oxide film on the surface of each Inlayer 131 is destroyed/melted so that the Inlayer 131 can be welded to Pt on the electrode surface of the CdTe chip). - Finally, the insulating
layer 132 is formed (step S4). More specifically, the underfill seals the gap (FC gap) between thesensor element array 11 and theIC substrate 15, which have been FC-connected in the process of step S3. Thereafter, the underfill is heated and hardened for a predetermined time so that the insulatinglayer 132 can be formed. - The above steps describe formation of the
image sensor 10. - (Embodiment of the Manufacturing Method)
- The embodiment of the manufacturing method will be described below in detail with reference to FIG. 8.
- FIG. 8 is a flowchart showing the embodiment of the method of manufacturing the
image sensor 10. In FIG. 8, first, theIC substrate 15 having the plurality of ICs arranged in a predetermined form is prepared. A stub bump (hereinafter, referred to as “Au stud bump”) using gold as the base material is molded on each flip chip pad 150 (step S1). - On the other hand, the stainless substrate is plated with indium (In) to a thickness of 20 μm, and thus, the transfer destination for In transfer to the distal end of the Au stud bump is formed (step S1′).
- Sequentially, the indium (In) is transferred to the distal end of the Au stud bump (step S2). The transfer in step S2 is carried out in the following manner using an FC bonder.
- More specifically, the IC substrate with the
stud bump 150 is set to the head side of the FC bonder. On the other hand, the stainless substrate plated with indium (In) is set to the table side. In this case, the table temperature is kept at 50° C., for example. After the above setup is completed, the head is pulled down, and then, the distal end of eachAu stud bump 130 can be pressed against the In plating layer of the stainless substrate two times. In this case, the first-time press is carried out under the following conditions. That is, the head is pressed at loading: 2.64 [kgf], pressing time: 11.0 sec., head temperature: 250° C., and head pull-down speed 0.2 [mm/s], and thereafter, pulled up by the height of 5 mm at the pull-up speed of 0.5 [mm/s] while maintaining the head temperature. Thereafter, the In plating layer is left to cool for 40 seconds, and then, the second-pressing is carried out under the following conditions. That is, the head is pressed at loading: 2.64 [kgf], pressing time: 5.0 sec., head temperature: 250° C., and head pull-down speed 0.2 [mm/s], and thereafter, pulled up by the height of 5 mm at the pull-up speed of 0.08 [mm/s] while maintaining the head temperature. The In transfer to the distal end of theAu stud bump 130 is then completed. - In the above In transfer, if the affinity between indium (In) and the stainless substrate is worse, the indium (In) of the stainless substrate is pressed against the Au stud bump so that the indium (In) can be heated/melted, and thereby, it is possible to effectively transfer the indium (In) to the au stud bump.
- Sequentially, FC mounting of the
sensor element array 11 to theIC substrate 15 is carried out (step S3). - More specifically, flattening is carried out with respect to the In
layer 131 formed in step S2. After the flattening, theIC substrate 15 is set to the head side of the FC bonder; on the other hand, thesensor element array 11 is set to the table side. After theIC substrate 15 andsensor element array 11 are positioned, the head is pulled down under the following conditions, that is, at loading: 10.00 [kgf], head temperature: 175° C., pressing time: 10.0 sec., and head pull-down speed 0.08 [mm/s]. Thereafter, the head is pressed against thestud bump 130 and theactive contact 113 of the Inlayer 131 under the following conditions. After the above press is completed, the head position is held for 1.0 second while maintaining the head temperature at 175° C. Thereafter, the head is pulled up by the height of 5 mm at the pull-up speed of 0.17 [mm/s] while keeping the head temperature at 175° C., and thereby, thesensor element array 11 and theIC substrate 15 can be FC-welded together. In step S3, the table temperature is kept at 80° C. - Finally, the insulating
layer 132 is formed (step S4). First, on the hot plate, thesensor element array 11 is heated at a temperature from 60° C. to 80° C., and an epoxy resin is kept at a temperature from 25° C. to 40° C. The epoxy resin is injected into the FC gap formed in the process of step S3. In this case, care must be taken to prevent the sensor element array comprising CdTe and the FC welding portion separating. The heating temperature of thesensor element array 11 must be set so as not to exceed 80° C. If the temperature exceeds 80° C., the epoxy resin is set faster; as a result, injection is not smoothly achieved. The injection processing is carried out for about 3 minutes. - After the injection processing is completed, heating and hardening are carried out under the condition that the heating temperature is 125° C. and the heating time is two hours, and thereby, the insulating
layer 132 is formed. - The above steps describe formation of the
image sensor 10. - One of the features of the above manufacturing method is the Au stud bump130 (plural-stage
Au stud bump 130, as the case may be,) and the Inlayer 131 having a predetermined height, formed at the distal end of theAu stud bump 130. More specifically, the height of the Inlayer 131 further increases in addition to the height of theau stud bump 130. By doing so, it is possible to obtain a larger pressing width when pressure-welding thesensor element array 11 to theIC substrate 15 in FC welding. Further, theAu stud bump 130 absorbs the error in the height between bumps connected in FC welding. Therefore, according to the manufacturing method, it is possible to readily realize an image sensor having a great number of pixels. - Further, according to above manufacturing method, no special manufacturing apparatus is newly required, and it is possible to manufacture the
image sensor 10 by applying presently available facilities. Therefore, the image sensor can be provided at low cost as compared with the conventional case. - Further, since the
image sensor 10 uses the CdTe element, it is possible to provide a high-performance image sensor as compared with the conventional case. - The present invention has been described based on the embodiments. In the scope of the concept of the present invention, it should be also understood that various changes and modifications will readily occur to those skilled in the art, and therefore, these changes and modifications belong to the scope of the present invention. For example, the following various modifications may be made without departing from the scope of the general inventive concept.
- In the above embodiment, the stud bump process has been described while giving the
image sensor 10 using the CdTe element as one example. In this case, the stud bump process is applicable to the method of manufacturing the image sensors using the base materials other than CdTe as the sensor element; for example, Si, Ge, CdZnTe or HgCdTe (mercury cadmium telluride). - The present invention is not limited to the above embodiment, and various modifications may be made without departing from the scope of the general inventive concept in the working stage of the invention. Each embodiment may be carried out based on proper combinations as much as possible; in this case, combined effects are obtained. Further, the above embodiment includes various-step inventions, and the plurality of constituent requirements disclosed is properly combined, and thereby, various inventions can be extracted. For example, even if some constituent requirements are deleted from all constituent requirements disclosed in the embodiment, it is possible to solve the problem described in the column of the problem that the invention is to solve. When at least one of the effects described in the column of the effects of the invention is obtained, the construction in which the constituent requirements is deleted can be extracted as an invention.
- According to the above structure, even if the image sensor has many sensor elements, it is possible to realize a highly sensitive image sensor, which can readily make electric connection between each sensor element and amplification IC, and to provide a method of manufacturing the image sensor.
Claims (10)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/871,029 US7041981B2 (en) | 2001-03-01 | 2004-06-21 | Image sensor and manufacturing method thereof |
US11/073,730 US6992297B2 (en) | 2001-03-01 | 2005-03-08 | Image sensor and manufacturing method thereof |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001057346A JP2002261262A (en) | 2001-03-01 | 2001-03-01 | Image sensor and manufacturing method |
JP2001-057346 | 2001-03-01 | ||
PCT/JP2002/001919 WO2002071489A1 (en) | 2001-03-01 | 2002-03-01 | Image sensor and production method therefore |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2002/001919 Continuation WO2002071489A1 (en) | 2001-03-01 | 2002-03-01 | Image sensor and production method therefore |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/871,029 Division US7041981B2 (en) | 2001-03-01 | 2004-06-21 | Image sensor and manufacturing method thereof |
US11/073,730 Continuation US6992297B2 (en) | 2001-03-01 | 2005-03-08 | Image sensor and manufacturing method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20030116816A1 true US20030116816A1 (en) | 2003-06-26 |
Family
ID=18917238
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/318,122 Abandoned US20030116816A1 (en) | 2001-03-01 | 2002-12-13 | Image sensor and manufacturing method thereof |
US10/871,029 Expired - Lifetime US7041981B2 (en) | 2001-03-01 | 2004-06-21 | Image sensor and manufacturing method thereof |
US11/073,730 Expired - Lifetime US6992297B2 (en) | 2001-03-01 | 2005-03-08 | Image sensor and manufacturing method thereof |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/871,029 Expired - Lifetime US7041981B2 (en) | 2001-03-01 | 2004-06-21 | Image sensor and manufacturing method thereof |
US11/073,730 Expired - Lifetime US6992297B2 (en) | 2001-03-01 | 2005-03-08 | Image sensor and manufacturing method thereof |
Country Status (4)
Country | Link |
---|---|
US (3) | US20030116816A1 (en) |
EP (1) | EP1365453A4 (en) |
JP (1) | JP2002261262A (en) |
WO (1) | WO2002071489A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050057783A1 (en) * | 2003-08-21 | 2005-03-17 | Hiroaki Kasuga | Image scanning apparatus |
US20090316026A1 (en) * | 2008-06-20 | 2009-12-24 | Sony Corporation | Image processing apparatus, image processing method and manufacturing apparatus |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002261262A (en) | 2001-03-01 | 2002-09-13 | Mitsubishi Heavy Ind Ltd | Image sensor and manufacturing method |
JP4379295B2 (en) | 2004-10-26 | 2009-12-09 | ソニー株式会社 | Semiconductor image sensor module and manufacturing method thereof |
US7589324B2 (en) * | 2006-12-21 | 2009-09-15 | Redlen Technologies | Use of solder mask as a protective coating for radiation detector |
JP2011509399A (en) * | 2007-12-20 | 2011-03-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Direct conversion detector |
DE102009009813A1 (en) | 2009-02-20 | 2010-08-26 | Espros Photonics Ag | Soldering and circuit |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5701011A (en) * | 1995-05-31 | 1997-12-23 | Matsushita Electric Industrial Co., Ltd. | apparatus for picking up image by electromagnetic wave ray |
US5723866A (en) * | 1996-06-26 | 1998-03-03 | He Holdings, Inc. | Method for yield and performance improvement of large area radiation detectors and detectors fabricated in accordance with the method |
US5812191A (en) * | 1994-06-01 | 1998-09-22 | Simage Oy | Semiconductor high-energy radiation imaging device |
US5952646A (en) * | 1996-12-27 | 1999-09-14 | Simage Oy | Low temperature bump-bonding semiconductor imaging device |
US6342700B1 (en) * | 1998-04-27 | 2002-01-29 | Sharp Kabushiki Kaisha | Two-dimensional image detector |
US6651320B1 (en) * | 1997-10-02 | 2003-11-25 | Matsushita Electric Industrial Co., Ltd. | Method for mounting semiconductor element to circuit board |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5043582A (en) | 1985-12-11 | 1991-08-27 | General Imagining Corporation | X-ray imaging system and solid state detector therefor |
US5071787A (en) * | 1989-03-14 | 1991-12-10 | Kabushiki Kaisha Toshiba | Semiconductor device utilizing a face-down bonding and a method for manufacturing the same |
JPH05166879A (en) | 1991-12-12 | 1993-07-02 | Matsushita Electric Ind Co Ltd | Ic mounting method |
KR0137190B1 (en) * | 1992-12-03 | 1998-04-28 | 모리시타 요이찌 | A direct-contact type image sensor device and an image sensor unit |
FR2715002B1 (en) * | 1994-01-07 | 1996-02-16 | Commissariat Energie Atomique | Electromagnetic radiation detector and its manufacturing process. |
JPH08115946A (en) * | 1994-10-13 | 1996-05-07 | Matsushita Electric Ind Co Ltd | Flip-chip mounting method |
JP3243956B2 (en) * | 1995-02-03 | 2002-01-07 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
US5650667A (en) * | 1995-10-30 | 1997-07-22 | National Semiconductor Corporation | Process of forming conductive bumps on the electrodes of semiconductor chips using lapping and the bumps thereby created |
JPH1022337A (en) * | 1996-07-04 | 1998-01-23 | Hitachi Ltd | Method for bonding semiconductor chip |
JPH10233401A (en) * | 1997-02-19 | 1998-09-02 | Ricoh Co Ltd | Semiconductor device |
JPH1126502A (en) * | 1997-07-01 | 1999-01-29 | Matsushita Electric Ind Co Ltd | Method of leveling bumps |
JP2000100874A (en) | 1998-09-21 | 2000-04-07 | Sony Corp | Device and method for manufacturing flip chip |
JP2001074847A (en) * | 1999-07-08 | 2001-03-23 | Canon Inc | Radiation image pickup device and radiation image pickup system |
US6593168B1 (en) * | 2000-02-03 | 2003-07-15 | Advanced Micro Devices, Inc. | Method and apparatus for accurate alignment of integrated circuit in flip-chip configuration |
US6348399B1 (en) * | 2000-07-06 | 2002-02-19 | Advanced Semiconductor Engineering, Inc. | Method of making chip scale package |
US6658082B2 (en) * | 2000-08-14 | 2003-12-02 | Kabushiki Kaisha Toshiba | Radiation detector, radiation detecting system and X-ray CT apparatus |
JP2002261262A (en) | 2001-03-01 | 2002-09-13 | Mitsubishi Heavy Ind Ltd | Image sensor and manufacturing method |
US6510195B1 (en) * | 2001-07-18 | 2003-01-21 | Koninklijke Philips Electronics, N.V. | Solid state x-radiation detector modules and mosaics thereof, and an imaging method and apparatus employing the same |
-
2001
- 2001-03-01 JP JP2001057346A patent/JP2002261262A/en active Pending
-
2002
- 2002-03-01 WO PCT/JP2002/001919 patent/WO2002071489A1/en active Application Filing
- 2002-03-01 EP EP02701675A patent/EP1365453A4/en not_active Ceased
- 2002-12-13 US US10/318,122 patent/US20030116816A1/en not_active Abandoned
-
2004
- 2004-06-21 US US10/871,029 patent/US7041981B2/en not_active Expired - Lifetime
-
2005
- 2005-03-08 US US11/073,730 patent/US6992297B2/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5812191A (en) * | 1994-06-01 | 1998-09-22 | Simage Oy | Semiconductor high-energy radiation imaging device |
US5701011A (en) * | 1995-05-31 | 1997-12-23 | Matsushita Electric Industrial Co., Ltd. | apparatus for picking up image by electromagnetic wave ray |
US5723866A (en) * | 1996-06-26 | 1998-03-03 | He Holdings, Inc. | Method for yield and performance improvement of large area radiation detectors and detectors fabricated in accordance with the method |
US5952646A (en) * | 1996-12-27 | 1999-09-14 | Simage Oy | Low temperature bump-bonding semiconductor imaging device |
US6651320B1 (en) * | 1997-10-02 | 2003-11-25 | Matsushita Electric Industrial Co., Ltd. | Method for mounting semiconductor element to circuit board |
US6342700B1 (en) * | 1998-04-27 | 2002-01-29 | Sharp Kabushiki Kaisha | Two-dimensional image detector |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050057783A1 (en) * | 2003-08-21 | 2005-03-17 | Hiroaki Kasuga | Image scanning apparatus |
US7518761B2 (en) * | 2003-08-21 | 2009-04-14 | Seiko Epson Corporation | Image scanning apparatus |
US20090316026A1 (en) * | 2008-06-20 | 2009-12-24 | Sony Corporation | Image processing apparatus, image processing method and manufacturing apparatus |
US8576311B2 (en) * | 2008-06-20 | 2013-11-05 | Sony Corporation | Image processing apparatus, image processing method and manufacturing apparatus |
Also Published As
Publication number | Publication date |
---|---|
US20050151088A1 (en) | 2005-07-14 |
JP2002261262A (en) | 2002-09-13 |
US20040232346A1 (en) | 2004-11-25 |
EP1365453A1 (en) | 2003-11-26 |
US7041981B2 (en) | 2006-05-09 |
EP1365453A4 (en) | 2008-04-30 |
US6992297B2 (en) | 2006-01-31 |
WO2002071489A1 (en) | 2002-09-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6992297B2 (en) | Image sensor and manufacturing method thereof | |
US7223981B1 (en) | Gamma ray detector modules | |
US6933505B2 (en) | Low temperature, bump-bonded radiation imaging device | |
US6372549B2 (en) | Semiconductor package and semiconductor package fabrication method | |
US7504637B2 (en) | Two component photodiode detector | |
US4943491A (en) | Structure for improving interconnect reliability of focal plane arrays | |
KR100647212B1 (en) | Conductive adhesive bonded semiconductor substrates for radiation imaging devices | |
US8524510B2 (en) | Method for manufacturing magnetic memory chip device | |
WO2006057097A1 (en) | Semiconductor device | |
WO1998029904A1 (en) | Bump-bonded semiconductor imaging device | |
US5904495A (en) | Interconnection technique for hybrid integrated devices | |
JP4397012B2 (en) | Semiconductor image sensor having hole-type electrode and manufacturing method thereof | |
Bigas et al. | Bonding techniques for hybrid active pixel sensors (HAPS) | |
CN112385025A (en) | Stacked semiconductor device and plurality of chips used for the same | |
JP2003229533A (en) | Semiconductor device and method for manufacturing same | |
JP4799746B2 (en) | Radiation detector module | |
JP2005101315A (en) | Semiconductor device | |
JP2005101332A (en) | Semiconductor device | |
KR100311979B1 (en) | infrared detector and method for manufacturing the same | |
JP3238256B2 (en) | Semiconductor device, image sensor device, and manufacturing method thereof | |
US7884485B1 (en) | Semiconductor device interconnect systems and methods | |
JPH0336744A (en) | Packaging of radiation detector | |
JP2006196525A (en) | Light or radiation detector and its manufacturing process | |
TWI273692B (en) | Semiconductor package and method for manufacturing the same | |
Capote et al. | Gamma ray detector modules |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MITSUBISHI HEAVY INDUSTRIES LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KURODA, YOSHIKATSU;TAKAHASHI, TADAYUKI;REEL/FRAME:013582/0226;SIGNING DATES FROM 20021202 TO 20021205 Owner name: JAPAN, REPRESENTED BY DIRECTOR-GENERAL OF THE INST Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KURODA, YOSHIKATSU;TAKAHASHI, TADAYUKI;REEL/FRAME:013582/0226;SIGNING DATES FROM 20021202 TO 20021205 |
|
AS | Assignment |
Owner name: JAPAN AEROSPACE EXPLORATION AGENCY, AN INDEPENDENT Free format text: TRANSFER OF RIGHTS BY GOVERNMENTAL ACTION;ASSIGNOR:JAPAN AEROSPACE EXPLORATION AGENCY, AN INDEPENDENT ADMINISTRATIVE INSTITUTION;REEL/FRAME:015003/0001 Effective date: 20031001 Owner name: JAPAN AEROSPACE EXPLORATION AGENCY, JAPAN Free format text: CONSOLIDATION, DISSOLUTION AND TRANSFER OF GOVERNMENTAL AGENCIES;ASSIGNOR:INSTITUTE OF SPACE AND ASTRONAUTICAL SCIENCE;REEL/FRAME:015003/0061 Effective date: 20031001 Owner name: INDEPENDENT ADMINISTRATIVE INSTITUTION, THE JAPAN Free format text: INCORPORATION OF INDEPENDENT ADMINISTRATIVE INSTITUTION;ASSIGNOR:JAPAN AEROSPACE EXPLORATION AGENCY, AN INDEPENDENT ADMINISTRATIVE INSTITUTION;REEL/FRAME:015002/0977 Effective date: 20031001 Owner name: JAPAN AEROSPACE EXPLORATION AGENCY, AN INDEPENDENT Free format text: GOVERNMENTAL PROVISIONS FOR ESTABLISHING AN INDEPENDENT ADMINISTRATIVE INSTITUTION AND TRANSFER OF RIGHTS;ASSIGNOR:JAPAN AEROSPACE EXPLORATION AGENCY, AN INDEPENDENT ADMINISTRATIVE INSTITUTION;REEL/FRAME:015003/0027 Effective date: 20031001 |
|
AS | Assignment |
Owner name: JAPAN AEROSPACE EXPLORATION AGENCY, JAPAN Free format text: DOCUMENT PREVIOUSLY RECORDED AT REEL 015002 FRAME 0997 CONTAINED AN ERROR IN THE ASSIGNEE'S NAME DOCUMENT RE-RECORDED TO CORRECT ERROR ON STATED REEL.;ASSIGNOR:JAPAN AEROSPACE EXPLORATION AGENCY;REEL/FRAME:015507/0312 Effective date: 20031001 Owner name: JAPAN AEROSPACE EXPLORATION AGENCY, JAPAN Free format text: DOCUMENT PREVIOUSLY RECORDED AT REEL 015003 FRAME 0061 CONTAINED AN ERROR IN THE ASSIGNEE'S NAME DOCUMENT RE-RECORDED TO CORRECT ERROR ON STATED REEL.;ASSIGNOR:INSTITUTE OF SPACE AND ASTRONAUTICAL SCIENCE, JAPANESE GOVERNMENT AGENCY;REEL/FRAME:015507/0756 Effective date: 20031001 Owner name: JAPAN AEROSPACE EXPLORATION AGENCY, JAPAN Free format text: DOCUMENT PREVIOUSLY RECORDED AT REEL;ASSIGNOR:JAPAN AEROSPACE EXPLORATION AGENCY;REEL/FRAME:015507/0474 Effective date: 20031001 Owner name: JAPAN AEROSPACE EXPLORATION AGENCY, JAPAN Free format text: CORRECTED COVER SHEET TO CORRECT ASSIGNEE NAME, PREVIOUSLY RECORDED AT REEL/FRAME 015003/0027 (GOVERNMENTAL PROVISIONS FOR ESTABLISHING AN INDEPENDENT ADMINISTRATIVE INSTITUTION AND TRANSFER OF RIGHTS);ASSIGNOR:JAPAN AEROSPACE EXPLORATION AGENCY;REEL/FRAME:015507/0508 Effective date: 20031001 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |