US20030151046A1 - Bipolar transistor characterization apparatus and method employing air bridge connectors to test probe pads - Google Patents
Bipolar transistor characterization apparatus and method employing air bridge connectors to test probe pads Download PDFInfo
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- US20030151046A1 US20030151046A1 US10/075,758 US7575802A US2003151046A1 US 20030151046 A1 US20030151046 A1 US 20030151046A1 US 7575802 A US7575802 A US 7575802A US 2003151046 A1 US2003151046 A1 US 2003151046A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Microelectronics & Electronic Packaging (AREA)
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- Bipolar Transistors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
- 1. Field of the Invention
- This invention relates to the characterization of bipolar transistors, and more particularly to a novel heterojunction bipolar transistor (HBT) test structure and method in which test probe pads are provided lateral to respective transistor regions prior to forming an upper metallization.
- 2. Description of the Related Art
- In characterizing newly manufactured bipolar transistors to determine whether they operate properly and meet specifications, a small portion of the transistors on a wafer (typically less than one percent) are dedicated as test devices. Since all of the transistors on the wafer are fabricated in a common process, they will generally exhibit common operating characteristics. Therefore, characterizing the relatively few test transistors can be taken as a characterization of the larger number of circuit transistors that are employed in the operating circuitry of the wafer.
- When the transistor fabrication has been completed, the wafer is coated with one or more dielectric layers, with metallized leads formed on each layer and extending through the underlying dielectric to establish electrical connections with the transistors. The metallization for the test transistors is provided with enlarged probe pads on the upper dielectric surface so that the test transistors can be electrically accessed via test probes brought into contact with the contact pads. (The term “metallization” as used herein is not limited to conventional metal elements, but also encompasses alternate conductive mechanisms such as heavily doped semiconductor.)
- While this approach has been found to be effective in characterizing a large number of transistors by actually testing only a small portion, it requires that the wafer fabrication be fully completed before characterization can take place. Thus, if the test transistors do not meet specifications, the completed wafer must be discarded. This is costly in terms of both processing time and expense.
- The present invention seeks to provide a novel test transistor structure and associated characterization method that allows transistor characterization to be completed before the wafer has been fully fabricated, and in particular before the upper metallization is laid down. The invention is particularly applicable to HBTs, and permits bad wafers to be identified and discarded without incurring the cost and time necessary to fabricate the upper metallization.
- These goals are achieved according to one embodiment of the invention by providing test probe pads, of sufficient size to receive test probes, lateral to, spaced from and substantially coplanar with one or more of the test transistor emitter, base and collector regions. The probe pads are fabricated prior to forming the upper metallization, and are preferably disposed on pedestals and connected to their associated transistor regions by air bridges. For an HBT, air bridge connections are preferably made to the emitter and base from probe pads on respective pedestals lateral to and spaced from the transistor, while a collector contact is made via the subcollector, either by an air bridge to a probe contact on a separate pedestal, or by a lead which extends along the substrate to a separate probe pad. A gap is preferably provided in the subcollector below the air bridges to reduce capacitive coupling. The test probe pads, air bridges and their respective transistor regions are preferably formed in respective simultaneous common metallizations.
- Once the transistors have been fabricated, but prior to forming the upper metallization, the test transistors are accessed and characterized via their respective probe pads. If the transistors do not meet specifications, the wafer can be discarded in its partially completed state. The upper metallization is fabricated only if the test transistors meet specifications, thus characterizing the circuit transistors as operating properly. Connections to the circuit transistors are then made through the dielectric underlying the upper metallization, while the test transistors need not be accessed again.
- These and further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings, in which:
- FIG. 1 is a simplified plan view of a semiconductor wafer bearing both circuit and test transistors;
- FIG. 2 is a perspective view illustrating a test transistor fabricated in accordance with the invention in the process of characterization;
- FIGS.3-6 are sectional views illustrating sequential stages in the fabrication on one embodiment of a test transistor in accordance with the invention;
- FIG. 7 is a sectional view illustrating an alternate structure for connecting the subcollector of an HBT to a test probe contact pad; and
- FIG. 8 is a sectional view illustrating test and circuit transistors on a completed wafer that includes an upper metallization.
- FIG. 1 illustrates in very simplified form a
semiconductor wafer 2 that bears an array of bipolar transistors. Some of the transistors aretest devices 4 which are provided only for purposes of characterizing all of the transistors on the wafer, and are not included in the functional operation of the wafer's circuitry. The remaining transistors, illustrated byreference number 6, are referred to herein as circuit transistors because they play an active role in the operation of the wafer's circuitry. The test transistors are much fewer in number than the circuit transistors, and are scattered around the wafer so that possible variations in transistor quality at different locations of the wafer can be detected. The transistors can be organized into an overall wafer-sized circuit, or the wafer can be diced into separate IC chips with their own respective circuits in which case the test transistors would normally be provided between chip areas. Lead wires and other circuit elements are not included in FIG. 1 for purposes of simplification. - Since all of the wafer transistors are formed in a common fabrication process, each of them should have similar operating characteristics. Therefore, in practice it has been found that test characterization of only a few test transistors can be used to effectively characterize all of the transistors of similar type on the wafer.
- The characterization approach using a small number of test transistors described thus far is conventional. However, the invention provides a novel structure for the test transistors and their associated test probe pads that allows all of the transistors on the wafer to be characterized before the wafer fabrication has been completed, thus eliminating the need for a portion of the normal fabrication process if the transistors do not meet specifications.
- One embodiment of the new test transistor structure for an HBT is illustrated in FIG. 2. The transistor itself is designated by
reference number 8, with the test probe pads and associated support structure offset lateral to this device. Progressing upward from thesubstrate 2, the HBT is formed as a stack that comprises a highlyconductive subcollector 10 which establishes an area contact with the underside of thecollector 12, athin base layer 14 surmounting the collector, and anarrower emitter structure 16 formed over the base. - Relatively large area collector, base and emitter
probe contact pads pedestals substrate 2. Each of the pedestals is laterally offset from thetransistor 8 in a different direction, with the collector, base andemitter probe pads subcollector 10,base 14 andemitter 16, respectively; the collector probe pad is also substantially coplanar with the lower surface of thecollector 12. - As described in more detail below, the transistor and pedestals are initially formed from a common stack of semiconductor layers, portions of which are etched away to form the structure illustrated in FIG. 2. Thus, the
pedestal 24 for thecollector pad 18 comprises an extension of thetransistor subcollector layer 10, designated 24-10. Similarly, thebase pedestal 26 comprises extensions ofsubcollector 10,collector 12 andbase 14, respectively designated 26-10, 26-12 and 26-14, while thepedestal 28 for theemitter probe pad 22 comprises extensions of the same three layers as thebase pedestal 26, plus an extension of theemitter layer 16; these extensions are designated 28-10, 28-12, 28-14 and 28-16, respectively. - The probe pads are electrically and mechanically connected to their respective portions of the transistor by relatively
thin air bridges - The
probe pads arrows automated tester 42 in which the locations of the various probe pads have been pre-programmed. Alternately, the probes can be applied to their respective pads manually. Test signals are applied to the transistor from thetester 42, and the transistor's response monitored, via the probes. - FIG. 3 is a cross-section of a wafer upon which various semiconductor layers have been deposited for transistor fabrication. In this example, an InP/InGaAs material system is used to fabricate HBTs. Other material systems and bipolar devices are also known.
- The
semi-insulating InP substrate 2 supports an InGaAssubcollector 10 that is heavily doped N++ so that it is substantially conductive. Thesubcollector 10 is typically about 0.5-1 micron thick, with a dopant concentration of about 1019/cm3. The purpose of the subcollector is to establish an electrical contact with thecollector 12, which directly contacts the upper surface of the subcollector. TheInGaAs collector 12 is typically about 0.3-0.7 microns thick, with a dopant concentration of about 1016-1017/cm3. - The
base layer 14 overlying thecollector layer 12 is heavily doped InGaAs, typically about 300-1000 Angstroms thick and carbon doped P++ to a concentration about 5×1019/cm3. - The emitter structure, designated by
reference number 16 in FIG. 2, actually consists of afunctional emitter layer 44 on thebase layer 14, surmounted by anemitter spacer layer 46 and anemitter cap layer 48. In this example theemitter layer 44 is InP typically about 400-2000 Angstroms thick and N+ doped to a concentration of about 3×1017/cm3. Theemitter spacer layer 46 is illustrated as an InP layer doped N− to a concentration of about 1016-1017/cm3, while theemitter cap 48 in this example is InGaAs doped N++ to a concentration of about 1019/cm3. The emitter spacer and cap layers are typically about 500 Angstroms and 200 Angstroms thick, respectively. - Also illustrated in FIG. 3 is an
emitter contact metallization 50 which has been patterned on the upper surface of theemitter cap layer 48. In the orientation of FIG. 3, theleft end 52 of the emitter metallization will provide the direct emitter contact when the transistor is fabricated, while the distal portion at the right end will function as the emitterprobe contact pad 22 of FIG. 2, and the intermediate portion as theemitter air bridge 34. Although shown in section in FIG. 3, the emitter metallization would have the geometry illustrated in FIG. 2. The width of theemitter contact 52 andair bridge 34 is not greater than about 1 micron; this enables the air bridge to be established by an etch step that removes the underlying semiconductor material, as described below. - Subsequent stages of the transistor fabrication are illustrated in FIGS.4-6. The fabrication sequence is the same for both the test and circuit transistors, except probe pads and associated air bridges are not provided for the circuit transistors. Instead, the contact metallizations patterned on the emitter, base and subcollectors of the circuit transistors do not extend beyond the limits of the transistors.
- FIG. 4 illustrates the results of the next several fabrication steps. A photoresist (not shown) is laid down over the intended emitter area, and the emitter layers44, 46 and 48 are etched away outside the photoresist down to the
base layer 14. The photoresist actually extends slightly beyond the intended emitter boundaries to allow for a certain amount of undercutting during etching. The etch step is generally insufficient for the material under theemitter bridge 34 to be removed, so that bridge remains a “land bridge”. After etching, abase metallization 54 is patterned over thebase layer 14 to establish abase contact 56 and the baseprobe contact pad 20 andbridge 32. Again, these elements have the geometry as illustrated in FIG. 2. - In the next step, a photoresist is laid down over the areas intended for the
transistor mesa 8 and the base and emitter probe pad pedestals 26 and 28, again extending outward slightly beyond the intended geometries to allow for undercutting, and the base and collector layers 14 and 12 are etched away from the exposed areas, leaving the structure illustrated in FIG. 5. At this stage of fabrication the base and emitter probe contact pedestals 26 and 28, and also theHBT 8, are formed down to thesubcollector layer 10. This etch is deep enough for the narrow base and emitter contact bridges to be completely undercut, leaving them as air bridges between their respective probe contact pads and the transistor. Since the air bridges do not receive a vertical load, they are structurally stable. - In the next stage of fabrication, the results of which are illustrated in FIG. 6, the HBT and the base and emitter pedestals are coated with photoresist and the portion of the
subcollector layer 10 surrounding them is etched away to leave the structure illustrated in FIG. 2. Prior to etching the subcollector, acollector contact metallization 58 is laid down over thesubcollector layer 10 to establish a contact to the subcollector via theprobe contact pad 18 andbridge 30 of FIG. 2. The subcollector material below thecollector bridge 30 is removed by undercutting during the etch, leaving thebridge 30 as a true air bridge. - The probe contact pads are relatively large, typically about 50 microns per side. This establishes a capacitance between the contact pads and the substrate that, when added to the transistor's intrinsic capacitance, can significantly reduce the device's frequency range. Etching through the conductive subcollector layer breaks the connections between the extrinsic probe pad capacitances and the intrinsic transistor capacitances, preventing the extrinsic capacitances from loading down the transistor. This is particularly important in limiting the overall base-collector capacitance, which can destroy transistor performance at high frequencies.
- An alternate structure to the collector air bridge is illustrated in FIG. 7, which is oriented 90° to FIGS.3-6. In this embodiment the collector air bridge is replaced with a
metallization 60 that extends from the upper surface of the subcollector, down its side and onto the upper substrate surface, where it expands into a probe contact pad. Since this contact pad is directly on the surface of thesubstrate 2, it does not add significant capacitance. - Upon completion of the test transistors, their probe pads are open for access by
test probes tester 42. Since the circuit transistors are fabricated in the same process as the test devices they have essentially the same operating characteristics, and characterizing the test transistors in effect simultaneously characterizes the circuit transistors. - If the testing reveals that the transistors do not satisfy specifications, the wafer can simply be discarded at this point. However, if the transistors are characterized as operating properly, the wafer fabrication is then completed by forming upper metallization contacts to the circuit transistors; no further fabrication is needed for the test transistors. The final product is illustrated in FIG. 8, in which the
test transistor 8 is spaced along the substrate away from a circuit transistor 62 (shown turned 90° to transistor 8). The two transistors are identical, except for the manner in which they are contacted. Thecircuit transistor 62 does not have any associated test probe pads. Rather, it includes conventional contact pads that are restricted to the transistor itself. If the surface area on the emitter, base or subcollector is not large enough to support an adequate contact pad, the transistor geometry can be modified to provide an enlarged area, or a contact pedestal can be provided immediately adjacent to the transistor. - External connections to the
circuit transistor 62 are made by upper level metallizations, commonly provided in two metallization layers M1 and M2. After completion of the test transistors, a first layer ofdielectric 64 is deposited over the surface of the entire wafer. The first metallization layer M1 is then patterned on top of thedielectric layer 64, with transistor leads extending through vias in the dielectric to appropriate contact pads on the transistors in a conventional manner. Anupper dielectric layer 66 is then deposited over the first dielectric layer and metallization M1, and an upper metallization M2 formed on the upper dielectric layer and connected through vias in the upper and lower dielectric layers to the circuit devices. In the illustration of FIG. 8, the M1 metallization provides contacts to the circuit transistor emitters and subcollectors, while the upper metallization M2 provides connections to the circuit transistor bases. The provision of upper and lower metallization layers enables crossovers between metallization leads, and is a conventional IC fabrication technique. - No connections between either of the metallization layers M1 or M2 need be made to the
test transistors 8, since those devices completed their function with the transistor testing through the test probe pads, and have no further role to play. The provision of test transistors with substantially planar probe contact pads as described enables a more efficient overall fabrication process, since bad wafers can be identified before the dielectric layers or upper level metallization are put in place, and that portion of the ordinary fabrication can simply be dispensed with. At the same time, the test transistors are relatively few in number and do not take up a significant portion of the wafer's “real estate”. - While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. For example, while described in connection with an InP/InGaAs material system, the invention is applicable to virtually all bipolar transistors with emitters, bases and collectors at different levels, and to all known material systems for such transistors. Accordingly, it is intended that the invention be limited only in terms of the appended claims.
Claims (34)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US10/075,758 US6605825B1 (en) | 2002-02-14 | 2002-02-14 | Bipolar transistor characterization apparatus with lateral test probe pads |
US10/423,676 US6958491B1 (en) | 2002-02-14 | 2003-04-24 | Bipolar transistor test structure with lateral test probe pads |
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US10/075,758 US6605825B1 (en) | 2002-02-14 | 2002-02-14 | Bipolar transistor characterization apparatus with lateral test probe pads |
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US10/423,676 Continuation US6958491B1 (en) | 2002-02-14 | 2003-04-24 | Bipolar transistor test structure with lateral test probe pads |
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US20030151046A1 true US20030151046A1 (en) | 2003-08-14 |
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US10/423,676 Expired - Fee Related US6958491B1 (en) | 2002-02-14 | 2003-04-24 | Bipolar transistor test structure with lateral test probe pads |
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Cited By (4)
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WO2005033720A2 (en) * | 2003-09-29 | 2005-04-14 | Rockwell Scientific Licensing, Llc | Testing apparatus and method for determining an etch bias associated with a semiconductor-processing step |
US20060148156A1 (en) * | 2003-12-04 | 2006-07-06 | Bae Systems Information And Electronic Systems Integration Inc. | Gan-based permeable base transistor and method of fabrication |
US20070265795A1 (en) * | 2006-05-09 | 2007-11-15 | Formfactor, Inc. | Air Bridge Structures And Methods Of Making And Using Air Bridge Structures |
CN110752166A (en) * | 2019-09-09 | 2020-02-04 | 福建省福联集成电路有限公司 | Air bridge monitoring structure and manufacturing method thereof |
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US6605825B1 (en) * | 2002-02-14 | 2003-08-12 | Innovative Technology Licensing, Llc | Bipolar transistor characterization apparatus with lateral test probe pads |
JP2004327717A (en) * | 2003-04-24 | 2004-11-18 | Sony Corp | Semiconductor device and manufacturing method therefor |
US7397260B2 (en) * | 2005-11-04 | 2008-07-08 | International Business Machines Corporation | Structure and method for monitoring stress-induced degradation of conductive interconnects |
US7679384B2 (en) * | 2007-06-08 | 2010-03-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Parametric testline with increased test pattern areas |
JP5893800B2 (en) | 2012-06-14 | 2016-03-23 | スカイワークス ソリューションズ, インコーポレイテッドSkyworks Solutions, Inc. | Related systems, devices, and methods including power amplifier modules |
KR101944337B1 (en) | 2012-06-14 | 2019-02-01 | 스카이워크스 솔루션즈, 인코포레이티드 | Process-compensated hbt power amplifier bias circuits and mehtods |
JP2016205906A (en) * | 2015-04-17 | 2016-12-08 | 株式会社東芝 | Probe, semiconductor inspection device, method for manufacturing the probe, method for manufacturing the semiconductor inspection device, method for inspecting semiconductor, and method for manufacturing semiconductor |
RU173641U1 (en) * | 2017-03-27 | 2017-09-04 | Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" | TEST PLANAR P-N-P TRANSISTOR |
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US4079505A (en) * | 1974-03-14 | 1978-03-21 | Fujitsu Limited | Method for manufacturing a transistor |
JPS5268376A (en) * | 1975-12-05 | 1977-06-07 | Nec Corp | Semiconductor device |
JPH05267415A (en) * | 1992-03-18 | 1993-10-15 | Fujitsu Ltd | Semiconductor device |
US6194739B1 (en) * | 1999-11-23 | 2001-02-27 | Lucent Technologies Inc. | Inline ground-signal-ground (GSG) RF tester |
US6605825B1 (en) * | 2002-02-14 | 2003-08-12 | Innovative Technology Licensing, Llc | Bipolar transistor characterization apparatus with lateral test probe pads |
-
2002
- 2002-02-14 US US10/075,758 patent/US6605825B1/en not_active Expired - Fee Related
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WO2005033720A3 (en) * | 2003-09-29 | 2005-08-04 | Rockwell Scient Licensing Llc | Testing apparatus and method for determining an etch bias associated with a semiconductor-processing step |
WO2005033720A2 (en) * | 2003-09-29 | 2005-04-14 | Rockwell Scientific Licensing, Llc | Testing apparatus and method for determining an etch bias associated with a semiconductor-processing step |
US20080265259A1 (en) * | 2003-12-04 | 2008-10-30 | Bae Systems Information And Electronic Systems Integration, Inc. | GaN-BASED PERMEABLE BASE TRANSISTOR AND METHOD OF FABRICATION |
US20060148156A1 (en) * | 2003-12-04 | 2006-07-06 | Bae Systems Information And Electronic Systems Integration Inc. | Gan-based permeable base transistor and method of fabrication |
US8247843B2 (en) | 2003-12-04 | 2012-08-21 | Bae Systems Information And Electronic Systems Integration Inc. | GaN-based permeable base transistor and method of fabrication |
USRE42955E1 (en) * | 2003-12-04 | 2011-11-22 | Bae Systems Information And Electronic Systems Integration Inc. | GaN-based permeable base transistor and method of fabrication |
US7413958B2 (en) * | 2003-12-04 | 2008-08-19 | Bae Systems Information And Electronic Systems Integration Inc. | GaN-based permeable base transistor and method of fabrication |
US7444253B2 (en) | 2006-05-09 | 2008-10-28 | Formfactor, Inc. | Air bridge structures and methods of making and using air bridge structures |
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US7729878B2 (en) | 2006-05-09 | 2010-06-01 | Formfactor, Inc. | Air bridge structures and methods of making and using air bridge structures |
WO2007133467A3 (en) * | 2006-05-09 | 2008-05-08 | Formfactor Inc | Air bridge structures and methods of making and using air bridge structures |
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CN110752166A (en) * | 2019-09-09 | 2020-02-04 | 福建省福联集成电路有限公司 | Air bridge monitoring structure and manufacturing method thereof |
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US6605825B1 (en) | 2003-08-12 |
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