US20030167427A1 - Partitionable embedded circuit test system for integrated circuit - Google Patents
Partitionable embedded circuit test system for integrated circuit Download PDFInfo
- Publication number
- US20030167427A1 US20030167427A1 US10/401,899 US40189903A US2003167427A1 US 20030167427 A1 US20030167427 A1 US 20030167427A1 US 40189903 A US40189903 A US 40189903A US 2003167427 A1 US2003167427 A1 US 2003167427A1
- Authority
- US
- United States
- Prior art keywords
- circuit
- control means
- test
- scan
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1206—Location of test circuitry on chip or wafer
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
A flexible built-in self-test (BIST) circuit is incorporated into an integrated circuit (IC) for testing one or random access memories or other memories embedded in an integrated circuit regardless of the number, size or test requirements of the memories. Input data from a controller that may be conveniently partitioned among components internal and external to the IC, supplies data to the BIST circuit indicating the size of the embedded memories to be tested and selecting from among several modes of BIST operation.
Description
- This application claims benefit of Provisional Application No. 60/160,233 filed Oct. 18, 1999. The entire disclosure of Provisional Application No. 60/160,233 is hereby incorporated by reference herein.
- 1. Field of the Invention
- The present invention relates in general to a system for testing circuits embedded in an integrated circuit (IC), and in particular to a system that may be flexibly partitioned between components internal and external to the IC.
- 2. Description of Related Art
- Many integrated circuits (ICs) include one or more embedded circuits such as random access memories (RAMs). While logic circuits implemented in an IC itself may read or write access an embedded RAM, the bus conveying data, address and control signals between the RAM and the logic circuits read and write accessing it may not be accessible to external test equipment via the IC's input/output (I/O) terminals. Conventional IC testers external to the IC therefore can't directly test such an embedded RAM.
- One way to allow an external IC tester to test an embedded RAM is to link the RAM's I/O ports to the IC's I/O terminals. However this approach requires a large number of extra I/O terminals to accommodate the RAM's I/O ports and can require a substantial amount of scarce space within the IC to route large buses between each embedded RAM and the IC's I/O terminals. Another way to allow provide a IC tester with access to terminals of an embedded RAM or other circuit is multiplex its terminals onto I/O terminals of other circuits so that an IC tester can selectively access the embedded circuit terminals as illustrated in FIG. 1. This approach can eliminate the need for extra I/O terminals, but can still require substantial amounts of IC space for routing the large embedded memory buses.
- FIG. 2 illustrates a third approach to providing an IC tester with access to an embedded circuit. A “built-in self-test” (BIST) circuit is formed on the IC that is designed to test the embedded circuit. A BIST circuit may require relatively few connections to the IC's I/O terminals for communicating with external test circuits. Thus when the BIST circuit is located proximate to the RAM or RAMs it tests, signal routing paths between the BIST circuit and the I/O terminals can require less space on the IC than would be required if the RAMs' I/O ports were directly routed to the IC's I/O terminals. The number and nature of the connections between the BIST circuit and the IC's I/O terminals depend on the nature of the test to be performed and on how test functions are apportioned between the IC's internal BIST circuit and equipment external to the IC that communicates with the BIST circuit. For example a self-contained BIST circuit carrying out all aspects of a simple pass/fail test may require only a START signal input to initiate the test, a DONE signal output to indicate the test is complete, and a PASS/FAIL signal output to indicate the results of a test. When the BIST circuit requires an external controller providing timing signals for sequencing address and data generation, additional IC I/O ports are needed to supply those timing signals to the BIST circuit. Also more I/O terminal connections may be needed when the BIST circuit is to report the address of each defective memory cell to external test circuits.
- When an IC includes more than one embedded RAM it is possible to use a single BIST circuit to test each RAM in turn, provided however that all RAMs are similar and are to be tested in the same manner. But this approach requires routing large buses within the IC for connecting a central BIST circuit to each embedded RAM, and those buses can require substantial space in the IC. It not possible to use a single BIST circuit for testing multiple embedded RAMs when the embedded RAMs have differing address ranges or are to be tested in different ways.
- To the extent possible, an IC designer usually prefers to design the layout of an IC by defining interconnections between a set of “standard cells”, each standard cell specifying the layout within an IC of a component having a specific function. For example a standard cell might define the layout of an embedded memory, an I/O port, or any of many types of logic circuits. The designer's job is simplified when it is not necessary for him to design any cells in detail or to substantially modify the design of any standard cell when incorporating it into an IC.
- Since each RAM embedded in an IC may be of differing size and have differing test requirements, an IC designer will typically provide a separate customized BIST circuit for each embedded RAM. A number of other factors also influence the nature of a BIST design. For example the available space within an IC and the number of available I/O terminals can influence how we apportion test functions between a BIST circuit and external test circuits.
- Since IC designers must custom design a test system for each IC to suit the nature of its embedded RAMs, they find BIST systems difficult to implement. What is needed is a system for testing RAMs embedded in an IC that allows a designer to flexibly apportion test functions between internal BIST circuits and external test circuits and which can test embedded RAMs of varying numbers and sizes in any of several ways, but which the designer can easily implement using standard cells requiring minimal modification.
- A test system in accordance with the invention includes a built-in self-test (BIST) circuit incorporated into an integrated circuit (IC) for testing one or more random access memories (RAMs) of varying size embedded in the IC. During normal circuit operation logic circuits implemented within the IC read and write access the RAMs. During a RAM test, the BIST system disconnects the logic circuits from the RAMs and connects internal test circuits to the RAMs I/O ports to enable them to test the RAMs.
- The BIST circuit is capable of operating in any of several modes when testing each embedded RAM, with its mode of operation being selected by a controller that may be conveniently implemented internal or external to the IC. Selectable modes include:
- a RAM “pass/fail” mode in which the BIST circuit tests each address of each RAM and generates an output FAILX signal indicating wherein any address of any RAM is defective;
- a “bit map” mode in which the BIST circuit tests each address of each RAM and produces output data indicating the pass/fail status of each bit at that RAM address, thereby providing a map of defective RAM storage bits;
- a “word map” mode in which the BIST circuit tests each RAM address and produces an output signal indicating whether that RAM address is defective, thereby providing a map of defective RAM addresses;
- a “scan capture” mode in which the BIST circuit captures data appearing on each RAM's bus in a scan register in response to a CAPTURE signal from the external control and serially shifts it out to the controller in response to a SHIFT signal from the controller; and
- a “scan force” mode in which the BIST circuit receives and stores data from the controller in the scan register and forces it onto the bus of an embedded RAM in response to a FORCE signal from the controller.
- In accordance with another aspect of the invention, the BIST circuit includes a set of “core wrappers”, each incorporated into the IC near a corresponding one of the embedded RAMs. Each core wrapper includes a test circuit that it connects to the bus of its corresponding RAM during a test. When connected to the bus of its corresponding RAM, each test circuit writes data into each RAM address within the RAM's range of addresses, reads data out of each RAM address, and compares the data it reads out of each RAM address to the data it wrote into that RAM address to determine whether the RAM address is defective.
- Each test circuit pulses an output error signal (CERR) whenever it determines a RAM address is defective, continuously asserts another output error signal (FAIL) after determining any RAM address is defective, and asserts a DONE signal when it has completed testing all RAM addresses. A glue logic circuit included in the IC logically ANDs the DONE output signals of the test circuits of all core wrappers to produce a single output DONEX signal, logically ORs the FAIL output signals of the test circuits of all core wrappers to produce a single output FAILX signal and multiplexes the CERR output signal of the test circuits of all core wrappers to select one of the them as a single output CERRX signal in response to selection data from an external controller. The controller monitors the DONE signal to determine when the test is complete during all modes of operation, monitors the FAILX signal during the pass/fail mode of operation to determine whether any IC is defective, and selects and monitors the glue logic output CERRX signal during the word map mode of operation to determine which memory addresses are defective.
- In accordance with another aspect of the invention the controller sends each the test circuits within each core wrapper MIN, MAX data defining the range of addresses of the corresponding RAM. When it tests the RAM in any mode of operation, each test circuit restricts its test activities to that range of addresses.
- In accordance with another aspect of the invention, the controller sends ROW/COL data to the test circuit of each core wrapper controlling whether the test circuit accesses RAM addresses on a row-by-row or column-by-column basis in any mode of operation.
- In accordance with another aspect of the invention, each core wrapper includes a scan register for storing data appearing on the bus of the corresponding RAM in response to an input CAPTURE signal and for shifting that data out to a test circuit external to the IC in response to an input SHIFT signal when operating in the scan capture mode.
- In accordance with another aspect of the invention, the test circuit within each core wrapper generates RESULTS data after testing each address of the corresponding RAM, when operating in the bit map mode. The results data indicates whether each bit of data written into that RAM address matches a corresponding bit of data read back out of that RAM address. The RESULTS data provides an additional input to the scan register so that may be stored in the scan register in response to the CAPTURE signal and shifted out to the controller in response to the SHIFT signal.
- The controller provides DIAG input data to the test circuit within each core wrapper controlling whether it is to operate in the bit map mode. When operating in the other modes a tester tests each successive RAM address without waiting for the external control to capture and acquire RESULTS data. In the bit map mode, each tester waits for a READY signal from a controller after testing each RAM address before testing a next RAM address. The wait allows the controller time to capture and acquire the RESULTS data stored in the scan register.
- In accordance with a further aspect of the invention, the function of the controller may be flexibly partitioned between a controller implemented internal to the IC, a controller implemented outside the IC, and a conventional general purpose integrated circuit tester without modifying the nature of the core wrappers or the glue logic circuit.
- It is accordingly an object of the invention to provide a system for testing one or more RAMs of varying size embedded in an IC.
- It is another object of the invention to provide a test system allowing an IC designer to flexibly select a manner in which each RAM is tested and to flexibly apportion test functions between test circuits internal and external to the IC.
- It is a further object of the invention to provide an embedded memory test system that may be easily incorporated into an IC using standard cells requiring minimal customization, regardless of the size and number of embedded RAMs and regardless of the nature of the test or tests to be performed on each embedded RAM.
- The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.
- FIGS. 1 and 2 illustrate in block diagram form prior systems for testing an integrated circuit including an embedded circuit;
- FIGS.3A-3C and 4 illustrates in block diagram form a system in accordance with the invention for testing an integrated circuit including an embedded circuit;
- FIG. 5 illustrates in block diagram form a system in accordance with the invention for testing an integrated circuit including several embedded random access memories;
- FIG. 6 illustrates a typical core wrapper of FIG. 5 in more detailed block diagram form;
- FIGS.7-11 illustrate alternative embodiments of the test system of the present invention in block diagram form,
- FIG. 12 illustrates the pattern generator of FIG. 6 in more detailed block diagram form;
- FIG. 13 illustrates the filter of FIG. 13 in more detailed block diagram form;
- FIG. 15 illustrates a suitable implementation of the glue logic circuit of FIG. 5 in more detailed block diagram form;
- FIG. 16 illustrates in block diagram form an alternative embodiment of a system in accordance with the invention for testing an integrated circuit including several embedded random access memories; and
- FIG. 17 illustrates a typical core wrapper of FIG. 16 in more detailed block diagram form.
- FIGS.3A-3C and 4 illustrate alternative versions of a system in accordance with the present invention for testing an
circuit 1 such as one or more random access memories embedded in an integrated circuit (IC) 2A-2D along withother circuits 3. Embeddedcircuit 1 communicates withother circuits 3 linked to via input/output (I/O)terminals 4 that may be accessed by anexternal IC tester 5. However since thebus 6 linking embeddedcircuit 1 toother circuit 3 is not linked to IC I/O terminals,IC tester 5 cannot directly test embeddedcircuit 1. However as illustrated in FIGS. 3A and 3B, a built-in, self-test (BIST)circuit 7 is provided withinintegrated circuit bus 6 and test embeddedcircuit 1.BIST circuit 7 communicates with aBIST controller circuit 8 which, as illustrated in FIG. 3A, may be implemented by a separate IC mounted on the same circuit board (load board 9) on whichIC 2A is mounted when being tested byIC tester 5.BIST controller circuit 8 may alternatively be located within theIC 2B as illustrated in FIG. 3B.BIST circuit 7 is suitably located near embeddedcircuit 1 to minimize the IC space needed to routebus 6 toBIST circuit 7.BIST circuit 7 receives commands from and reports test results toBIST controller 8 through a relativelysmall bus 4B.BIST controller 8 communicates withIC tester 5 via asmall bus 4C.BIST circuit 7 andBIST controller 8 not only test embeddedcircuit 1, they also eliminate the need to route alarge bus 6 betweenIC tester 5 and embeddedcircuit 1. - Alternatively, as illustrated in FIG. 3C,
tester 5 may directly access aBIST circuit 7 within anIC 2C viabus 4B and carry out the function ofBIST controller 8. As shown in FIG. 4, when it convenient to routebus 6 to I/O terminals of anIC 2D, the functions of a BIST circuit and a BIST controller can be carried out by a “built-off self-test” (BOST)circuit 13 mounted on aload board 9 and communicating withIC tester 5 throughbus 4B.BOST controller 13 as well asBIST controller 8 of FIGS. 3A and 3B can be implemented as a field programmable gate array. - Thus the task of testing embedded
circuit 1 can be conveniently partitioned between anIC tester 5, aBIST circuit 7, aBIST controller 8 and aBOST circuit 13. This flexibility in placing test circuit functionality is helpful, for example, when an integrated circuit chip is being developed. In many cases, a designer may want to experimentally determine how to best configure a BIST system to test an embedded circuit by trying out several different test designs. However it is too time consuming and expensive to produce a series of development IC's having differently configured BIST systems. The flexible system of the present invention allows the designer to initially produce a development chip that does not include the BIST circuit and/or its controller. The designer can then test the embedded circuit in the development IC using various external BIST controller or BOST configurations to see which is most suitable. Thereafter the best BIST controller or BOST configuration can be incorporated into a production version of the IC. - For example,
IC 2A of FIG. 3A may be a development chip including the embeddedcircuit 1 to be tested and theinternal BIST circuit 7, but which does not include aBIST controller 8. Anexternal BIST controller 8 may then be coupled toBIST circuit 7, for example, throughcontact points 4D (e.g. probe contact pads) onIC 2A or via dedicated IC terminals. Theexternal BIST controller 8 can then be developed and hardware and/or software modified to controlBIST 7 so that it appropriately tests embeddedcircuit 1. Later, as illustrated in FIG. 3B, elements of the externalBIST controller circuit 8 of FIG. 3A as developed and modified can be directly incorporated into theproduction version 2B of the IC as an internal BIST controller. - Also, referring to FIG. 4, a
development chip 2D including an embeddedcircuit 1 can be provided without either a BIST circuit or a BIST controller. In such case anexternal BOST circuit 13 accessingbus 6, for example throughprobes 6 A contacting pads 6B connected tobus 6 or dedicated IC terminals, can be developed and modified to appropriately test embeddedcircuit 1. Thereafter as illustrated in FIG. 3C, aBIST circuit 7 mimicking relevant elements of thedeveloped BOST circuit 13 can be placed on aproduction version 2C of the IC. - Alternatively, after configuring the
BOST circuit 13 of FIG. 4 to test thedevelopment IC 2D of FIG. 4, the BOST circuit design can be partitioned into aBIST circuit 7 and aBIST controller 8, with theBIST circuit 7 only being included in aproduction version 2A of the IC as illustrated in FIG. 3A, or with bothBIST 7 andBIST controller 8 being incorporated into aproduction version 2B of IC as illustrated in FIG. 3B. - Embedded Memory Test System
- FIG. 5 is a block diagram of a
test system 8 illustrating a version of the test system of the present invention as applied to an integrated circuit (IC) 10 including several embedded random access memories (RAMs) 12. In addition to one or more embedded random access memories (RAMs) 12,IC 10 includeslogic circuits RAMs 12, for communicating with external circuits though IC input/output (I/O)terminals 18, and for communicating with one another through internal lines orbuses 20. A conventional externalintegrated tester 21 is provided to perform a logic test onlogic circuits O terminals 18 and monitoring output signalspatterns logic circuits O terminals 18 in response to the input signal patterns. - RAM Testing
-
Test system 8 includes a built-in self-test (BIST)circuit 11 incorporated intoIC 10 for carrying out or facilitating any of several different types of tests onIC 10 including directly testing eachRAM 12, and assisting in tests oflogic circuits RAMs 12 are not directly accessible toIC 21,tester 21 cannot directly test their operation to determine whether each address of eachRAM 12 is correctly storing and reading out data.BIST circuit 11 is therefore provided to testRAMs 12 by disconnectinglogic circuits RAMs 12 and directly read and write accessing them via their I/O ports. - Shadow Logic Testing
-
BIST circuit 11 also gives IC tester 21 a view of data appearing on thebuses 32 thatlogic circuits access RAMs 12.Logic circuits 14 are “I/O visible” totester 21 in the sense that they include a sufficient number of nodes directly linked to I/O terminals 18 thattester 21 can adequately monitor the behavior oflogic circuits 14 during a test. On the other hand, “shadow”logic circuits 16 read and write access RAMS 12 and communicate withlogic circuits 14, but have few (if any) nodes of interest directly connected to I/O terminals 18. Thus during a logic test,tester 21 is not able to directly monitor the behavior of nodes of interest withinshadow logic circuits 16 via I/O terminals 18.Shadow logic circuits 16 derive their name from the notion that they are in the “shadow” ofvisible logic circuits 14 andRAMs 12 from the point of view oftester 21. Whentester 21 cannot directly stimulate or monitor the behavior of various nodes of interest withinIC 10, it can be difficult to determine the source of IC test failures based solely on data the tester acquires at I/O terminals 18. As discussed below,test system 8 of the present invention enablestester 21 to directly view nodes of interest not directly connected to I/O terminals 18 ofIC 10. In particular,BIST circuit 11 allowstester 21 to monitor data traveling betweenlogic circuits RAMs 12 onbuses 32 during memory accesses.BIST circuit 11 can also simulate the operation ofRAM 12 by forcing known data ontobuses 32. - BIST Circuit Portability
- An IC designer typically designs the layout of an IC by defining interconnections between a set of “standard cells”, each standard cell specifying the layout within an IC of a circuit component having a particular function. For example a standard cell might define the layout of an embedded RAM, an I/O port, or any of many types of logic circuits. The designer's job is simplified when it is not necessary for him to modify a standard cell when incorporating it into an IC design. However since embedded RAMs vary in size and testing requirements from IC-to-IC, prior art BIST circuits for testing embedded RAMs had to be customized to accommodate the particular number of RAMs embedded in the IC, for the particular size of each embedded RAM and for each kind of test to be performed. One of the objects of the invention is to provide a
BIST circuit 11 that may be implemented in the form of standard cells for incorporation into almost any integrated circuit having one or more embedded RAMs with little modification regardless of the number and sizes of RAMs embedded in the IC, and regardless of the nature of the test to be performed on each RAM. - BIST Control Partitioning
-
BIST circuit 11 requires a controller for configuring it to carry out the desired tests onRAMs 12 and for receiving test results.BIST circuit 11 requires relatively few connections to its controller and allows flexibility in the partitioning of BIST control functions between internal and external control circuits. For example controller functions may be implemented byIC tester 21 as illustrated in FIG. 5, by a BIST controller embedded inIC 10 itself, by a BIST controller external to the IC, by a conventional, general purpose integrated circuit tester (automated test equipment), or by a combination of internal and external BIST controller and IC tester. -
BIST 11 has several modes of operation that allow it to testRAMs 12 and report test results in various ways, and to assistIC tester 21 in performing logic tests onlogic circuits - User Mode
-
BIST circuit 11 includes a separate “core wrapper” 24 positioned near eachRAM 12. Duringnormal IC 10 operation, whenIC 10 is not being tested,BIST circuit 11 operates in a “user” mode in which eachcore wrapper 24 connecting its correspondingRAM 12 through a bus 32 (including data, address and read/write control lines) to thelogic circuits BIST circuit 11 also operates in the user mode whenIC tester 21 is performing a conventional logic test onlogic circuits logic circuit - Scan Capture Mode
- Each
logic circuit tester 21 through aconventional scan bus 23. Each node of interest within anylogic circuit tester 21 may transmit a CAPTURE signal to the scan registers withinlogic circuits scan bus 23 telling them to load their input data.Tester 21 may thereafter serially shift that data outward from the scan registers via a SCANOUT line ofscan bus 23. This givestester 21 the ability to acquire a “snapshot” view of the states of a large number of internal circuit nodes not otherwise accessible via I/O terminals 18. - In accordance with the invention, each
core wrapper 24 also includes a scan register accessible throughscan bus 23. In a “scan capture” mode of operation, the scan register within eachcore wrapper 24 responds to the CAPTURE signal onscan bus 23 by storing the data, address and control information appearing on thebus 32 providinglogic circuits RAM 12. Whentester 21 acquires scan data from the scan registers withinlogic circuits scan bus 23, it also acquires the RAM bus data stored in the scan registers withincore wrappers 14. Thus in the scan capture mode of operation,core wrappers 24 providetester 10 with a snapshot view of states oflogic circuit RAM buses 32. - Scan Force Mode
- The scan register within each
core wrapper 24 includes a section connected to lines of theRAM bus 32 that convey the data output ofRAM 12 tologic circuits O terminals 18,tester 21 can shift data into that section of the scan register within eachcore wrapper 24 viascan bus 23. Thereafter, when testing the logic oflogic circuits IC tester 21 can assert a FORCE signal line ofSCAN bus 23 telling eachcore wrapper 24 to force the data stored in that section of its internal scan register onto the data output lines ofscan bus 23 in lieu of any data currently being read out of theRAM 12. Thus anylogic circuit RAM 12 address will receive the data stored in a scan register instead of the data stored at that RAM address. This force testing capability allowstester 21 to bypassRAMs 12 and to directly provide input data to eachshadow logic circuit 16 via data lines ofRAM bus 32 during a logic test. - RAM Pass/Fail Mode
- A RAM is defective when any one of its addressable cells is defective, so IC test engineers would like to be able to test each cell to make sure that it is correctly storing and reading out data. But since
RAMs 12 are not directly accessible totester 21 via I/O terminals 18, it can be difficult to design a test thattester 21 can carry out at I/O terminals 18 that will ensure that everyRAM 12 address is properly tested. - It is helpful to be able to directly test embedded
RAMs 12 independent of the operation oflogic circuits RAMs 12 by multiplexing their address, data andcontrol lines 32 onto I/O terminals 18. During normal IC operation or during a normal logic test,terminals 18 would be connectedlogic circuits 14, but duringmemory tests terminals 18 would be connected to RAM 12 input/output lines 32. However this approach requires us to route alarge bus 32 from eachRAM 12 to I/O terminals 18, and routing large buses often requires too much scarce space in an IC. - In the
BIST circuit 11 of the present invention, eachcore wrapper 24 may be configured to operate in a pass/fail RAM testing mode in which it disconnects itsRAM 12 fromlines 32 and connects it instead to test circuits within the core wrapper itself. The test circuit of eachcore wrapper 24 then directly read and write accesses each address ofRAM 12, comparing data written into the address to the data read back out to determine whether they match. When acore wrapper 24 detects aRAM 12 failure it asserts an output error signal (FAIL) and continues to assert the FAIL signal for the duration of the RAM test. When the test is complete, eachcore wrapper 24 asserts an output DONE signal. Thus the state FAIL signal output of eachcore wrapper 24 at the end of the test indicates whether its corresponding RAM passed or failed the RAM test. - The DONE and FAIL signal outputs of each
core wrapper 24 could be provided directly totester 21 so thattester 21 could determine when eachcore wrapper 24 has finished the test and can determine whichRAMs 12, if any, failed. However whentester 21 only needs to know if any RAM failed the test, it is not necessary to provide it with a separate FAIL signal output from each core wrapper. As shown in FIG. 5IC 10 includes a “glue logic”circuit 33 for logically combining (for example “ORing”) the FAIL signal outputs ofcore wrappers 24 to produce a single output FAILX signal provided toIC tester 21 indicating when anyRAM 12 failed its RAM test, and for combining (suitably “ANDing”) the DONE output signals ofcore wrappers 24 to produce a single DONEX signal indicating that all RAM tests are complete. -
Glue logic circuit 33 may alternatively multiplex the FAIL and DONE signal outputs ofcore wrappers 24 onto the FAILX and DONEX signals, with the selection being controlled byIC tester 21. This givestester 21 the ability to successively inspect the FAIL output of eachcore wrapper 24 via the single DONEX connection to determine whichRAMs 12 failed the test.Glue logic circuit 33 includes an internal control register (“a JTAG register”) for holding data controlling glue logic circuit logic.Tester 21 write accesses that control register via aconventional JTAG bus 25 in order to configure the logic operations it carries out on the FAIL and DONE signals. - Each
core wrapper 24 also includes an internal JTAG register accessed bytester 21 viaJTAG bus 25 for storing data for controlling their operations.Tester 21 initiates a pass/fail RAM test by first setting and resetting a RESET bit in the JTAG registers withincore wrappers 24 to reset their DONE and FAIL signal outputs and to initialize them to carry out RAM tests.Tester 21 also sets a MODE bit in the JTAG register within eachcore wrapper 24 to tell it to disconnect itslocal RAM 12 from itsRAM bus 32 and to re-connect the RAM to an internal test circuit within the core wrapper.Tester 21 also writes a separate set of MIN and MAX data into the JTAG registers within eachcore wrapper 24 to tell eachcore wrapper 24 the address range of theRAM 12 it is to test.Tester 21 then sets a START bit in the JTAG register within each core wrapper to tell it to begin testing its correspondingRAM 12. - Each
core wrapper 24 then tests itsRAM 12, asserts its FAIL output signals if it detects a RAM error, and asserts its output DONE signal at the end of the test.Glue logic circuit 33 then supplies its FAILX signal andDONEX signal tester 21. Whenglue logic circuit 33 is configured to AND the DONE signals and OR the FAIL signals to produce the FAILX and DONEX signals,tester 21 checks the state of the FAILX signal output ofglue logic circuit 33 when the DONEX signal is asserted to determine whether anyRAM 12 failed the RAM test. Whenglue logic circuit 33 is configured to multiplex the DONE signals and multiples the FAIL signals to produce the FAILX and DONEX signal,tester 21 checks the state of the FAILX signal output ofglue logic circuit 33 when the DONEX signal is asserted to determine whether oneparticular RAM 12 has failed its RAM test.Tester 21 may then use the JTAG bus to reconfigureglue logic circuit 33 to select the DONE and FAIL output of anothercore wrapper 24 and repeat the process to determine whether anext RAM 12 is defective. - RAM Bit Map Mode
- It is sometimes helpful to know the particular location within each
RAM 12 of every defective bit. For example,RAMs 12 may include spare rows or columns of memory cells for replacing rows or columns of cells containing one or more defective memory cells. When an external RAM repair system learns the addresses of defective cells within eachRAM 12, it can reconfigure the RAMs so to use a spare row or column in lieu of any row or column containing a defective memory cell, for example by using a laser to alter signal routing paths within the RAM. Such RAM repair technology is well-known. In order to make use of spare row and column replacement, it is necessary for the repair circuit to know the row and column address of memory cells ofRAMs 12 that fail a test as well as the particular bit or bits of that memory cell that failed. In its “bit map” mode of operation, eachcore wrapper 24 loads test result data for each addressable memory cell into its internal scan register so thattester 21 can acquire that data viascan bus 23. The result data indicates whether each bit of the memory cell is defective. The result data IC tester acquires for all memory cells forms a bit map of the defective storage locations within eachRAM 12 that may be provided to an external RAM repair system. - To initiate a bit map mode RAM test,
tester 21 first writes the MODE bit and a DIAG bit into the JTAG register withinglue logic circuit 33. The MODE bit tells eachcore wrapper 24 that it is to connect its test circuit to itsRAM 12, and the DIAG bit tells eachcore wrapper 24 that it is to perform a bit map mode test rather than a pass/fail mode test.Tester 21 then sets the START bit in the JTAG register to tell eachcore wrapper 24 to begin to test the first address of itsRAM 12 and to make its test results available at the input of its internal scan register. In this mode each core wrappers 24 then assert its output DONE signal after testing its first address, thereby causingglue logic circuit 33 to pulse its output DONEX signal.Tester 21 responds to the DONEX signal by pulsing the CAPTURE signal line ofscan bus 23 to tellcore wrappers 24 to load test results data into their scan registers and by repeatedly pulsing a SHIFT signal line ofscan bus 23 to shift the test results out of the scan registers via a SCANOUT line ofscan bus 23 so thattester 21 can acquire the results data.Tester 21 then pulses a READY signal input tocore wrappers 24 telling them to test a next memory address. The process repeats for each memory address so that by the end of the test,tester 21 will have acquired test results for every memory address.Tester 21 may then, for example, forward the test results to an external repair system. - RAM Word Map Mode
- When a
core wrapper 24 operates in a “word map” mode,tester 21 is able to acquire a map of defective RAM addresses for anyparticular RAM 12 although, unlike the bit map mode,tester 21 it does not learn which particular bits of each defective address are defective. The advantage to the word map mode is that it is not necessary for the system to stop after each test to provideIC tester 21 with the time it needs to acquire results data after each RAM address is tested. - During a RAM test, when a
core wrapper 24 detects a defective memory cell, it pulses an output current error signal (CERR). WhenBIST 11 is to operate in a “word map” mode,tester 21 writes data to a JTAG register withinglue logic circuit 33 telling it to provide the DONE signal and CERR output signal of a particular one ofcore wrappers 24 as DONEX and CERRX inputs totester 21. Therefore whentester 21 initiates a RAM test,tester 21 sees the DONE and CERR outputs of only onecore wrapper 24. During each cycle of the RAM test in which a particular RAM address is tested, the CERRX signal output ofglue logic 33 indicates whether theRAM 12 address last tested byparticular core wrapper 14 passed the test and the DONEX signal indicates when the CERRX signal is valid. The sequence of CERR signal bit states produced during a RAM test acts as a map of the failed addresses of theparticular RAM 12 controlling the CERR output ofglue logic 33. To provide such a bit map for eachRAM 12,tester 21 repeats the RAM test for eachRAM 12, sending selection data via the JTAG bus to reconfigureglue logic 33 before each test to select the DONE and CERR outputs of thecore wrapper 24 of theRAM 12 to be next tested. - CORE Wrapper Architecture
- FIG. 6 illustrates a
typical core wrapper 24 of FIG. 5 in more detailed block diagram form.Core wrapper 24 is designed to carry out any of the above-described test modes on a RAM of any size without modification.Core wrapper 24 includes aRAM test circuit 40, clocked by a CLOCK signal fromIC tester 21 of FIG. 5, for responding to an input START signal by read and write accessing each address of RAM 12 (FIG. 5) and for comparing data written into each address with data thereafter read out to determine whether they match.Test circuit 40 asserts a FAIL output signal whenever it detects a defective RAM address and thereafter continues to assert the FAIL signal until the end of the test.RAM test circuit 40 also briefly pulses a “current error” output signal (CERR) whenever it detects a defective RAM address and pulses an output DONE signal either after testing each RAM address (bit map or word map modes) or after it has tested all addresses (pass/fail mode). -
Core wrapper 24 includes ascan register 46 for storing data, address and control signals appearing onbus 32 in response to the CAPTURE signal fromtester 21 and shifts out its stored data onto the SHIFT_OUT line ofscan bus 23 in response to successive pulses of the SHIFT signal fromtester 21. -
Core wrapper 24 also includes a set of multiplexers 42-44 under control of a MODE signal for alternatively connecting the control (CNT), address (ADDR), and data in (DI) input ports of RAM 12 (FIG. 5) selectively either to testcircuit 40 or to control (CONT), address (ADDRESS) and data in (DATA_IN) lines ofRAM bus 32 leading tologic circuits multiplexer 48 under control of a FORCE signal line of the scan bus normally connects the data out (DO) output port ofRAM 12 to bothtest circuit 40 and to data in lines (DATA_IN) ofbus 32 leading tologic circuits tester 21 of FIG. 5 asserts the FORCE signal,multiplexer 48 forces a word (SCAN_INSERT) stored inscan register 46 onto the DATA_OUT lines ofbus 32 so thatlogic circuits register 46 instead of the data stored inRAM 21 when they attempt to readaccess RAM 12. To load the SCAN_INSERT data intoscan register 46,tester 21 serially shifts the SCAN_INSERT data onto the SCAN_IN line ofscan bus 23 as it pulses the SHIFT signal. -
Tester circuit 40 includes apattern generator 50 clocked by the CLOCK signal for generating data, address and control data patterns supplied as inputs to RAM 12 via multiplexers 42-44 during a RAM test.Pattern generator 50 writes data into each address ofRAM 12 and then signalsRAM 12 to read it back out. DuringRAM 12 read cycles,pattern generator 50 sends a COMP signal to adata comparator 52 which compares thedata pattern generator 50 wrote into a RAM address to the data the RAM is currently reading back out of that address. When the RAM input and output data fail to match,comparator 52 asserts the CERR signal. The CERR signal drives a set input of an RS flip-flop 54 reset by a RESET signal at the start of a test. Flip-flop 54 produces a FAIL signal at its Q output. When data comparator 52 first detects a faulty RAM address, the CERR signal sets flip-flop 54 to assert the FAIL signal. Flip-flop 54 then continues to assert the FAIL signal untiltester 21 resets it. - An
XOR gate 53 combines theRAM 21 data input produced bypattern generator 50 to the data read out ofRAM 21 to produce a RESULT data word supplied as input to scanregister 46. Each bit of the RESULT data word corresponds to a bit ofRAM 12 output data and indicates whether that bit matches a corresponding bit of input data. In the bit map mode,tester 21 pulses the CAPTURE signal line of the SCAN bus to capture the RESULT data inscan register 46 and then repeatedly pulses a SHIFT signal line of the scan bus to signalscan register 46 to shift the captured data out onto the SCAN_IN line of the scan bus. -
Core wrappers 24 of FIG. 5 may be implemented as “standard cells” easily incorporated without modification into the design of anyIC 10 having one or more embeddedRAMs 12, even thoughRAMs 12 of FIG. 5 may have differing address spaces. Since the pattern produced by thepattern generator 50 within eachcore wrapper 24 must match the characteristics of theRAM 12 being tested, MIN and MAX control data stored in aJTAG register 55 defines the range ofRAM 12 addresses eachcore wrapper 24 is to test. With separate MIN and MAX data provided to eachcore wrapper 24, the core wrappers are able to concurrently testRAMs 12 of differing size.Tester 21 may write the MIN and MAX data into JTAG register 55 viaJTAG bus 25 before the start of a test. -
Pattern generator 50 can generate either of two types of output data patterns that sequence RAM addresses in two different ways. ARAM 21 is typically organized into an array of rows and columns of addressable memory cells and a cell's address includes the addresses of its row and column.Pattern generator 50 can be configured to write and read address each successive cell of a row before moving on to a next row (“fast row mode”) or to write and read address each cell of a column before moving on to a next column (“fast column mode”) The choice of fast row or column mode depends on whetherRAM 12 can respond faster to a change in row or column address.Tester 21 of FIG. 5 writes a ROW/COL word intoJTAG register 55 viaJTAG bus 25 to tell it whether it is to operate in the fast row or fast column mode. -
Tester 21 also sets and then resets a RESET bit stored in JTAG register 55 to reset flip-flop 54 and to placepattern generator 50 in an initial state, sets a MODE bit inregister 55 to switch multiplexers 42-44, set a DIAG bit inregister 55 to indicate when pattern generator is to operate in the bit map or word map mode, and sets a START bit inregister 55 to signalpattern generator 50 to begin a test.SKEW data tester 21 writes intoJTAG register 55 tellspattern generator 50 how to adjust the relative timing of the CONT, ADDR and DI signals it produces in order to accommodate the signal timing of the RAM under test. - Controller Partitioning
- As illustrated in FIG. 5 and discussed herein above,
IC tester 21 may use the JTAG bus to configurecore wrappers 24 andglue logic circuit 33 to carry out any of the above-described modes of operation and may use the RC and SCAN buses during the test to acquire data produced by the core wrappers andglue logic circuit 33. However as described below, much of the BIST control functions oftester 21 may be assumed by dedicated controllers either internal or external toIC 10 without any modifications tocore wrappers 24 orglue logic circuit 33. The manner in which we choose to implement control functions depends on many factors. For example when there is available space withinIC 10, when we are interested in minimizing the number ofterminals IC 10 needs to convey information betweentester 21 andBIST circuit 11, and when we want to limit the need for tester resources, we can include a BIST controller insideIC 10. Otherwise we can implement the controller in the form of a separate IC located outsideIC 10. Or BIST control functions can be shared by internal and external controllers. - IC Tester/BIST Controller
- FIG. 7 illustrates an alternative embodiment of the test system of FIG. 5 in which an
internal BIST controller 64 has been included inIC 10 for assuming various functions ofIC tester 21 in configuring and controllingcore wrappers 24 andglue logic 36.BIST controller 64 is suitably a conventional pattern generator for producing an appropriate sequence of patterns on the JTAG and RC buses whenIC tester 21 commands it to start a test, for example, by a dedicated START signal.BIST controller 64 produces the same sequence of control data thattester 21 would otherwise have to provide on the RC and JTAG buses in order to configureglue logic 36 andcore wrappers 24 to carry out various tests onRAMs 12 and to start their test operations. Since pattern generators capable of carrying out the function ofBIST controller 64 are well-known,BIST controller 64 is no not further detailed herein. - Installing a
BIST controller 64 onIC 10 allows us to reduce use ofIC tester 21 resources and to reduce the number ofIC 20 terminals needed to interconnectIC tester 21 toIC 10. Table I lists the connections needed betweenIC tester 21 andIC 10 for each of the test modes whenBIST controller 64 is installed onIC 10.TABLE I TEST MODE CONNECTIONS All Modes CLOCK, START Pass/Fail DONEX, FAILX Scan Capture SCAN bus Scan Force SCAN bus Bit Map SCAN bus, READY Word Map CERRX - A JTAG bus connection between
IC 10 andtester 21 isn't required sinceBIST controller 64 produces the appropriate patterns on the JTAG bus. However when available,tester 21 could use the JTAG bus to send a START command toBIST controller 64 instead of directly sending a dedicated START signal toBIST controller 64. The SCAN bus connection fromtester 21 is needed only when either scan capture, scan force or bit map mode testing is needed. The CERR signal of the RC bus is needed only when a Word map mode test is to be performed. - Those skilled in the art will appreciate that the test control pattern BIST controller62 produces on the JTAG and RC buses in response to the START signal can be programmed into
BIST controller 64 at the mask level. However this requiresBIST controller 64 to be custom-designed for each IC in which it is installed because the nature of the test pattern it must produce depends on the size and number of embeddedRAMs 12 and on nature of tests to be performed. However BIST controller 62 can be implemented as a conventional programmable pattern generator programmed by input data supplied, for example, via a JTAG or similar bus from an external host computer or other data source. In such case the BIST controller 62 can be implemented as a standard cell that may be incorporated into any IC employing one ormore core wrappers 24 regardless of the number or size of embedded RAMs to be tested and regardless of which tests are to be performed. Whenglue logic circuit 33 is also programmable, the test system can be implemented entirely as standard cells that do not need to be modified to accommodate the size or test requirements of the RAMs embedded in the IC. - Tester and External BIST Controller
- FIG. 8 illustrates an alternative version of the test system of FIG. 5 in which
IC 10 is mounted on a “load board” 66, a conventional printed circuit board for holdingIC 10 and for routing signal betweentester 21 andIC 10 during tests. When it is not possible or otherwise desirable to install a BIST controller within IC, the function ofinternal BIST controller 64 of FIG. 7 can be implemented by anexternal BIST controller 68, a separate IC suitably mounted onload board 66.External BIST controller 68 may be similar in nature and operation tointernal BIST controller 64 of FIG. 7. Although anexternal BIST controller 68 requires us to providemore IC 10 terminals than theinternal BIST controller 64 of FIG. 7, it nonetheless allows us to minimize the required number ofIC tester 21 channels. - External BIST Controller Only
- In some applications it may be desirable for all functions of
tester 21 of FIG. 5 to be carried out by a dedicated external BIST controller. FIG. 9 illustrates an embodiment of the test system of FIG. 9 including aload board 66 holdingIC 10, aRAM 70 and aprogrammable BOST controller 71 clocked by a CLOCK signal from a source that may be internal or external to loadboard 66. Anexternal host computer 74 writes a test program intoRAM 70 viaconventional computer bus 76, and then sends a START command toBOST controller 71 viabus 76 telling it to execute that test program. The program stored inRAM 70 tellsBOST controller 71 to carry out all test functions that might otherwise be carried out bytester 21 of FIG. 9 including supplying test pattern inputs tologic circuits IC 10, supplying control signal patterns tocore wrappers 24 andglue logic circuit 36 via the RC, SCAN and JTAG buses, and appropriately processing IC output data appearing on the I/O, and SCAN buses.RAM 70 of FIG. 9 may replaced with a read only memory (ROM) storing a test program appropriate forIC 10. In suchcase host computer 74 need only supply a START command toBOST controller 71 and acquire test results—it need not actively program theBOST controller 71. - BIST/BOST Controllers
- FIG. 10 illustrates an embodiment of the test system similar to that of FIG. 9 except the BIST control functions are shared by an
internal BIST controller 64 andexternal BIST controller 71. This reduces the number of I/O terminals ofIC 10. - BIST Controller Only
- FIG. 11 illustrates an embodiment of the test system of the present invention in which a
BIST controller 64 connected to the JTAG and RC buses independently carries out a pass/fail test onRAMs 12 in response to an input START signal from any source. The START signal may, for example, be generated by an internal IC circuit on system start up or by any circuit external toIC 10. The only IC output is the FAILX signal provided byglue logic circuit 36. The FAILX signal can, for example, be used to trigger an alarm. This arrangement system is useful for testingRAMs 12 whenIC 10 is in its normal working environment and not accessible to external test equipment. - BOST Circuit
- When it is convenient to connect the
buses logic circuits RAMs 12 to I/O terminals ofIC 10, the functions of core wrappers 34,glue logic 36 andbist controller 68 of FIG. 8 can be implemented by a built off-chip self test (BOST)circuit 67, an integrated circuit mounted onload board 66. While use ofBOST circuit 67 does not eliminate the need for bring thebuses accessing RAMs 12 to I/O terminals ofIC 10,BOST circuit 67 reduces the number ofchannels tester 5 needs to testIC 10.BOST circuit 67 may be implemented, for example, by an appropriately programmed field programmable gate array (FPGA). - Core Wrapper Pattern Generator
- FIG. 13 illustrates
pattern generator 50 of FIG. 6 in more detailed block diagram form.Pattern generator 50 includes adata generator 70 clocked by a DATA CLOCK signal from asequencer 72 for producing the data pattern to be placed on the data input lines (I) of RAM 21 (see FIG. 6). A pair ofpseudorandom number generators sequencer 72 by producing a sequence of row or column numbers (ROW or COL) spanning the widest ranges of RAM row and column addresses that the BIST system is capable of handling. A pseudorandom generator is similar to a counter in that it produces a sequence of numbers spanning a particular range. However whereas a counter generates the number in numerical order, a pseudorandom number generator generates them in pseudorandom order. A pseudorandom number generator can be implemented with fewer gates than a counter. - A pair of
digital filters number generators generators RAM 12 has an 8-bit ROW address spanning the range of 0-255 but thatnumber generator 74 produces a 16-bit output ROW address 0-65535. Supposenumber generator 74 producesoutput ROW address 112 on the nth cycle of the ROW address clock but produces address 1112 on the (n+1)th cycle. Then on thenth cycle filter 78 will forward itsincoming ROW address 112 as the row address portion of the output ADDR word and will also saveaddress 112 in an internal register. On the (n+1)th cycle of the row address clock, filter 78 will forward therow address 112 stored in its internal register rather than the current incoming row address 1112, because the incoming row address is outside the range of RAM being tested. Thus the cell atrow address 112 is tested twice. - A
skew circuit 81 adjustably delays each of the DI, ADDR and CNT outputs of data generator 60, filters 78 and 80, andsequencer 72 with delays controlled by the SKEW data input from JTAG register 55 of FIG. 6. The delays are set to accommodate the timing requirements of the RAM under test. - Address Filter
- FIG. 14 illustrates the
row filter 78 of FIG. 13 in more detailed block diagram form;column filter 80 is similar. Referring to FIG. 13,filter 78 includes aregister 82 for storing an incoming ROW address, acomparator 84 for determining whether the incoming ROW address is within the range indicated by the input MIN, MAX data and for loading the incoming row address intoregister 82 when it does. Amultiplexer 86 controlled bycomparator 84 selectively provides either the incoming ROW address or a ROW address stored in the register depending on the result of the comparison. - Glue Logic
- FIG. 15 illustrates a suitable implementation of
glue logic circuit 33 of FIG. 5 in more detailed block diagram form.Glue logic circuit 33 includes a set ofprogrammable logic circuit core wrappers 24 of FIG. 5. AJTAG register 96 receives configuration data (CONFIG) fromtester 21 viaJTAG bus 25 and supplies it toprogrammable logic circuits logic circuit glue wrapper 33 are fixed,programmable logic circuits - FIG. 16 illustrates an alternative version of the invention that is somewhat similar to the embodiment of FIG. 5 and similar elements are designated by similar reference characters. However in the test system of FIG. 16, some of the functionality included within
core wrappers 24 of FIG. 1, along with the function ofglue logic 33, has been centralized into aBIST controller 100 that communicates with allcore wrappers 102 of FIG. 16 via a set of control lines and withintegrated circuit tester 21 via abus 104.BIST controller 100 may be implemented withinIC 10 as shown if FIG. 16 or may be implemented external toIC 10. - FIG. 17 illustrates a
typical core wrapper 102 of FIG. 16 in more detailed block diagram form.Core wrapper 102 has many element in common withcore wrapper 24 of FIG. 6, and similar elements are designated by similar reference characters, however thepattern generator 50, JTAG register 55 and flip-flop 54 ofcore wrapper 24 have been replaced incore wrapper 102 with a set of devices 110-120. Referring to FIGS. 16 and 17, acolumn address generator 110 and arow address generator 112 respectively reset an output memory column address (COL) and memory row address (ROW) to 0 in response to an input RESET signal fromBIST controller 100. Thereafter, during a test,column address generator 110 changes its output COL address in response to each pulse of a column address clock signal (COL CLOCK) fromBIST controller 100. Similarlyrow address generator 112 changes its output ROW address in response to each pulse of a row address clock signal (ROW CLOCK) fromBIST controller 100.Address generators generators - A pair of
filters 114 and 116 (similar tofilters circuit 81 of FIG. 13).Filters BIST controller 100. In particular, whenever a COL or ROW value is within the indicated address range,filter filter filters core wrappers 102 via aserial bus 120. - A
data decoder 118 acts as a lookup table to decode an encoded data word (ENCODED DATA) having a relatively few bits provided byBIST controller 100 to produce a wider output DATA word to be written intoRAM 12 during a test. Since the range of DATA word patterns that may be written intomemory 24 during a test be small, only a relatively small ENCODED DATA word input todecoder 118 is needed to select a relatively DATA word output. This helps minimize the number of signal paths betweencontroller 100 andcore wrappers 102 will still allowingcontroller 100 to control the sequence of data supplied toRAM 12. - The DATA value output of
decoder 118 provides as another input to skewingcircuit 120. Skewingcircuit 120, which also receives an input memory read/write control signal (or signals) CNT fromBIST controller 100, suitably delays the CNT, COL ADDR, ROW ADDR and DATA signals to provide control (CNT), addressing input (ADDR) and data (DI) inputs to RAM 12 via multiplexers 42-44, controlled by a MODE signal fromBIST controller 100. The CERR output of acomparator 52 which compares the RAM's input and output data is supplied as an input toBIST controller 100. -
BIST controller 104 may be implemented, for example, in the form of a programmable gate array programmed bytester 21 or any other source of programming data (PROS) via aserial bus 106.BIST controller 104 may be programmed as a state machine to produce a sequence of output signal patterns on its output lines tocore wrappers 102 that will causecore wrappers 102 to testRAM 12. SinceBIST controller 100 is programmable, the nature of its the signal patterns it produces and supplied tocore wrappers 102 can be adjusted to suit the nature of the test to be performed onRAMs 12.Core wrappers 102 andBIST controller 102 can be used without hardware customization to accommodate a wide variety and sizes ofRAMs 12 and to provide a variety of test patterns. - The manner in which manner the functions of
core wrappers 102 andBIST controller 100 are partitioned ensures that only a relatively small number of control and data lines need be routed to several locations onIC 10 in order to testRAMS 12. This helps to minimize the amount of IC floor space the test system requires. The small control and data signal bus also permits much flexibility in where the control elements the physically located.BIST controller 100 can be easily moved offIC 10 because the connections tocore wrappers 102 do not require the use of very many IC pins. Note that the test system architecture of FIG. 16 parallels that of FIG. 3B. FIG. 3B shows aBIST circuit 7 and aBIST controller 8 implemented within anintegrated circuit 2B and these correspond tocore wrapper 102 of FIG. 16,BIST controller 110 implemented within integratedcircuit 10 of FIG. 16. The data and control signal lines linking thecore wrappers 102 toBIST controller 100 correspond tobus 4B of FIG. 3B. It should therefore be appreciated thatBIST controller 100 can alternatively be implemented external toIC 10, for example on a load board on which the IC is mounted as illustrated in FIG. 3A. The function ofBIST controller 100 can also be implemented byIC tester 21 providing a topology similar to that illustrated in FIG. 3C. Further, the function of acore wrapper 102 can be alternatively implemented by an externally mounted BOST circuit, providing a test circuit topology similar to that of FIG. 4. - We have described a test system for an integrated circuit having one or more embedded RAMs, wherein the test system includes a flexible BIST circuit for testing the RAMS, and wherein the BIST circuit may be incorporated with little customization into the IC regardless of the number, size or test requirements of its embedded RAMs. We have also described how a controller can configure the BIST circuit to accommodate the varying sizes of the embedded RAMs and to select from among several modes of BIST operation to accommodate the test requirements of each RAM. We have further shown how the controller functions may be conveniently and flexibly partitioned between a BIST controller inside the IC, a BOST controller outside the IC, and a conventional integrated circuit tester.
- While the forgoing specification has described preferred embodiments of the present invention, one skilled in the art may make many modifications thereto without departing from the invention in its broader aspects. The appended claims are intended to cover all such modifications as fall within the true scope and spirit of the invention.
Claims (48)
1. An apparatus for testing a memory embedded in an integrated circuit (IC), wherein said memory (12) includes a plurality of addressable memory cells and wherein said IC includes a logic circuit (14,16) linked to said memory for read and write accessing said memory, the apparatus comprising:
a test circuit (40) included in said IC for receiving input MIN, MAX data and for successively testing all memory cells of said memory having addresses within a range of addresses indicated by said input MIN, MAX data to determine whether each memory cell is defective, and
control means (21, 66 or 68 and 55) for supplying said MIN, MAX data to said test circuit.
2. The apparatus in accordance with claim 1 wherein said control means also supplies a START signal to said test circuit to tell it when to begin testing the memory cells of said memory.
3. The apparatus in accordance with claim 1 further comprising switch means (42-44) included in said IC for responding to an input MODE signal by disconnecting said logic circuit from said memory and by connecting said test circuit to said memory so that said test circuit can test the memory cells of said memory,
wherein said control means supplies said MODE control signal to said switch means.
4. The apparatus in accordance with claim 1 wherein said test circuit pulses an output CERR signal whenever it determines one of said memory cells is defective.
5. The apparatus in accordance with claim 1 wherein said test circuit continuously asserts an output FAIL signal after determining that any one of said memory cells is defective.
6. The apparatus in accordance with claim 1
wherein said control means supplies a DIAG signal to said test circuit, and
wherein in response to a state of said DIAG signal, said test circuit selectively either asserts a DONE signal when it has completed testing all of said memory cells or pulses said DONE signal each time it completes testing any one of said memory cells.
7. The apparatus in accordance with claim 6 wherein said control means also monitors said DONE signal to determine when said test circuit has completed a test.
8. The apparatus in accordance with claim 6
wherein said test circuit continuously asserts an output FAIL signal after determining that any one of said memory cells is defective,
wherein said test circuit pulses an output CERR signal whenever it determines any one of said memory cells is defective, and selectively asserts a DONE signal when it has completed testing all memory addresses.
9. The apparatus in accordance with claim 8
wherein said control means monitors said DONE signal to determine when said test circuit has completed a test,
wherein said control means monitors said FAIL signal to determine whether any one of said memory cells is defective, and
wherein said control means monitors said DONE signal to determine which of said memory cells is defective.
10. The apparatus in accordance with claim 1
wherein said addressable memory cells are arrayed in rows and columns, and
wherein said control means transmits ROW/COL data to said test circuit controlling whether the test circuit tests all cells of a row before testing cells of a next row, or tests all cells of a column before testing cells of a next column.
11. The apparatus in accordance with claim 1 further comprising:
a scan register (46) implemented within said IC, and
a scan bus (23) linking said scan register to said control means,
wherein said scan register stores data appearing at input and output ports of said memory in response to an input CAPTURE signal supplied by said control means via said scan bus,
wherein said scan register shifts out its stored data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.
12. The apparatus in accordance with claim 1 further comprising:
a scan register (46) implemented within said IC, and
a scan bus (23) linking said scan register to said control means,
wherein said test circuit generates RESULT data after testing each of said memory cells, said RESULT data indicating whether each bit of data written into that memory cell matches a corresponding bit of data it thereafter reads back out of that memory cell,
wherein said scan register stores said RESULT data in response to an input CAPTURE signal supplied by said control means via said scan bus, and
wherein said scan register shifts out its stored RESULT data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.
13. The apparatus in accordance with claim 1 further comprising:
a scan register (46) implemented within said IC, and
a scan bus (23) linking said scan register to said control means,
wherein said scan register stores data appearing at input and output ports of said memory in response to an input CAPTURE signal supplied by said control means via said scan bus,
wherein said scan register shifts out its stored data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.
14. The apparatus in accordance with claim 1 further comprising:
a scan register (46) implemented within said IC, and
a scan bus (23) linking said scan register to said control means,
wherein said test circuit generates RESULT data after testing each of said memory cells, said RESULT data indicating whether each bit of data written into that memory cell matches a corresponding bit of data it thereafter reads back out of that memory cell,
wherein said scan register stores said RESULT data and data appearing at input and output ports of said memory in response to an input CAPTURE signal supplied by said control means via said scan bus, and
wherein said scan register shifts out its stored data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.
15. The apparatus in accordance with claim 1 wherein said control means comprises an integrated circuit tester external to said IC.
16. The apparatus in accordance with claim 1 further comprising a load board (66) for holding said IC, wherein said control means comprises a built-off self test (BOST) circuit external to said IC mounted on said load board.
17. The apparatus in accordance with claim 1 wherein said control means is implemented within said IC.
18. The apparatus in accordance with claim 1 further comprising:
a scan register (46) implemented within said IC,
a scan bus (23) linking said scan register to said control means, wherein said control means stores SCAN_INSERT data in said scan register via said scan bus, and
multiplexing means (48) connected to said scan bus for responding to a FORCE signal supplied by said control means via said scan bus by disconnecting a data output port (DO) of said memory from said logic circuit and supplying said SCAN_INSERT data stored in said scan register to said logic circuit.
19. The apparatus in accordance with claim 1 further comprising switch means (42-44) included in said IC for responding to an input MODE signal by disconnecting said logic circuit from said memory and by connecting said test circuit to said memory so that said test circuit can test the memory cells of said memory,
wherein said test circuit pulses an output CERR signal whenever it determines one of said memory cells is defective,
wherein said test circuit continuously asserts an output FAIL signal after determining that any one of said memory cells is defective,
wherein said control means supplies a DIAG signal to said test circuit to tell it test said memory in a bit map mode,
wherein when said test circuit tests said memory other than in said bit map mode, it asserts a DONE signal when it has completed testing all memory cells of said memory,
wherein when said test circuit tests said memory in said bit map mode it pulses said DONE signal when it completes testing any one memory cell of said memory and waits until it receives a READY signal from said control means before testing a next memory cell of said memory,
wherein said control means monitors said DONE signal to determine when said test circuit has completed a test.
20. The apparatus in accordance with claim 19 wherein said control means comprises:
means internal to said IC for generating and supplying said MIN, MAX data and said DIAG signal to said test circuit, and
means external to said IC for generating said READY signal and for monitoring said CERR, FAIL and DIAG signals.
21. The apparatus in accordance with claim 19 wherein said control means comprises:
a load board (66) for holding said IC, and
a built-off self test (BOST) circuit external to said IC mounted on said load board for generating and supplying said MIN, MAX data and said MODE, DIAG and READY signals to said test circuit and for monitoring said CERR, FAIL and DIAG signals.
22. The apparatus in accordance with claim 19 wherein said control means comprises:
a load board (66) for holding said IC, and
a built-off self test (BOST) circuit external to said IC mounted on said load board for generating and supplying said MIN, MAX data and said MODE and DIAG signals to said test circuit, and
means external to said load board for generating said READY signal and for monitoring said CERR, FAIL and DIAG signals.
23. The apparatus in accordance with claim 19 wherein said control means comprises:
a load board (66) for holding said IC,
a built-off self test (BOST) circuit external to said IC mounted on said load board for generating and supplying said READY signal to said test circuit and for generating said READY signal and for monitoring said CERR, FAIL and DIAG signals, and
means internal to said IC for generating and supplying said MIN, MAX data and said MODE and DIAG signals to said test circuit.
24. The apparatus in accordance with claim 19 further comprising:
a scan register (46) implemented within said IC, and
a scan bus (23) linking said scan register to said control means,
wherein said scan register stores data appearing at input and output ports of said memory in response to an input CAPTURE signal supplied to said scan register by said control means via said scan bus,
wherein said scan register shifts out its stored data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus, and
wherein when the test circuit tests said memory in the bit map mode, said control means supplies said CAPTURE signal to said shift register and pulses said SHIFT signal in response to said DONE signal so that said scan register shifts out it stored data to said control means, said control means thereafter supplying said READY signal to said test circuit.
25. The apparatus in accordance with claim 24 wherein said test circuit generates RESULT data after testing each of said memory cells, said RESULT data indicating whether each bit of data written into that memory cell matches a corresponding bit of data it thereafter reads back out of that memory cell,
wherein said scan register stores said RESULT data in response to an input CAPTURE signal supplied by said control means via said scan bus, and
wherein said scan register also shifts out its stored RESULT data to said control means via said scan bus in response to pulses of said SHIFT signal.
26. The apparatus in accordance with claim 25 further comprising multiplexing means (48) connected to said scan bus for responding to a FORCE signal supplied thereto by said control means via said scan bus by disconnecting a data output port (DO) of said memory from said logic circuit and supplying to said logic circuit said SCAN_INSERT data said control means stores in said scan register via said scan bus.
27. An apparatus for testing a memory embedded in an integrated circuit (IC), wherein said memory (12) includes a plurality of addressable memory cells and wherein said IC includes a logic circuit (14,16) linked to said memory for read and write accessing said memory, the apparatus comprising:
a test circuit (40) included in said IC for successively testing all memory cells of said memory, pulsing an output CERR signal whenever it determines one of said memory cells is defective, and continuously asserting an output FAIL signal after determining that any one of said memory cells is defective, and wherein in response to a state of an input DIAG signal, said test circuit selectively either asserts a DONE signal when it has completed testing all of said memory cells or pulses said DONE signal each time it completes testing any one of said memory cells; and
a control means for supplying said DIAG signal to said test circuit and for monitoring said DONE signal to determine when said test circuit has completed a test.
28. The apparatus in accordance with claim 27 further comprising:
a scan register (46) implemented within said IC, and
a scan bus (23) linking said scan register to said control means,
wherein said scan register stores data appearing at input and output ports of said memory in response to an input CAPTURE signal supplied by said control means via said scan bus,
wherein said scan register shifts out its stored data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.
29. The apparatus in accordance with claim 28
wherein said test circuit generates RESULT data after testing each of said memory cells, said RESULT data indicating whether each bit of data written into that memory cell matches a corresponding bit of data it thereafter reads back out of that memory cell,
wherein said scan register stores said RESULT data in response to an input CAPTURE signal supplied by said control means via said scan bus, and
wherein said scan register shifts out its stored RESULT data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.
30. An apparatus for testing a plurality of memories embedded in an integrated circuit (IC), wherein each of said memories (12) includes a plurality of addressable memory cells, wherein at least two of said memories have differing address ranges, and wherein said IC includes logic circuits (14,16) linked to said memories for read and write accessing said memories, the apparatus comprising:
a plurality of test circuits (40) included in said IC, each corresponding to a separate one of said memories, for successively testing all memory cells of the corresponding memory having addresses within the corresponding memory's range of addresses as indicated by input MIN, MAX data to determine whether each memory cell is defective, and
control means (21, 66 or 68 and 55) for supplying said input MIN, MAX data to each of said test circuits.
31. The apparatus in accordance with claim 30 further comprising switch means (42-44) included in said IC for responding to an input MODE signal by disconnecting said logic circuit from said memories and by connecting each said test circuit to its corresponding memory so that said test circuit can test the memory cells of its corresponding memory,
wherein said control means also supplies said MODE control signal to said switch means.
32. The apparatus in accordance with claim 31
wherein each said test circuit pulses an output CERR signal whenever it determines one of said memory cells is defective and continuously asserts an output FAIL signal after determining that any one of said memory cells is defective.
wherein said control means supplies a DIAG signal to each said test circuit, and
wherein in response to a state of said DIAG signal, each said test circuit selectively either asserts an output DONE signal when it has completed testing all of said memory cells or pulses said DONE signal each time it completes testing any one of said memory cells.
33. The apparatus in accordance with claim 32 further comprising a glue logic circuit (33) for processing output DONE signals of all of said test circuits to provide a single DONEX signal provided as input to said control means, for processing output FAIL signals of all of said test circuits to produce a single FAILX signal provided as input to said control means, and for delivering one of said output CERR signals of said test circuits as input to said control means.
34. The apparatus in accordance with claim 30 further comprising:
a plurality of scan registers (46) implemented within said IC, each corresponding to a separate one of said embedded memories, and
a scan bus (23) linking each scan register to said control means,
wherein each said scan register stores data appearing at input and output ports of its corresponding memory in response to an input CAPTURE signal supplied by said control means via said scan bus,
wherein each said scan register shifts out its stored data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.
35. The apparatus in accordance with claim 34 wherein each said test circuit generates RESULT data after testing each of said memory cells, said RESULT data indicating whether each bit of data written into that memory cell matches a corresponding bit of data it thereafter reads back out of that memory cell,
wherein each said scan register stores its input RESULT data in response to an input CAPTURE signal supplied by said control means via said scan bus, and
wherein each said scan register shifts out its stored RESULT data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.
36. The apparatus in accordance with claim 30 wherein said control means comprises an integrated circuit tester external to said IC.
37. The apparatus in accordance with claim 30 further comprising a load board (66) for holding said IC, wherein said control means comprises a built-off self test (BOST) circuit external to said IC mounted on said load board.
38. The apparatus in accordance with claim 30 wherein said control means is implemented within said IC.
39. The apparatus in accordance with claim 35 further comprising multiplexing means (48) corresponding to each of said memories for responding to a FORCE signal supplied by said control means via said scan bus by disconnecting a data output port (DO) of its corresponding memory from said logic circuit and supplying SCAN_INSERT data stored in said scan register to said logic circuit,
wherein said control means stores SCAN_INSERT data in said scan register via said scan bus.
40. An apparatus for testing a plurality of memories embedded in an integrated circuit (IC), wherein each memory (12) includes a plurality of addressable memory cells and wherein said IC includes logic circuits (14,16) linked to said memory for read and write accessing said memory, the apparatus comprising:
a plurality of test circuits(40) included in said IC, each corresponding to a separate one of said Memories, for successively testing all memory cells of the corresponding memory, pulsing an output CERR signal whenever it determines one of said memory cells is defective, and continuously asserting an output FAIL signal after determining that any one of said memory cells is defective, and wherein in response to a state of an input DIAG signal, said test circuit selectively either asserts a DONE signal when it has completed testing all of said memory cells or pulses said DONE signal each time it completes testing any one of said memory cells;
glue logic means (33) for processing the DONE signal output of all of said test circuits to produce a single DONEX output signal, for processing the CERR output signals of all of said test circuits to produce a single CERRX output signal, and for processing the FAIL output signals of all of said test circuits to produce a single FAILX output signal,
control means for supplying said DIAG signal to said test circuit and for monitoring said CERRX, FAILX and DONEX.
41. The apparatus in accordance with claim 40 further comprising:
a plurality of scan register (46) implemented within said IC, each scan register corresponding to a separate one of said memories, and
a scan bus (23) linking said scan registers to said control means,
wherein each test circuit generates RESULT data after testing any memory cell its corresponding memory, said RESULT data indicating whether each bit of data written into that memory cell matches a corresponding bit of data it thereafter reads back out of that memory cell,
wherein said scan register stores said RESULT data in response to an input CAPTURE signal supplied by said control means via said scan bus, and
wherein said scan register shifts out its stored RESULT data to said control means via said scan bus in response to pulses of a SHIFT signal supplied to said scan register by said control means via said scan bus.
42. The apparatus in accordance with claim 41 wherein each scan register stores also data appearing at input and output ports of its corresponding memory in response to said CAPTURE signal.
43. A method of developing a BIST circuit for testing an embedded circuit on a production chip, comprising:
providing a development chip including an on-chip circuit configured as the embedded circuit and connections coupling the on-chip circuit to contact points; and
modifying an off-chip circuit external to said development chip and coupled to said contact points, to define said BIST circuit to be included on said production chip.
44. A method of developing a BIST controller circuit for controlling a BIST circuit when testing an embedded circuit on a production chip, comprising:
providing a development chip including an on-chip circuit configured as the embedded circuit, a BIST circuit for testing said on-chip circuit, and connections for coupling the BIST circuit to contact points; and
modifying an off-chip circuit external to said development chip coupled to said contact points to define said BIST controller circuit to be included on said production chip.
45. A method of developing a production chip including an embedded circuit and a BIST circuit connected to said embedded circuit for performing a test on the embedded circuit, the method comprising the steps of:
providing a development chip including said embedded circuit and connections coupling the embedded circuit to contact points;
providing an off-chip circuit external to said development chip and coupled to said contact points,
modifying said off-chip circuit so that it performs said test on said embedded circuit; and
defining said production chip including said embedded circuit and said BIST circuit, wherein said BIST circuit incorporates elements of the off-chip circuit as modified.
46. A method of developing a production chip including an embedded circuit, a BIST controller, and a BIST circuit, said BIST circuit being connected coupled to said embedded circuit and to said BIST controller for performing a test on the embedded circuit under control of said BIST controller, the method comprising the steps of:
providing a development chip including said embedded circuit, said BIST circuit coupled to said embedded circuit, and connections coupling the BIST circuit to contact points;
providing an off-chip circuit external to said development chip and coupled to said contact points,
modifying said off-chip circuit so that it appropriately controls said BIST circuit to perform said test on said embedded circuit; and
defining said production chip including said embedded circuit, said BIST circuit and said BIST controller, wherein said BIST controller incorporates elements of said off-chip circuit as modified.
47. A method of developing a production chip including an embedded circuit and a BIST circuit connected to said embedded circuit for performing a test on the embedded circuit, the method comprising the steps of:
producing a development chip including said embedded circuit and connections coupling the embedded circuit to contact points;
providing an off-chip circuit external to said development chip and coupled to said contact points;
modifying said off-chip circuit so that it performs said test on said embedded circuit; and
producing said production chip including said embedded circuit and said BIST circuit, wherein said BIST circuit incorporates elements of the off-chip circuit as modified.
48. A method of developing a production chip including an embedded circuit, a BIST controller, and a BIST circuit, said BIST circuit being connected to said embedded circuit and to said BIST controller for performing a test on the embedded circuit under control of said BIST controller, the method comprising the steps of:
producing a development chip including said embedded circuit, said BIST circuit connected to said embedded circuit, and connections coupling the BIST circuit to contact points;
providing an off-chip circuit external to said development chip and coupled to said contact points;
modifying said off-chip circuit so that it controls said BIST circuit in performing said test on said embedded circuit; and
producing said production chip including said embedded circuit, said BIST circuit and said BIST controller, wherein said BIST controller incorporates elements of said off-chip circuit as modified.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/401,899 US20030167427A1 (en) | 1999-10-18 | 2003-03-31 | Partitionable embedded circuit test system for integrated circuit |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16023399P | 1999-10-18 | 1999-10-18 | |
US09/494,824 US6587979B1 (en) | 1999-10-18 | 2000-01-31 | Partitionable embedded circuit test system for integrated circuit |
US10/401,899 US20030167427A1 (en) | 1999-10-18 | 2003-03-31 | Partitionable embedded circuit test system for integrated circuit |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/494,824 Division US6587979B1 (en) | 1999-10-18 | 2000-01-31 | Partitionable embedded circuit test system for integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
US20030167427A1 true US20030167427A1 (en) | 2003-09-04 |
Family
ID=26856713
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/494,824 Expired - Fee Related US6587979B1 (en) | 1999-10-18 | 2000-01-31 | Partitionable embedded circuit test system for integrated circuit |
US10/401,899 Abandoned US20030167427A1 (en) | 1999-10-18 | 2003-03-31 | Partitionable embedded circuit test system for integrated circuit |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/494,824 Expired - Fee Related US6587979B1 (en) | 1999-10-18 | 2000-01-31 | Partitionable embedded circuit test system for integrated circuit |
Country Status (1)
Country | Link |
---|---|
US (2) | US6587979B1 (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030200046A1 (en) * | 2001-10-30 | 2003-10-23 | Corr William E. | Apparatus and method for determining effect of on-chip noise on signal propagation |
US20050066226A1 (en) * | 2003-09-23 | 2005-03-24 | Adams R. Dean | Redundant memory self-test |
US20050223232A1 (en) * | 2004-04-06 | 2005-10-06 | Anderson Roy E | Provisioning and use of security tokens to enable automated test equipment |
US7203873B1 (en) * | 2004-06-04 | 2007-04-10 | Magma Design Automation, Inc. | Asynchronous control of memory self test |
US7260759B1 (en) * | 2004-06-16 | 2007-08-21 | Sun Microsystems, Inc. | Method and apparatus for an efficient memory built-in self test architecture for high performance microprocessors |
US20070255986A1 (en) * | 2004-12-29 | 2007-11-01 | Industrial Technology Research Institute | Wrapper testing circuits and method thereof for system-on-a-chip |
US20080016421A1 (en) * | 2006-07-13 | 2008-01-17 | International Business Machines Corporation | Method and apparatus for providing programmable control of built-in self test |
US20080222460A1 (en) * | 2007-03-08 | 2008-09-11 | Qimonda North America Corp. | Memory test circuit |
US20090164845A1 (en) * | 2006-06-16 | 2009-06-25 | Texas Instruments Incorporated | Device testing architecture, method and system |
US20090204861A1 (en) * | 2008-02-13 | 2009-08-13 | Cleavelin Cloves R | System and Method for Increasing the Extent of Built-In Self-Testing of Memory and Circuitry |
US9047252B1 (en) * | 2002-12-26 | 2015-06-02 | Marvell International Ltd. | Method and apparatus for detecting a row or a column of a memory to repair without reporting all corresponding defective memory cells |
US9755766B2 (en) * | 2015-12-07 | 2017-09-05 | Teradyne, Inc. | Front end module for automatic test equipment |
US10991445B2 (en) * | 2018-09-06 | 2021-04-27 | Micron Technology, Inc. | Memory sub-system including an in-package sequencer to perform error correction and memory testing operations |
Families Citing this family (59)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19917884C1 (en) * | 1999-04-20 | 2000-11-16 | Siemens Ag | Circuit with built-in self-test |
DE10034900C2 (en) * | 2000-07-18 | 2002-07-18 | Infineon Technologies Ag | System for testing fast synchronous digital circuits, especially semiconductor memory devices |
US6829728B2 (en) * | 2000-11-13 | 2004-12-07 | Wu-Tung Cheng | Full-speed BIST controller for testing embedded synchronous memories |
US20020093356A1 (en) * | 2000-11-30 | 2002-07-18 | Williams Thomas W. | Intelligent test vector formatting to reduce test vector size and allow encryption thereof for integrated circuit testing |
US6877122B2 (en) | 2001-12-21 | 2005-04-05 | Texas Instruments Incorporated | Link instruction register providing test control signals to core wrappers |
US6851079B1 (en) * | 2001-03-28 | 2005-02-01 | Lsi Logic Corporation | Jtag test access port controller used to control input/output pad functionality |
US7246277B2 (en) * | 2001-06-20 | 2007-07-17 | Jeffrey Lukanc | Test bus architecture for embedded RAM and method of operating same |
JP5050303B2 (en) * | 2001-06-29 | 2012-10-17 | 富士通セミコンダクター株式会社 | Semiconductor test equipment |
US6996760B2 (en) * | 2001-10-12 | 2006-02-07 | Sun Microsystems | ASIC BIST employing stored indications of completion |
US6901543B2 (en) * | 2001-10-12 | 2005-05-31 | Sun Microsystems, Inc. | Utilizing slow ASIC logic BIST to preserve timing integrity across timing domains |
US6981191B2 (en) * | 2001-10-12 | 2005-12-27 | Sun Microsystems, Inc. | ASIC logic BIST employing registers seeded with differing primitive polynomials |
US20030074619A1 (en) * | 2001-10-12 | 2003-04-17 | Dorsey Michael C. | Memory bist employing a memory bist signature |
US20030074618A1 (en) * | 2001-10-12 | 2003-04-17 | Dorsey Michael C. | Dual mode ASIC BIST controller |
US20030074620A1 (en) * | 2001-10-12 | 2003-04-17 | Dorsey Michael C. | Configurable asic memory bist controller employing multiple state machines |
US20030074616A1 (en) * | 2001-10-12 | 2003-04-17 | Dorsey Michael C. | ASIC BIST controller employing multiple clock domains |
US6941494B1 (en) * | 2001-12-21 | 2005-09-06 | Lsi Logic Corporation | Built-in test for multiple memory circuits |
KR100430074B1 (en) * | 2002-01-08 | 2004-05-03 | 학교법인 한양학원 | Wrapped core linking module for accessing system on chip test |
US20030172333A1 (en) * | 2002-03-08 | 2003-09-11 | Wehage Eric R. | Built-in self test parallel JTAG serial chain architecture for reduced test vector size |
TWI221202B (en) * | 2002-05-08 | 2004-09-21 | Via Tech Inc | Test platform device and test method for use with tested chip with embedded memory |
JP2003346500A (en) * | 2002-05-29 | 2003-12-05 | Hitachi Ltd | Semiconductor integrated circuit and its test method |
JP3484181B1 (en) * | 2002-09-02 | 2004-01-06 | 沖電気工業株式会社 | Semiconductor test circuit |
US6978411B2 (en) * | 2002-10-08 | 2005-12-20 | Faraday Technology Corp. | Memory test system for peak power reduction |
US7103814B2 (en) * | 2002-10-25 | 2006-09-05 | International Business Machines Corporation | Testing logic and embedded memory in parallel |
JP4274806B2 (en) * | 2003-01-28 | 2009-06-10 | 株式会社リコー | Semiconductor integrated circuit and scan test method |
US20040193979A1 (en) * | 2003-03-31 | 2004-09-30 | Koninklijke Philips Electronics N.V. | Circuit configurator arrangement and approach therefor |
US7219278B2 (en) * | 2003-03-31 | 2007-05-15 | Nxp B.V. | Configurator arrangement and approach therefor |
US7290186B1 (en) * | 2003-09-16 | 2007-10-30 | Virage Logic Corporation | Method and apparatus for a command based bist for testing memories |
US7681046B1 (en) | 2003-09-26 | 2010-03-16 | Andrew Morgan | System with secure cryptographic capabilities using a hardware specific digital secret |
JP4105077B2 (en) * | 2003-10-30 | 2008-06-18 | 株式会社東芝 | Semiconductor integrated circuit |
US7031866B1 (en) * | 2003-11-05 | 2006-04-18 | Virage Logic Corp. | System and method for testing a memory |
US7694151B1 (en) * | 2003-11-20 | 2010-04-06 | Johnson Richard C | Architecture, system, and method for operating on encrypted and/or hidden information |
US7308561B2 (en) * | 2003-12-12 | 2007-12-11 | Alcatel Lucent | Fast, scalable pattern-matching engine |
US7404128B2 (en) * | 2004-02-17 | 2008-07-22 | Texas Instruments Incorporated | Serial data I/O on JTAG TCK with TMS clocking |
JP4371856B2 (en) * | 2004-03-04 | 2009-11-25 | 株式会社東芝 | Safety protection instrumentation system and its handling method |
DE102004012279B3 (en) * | 2004-03-12 | 2005-06-09 | Infineon Technologies Ag | Self-testing method for memories embedded in semicomnductor chip using memory self-testing control with memory self-testing register for storing memory test configuration data |
US6972571B2 (en) * | 2004-03-22 | 2005-12-06 | Freescale Semiconductor, Inc. | Load board with embedded relay tracker |
US7362089B2 (en) * | 2004-05-21 | 2008-04-22 | Advantest Corporation | Carrier module for adapting non-standard instrument cards to test systems |
DE102004041657A1 (en) * | 2004-08-27 | 2006-03-09 | Infineon Technologies Ag | Circuit arrangement and method for operating such |
DE102004044813A1 (en) * | 2004-09-16 | 2006-03-23 | Robert Bosch Gmbh | Method for testing an integrated circuit |
JP4864306B2 (en) * | 2004-09-27 | 2012-02-01 | 富士通セミコンダクター株式会社 | Semiconductor device and test method thereof |
US8145958B2 (en) * | 2005-11-10 | 2012-03-27 | Arm Limited | Integrated circuit and method for testing memory on the integrated circuit |
US7224638B1 (en) | 2005-12-15 | 2007-05-29 | Sun Microsystems, Inc. | Reliability clock domain crossing |
US7627065B2 (en) * | 2005-12-21 | 2009-12-01 | Sun Microsystems, Inc. | Generating a clock crossing signal based on clock ratios |
ATE492885T1 (en) * | 2006-05-18 | 2011-01-15 | Dialog Semiconductor Gmbh | MEMORY TEST APPARATUS |
WO2008042248A2 (en) | 2006-09-29 | 2008-04-10 | Teradyne, Inc. | Method and apparatus for cooling non-native instrument in automatic test equipment |
US20080282120A1 (en) * | 2007-05-11 | 2008-11-13 | Macronix International Co., Ltd. | Memory structure, repair system and method for testing the same |
JP5095273B2 (en) * | 2007-06-22 | 2012-12-12 | 株式会社東芝 | Control device |
US7930162B1 (en) | 2008-05-05 | 2011-04-19 | Xilinx, Inc. | Accelerating hardware co-simulation using dynamic replay on first-in-first-out-driven command processor |
US8156391B2 (en) * | 2008-05-27 | 2012-04-10 | Lsi Corporation | Data controlling in the MBIST chain architecture |
US7847572B2 (en) * | 2008-06-01 | 2010-12-07 | Advantest Corporation | Test system, electronic device, and test apparatus |
US8046643B2 (en) * | 2008-06-09 | 2011-10-25 | Lsi Corporation | Transport subsystem for an MBIST chain architecture |
US7679391B2 (en) * | 2008-07-11 | 2010-03-16 | Advantest Corporation | Test equipment and semiconductor device |
US9003255B2 (en) | 2011-07-01 | 2015-04-07 | Stmicroelectronics International N.V. | Automatic test-pattern generation for memory-shadow-logic testing |
US9336342B2 (en) * | 2011-09-23 | 2016-05-10 | Synopsys, Inc. | Memory hard macro partition optimization for testing embedded memories |
US9304968B2 (en) * | 2012-07-18 | 2016-04-05 | Micron Technology, Inc. | Methods and devices for programming a state machine engine |
US9052900B2 (en) | 2013-01-29 | 2015-06-09 | Oracle International Corporation | Serdes fast retrain method upon exiting power saving mode |
GB2542214B (en) * | 2015-11-11 | 2019-08-28 | Imagination Tech Ltd | Hardware monitor to verify memory units |
US10866283B2 (en) * | 2018-11-29 | 2020-12-15 | Nxp B.V. | Test system with embedded tester |
US20220206068A1 (en) * | 2020-12-31 | 2022-06-30 | Deepx Co., Ltd. | System capable of detecting failure of component of system and method thereof |
Citations (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4873705A (en) * | 1988-01-27 | 1989-10-10 | John Fluke Mfg. Co., Inc. | Method of and system for high-speed, high-accuracy functional testing of memories in microprocessor-based units |
US5271019A (en) * | 1991-03-15 | 1993-12-14 | Amdahl Corporation | Scannable system with addressable scan reset groups |
US5375091A (en) * | 1993-12-08 | 1994-12-20 | International Business Machines Corporation | Method and apparatus for memory dynamic burn-in and test |
US5471482A (en) * | 1994-04-05 | 1995-11-28 | Unisys Corporation | VLSI embedded RAM test |
US5473616A (en) * | 1992-03-31 | 1995-12-05 | Ando Electric Co., Ltd. | Address pattern generator |
US5506499A (en) * | 1995-06-05 | 1996-04-09 | Neomagic Corp. | Multiple probing of an auxilary test pad which allows for reliable bonding to a primary bonding pad |
US5535164A (en) * | 1995-03-03 | 1996-07-09 | International Business Machines Corporation | BIST tester for multiple memories |
US5572712A (en) * | 1994-09-30 | 1996-11-05 | Vlsi Technology, Inc. | Method and apparatus for making integrated circuits with built-in self-test |
US5592616A (en) * | 1995-06-07 | 1997-01-07 | Dell Usa, Lp | Method for performing efficient memory testing on large memory arrays using test code executed from cache memory |
US5708773A (en) * | 1995-07-20 | 1998-01-13 | Unisys Corporation | JTAG interface system for communicating with compliant and non-compliant JTAG devices |
USH1741H (en) * | 1994-12-05 | 1998-07-07 | Tandem Computers Corporation | Method and apparatus for pattern sensitivity stress testing of memory systems |
US5854796A (en) * | 1996-05-29 | 1998-12-29 | Advantest Corporation | Method of and apparatus for testing semiconductor memory |
US6029262A (en) * | 1997-11-25 | 2000-02-22 | Mosaid Technologies Incorporated | Graphical editor for defining memory test sequences |
US6065141A (en) * | 1992-07-27 | 2000-05-16 | Fujitsu Limited | Self-diagnosable semiconductor memory device having a redundant circuit and semiconductor apparatus having the same in which the memory device cannot be accessed from outside the semiconductor apparatus |
US6067262A (en) * | 1998-12-11 | 2000-05-23 | Lsi Logic Corporation | Redundancy analysis for embedded memories with built-in self test and built-in self repair |
US6072737A (en) * | 1998-08-06 | 2000-06-06 | Micron Technology, Inc. | Method and apparatus for testing embedded DRAM |
US6085334A (en) * | 1998-04-17 | 2000-07-04 | Motorola, Inc. | Method and apparatus for testing an integrated memory device |
US6088823A (en) * | 1998-06-12 | 2000-07-11 | Synopsys, Inc. | Circuit for efficiently testing memory and shadow logic of a semiconductor integrated circuit |
US6182257B1 (en) * | 1997-07-31 | 2001-01-30 | Mosaid Technologies Incorporated | BIST memory test system |
US6286115B1 (en) * | 1998-06-29 | 2001-09-04 | Micron Technology, Inc. | On-chip testing circuit and method for integrated circuits |
US6304989B1 (en) * | 1999-07-21 | 2001-10-16 | Credence Systems Corporation | Built-in spare row and column replacement analysis system for embedded memories |
US6311299B1 (en) * | 1999-03-01 | 2001-10-30 | Micron Technology, Inc. | Data compression circuit and method for testing embedded memory devices |
US6317846B1 (en) * | 1998-10-13 | 2001-11-13 | Agere Systems Guardian Corp. | System and method for detecting faults in computer memories using a look up table |
US6367042B1 (en) * | 1998-12-11 | 2002-04-02 | Lsi Logic Corporation | Testing methodology for embedded memories using built-in self repair and identification circuitry |
US6374377B1 (en) * | 1998-12-14 | 2002-04-16 | Intel Corporation | Low yield analysis of embedded memory |
-
2000
- 2000-01-31 US US09/494,824 patent/US6587979B1/en not_active Expired - Fee Related
-
2003
- 2003-03-31 US US10/401,899 patent/US20030167427A1/en not_active Abandoned
Patent Citations (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4873705A (en) * | 1988-01-27 | 1989-10-10 | John Fluke Mfg. Co., Inc. | Method of and system for high-speed, high-accuracy functional testing of memories in microprocessor-based units |
US5271019A (en) * | 1991-03-15 | 1993-12-14 | Amdahl Corporation | Scannable system with addressable scan reset groups |
US5473616A (en) * | 1992-03-31 | 1995-12-05 | Ando Electric Co., Ltd. | Address pattern generator |
US6065141A (en) * | 1992-07-27 | 2000-05-16 | Fujitsu Limited | Self-diagnosable semiconductor memory device having a redundant circuit and semiconductor apparatus having the same in which the memory device cannot be accessed from outside the semiconductor apparatus |
US5375091A (en) * | 1993-12-08 | 1994-12-20 | International Business Machines Corporation | Method and apparatus for memory dynamic burn-in and test |
US5471482A (en) * | 1994-04-05 | 1995-11-28 | Unisys Corporation | VLSI embedded RAM test |
US5572712A (en) * | 1994-09-30 | 1996-11-05 | Vlsi Technology, Inc. | Method and apparatus for making integrated circuits with built-in self-test |
USH1741H (en) * | 1994-12-05 | 1998-07-07 | Tandem Computers Corporation | Method and apparatus for pattern sensitivity stress testing of memory systems |
US5535164A (en) * | 1995-03-03 | 1996-07-09 | International Business Machines Corporation | BIST tester for multiple memories |
US5506499A (en) * | 1995-06-05 | 1996-04-09 | Neomagic Corp. | Multiple probing of an auxilary test pad which allows for reliable bonding to a primary bonding pad |
US5592616A (en) * | 1995-06-07 | 1997-01-07 | Dell Usa, Lp | Method for performing efficient memory testing on large memory arrays using test code executed from cache memory |
US5708773A (en) * | 1995-07-20 | 1998-01-13 | Unisys Corporation | JTAG interface system for communicating with compliant and non-compliant JTAG devices |
US5854796A (en) * | 1996-05-29 | 1998-12-29 | Advantest Corporation | Method of and apparatus for testing semiconductor memory |
US6182257B1 (en) * | 1997-07-31 | 2001-01-30 | Mosaid Technologies Incorporated | BIST memory test system |
US6029262A (en) * | 1997-11-25 | 2000-02-22 | Mosaid Technologies Incorporated | Graphical editor for defining memory test sequences |
US6085334A (en) * | 1998-04-17 | 2000-07-04 | Motorola, Inc. | Method and apparatus for testing an integrated memory device |
US6088823A (en) * | 1998-06-12 | 2000-07-11 | Synopsys, Inc. | Circuit for efficiently testing memory and shadow logic of a semiconductor integrated circuit |
US6286115B1 (en) * | 1998-06-29 | 2001-09-04 | Micron Technology, Inc. | On-chip testing circuit and method for integrated circuits |
US6072737A (en) * | 1998-08-06 | 2000-06-06 | Micron Technology, Inc. | Method and apparatus for testing embedded DRAM |
US6317846B1 (en) * | 1998-10-13 | 2001-11-13 | Agere Systems Guardian Corp. | System and method for detecting faults in computer memories using a look up table |
US6067262A (en) * | 1998-12-11 | 2000-05-23 | Lsi Logic Corporation | Redundancy analysis for embedded memories with built-in self test and built-in self repair |
US6367042B1 (en) * | 1998-12-11 | 2002-04-02 | Lsi Logic Corporation | Testing methodology for embedded memories using built-in self repair and identification circuitry |
US6374377B1 (en) * | 1998-12-14 | 2002-04-16 | Intel Corporation | Low yield analysis of embedded memory |
US6311299B1 (en) * | 1999-03-01 | 2001-10-30 | Micron Technology, Inc. | Data compression circuit and method for testing embedded memory devices |
US6304989B1 (en) * | 1999-07-21 | 2001-10-16 | Credence Systems Corporation | Built-in spare row and column replacement analysis system for embedded memories |
Cited By (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6785626B2 (en) * | 2001-10-30 | 2004-08-31 | Micron Technology, Inc. | Apparatus and method for determining effect of on-chip noise on signal propagation |
US20030200046A1 (en) * | 2001-10-30 | 2003-10-23 | Corr William E. | Apparatus and method for determining effect of on-chip noise on signal propagation |
US9047252B1 (en) * | 2002-12-26 | 2015-06-02 | Marvell International Ltd. | Method and apparatus for detecting a row or a column of a memory to repair without reporting all corresponding defective memory cells |
US20050066226A1 (en) * | 2003-09-23 | 2005-03-24 | Adams R. Dean | Redundant memory self-test |
US7519827B2 (en) * | 2004-04-06 | 2009-04-14 | Verigy (Singapore) Pte. Ltd. | Provisioning and use of security tokens to enable automated test equipment |
US20050223232A1 (en) * | 2004-04-06 | 2005-10-06 | Anderson Roy E | Provisioning and use of security tokens to enable automated test equipment |
US7203873B1 (en) * | 2004-06-04 | 2007-04-10 | Magma Design Automation, Inc. | Asynchronous control of memory self test |
US7260759B1 (en) * | 2004-06-16 | 2007-08-21 | Sun Microsystems, Inc. | Method and apparatus for an efficient memory built-in self test architecture for high performance microprocessors |
US20070255986A1 (en) * | 2004-12-29 | 2007-11-01 | Industrial Technology Research Institute | Wrapper testing circuits and method thereof for system-on-a-chip |
US7506231B2 (en) * | 2004-12-29 | 2009-03-17 | Industrial Technology Research Institute | Wrapper testing circuits and method thereof for system-on-a-chip |
US7788559B2 (en) * | 2006-06-16 | 2010-08-31 | Texas Instruments Incorporated | Test access mechanisms, associated controllers and a selector |
US8984357B2 (en) * | 2006-06-16 | 2015-03-17 | Texas Instruments Incorporated | Wrapper selector data register having control outputs and SELECTAM input |
US11846673B2 (en) | 2006-06-16 | 2023-12-19 | Texas Instruments Incorporated | Device testing architecture, method, and system |
US11609269B2 (en) | 2006-06-16 | 2023-03-21 | Texas Instruments Incorporated | Device testing architecture of an integrated circuit |
US10024918B2 (en) | 2006-06-16 | 2018-07-17 | Texas Instruments Incorporated | Cores, TAMS, TAM controllers, TAM selector, and scan router circuitry |
US11125818B2 (en) | 2006-06-16 | 2021-09-21 | Texas Instruments Incorporated | Test access mechanism controller including instruction register, instruction decode circuitry |
US20090164845A1 (en) * | 2006-06-16 | 2009-06-25 | Texas Instruments Incorporated | Device testing architecture, method and system |
US20100313087A1 (en) * | 2006-06-16 | 2010-12-09 | Texas Instruments Incorporated | Device testing architecture, method and system |
US7954026B2 (en) * | 2006-06-16 | 2011-05-31 | Texas Instruments Incorporated | TAM controller connected with TAM and functional core wrapper circuit |
US20130227364A1 (en) * | 2006-06-16 | 2013-08-29 | Texas Instruments Incorporated | Device testing architecture, method, and system |
US10281526B2 (en) | 2006-06-16 | 2019-05-07 | Texas Instruments Incorporated | Device testing architecture, method, and system |
US10605865B2 (en) | 2006-06-16 | 2020-03-31 | Texas Instruments Incorporated | IC taps with control register and scan router coupling taps |
US20080016421A1 (en) * | 2006-07-13 | 2008-01-17 | International Business Machines Corporation | Method and apparatus for providing programmable control of built-in self test |
US20080222460A1 (en) * | 2007-03-08 | 2008-09-11 | Qimonda North America Corp. | Memory test circuit |
US20100229056A1 (en) * | 2008-02-13 | 2010-09-09 | Texas Instruments Incorporated | System and Method for Increasing the Extent of Built-In Self-Testing of Memory and Circuitry |
US7793186B1 (en) | 2008-02-13 | 2010-09-07 | Texas Instruments Incorporated | System and method for increasing the extent of built-in self-testing of memory and circuitry |
US7752518B2 (en) * | 2008-02-13 | 2010-07-06 | Texas Instruments Incorporated | System and method for increasing the extent of built-in self-testing of memory and circuitry |
US20090204861A1 (en) * | 2008-02-13 | 2009-08-13 | Cleavelin Cloves R | System and Method for Increasing the Extent of Built-In Self-Testing of Memory and Circuitry |
US9755766B2 (en) * | 2015-12-07 | 2017-09-05 | Teradyne, Inc. | Front end module for automatic test equipment |
US10991445B2 (en) * | 2018-09-06 | 2021-04-27 | Micron Technology, Inc. | Memory sub-system including an in-package sequencer to perform error correction and memory testing operations |
US11869618B2 (en) | 2018-09-06 | 2024-01-09 | Micron Technology, Inc. | Memory sub-system including an in-package sequencer to perform error correction and memory testing operations |
Also Published As
Publication number | Publication date |
---|---|
US6587979B1 (en) | 2003-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6587979B1 (en) | Partitionable embedded circuit test system for integrated circuit | |
US7353442B2 (en) | On-chip and at-speed tester for testing and characterization of different types of memories | |
US5173904A (en) | Logic circuits systems, and methods having individually testable logic modules | |
US6668347B1 (en) | Built-in self-testing for embedded memory | |
US4860290A (en) | Logic circuit having individually testable logic modules | |
US5568437A (en) | Built-in self test for integrated circuits having read/write memory | |
US7284166B2 (en) | Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays | |
US6665817B1 (en) | Apparatus and method for implementing a wireless system-on-a-chip with a reprogrammable tester, debugger, and bus monitor | |
US8145958B2 (en) | Integrated circuit and method for testing memory on the integrated circuit | |
KR100267432B1 (en) | Processor based bist for an embedded memory | |
JP4515545B2 (en) | Memory interface device and method for supporting debugging | |
US6745359B2 (en) | Method of masking corrupt bits during signature analysis and circuit for use therewith | |
US5271019A (en) | Scannable system with addressable scan reset groups | |
US20030167426A1 (en) | Method and apparatus for memory self testing | |
US20020071325A1 (en) | Built-in self-test arrangement for integrated circuit memory devices | |
US7269766B2 (en) | Method and apparatus for memory self testing | |
US20040199843A1 (en) | Tiered built-in self-test (BIST) architecture for testing distributed memory modules | |
JP2008310955A (en) | Method for preventing consumption of time to program address in defective column | |
US7752512B2 (en) | Semiconductor integrated circuit | |
CN106291313B (en) | Method and apparatus for testing integrated circuits | |
JP3597972B2 (en) | Programmable logic device, test method therefor, and test data creation method | |
US6060897A (en) | Testability method for modularized integrated circuits | |
JP3298955B2 (en) | Semiconductor device | |
US5978945A (en) | Tester arrangement comprising a connection module for testing, by way of the boundary scan test method, a carrier provided with a first number of digital ICS with BST logic and a second number of digital ICS without BST logic | |
US20100115353A1 (en) | System and method for testing application-specific blocks embedded in reconfigurable arrays |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |