US20030172101A1 - Processing multiply-accumulate operations in a single cycle - Google Patents
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Abstract
A multiply-accumulate unit, or MAC, may achieve high throughput. The MAC need not use redundant hardware, such as multiple Wallace trees, or pipelining logic, yet may perform Wallace tree and carry look-ahead adder functions simultaneously for different operations.
Description
- This invention relates to processor-based systems and, more particularly, to multiply-accumulate units.
- A multiply-accumulate unit, or MAC, is a unit designed to perform multiplication operations. In a processor-based system, for example, such operations may be plentiful.
- MACs may be implemented using a variety of logic. Because of the abundance of multiplication operations in some applications, the fastest performing MAC is generally preferred. The success of any MAC design may depend upon the power requirements, the available space which may be allocated to MAC circuitry, and the intended use for the MAC, among other considerations.
- Usually, however, a tradeoff between speed and cost makes the design of an optimally performing MAC difficult. The cost may come in the form of additional hardware, the chip space necessary to accommodate that hardware, or in the power needed to drive the hardware.
- For example, in many digital signal processing, or DSP, applications, some critical operations may involve a series of multiplications and or accumulations. Accordingly, a high-throughput MAC is essential to achieving high performance. However, many DSP applications today require low power consumption, particularly in the portable electronics market.
- Thus, there is a continuing need for a MAC which may achieve high throughput without excessively consuming power.
- In one embodiment of the invention, a method includes receiving a first set of operands in a first portion of a unit, performing a plurality of operations on the first set of operands to arrive at a first intermediate result and receiving a second set of operands in the first portion of the unit. Following these, a second plurality of operations is performed on the first intermediate result to arrive at a first final result while the first plurality of operations is performed on the second set of operands to arrive at a second intermediate result.
- Advantages and other features of the invention will become apparent from the following description, the drawings, and the claims.
- FIG. 1 is a block diagram of a multiply accumulate unit according to one embodiment of the invention;
- FIGS. 2A and 2B are flow diagrams of a multiply operation performed using the MAC of FIG. 1 according to one embodiment of the invention;
- FIG. 3 is a chart of the performance time for 16-bit multiplication operations using the MAC of FIG. 1 according to one embodiment of the invention;
- FIGS.4A-4C are flow diagrams of an implicit multiply operation performed using the MAC of FIG. 1 according to one embodiment of the invention; and
- FIG. 5 is a flow diagram of a multiply operation using packed data instructions performed using the MAC of FIG. 1 according to one embodiment of the invention.
- At the most basic level, a MAC may receive two integer values, multiply the values together and send out the result of the operation. For some applications, an additional constant value, an accumulate value, may be added to the result. So, the MAC may produce a result, d, from the multiplication of a multiplicand, a, and a multiplier, b, plus the accumulation of c, as shown in the following equation:
- d=(a×b)+c
- Multiplication operations may essentially be performed as a series of additions of partial products. To achieve optimum performance, MACs may include features which perform addition operations more quickly or which reduce the number of necessary addition operations.
- For example, a MAC typically includes a Booth encoder, also called a Booth recoder or Booth multiplier. A Booth encoder may reduce the number of stages used to perform the multiplication. The number of partial products that are added together thus may be reduced. For example, for a 16-bit word, the number of partial products may be reduced from sixteen to eight, a factor of two.
- Another feature which may be found in a MAC is known as a Wallace tree. Wallace trees are structures for performing multiple addition operations. Wallace trees typically include features, such as adders, to help perform the addition of multiple partial products.
- For example, a Wallace tree may include a group of carry-save adders. A 3-to-2 carry-save adder, for example, receives three inputs, a, b, and c, and produces two outputs, a sum, y, and a carry, z, as illustrated by the following equation:
- a+b+c=y+z*2
- The output carry is “saved” for the next operation, thus, the name.
- Wallace trees may organize carry-save adders or similar logic such that a number of input values typically produces two results, a sum value and a carry value. For example, a four-stage Wallace tree may include four stages of 3-to-2 carry-save adders. The four-stage Wallace tree may receive nine input vectors, and produce a sum vector and a carry vector as its result.
- Another feature of many MAC designs is logic for adding all the bits of two vectors, to produce a final result, for example. A carry look-ahead adder, or CLA, is one such logic device. The CLA may efficiently perform the addition of two multi-bit operands.
- Especially for digital signal processing and other applications, the ability of the MAC to multiply 16-bit signed integers at a very fast rate is a paramount concern. To speed up the multiplication of 16-bit and even larger integer operations, the MAC could include additional circuitry. For example, each component of the MAC could be duplicated, such that multiple operations run simultaneously. Control logic to keep track of the parallel operations would be part of the MAC as well. However, the additional hardware may be costly, the available space may be limited, and additional power to support the new hardware may be used.
- Another MAC design may pipeline the operations, such that a new multiply operation may be processed while a prior operation is not yet completed by the MAC hardware, somewhere down the pipeline. Pipelining may involve a number of stages of the operation being performed, each stage operating independently from the others. Pipelining may thus utilize additional control logic and hardware, such as registers, for temporarily storing the state of the two, three, or more, independent operations being conducted simultaneously by the MAC hardware. Although less costly than providing parallel hardware, the additional control logic may add to development cost and diminish available board or chip space. Further, a MAC which supports pipelining may run more slowly.
- A higher throughput MAC may be implemented using conventional architectural features, without excessively impacting the cost or power requirements of the hardware. In some embodiments of the invention, a MAC design provides a single-cycle throughput for 16-bit multiplication operations by simultaneously operating two functional units of the MAC.
- In FIG. 1, a
MAC 100 includes aBooth encoder 10, a multiplexer, or MUX,array 14, aWallace tree 20, and a carry look-ahead adder, or CLA, 30, according to one embodiment of the invention. TheMAC 100 may receive two input values, a multiplicand, A, and a multiplier, B, as well as an accumulate data value, C. The input values A, B, and C may be 16-bit, 32-bit, or larger signed integer values, for example. - In one embodiment of the invention, the Booth encoder receives up to sixteen bits of the multiplier, B, at a time, and thus produces up to eight
control signals 12 a-12 h. TheMUX array 14 receives the eightcontrol signals 12 a 12 h from theBooth encoder 10 as well as receiving the multiplicand, A. TheMUX array 14 produces up to eight partial products, 16 a-16 h, which are then sent to theWallace tree 20. - In one embodiment of the invention, the
Wallace tree 20 is a four-stage unit, including a plurality of carry-save adders (not shown). TheWallace tree 20 thus receives nine input signals and produces two output signals, asum vector 22 a and acarry vector 22 b. Thesum vector 22 a and thecarry vector 22 b may subsequently be fed into theCLA 30, to be added together. Alternatively or simultaneously, thesum vector 22 a and thecarry vector 22 b may be routed back to theMUX array 14, for further processing. - The
MAC 100 includes three banks of flip-flops 6 a-6 c. The flip-flops 6 enable portions of the multiplicand A, the multiplier B, and the accumulate data C to be sent to the other logic of theMAC 100 for processing. For example, if a 32-bit multiplier, B[31:0], is sent to theMAC 100 as part of a multiplication operation, the flip-flops 6 b may toggle between two 16-bit portions, B[31:16] or B[15:0], controlling which portion of the multiplier B is sent to theBooth encoder 10. - The
MAC 100 also includesMUXs 8 a-8 e. TheMUXs 8 may control the receipt of a signal by a subsequent unit of theMAC 100. For example, theMUXs 8 a-8 c work in conjunction with the flip-flops 6 a-6 c to control which portion of the multiplicand A, the multiplier B, or the accumulator C may be received by theMUX array 14, theBooth encoder 10, or theWallace tree 20, respectively. TheMUXs 8 d control receipt of thesum vector 22 a and thecarry vector 22 b by theCLA 30. TheMUXs 8 e enable theoutput value 34 from theCLA 30 to be sign-extended, if needed. - The
MAC 100 includes two banks of MUXs and flip-flops units Wallace tree 20. The MUXs and flip-flops unit 24 a is used to feed part of thesum vector 22 a and thecarry vector 22 b back to theMUX array 14. Theportion 26 a fed back to theMUX array 14 depends upon the type of operation being performed. Such feedback is a feature common to multi-stage MAC operations, such as for performing a 32-bit multiplication. - The
MAC 100 includes a second MUXs and flip-flops unit 24 b, to which thesum vector 22 a and thecarry vector 22 b are also sent. Subsequently, these values may be sent to theCLA 30 via theMUXs 8 d. In one embodiment of the invention, thesum vector 22 a and thecarry vector 22 b are sent to bothunits - In some embodiments of the invention, the
MAC 100 includes architectural enhancements which may improve throughput for multiplication operations. For example, in one embodiment of the invention, theMAC 100 includes two registers, anaccumulator A 32 a and anaccumulator B 32 b. Theaccumulators 32 may receive theresult vector 34 from theCLA 30. In one embodiment of the invention, theresult vector 34 is alternatively stored in theaccumulators 32. For example, in a first operation, the result vector, which may be an intermediate result, is stored in theaccumulator A 32 a. In a subsequent operation, the subsequent result vector is stored in theaccumulator B 32 b. - The
accumulators 32 are each connected to theMUXs 8 c, for submission to theWallace tree 20. The configuration allows the values stored in eitheraccumulator 32 to be submitted to theWallace tree 20 as the accumulate data instead of receiving the accumulated data from a source (C) external to theMAC 100. As will be shown below, theaccumulators 32 may facilitate the throughput of operations performed in theMAC 100 in one embodiment of the invention. - The
MAC 100 may support implicit instructions such as an implicit multiply instruction. An implicit instruction is one where one or more intermediate results may be stored internally to the MAC, such as in a register. Including a register in the MAC circuitry may allow the MAC to avoid sending intermediate results to a storage location outside the MAC over an external bus, for example. Thus, a MAC which supports implicit operations may process instructions more quickly than a MAC with no such support. - For many multiplication operations, the MAC circuitry may provide multiple intermediate results before arriving at the final result. The conventional MAC design typically receives an intermediate result, an intermediate sum vector and an intermediate carry vector, from the Wallace tree and feeds the results back into the MUX array for subsequent processing. This scheme is repeated as necessary. Eventually, the sum vector and the carry vector produced by the Wallace tree represent the final result. These values are subsequently sent to the CLA, where they are added together and sent out of the MAC circuitry as the final result.
- In the embodiment of FIG. 1, the
intermediate sum vector 22 a and theintermediate carry vector 22 b may be sent to theCLA 30 in each cycle, if desired. TheCLA 30 may then add theintermediate sum vector 22 a and theintermediate carry vector 22 b, to produce anintermediate result 34, which may then be stored in one of theaccumulators 32. - Feedback logic in the
MAC 100 design permits theintermediate result 34 to be fed from one of theaccumulators 32 back into theWallace tree 20, via theMUXs 8 c, as accumulatedata 18. Recall that theWallace tree 20 includes aninput line 18 for the accumulator C. In FIG. 1, theMUXs 8 c permit the source of the accumulatedata 18 to include theaccumulators 32. - In one embodiment of the invention, the
MAC 100 provides circuitry which allows simultaneous operation of both theWallace tree 20 and theCLA 30. This circuitry includesearly termination logic 50 andMAC control logic 52, in one embodiment of the invention. This circuitry may control the simultaneous processing of more than one multiplication operation or of more than one portion of a single multiplication operation by theMAC 100. - In a typical implementation, a MAC may receive signed binary values as operands. For example, a two's complement notation may be used. In two's complement notation, the most significant bit of the value may represent the sign: zero for positive values, one for negative values. Accordingly, in two's complement notation, the 16-bit operand 0FFC1h may represent −63d and the operand 003Fh may represent +63d.
- Additionally, 16-bit values may be represented as 32-bit values, for some applications. The sign bit (bit fifteen) may thus be “extended” or duplicated in the upper sixteen bits. The sign-extended operand 0FFFFFFC1h may thus again represent −63d while the operand 0000003Fh may represent +63d. The upper seventeen bits of both operands are identical, as the sign bit (bit fifteen) is extended. Likewise, for either value, the upper sixteen bits are not needed to perform a multiplication operation.
- In one embodiment of the invention, the
early termination logic 50 uses this feature of signed binary values to the advantage of theMAC 100. In FIG. 1, theearly termination logic 50 receives a signal from the multiplier B. Theearly termination logic 50 may be invoked when the upper seventeen bits of a 32-bit multiplier B are identical. In such a case, the upper sixteen bits of the multiplier B are not used in the multiplication operation. - Once invoked, the
early termination logic 50 sends a signal to theMAC control logic 52. TheMAC control logic 52 controls the flip-flops 6, theMUXs 8, and the MUXs and flip-flops 24, as well as theaccumulators 32. TheMAC control logic 52 thus may enable the next multiplicand A to be latched by the flip-flops 6 a and theMUXs 8 a, the next multiplier B to be latched by the flip-flops 6 b and theMUXs 8 b, or the next accumulate data C to be latched by the flip-flops 6 c and theMUXs 8 c. - Additionally, the
MAC control logic 52 may control the routing of theintermediate sum vector 22 a and theintermediate carry vector 22 b, received from theWallace tree 30. TheMAC control logic 52 may enable the MUXs and flip-flops 24 a, the MUXs and flip-flops 24 b, and theMUXs 8 d, as needed. - The
MAC control logic 52 further controls theaccumulator A register 32 a and theaccumulator B register 32 b, permitting the values contained therein to be routed back to theWallace tree 20 as accumulateinput 18. Finally, theMAC control logic 52 may control theMUXs 8 e such that thefinal output vector 34 may be sign-extended, if desired, and produce theoutput value 40. - In one embodiment of the invention, the
MAC control unit 52 may receive control signals from a source external to theMAC 100, such as an instruction decoder (not shown). TheMAC control unit 52 may also submit control signals to another source external to theMAC 100. - Depending upon the operation being performed, the
MAC 100 may produce intermediate vector values. For example, in one embodiment of the invention, theBooth encoder 10 receives a 16-bit value from the multiplier, B. Accordingly, to multiply two 32-bit numbers, or a 16-bit multiplicand and a 32-bit multiplier, theBooth encoder 10 may receive the lower sixteen bits of the multiplier in a first cycle and then receive the upper sixteen bits of the multiplier in a second cycle. Likewise, the other circuitry of theMAC 100 may receive data in both a first and a second cycle. The multiplication operation thus takes, at a minimum, two cycles to complete. - For some operations, the
MAC 100 may achieve single-cycle throughput. In one embodiment of the invention, theMAC 100 achieves single-cycle throughput in performing 16-bit multiplication operations. Following receipt of the first set of operands into theMAC 100, theWallace tree 66 and the CLA 68 may simultaneously process all subsequent operands. For example, theWallace tree 66 may be processing data for cycle n, while, at the same time, the CLA 68 is processing data for cycle n-1. - In FIG. 2A, a flow diagram illustrates how the
MAC 100 logic processes a multiply or multiply/accumulate operation. In this example, two 16-bit operands are sign-extended as 32-bit values. Such operands are common in DSP applications and may particularly illustrate performance of theearly termination logic 50 in theMAC 100. TheMAC 100, however, may perform multiply or multiply/accumulate operations on operands with other characteristics. - A first cycle,
cycle 0, begins (block 200). In one embodiment of the invention, the lower sixteen bits of the multiplier B[15:0] are sent to the Booth encoder 10 (block 202). TheMUX array 14 receives eightcontrol signals 12 from theBooth encoder 10 as well as the multiplicand A[31:0] (block 204). TheMUX array 14 processes these signals such that theWallace tree 20 receives eightpartial product vectors 16 from theMUX array 14. Additionally, theWallace tree 20 receives accumulate data C[31:0] (block 206). From this data, theWallace tree 20 produces an intermediate sum vector (ISV) 22 a and an intermediate carry vector (ICV) 22 b (block 208). Theintermediate sum vector 22 a and theintermediate carry vector 22 b are sent to the MUXs and flip-flops - Independently from the preceding operations, at the beginning of cycle0 (block 200), the
early termination logic 50 may receive the 32-bit multiplier B[31:0] (block 212). Because the operands are sign-extended 16-bit values, the upper seventeen bits of the multiplier B are identical. Accordingly, theearly termination logic 50 sends a signal to the MAC control logic 52 (block 214). TheMAC control logic 52 then sends a signal to latch the flip-flops MUXs MAC control logic 52 enables the circuitry to latch the next MAC operands A, B and C. - In FIG. 2B, the second cycle, cycle one, is a continuation of the operations of FIG. 2A. After cycle one begins (block230), the
MAC control logic 52 sends a signal to theMUXs 8 d to release theintermediate sum vector 22 a and theintermediate carry vector 22 b (block 232). Theintermediate sum vector 22 a and theintermediate carry vector 22 b are sent to the CLA 30 (block 234). Accordingly, theCLA 30 adds theintermediate sum vector 22 a and theintermediate carry vector 22 b together (block 236). Theresult 40 is then sent out of the MAC 100 (block 238). Thus, cycle one is completed. - In FIG. 3, the single-cycle throughput of 16-bit multiplication operations using the
MAC 100 according to one embodiment of the invention may be demonstrated using a chart. At the top of the chart, a numbered series of 16-bit multiplication operations performed by theMAC 100 is depicted. On the left side of the chart, the cycle in which an operation was performed is specified. The chart tracks operations performed by theWallace tree 20, indicated as “W”, and theCLA 30, indicated as “C” according to one embodiment of the invention. - For the first 16-bit multiplication operation, the
Wallace tree 20 is executed in cycle zero while theCLA 30 is executed in cycle one. For the second 16-bit multiplication operation, theWallace tree 20 is executed in cycle one and theCLA 30 is executed in cycle two. The execution of theCLA 30 for the first multiplication operation occurs simultaneously with the execution of theWallace tree 20 for the second 16-bit multiplication operation. As the chart demonstrates, the subsequent 16-bit multiplication operations proceed like the two already described. At the end of the fifteenth cycle, fifteen 16-bit multiplication operations have been completed. For some multiplication operations according to one embodiment of the invention, theMAC 100 thus provides a single-cycle throughput. - The
accumulators 32 allow theMAC 100 to perform implicit multiply and multiply/accumulate operations. In a second embodiment, theMAC 100 may include a single accumulator. Theaccumulators 32 may be implicitly referenced by several implicit instructions. Those implicit multiply/accumulate instructions reference theaccumulators 32 instead of a register-specified accumulator. - For example, the instructions in one embodiment of the invention, MAR or MRA may be received by the
MAC control logic 52 in order for theaccumulators 32 to be read from or written to, respectively. In FIG. 4A, a flow diagram illustrates the implicit multiply/accumulate operation in which early termination is invoked. Recall that, in order for early termination to be invoked, the other seventeen bits of the multiplier B are all zeros or all ones. - When cycle zero begins (block300), the multiplier B[15:0] is sent to the Booth encoder 10 (block 302). The
MUX array 14 then receives eightcontrol signals 12 from theBooth encoder 10 as well as the multiplicand A[31:0] (block 304). - The
Wallace tree 20 receives eight partial product vectors from theMUX array 14. Additionally, theWallace tree 20 receives an accumulate value from eitheraccumulator A 32 a oraccumulator B 32 b (block 306). TheWallace tree 20 subsequently produces anintermediate sum vector 22 a and anintermediate carry vector 22 b (block 308). - In one embodiment of the invention, the carry look-
ahead adder 30 is a 40-bit CLA, which may perform 16-bit DSP operations. Likewise, theaccumulator A register 32 a and theaccumulator B register 32 b are 40-bit registers. Thus, in the next operation, the lower 40 bits of theintermediate sum vector 22 a and theintermediate carry vector 22 b are sent to the MUXs and flip-flops - Also at the beginning of cycle zero, the entire 32-bit multiplier B is sent to the early termination logic (ETL)50 (block 312). Because the upper seventeen bits of the multiplier B are identical, the
early termination logic 50 sends a signal to the MAC control logic 52 (block 314). TheMAC control logic 52 then sends a signal to latch the flip-flops MUXs Wallace tree 20 will be available to accept the next implicit multiply/accumulate instruction in the next cycle (block 318). - In FIG. 4B,
cycle 1 begins (block 330). TheMAC control logic 52 sends a signal to theMUXs 8 d to release theintermediate sum vector 22 a and theintermediate carry vector 22 b (block 332). TheCLA 30 then adds the two values 22 together to produce an intermediate result 34 (block 334). Because this is an implicit instruction, theresult 34 is next stored in eitheraccumulator A 32 a oraccumulator B 32 b (block 336). This completes the end of cycle one (block 338). - In one embodiment of the invention, the
MAC 100 may receive implicit instructions which reference the accumulators. These instructions may be received from theMAC control logic 52, which ultimately controls theaccumulator A 32 a and theaccumulator B 32 b. - For example, in FIG. 4C, the
MAC control logic 52 may receive an implicit instruction for reading theaccumulator A 32 a (block 350). The values stored in theaccumulator A 32 a and theaccumulator B 32 b are sent to the CLA 30 (block 352). TheCLA 30 then adds thevalues CLA 30 then sends theresult 40 as output data (block 356). Theresult 40 may then be sent to a register file external to theMAC 100. - In FIG. 5, a multiply with implicit accumulate operation uses packed data instructions. In one embodiment of the invention, the
MAC 100 may receive four different packed data instructions. These four packed data instructions operate on sixteen bits or half of two 32-bit operands. For example, one instruction may operate on the lower sixteen bits of both the multiplier B and the multiplicand A. Another may operate on the upper sixteen bits of the multiplicand A and the lower sixteen bits of the multiplier B. Ultimately, each packed-data instruction thus performs a 16-bit multiply operation on two 16-bit operands. - At the beginning of cycle zero (block400), a 32-bit multiplicand A[31:0] and a 32-bit multiplier B[31:0] are sent to the MAC 100 (block 402). The
MAC control logic 52 also receives a packed-data instruction (block 404). - Sixteen bits of the multiplicand A are extended to 32 bits. For example, if the packed-data instruction is operating on the lower sixteen bits of the multiplicand A, then the upper sixteen bits of the multiplicand A are replaced with the contents of the 16th bit of the multiplicand A. In essence, the sign is extended from the 16th to the 32nd bit. Likewise, if the packed-data instruction is operating on the upper sixteen bits of the multiplicand A, then the upper sixteen bits are shifted to the lower 16 bits and the upper sixteen bits are filled with the value of the sign bit.
- Sixteen bits of the multiplier B are sent to the Booth encoder10 (block 408). For example, if the packed-data instruction operates on the lower half of the multiplier B, then B[15:0] are sent to the
Booth encoder 10. Likewise, for a packed-data instruction which operates on the upper half of the multiplier B, the B[31:16] bits are sent to theBooth encoder 10. - From this point, the packed-data instructions are operated upon just as any other implicit instruction would be. Accordingly, the next operation to be performed by the
MAC 100 is in FIG. 4A (block 304). - Just as for other operations, the
MAC 100 is simultaneously determining whether theearly termination logic 50 will be invoked. That is, the multiplier B[31:0] is sent to the early termination logic 50 (block 420). Because the upper seventeen bits of the multiplier B are identical, theearly termination logic 50 sends a signal to the MAC control logic 52 (block 422). TheMAC control logic 52 then sends a signal to latch the flip-flops MUXs - Thus, a multiply-accumulate unit may provide single-cycle throughput for certain operations. In one embodiment of the invention, the MAC avoids using redundant hardware, which may consume additional power, and includes no pipelining circuitry, which may run more slowly. Instead, the Wallace tree and the carry look-ahead adder which are part of the MAC may simultaneously operate. Where such simultaneous operations occur, a higher throughput may be possible.
- While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
Claims (30)
1. A method comprising:
receiving a first set of operands into a multiply-accumulate unit;
performing a first operation on the first set of operands to arrive at a first intermediate result;
receiving a second set of operands into the multiply-accumulate unit; and
performing the first operation on the second set of operands to arrive at a second intermediate result while performing a second operation on the first intermediate result.
2. The method of claim 1 , wherein receiving a first set of operands further comprises:
receiving a multiplier into a Booth encoder; and
receiving a multiplicand into an array of multiplexers.
3. The method of claim 2 , wherein performing a first operation on the first set of operands further comprises sending a plurality of control signals from the Booth encoder to the array of multiplexers.
4. The method of claim 2 , wherein performing a first operation on the first set of operands further comprises sending a plurality of partial products from the array of multiplexers to a Wallace tree.
5. The method of claim 4 , wherein receiving a first set of operands further comprises receiving an accumulate value into the Wallace tree.
6. The method of claim 5 , wherein performing a first operation on the first set of operands further comprises invoking a plurality of carry-save adders in the Wallace tree upon receipt of the plurality of partial products and the accumulate value.
7. The method of claim 1 , wherein performing a second operation on the first intermediate result further comprises:
receiving the first intermediate result as a first portion and a second portion; and
adding the first portion and the second portion together.
8. The method of claim 7 , wherein performing a second operation on the first intermediate result further comprises:
sending the first portion and the second portion to a carry look-ahead adder; and
invoking the carry look-ahead adder.
9. An apparatus, comprising:
a structure for performing multiple addition operations;
an adder; and
a controller which permits a first operation to be performed on a portion of a first operand using the structure while the adder is performing a second operation on another portion of the first operand.
10. The apparatus of claim 9 , further comprising an internal storage medium coupled to the adder.
11. The apparatus of claim 9 , wherein the structure for performing multiple addition operations comprises a Wallace tree.
12. The apparatus of claim 11 , wherein the Wallace tree comprises a plurality of carry-save adders.
13. The apparatus of claim 12 , wherein the Wallace tree is a four-stage Wallace tree.
14. The apparatus of claim 9 , wherein the adder is a carry look-ahead adder.
15. The apparatus of claim 9 , further comprising a Booth encoder coupled to the structure for performing multiple addition operations.
16. The apparatus of claim 12 , wherein the Wallace tree receives nine input vectors and produces two output vectors.
17. The apparatus of claim 10 , wherein the internal storage medium comprises one or more accumulators.
18. The apparatus of claim 17 , wherein one or more accumulators are coupled to the output of the adder.
19. An apparatus comprising:
a Wallace tree;
an adder; and
a controller that sends a plurality of signals to cause the Wallace tree to execute a part of an instruction while the adder executes another part of the instruction.
20. The apparatus of claim 19 , wherein the adder is a carry look-ahead adder.
21. The apparatus of claim 20 , wherein the Wallace tree receives packed-data instructions.
22. The apparatus of claim 20 , further comprising a Booth encoder coupled to the Wallace tree.
23. An article comprising a medium storing instructions that cause a processor-based system to:
receive a first set of operands into a multiply-accumulate unit;
perform a first operation on the first set of operands to arrive at a first result;
receive a second set of operands into the multiply-accumulate unit; and
performing the first operation on the second set of operands to arrive at a second result while performing a second operation on the first result.
24. The article of claim 23 , further storing instructions that cause a processor-based system to receive a first set of operands by receiving a multiplier into a Booth encoder.
25. The article of claim 24 , further storing instructions that cause a processor-based system to receive a first set of operands by receiving a multiplicand into an array of multiplexers.
26. The article of claim 25 , further storing instructions that cause a processor-based system to perform a first operation on the first set of operands by sending a plurality of control signals from the Booth encoder to the array of multiplexers.
27. The article of claim 25 , further storing instructions that cause a processor-based system to perform a first operation on the first set of operands by sending a plurality of partial products from the array of multiplexers to a Wallace tree.
28. The article of claim 27 , further storing instructions that cause a processor-based system to receive a first set of operands by receiving an accumulate value into the Wallace tree.
29. The article of claim 28 , further storing instructions that cause a processor-based system to perform a first operation on the first set of operands by invoking a plurality of carry-save adders in the Wallace tree upon receipt of the plurality of partial products and the accumulate value.
30. The article of claim 23 , further storing instructions that cause a processor-based system to perform a second operation on the first result by:
receiving the first result as a first portion and a second portion; and
sending the first portion and the second portion to a carry look-ahead adder; and
adding the first portion and the second portion together in the carry look-ahead adder.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/407,048 US20030172101A1 (en) | 1999-12-23 | 2003-04-04 | Processing multiply-accumulate operations in a single cycle |
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Application Number | Priority Date | Filing Date | Title |
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US09/470,836 US6611856B1 (en) | 1999-12-23 | 1999-12-23 | Processing multiply-accumulate operations in a single cycle |
US10/407,048 US20030172101A1 (en) | 1999-12-23 | 2003-04-04 | Processing multiply-accumulate operations in a single cycle |
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US09/470,836 Division US6611856B1 (en) | 1999-12-23 | 1999-12-23 | Processing multiply-accumulate operations in a single cycle |
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US10/407,048 Abandoned US20030172101A1 (en) | 1999-12-23 | 2003-04-04 | Processing multiply-accumulate operations in a single cycle |
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JP (1) | JP3869269B2 (en) |
KR (1) | KR100470299B1 (en) |
CN (1) | CN1230735C (en) |
AU (1) | AU2059401A (en) |
GB (1) | GB2371657B (en) |
TW (1) | TW588281B (en) |
WO (1) | WO2001048595A1 (en) |
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GB0208937D0 (en) | 2002-05-29 |
JP2003518690A (en) | 2003-06-10 |
GB2371657A (en) | 2002-07-31 |
US6611856B1 (en) | 2003-08-26 |
CN1230735C (en) | 2005-12-07 |
JP3869269B2 (en) | 2007-01-17 |
GB2371657B (en) | 2004-09-15 |
WO2001048595A1 (en) | 2001-07-05 |
KR20030011063A (en) | 2003-02-06 |
CN1402843A (en) | 2003-03-12 |
AU2059401A (en) | 2001-07-09 |
KR100470299B1 (en) | 2005-02-05 |
TW588281B (en) | 2004-05-21 |
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