US20030227052A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- US20030227052A1 US20030227052A1 US10/400,625 US40062503A US2003227052A1 US 20030227052 A1 US20030227052 A1 US 20030227052A1 US 40062503 A US40062503 A US 40062503A US 2003227052 A1 US2003227052 A1 US 2003227052A1
- Authority
- US
- United States
- Prior art keywords
- conductivity type
- layer
- jfet
- type base
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 85
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims description 18
- 239000010410 layer Substances 0.000 description 148
- 238000000034 method Methods 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 9
- 238000004088 simulation Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBBGRARXTFLTSG-UHFFFAOYSA-N Lithium ion Chemical compound [Li+] HBBGRARXTFLTSG-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910001416 lithium ion Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Definitions
- the present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure.
- MOSFET Metal Oxide Semiconductor Field Effect Transistor
- a conventional vertical-type power MOSFET will be described with reference to a schematic cross section of FIG. 26.
- like parts are designated by like reference numerals and repetitive descriptions thereof will be appropriately omitted.
- a drain electrode 12 is provided on the under face of an n + type low-resistance semiconductor substrate 10 , and an n ⁇ type high-resistance epitaxial layer 50 is formed on the top face of the low-resistance semiconductor substrate 10 .
- a p type base layer 14 is selectively formed in a surface portion of the high-resistance epitaxial layer 50 .
- an n + type source layer 16 is selectively formed.
- a highly-doped p type region 18 is selectively formed so as to be adjacent to the n + type source layer 16 .
- an Njfet region 90 is selectively formed, into which an n-type impurity is doped at a higher concentration as compared with the high-resistance epitaxial layer 50 .
- a gate electrode 94 is provided via a gate insulating film 92 .
- source electrodes 20 are provided so as to sandwich the gate electrode 94 .
- a semiconductor device comprising: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of the first conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed in a surface portion of the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a jfet layer of the first conductivity type selectively formed in a region sandwiched by the second-conductivity type base layers in a surface portion of the high-resistance epitaxial layer and having impurity concentration higher than that of the high-resistance epitaxial layer; a gate insulating film formed on at least a part of the surface of the
- a semiconductor device comprising: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of the first conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed in a surface portion of the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a jfet layer of the first conductivity type selectively formed in a region sandwiched by the second-conductivity type base layer in the surface portion of the high-resistance epitaxial layer and having impurity concentration higher than that of the high-resistance epitaxial layer; a gate insulating film formed on at least a part of the surface of the first conductivity type;
- a semiconductor device comprising: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in
- a semiconductor device comprising: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a first insulating layer formed on the low-resistance drain layer; a second-conductivity type base layer formed on the first insulating layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed so as to extend from the surface of the second-conductivity type base layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; a second insulating layer formed in the trench; an LDD layer of the first conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the jfet layer of the first conductivity type around a top face of the trench;
- FIG. 1 is a schematic cross section showing a first embodiment of a semiconductor device according to the invention.
- FIG. 2 is a graph showing a simulation result of width L of an Njfet region in the semiconductor device illustrated in FIG. 1.
- FIG. 3 is a graph showing a simulation result of the amount of a dose in the surface of the Njfet region in the semiconductor device illustrated in FIG. 1.
- FIG. 4 is a schematic cross section showing a second embodiment of the semiconductor device according to the invention.
- FIG. 5 is a schematic cross section showing a third embodiment of the semiconductor device according to the invention.
- FIG. 6 is a diagram showing electron density in a conventional power MOSFET 100 illustrated in FIG. 26.
- FIG. 7 is a diagram for explaining reduction in gate-drain capacitance Q gd by the semiconductor device illustrated in FIG. 5.
- FIG. 8 is a graph showing a simulation result of a proper range of impurity concentration in an LDD region in the semiconductor device illustrated in FIG. 5.
- FIG. 9 is a plan view showing a first example of a plane shape of a gate electrode of the semiconductor device illustrated in FIG. 5.
- FIG. 10 is a plan view showing a second example of a plane shape of the gate electrode of the semiconductor device illustrated in FIG. 5.
- FIG. 11 is a schematic cross section taken along line A-A of FIG. 10.
- FIG. 12 is a schematic cross section taken along line B-B of FIG. 10.
- FIG. 13 is a plan view showing a third example of a plane shape of the gate electrode of the semiconductor device illustrated in FIG. 5.
- FIG. 14 is a plan view showing a fourth example of a plane shape of the gate electrode of the semiconductor device illustrated in FIG. 5.
- FIG. 15 is a schematic cross section showing a fourth embodiment of the semiconductor device according to the invention.
- FIG. 16 is a schematic cross section showing a fifth embodiment of the semiconductor device according to the invention.
- FIGS. 17 through 22 are schematic cross sections for explaining a method of manufacturing the semiconductor device shown in FIG. 16.
- FIG. 23 is a schematic cross section showing a sixth embodiment of the semiconductor device according to the invention.
- FIG. 24 is a schematic cross section showing a seventh embodiment of the semiconductor device according to the invention.
- FIG. 25 is a schematic cross section showing a modification of the semiconductor device illustrated in FIG. 24.
- FIG. 26 is a schematic cross section showing an example of a conventional vertical-type power MOSFET.
- FIG. 1 is a schematic cross section showing a first embodiment of a semiconductor device according to the invention.
- the semiconductor device of the present embodiment is characterized in that an Njfet region 40 is formed in a narrow width at a high concentration.
- the structure of the semiconductor device of the embodiment will be described in more detail hereinbelow.
- a power MOSFET 1 shown in FIG. 1 is a power MOSFET of a vertical type to which the invention is applied, and includes an n + type low-resistance semiconductor substrate 10 , a drain electrode 12 , an n ⁇ type high-resistance epitaxial layer 50 , a p type base layer 14 , an n + type source layer 16 , the Njfet region 40 , a gate electrode 24 , and a source electrode 20 .
- the drain electrode 12 is provided on one of the surfaces (under face in FIG. 1) of the n + type low-resistance semiconductor substrate 10 , and the n ⁇ type high-resistance epitaxial layer 50 is formed on the other face (top face in FIG. 1) of the n + type low-resistance semiconductor substrate 10 .
- the p type base layer 14 is selectively formed in a surface portion of the n ⁇ type high-resistance epitaxial layer 50
- the n + type source layer 16 is selectively formed in a surface portion of the p type base layer 14 .
- the highly-doped p type region 18 is formed in the surface portion of the p type base layer 14 .
- the Njfet region 40 is selectively formed in a region sandwiched by the p type base layers 14 in the surface portion of the n ⁇ type high-resistance epitaxial layer 50 .
- a gate electrode 24 is provided via a gate insulating film 22 on the surface of the Njfet region 40 , on the surfaces of the regions of the p type base layer 14 sandwiching the Njfet region 40 , and on the surfaces of end portions of the n + type source layers 16 facing each other across the Njfet region 40 .
- the source electrodes 20 are provided on the surfaces of the n + type source layers 16 and the surfaces of the highly-doped p type regions 18 so as to sandwich the gate electrode 24 .
- the Njfet region 40 is a characteristic part in the embodiment and, as obviously understood by comparison with FIG. 26, the Njfet region 40 is formed so as to be narrower than the Njfet region 90 of the conventional power MOSFET.
- the width L of the Njfet region 40 is substantially equal to or narrower than the spacing between two neighboring gate electrodes 24 .
- FIG. 2 is a graph showing a result of the simulation of the width L of the Njfet region 40 .
- R on Q gd is about 24 [m ⁇ nC] or less in the region satisfying the relation of L ⁇ 1.0 ⁇ m as shown in FIG. 2. It is understood that particularly in the region satisfying the relation of Xj ⁇ 0.7 or less, conspicuous effects appear on both R on Q gd and a breakdown voltage BV.
- the Njfet region 40 is formed with a depth almost equal to the depth Xj of the p type base layer 14 .
- the Njfet region 40 is also formed so that the junction interface thereof with the p-type base layer 14 becomes perpendicular to the surface of the Njfet region 40 as it approaches the surface.
- the surface density of the Njfet region 40 can be increased to the range from about 1E16 to about 3E17 [cm ⁇ 3 ], so that on-state resistance R on can be also reduced.
- FIG. 3 is a graph showing a simulation result of the amount of a dose in the surface of the Njfet region 40 .
- the simulation teaches that, when the width L of the Njfet region 40 is 1 ⁇ m, the breakdown voltage BV of 30V or higher is obtained and the value of R on Q gd is also low, over a range in which the amount N of the surface dose of the Njfet region 40 satisfies the relation of N ⁇ 4E ⁇ 12.
- FIG. 4 is a schematic cross section showing a second embodiment of a semiconductor device according to the invention.
- a power MOSFET 3 of the second embodiment is characterized in that a gate insulating film 23 is formed so as to be thicker in a region facing the Njfet region 40 as well as in that the Njfet region 40 is formed in narrow width and at high concentration. More specifically, a portion 23 a of the gate insulating film 23 facing the Njfet region 40 has a thickness of about 90 nm whereas the other portion of the gate insulating film 23 is formed to have a thickness of about 30 nm.
- a gate electrode 25 can be further isolated from the Njfet region 40 in the region facing the Njfet region 40 in the region facing the Njfet region 40 .
- the Njfet region 40 is formed in narrow width and at high concentration, at the time of depleting the Njfet region 40 , depletion from the p type base layer 14 becomes dominant. Thus, it is possible to employ such structures of the gate insulating film 23 and the gate electrode 25 .
- the gate electrode 25 is provided via the gate insulating film 23 which is formed so that the region facing the Njfet region 40 is thicker than the other region.
- the amount of contribution to the gate-drain capacitance Q gd of the gate electrode can be further reduced.
- FIG. 5 is a schematic cross section showing a third embodiment of a semiconductor device according to the invention.
- a power MOSFET 5 of the third embodiment is characterized in that a portion facing the Njfet region 40 in the gate electrode 28 is selectively removed.
- the width L of the Njfet region 40 can be further narrowed, so that the gate-drain capacitance Q gd is further reduced and operation speed of the device is further increased.
- the Njfet region 40 can be formed in a self-aligned manner.
- FIGS. 6 and 7 are diagrams for explaining reduction in the gate-drain capacitance Q gd according to the third embodiment.
- FIG. 6 shows electron density in the conventional power MOSFET 100 illustrated in FIG. 26, and
- FIG. 7 shows electron density in the case where the gate electrode of the power MOSFET 100 of FIG. 26 is simply divided without reducing the width L of the Njfet region.
- Each of FIGS. 6 and 7 shows electron density when 20V is applied as Vds.
- the power MOSFET 5 of the embodiment further includes an LDD (Lightly Doped Drain) region 44 formed in the surface portion of the Nifet region 40 .
- the LDD region 44 is formed in a self-aligned manner by shallowly implanting n-type impurity ions into the Njfet region 40 by using the divided gate electrode 28 as a mask and, after that, performing thermal diffusion.
- FIGS. 9 through 14 some plane shapes of the gate electrode of the power MOSFET 5 of the embodiment will be described.
- FIG. 9 shows a plane shape of a gate electrode 29 as a first example.
- the gate electrode 29 of the example is divided into two parts and each part is formed so as to have a stripe pattern similar to the plane shape of the gate electrode of a conventional power MOSFET.
- Such an electrode shape has a drawback such that resistance of the gate electrode itself might become high and it might disturb increase in the processing speed of the device.
- the Njfet region 40 of the power MOSFET 5 is not formed in stripes in the longitudinal direction of the gate electrode 28 in the surface portion of the n ⁇ type high-resistance epitaxial layer 50 .
- divided gate electrodes each having a hollow rectangular plane shape are disposed at regular intervals in the longitudinal direction, each Njfet region 40 just bellow the hollow rectangular is surrounded by the p type base layer 14 , and divided gate electrodes are connected to each other at regular intervals so as to form a plane shape like a ladder in a region where the Njfet region 40 does not exist in the lower layer.
- FIG. 11 shows a schematic cross section taken along line A-A of FIG. 10
- FIG. 12 shows a schematic cross section taken along line B-B of FIG. 10.
- the shape of the Njfet region 40 surrounded by the p type base layer 14 is a rectangular shape.
- the shape of the Njfet region 40 is not limited to the rectangular shape but may be, for example, a circular shape 32 as a third example shown in FIG. 13 or a polygonal shape 34 as a fourth example show in FIG. 14.
- FIG. 15 is a schematic cross section showing a fourth embodiment of the semiconductor device according to the invention.
- a power MOSFET 9 shown in FIG. 15 is obtained by applying the foregoing third embodiment to a lateral-type power MOSFET.
- an n + type low-resistance drain layer 68 is formed so as to extend from the surface of the n ⁇ type high-resistance epitaxial layer 50 to an n + low-resistance semiconductor layer 70 just below the layer 50 .
- a drain electrode 62 is provided on the surface of the n + type low-resistance drain layer 68 , thereby constructing a vertical-type power MOSFET.
- the power MOSFET 9 is substantially the same as the power MOSFET 5 shown in FIG. 5 in that the Njfet region 40 sandwiched (or surrounded) by the p type base layer 14 is formed so that its width L is narrow, in that the Njfet region 40 is formed at high concentration, in that the gate electrode 28 is provided in a divided form, and in that the LDD region 44 is formed in the surface portion of the Njfet region 40 .
- FIG. 16 is a schematic cross section showing a fifth embodiment of a semiconductor device according to the invention.
- a power MOSFET 7 shown in FIG. 16 is characterized in that it further includes an insulating film 52 formed in a trench TR 2 provided with a depth which is approximately the same as diffusion depth of the p type base layer 14 in an almost center portion in the Njfet region 46 and it further includes an electrode 54 of a fixed potential provided in the insulating film 52 .
- the trench TR 2 in the Njfet region 46 sandwiched (or surrounded) by the p type base layer 14 as described above ions can be implanted obliquely to the surface of the wafer. Consequently, the highly-doped Njfet region 46 can be formed in a fine structure on the side walls of the trench TR 2 .
- the electrode 54 via the insulating film 52 in the trench TR 2 and fixing the potential of the electrode 54 the breakdown voltage can be further increased by about 5V and the gate-drain capacitance Q gd can be further reduced by about 20%.
- an n ⁇ type high-resistance epitaxial layer 50 is formed on the top face of the n + type low-resistance semiconductor substrate 10 having the drain electrode 12 on its under face, and a p type base layer 15 is formed on the top face of the n ⁇ type epitaxial layer 50 .
- a gate insulating film 26 and the gate electrode 28 are formed on the surface of the p type base layer 15 . After that, the gate electrode 28 is divided into at least two parts.
- a photoresist 102 is formed, and n type impurities are selectively implanted between the divided gate electrodes 28 a, thereby forming a shallow n-type lightly doped drain (LDD) region 48 so that its both ends face the divided gate electrodes 28 a via the gate insulating film 26 (refer to FIG. 18).
- LDD lightly doped drain
- an insulating film is deposited on the whole wafer and RIE (Reactive Ion Etching) is executed.
- RIE Reactive Ion Etching
- the deposited insulating film can be left only on the side walls of the gate insulating film 26 and the gate electrodes 28 a (side walls 104 ).
- a conductive material such as polysilicon can be used in place of the insulating film.
- the gate electrode 28 a has to be oxidized so as to be insulated from the conductive material by post-oxidation or the like.
- a photoresist 106 is formed.
- the p type base layer 15 is selectively removed by RIE, thereby forming the trench TR 2 with the ends of the LDD region 48 being retained by widths each of which corresponds to that of the side wall 104 .
- n-type impurities are implanted at oblique angles to the wafer as shown by arrows in FIG. 19.
- the n type region 46 serving as an Njfet region is selectively formed only on the side walls of the trench TR 2 (FIG. 20).
- the oxide film 52 is formed on the silicon on the surface of the wafer with an oxidizing process. If ions implanted in the side walls of the trench TR 2 are, for example, of arsenic, the extent of thermal diffusion is less than in a case of phosphorus and, by speed-increased oxidization, the oxide film in the surface portion of arsenic can be formed thicker than that of the other silicon surface portion.
- the trench TR 2 is buried with the insulating film 52 , or the insulating film 52 and a conductive material. Finally, an interlayer insulating film 72 and the source electrode 20 are formed.
- the size of the gate-drain overlap region below the gate electrode is minimized by the LDD region 48 , and the highly-doped Njfet region 46 can be formed on the side walls of the trench TR 2 .
- the insulating film or the conductive material via the insulating film 52 and connecting and fixing the electrode 54 made of the conductive material to the source potential or other potential, a field plate effect can be expected in the Njfet region 46 of the side walls of the trench TR 2 .
- depletion is promoted.
- the concentration of the Njfet region 46 of the side walls of the trench TR 2 can thus be made higher than that of the drift layer necessary to obtain a breakdown voltage for an ordinary purpose.
- the manufacturing method of the power MOSFET according to the embodiment is not limited to the above described method.
- p type impurities may be diffused only from the source region after division of the gate electrode 28 .
- the LDD region 48 in place of the method of implanting n type impurities in the self-alignment process so that both ends of the LDD region 48 face the gate electrode 28 a via the gate oxide film 26 , the LDD region 48 may be formed by implanting after forming the trench TR or after forming the oxide film 52 . In this case, the number of processes of thermal diffusion can be reduced, and the overlap of the gate and drain can be adjusted to the minimum amount.
- FIG. 23 is a schematic cross section showing a sixth embodiment of a semiconductor device according to the invention.
- a power MOSFET 11 shown in FIG. 23 is characterized in that the electrode 56 formed in the insulating film 52 in the trench TR 2 is electrically connected to an upper part of the source electrode 20 . With such a structure, the potential of the electrode 56 in the trench TR 2 can be fixed to the potential of the source electrode 20 .
- FIG. 24 is a schematic cross section showing a seventh embodiment of a semiconductor device according to the invention.
- a power MOSFET 13 shown in the diagram is characterized in that a trench TR 4 is formed so deep as to reach the n + type semiconductor substrate 10 so that the n-type highly-doped region 56 of the side walls of the trench TR 4 is directly connected to the n + type semiconductor substrate 10 and in that the n type highly doped region 56 is sandwiched by the insulating film 62 in the trench TR 4 and the p ⁇ type region 30 on the outside of the trench TR 4 .
- the Njfet region 46 on the side walls of the trench also has to be formed with approximate same depth as the depth of the p-type base layer 14 for the following reason. If the trench is too shallow, a current path between the source and the drain is interrupted. On the other hand, if the trench is too deep, the impurity concentration of the n ⁇ type drain layer increases. In this case, it is concerned that a depletion layer does not extend and the breakdown voltage decreases.
- the power MOSFET 13 of the seventh embodiment employs the structure in which the n type highly-doped region 56 serving as the Njfet region is sandwiched by the insulating film 62 in the trench TR 4 and the p ⁇ type region 30 on the outside of the trench TR 4 , a current can directly pass to the n + type low-resistance semiconductor substrate 10 via no n ⁇ type drift layers, so that ON-state resistance can be decreased.
- the n-type highly-doped region 56 is therefore easily depleted and the depletion layer extends also to the p ⁇ type region 30 . As a result, a desired breakdown voltage can be obtained.
- FIG. 25 is a schematic cross section showing a modification of the seventh embodiment.
- a power MOSFET 17 shown in the diagram has an insulating layer 80 formed on the outside of the trench TR 4 in place of the p ⁇ type region 30 formed on the outside of the trench TR 4 in the power MOSFET 13 shown in FIG. 24. Even with such an insulating layer 80 , the n type highly-doped region 56 on the side walls of the trench is depleted.
- the third through seventh embodiments employ the structure in which the gate electrode is divided into two or more parts, there may occur a concern about increase in gate resistance.
- Examples of methods of eliminating such a concern include a method of metallizing the surface of a gate polysilicon electrode with a silicide process and a method of re-connecting the divided parts of the gate electrode in a terrace state in a wiring process to be performed after forming element regions.
Abstract
A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.
Description
- This application claims benefit of priority under 35USC §119 to Japanese patent application No. 2002-94361, filed on Mar. 29, 2002, the contents of which are incorporated by reference herein.
- 1. Field of the Invention
- The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure.
- 2. Related Background Art
- In recent years, demand for a power MOSFET has been rapidly increasing in the field of a switching power source of heavy current and high breakdown voltage and, in addition, in the field of switching elements for energy saving of mobile communication devices such as a notebook-sized PC (Personal Computer). Since the power MOSFET is often used for a power management circuit, a safety circuit of a lithium ion battery, and the like in these fields, driving with a lower voltage so that the device can be directly driven with a battery voltage, lower ON-state resistance, reduction in capacitance Qgd between a gate and a drain for reducing a switching loss, and the like are strongly demanded.
- A conventional vertical-type power MOSFET will be described with reference to a schematic cross section of FIG. 26. In the following diagrams, like parts are designated by like reference numerals and repetitive descriptions thereof will be appropriately omitted.
- In a
power MOSFET 100 shown in FIG. 26, adrain electrode 12 is provided on the under face of an n+ type low-resistance semiconductor substrate 10, and an n− type high-resistanceepitaxial layer 50 is formed on the top face of the low-resistance semiconductor substrate 10. In a surface portion of the high-resistanceepitaxial layer 50, a ptype base layer 14 is selectively formed. In a surface portion of the ptype base layer 14, an n+type source layer 16 is selectively formed. In a surface portion of the ptype base layer 14, a highly-dopedp type region 18 is selectively formed so as to be adjacent to the n+type source layer 16. In the surface portion of the high-resistanceepitaxial layer 50, in a region sandwiched by the p-type base layers 14, an Njfetregion 90 is selectively formed, into which an n-type impurity is doped at a higher concentration as compared with the high-resistanceepitaxial layer 50. On the surface of the Njfetregion 90, the surfaces of the p-type base layers 14 sandwiching the Njfetregion 90, and the surfaces of end portions of the n+type source layers 16 facing each other so as to sandwich the Njfetregion 90, agate electrode 94 is provided via agate insulating film 92. On the surfaces of the n+type source layers 16 and the surfaces of the highly-dopedp type regions 18,source electrodes 20 are provided so as to sandwich thegate electrode 94. - For the
power MOSFET 100 having such a structure, it is necessary to make the Njfetregion 90 easily depleted in order to reduce the gate-drain capacitance Qgd. - However, when the impurity concentration of the Njfet
region 90 is lowered to make the Njfetregion 90 easily depleted, a problem occurs such that an ON-state resistance Ron of the device increases and, as a result, a breakdown voltage of the device decreases. - According to a first aspect of the invention, there is provided a semiconductor device comprising: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of the first conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed in a surface portion of the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a jfet layer of the first conductivity type selectively formed in a region sandwiched by the second-conductivity type base layers in a surface portion of the high-resistance epitaxial layer and having impurity concentration higher than that of the high-resistance epitaxial layer; a gate insulating film formed on at least a part of the surface of the first-conductivity type jfet layer, on the surfaces of the second-conductivity type base layers facing each other across the first-conductivity type jfet layer, and on the surfaces of end portions of the first-conductivity type source layers facing each other across the first-conductivity type jfet layer; a control electrode formed on the gate insulating film; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode, wherein assuming that depth of the second-conductivity type base layer is Xj, width L of the first-conductivity type jfet layer in the direction orthogonal to the longitudinal direction of the control electrode is substantially equal to or less than that of an interval between neighboring control electrodes and satisfies the following expression.
- L≦Xj×0.7
- According to a second aspect of the invention, there is provided a semiconductor device comprising: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of the first conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed in a surface portion of the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a jfet layer of the first conductivity type selectively formed in a region sandwiched by the second-conductivity type base layer in the surface portion of the high-resistance epitaxial layer and having impurity concentration higher than that of the high-resistance epitaxial layer; a gate insulating film formed on at least a part of the surface of the first-conductivity type jfet layer, on the surfaces of the second-conductivity type base layers facing each other across the first-conductivity type jfet layer, and on the surfaces of end portions of the first-conductivity type source layers facing each other across the first-conductivity type jfet layer; a control electrode formed on the gate insulating film; and; a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode, wherein the, second-conductivity type base layers sandwiching the first-conductivity type jfet layer are disposed close to each other so that depletion from the second-conductivity type base layer becomes dominant, and the gate insulating film and the control electrode are formed by selectively removing a part of a region facing the first-conductivity type jfet layer.
- According to a third aspect of the invention, there is provided a semiconductor device comprising: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.
- According to a fourth aspect of the invention, there is provided a semiconductor device comprising: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a first insulating layer formed on the low-resistance drain layer; a second-conductivity type base layer formed on the first insulating layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed so as to extend from the surface of the second-conductivity type base layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; a second insulating layer formed in the trench; an LDD layer of the first conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the jfet layer of the first conductivity type around a top face of the trench; a control electrode formed so as to be divided into a plurality of parts above the semiconductor substrate, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end portions of the first-conductivity type source layer facing each other across the trench, and on a region of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.
- FIG. 1 is a schematic cross section showing a first embodiment of a semiconductor device according to the invention.
- FIG. 2 is a graph showing a simulation result of width L of an Njfet region in the semiconductor device illustrated in FIG. 1.
- FIG. 3 is a graph showing a simulation result of the amount of a dose in the surface of the Njfet region in the semiconductor device illustrated in FIG. 1.
- FIG. 4 is a schematic cross section showing a second embodiment of the semiconductor device according to the invention.
- FIG. 5 is a schematic cross section showing a third embodiment of the semiconductor device according to the invention.
- FIG. 6 is a diagram showing electron density in a
conventional power MOSFET 100 illustrated in FIG. 26. - FIG. 7 is a diagram for explaining reduction in gate-drain capacitance Qgd by the semiconductor device illustrated in FIG. 5.
- FIG. 8 is a graph showing a simulation result of a proper range of impurity concentration in an LDD region in the semiconductor device illustrated in FIG. 5.
- FIG. 9 is a plan view showing a first example of a plane shape of a gate electrode of the semiconductor device illustrated in FIG. 5.
- FIG. 10 is a plan view showing a second example of a plane shape of the gate electrode of the semiconductor device illustrated in FIG. 5.
- FIG. 11 is a schematic cross section taken along line A-A of FIG. 10.
- FIG. 12 is a schematic cross section taken along line B-B of FIG. 10.
- FIG. 13 is a plan view showing a third example of a plane shape of the gate electrode of the semiconductor device illustrated in FIG. 5.
- FIG. 14 is a plan view showing a fourth example of a plane shape of the gate electrode of the semiconductor device illustrated in FIG. 5.
- FIG. 15 is a schematic cross section showing a fourth embodiment of the semiconductor device according to the invention.
- FIG. 16 is a schematic cross section showing a fifth embodiment of the semiconductor device according to the invention.
- FIGS. 17 through 22 are schematic cross sections for explaining a method of manufacturing the semiconductor device shown in FIG. 16.
- FIG. 23 is a schematic cross section showing a sixth embodiment of the semiconductor device according to the invention.
- FIG. 24 is a schematic cross section showing a seventh embodiment of the semiconductor device according to the invention.
- FIG. 25 is a schematic cross section showing a modification of the semiconductor device illustrated in FIG. 24.
- FIG. 26 is a schematic cross section showing an example of a conventional vertical-type power MOSFET.
- Embodiments of the invention will be described in detail hereinbelow with reference to the drawings.
- (1) First Embodiment
- FIG. 1 is a schematic cross section showing a first embodiment of a semiconductor device according to the invention. The semiconductor device of the present embodiment is characterized in that an
Njfet region 40 is formed in a narrow width at a high concentration. The structure of the semiconductor device of the embodiment will be described in more detail hereinbelow. - A
power MOSFET 1 shown in FIG. 1 is a power MOSFET of a vertical type to which the invention is applied, and includes an n+ type low-resistance semiconductor substrate 10, adrain electrode 12, an n− type high-resistance epitaxial layer 50, a ptype base layer 14, an n+type source layer 16, theNjfet region 40, agate electrode 24, and asource electrode 20. - The
drain electrode 12 is provided on one of the surfaces (under face in FIG. 1) of the n+ type low-resistance semiconductor substrate 10, and the n− type high-resistance epitaxial layer 50 is formed on the other face (top face in FIG. 1) of the n+ type low-resistance semiconductor substrate 10. The ptype base layer 14 is selectively formed in a surface portion of the n− type high-resistance epitaxial layer 50, and the n+type source layer 16 is selectively formed in a surface portion of the ptype base layer 14. In the surface portion of the ptype base layer 14, the highly-dopedp type region 18 is formed. TheNjfet region 40 is selectively formed in a region sandwiched by the p type base layers 14 in the surface portion of the n− type high-resistance epitaxial layer 50. Agate electrode 24 is provided via agate insulating film 22 on the surface of theNjfet region 40, on the surfaces of the regions of the ptype base layer 14 sandwiching theNjfet region 40, and on the surfaces of end portions of the n+ type source layers 16 facing each other across theNjfet region 40. Thesource electrodes 20 are provided on the surfaces of the n+ type source layers 16 and the surfaces of the highly-dopedp type regions 18 so as to sandwich thegate electrode 24. - The
Njfet region 40 is a characteristic part in the embodiment and, as obviously understood by comparison with FIG. 26, theNjfet region 40 is formed so as to be narrower than theNjfet region 90 of the conventional power MOSFET. The width L of theNjfet region 40 is substantially equal to or narrower than the spacing between two neighboringgate electrodes 24. By forming theNjfet region 40 so as to have such a narrow width L, a structure is obtained with which an amount contributed to the gate-drain capacitance Qgd by thegate electrode 24 decreases and depletion from the neighboring p type base layers 14 becomes dominant in depletion of theNjfet region 40. More specifically, a simulation shows that the width L of theNjfet region 40 satisfies the relation of L≦1.0 μm when depth Xj of the ptype base layer 14 is 1.0 μm. - FIG. 2 is a graph showing a result of the simulation of the width L of the
Njfet region 40. When thegate insulating film 22 is formed in almost uniform thickness of about 30 nm, RonQgd is about 24 [mΩnC] or less in the region satisfying the relation of L≦1.0 μm as shown in FIG. 2. It is understood that particularly in the region satisfying the relation of Xj×0.7 or less, conspicuous effects appear on both RonQgd and a breakdown voltage BV. - Referring again to FIG. 1, the
Njfet region 40 is formed with a depth almost equal to the depth Xj of the ptype base layer 14. TheNjfet region 40 is also formed so that the junction interface thereof with the p-type base layer 14 becomes perpendicular to the surface of theNjfet region 40 as it approaches the surface. - By narrowing the width L of the
Njfet region 40 as described above, the surface density of theNjfet region 40 can be increased to the range from about 1E16 to about 3E17 [cm−3], so that on-state resistance Ron can be also reduced. - FIG. 3 is a graph showing a simulation result of the amount of a dose in the surface of the
Njfet region 40. As shown in FIG. 3, the simulation teaches that, when the width L of theNjfet region 40 is 1 μm, the breakdown voltage BV of 30V or higher is obtained and the value of RonQgd is also low, over a range in which the amount N of the surface dose of theNjfet region 40 satisfies the relation of N≦4E×12. - (2) Second Embodiment
- FIG. 4 is a schematic cross section showing a second embodiment of a semiconductor device according to the invention. As obviously understood from comparison with FIG. 1, a
power MOSFET 3 of the second embodiment is characterized in that agate insulating film 23 is formed so as to be thicker in a region facing theNjfet region 40 as well as in that theNjfet region 40 is formed in narrow width and at high concentration. More specifically, aportion 23 a of thegate insulating film 23 facing theNjfet region 40 has a thickness of about 90 nm whereas the other portion of thegate insulating film 23 is formed to have a thickness of about 30 nm. By the configuration, in the region facing theNjfet region 40, agate electrode 25 can be further isolated from theNjfet region 40. - Since the
Njfet region 40 is formed in narrow width and at high concentration, at the time of depleting theNjfet region 40, depletion from the ptype base layer 14 becomes dominant. Thus, it is possible to employ such structures of thegate insulating film 23 and thegate electrode 25. - In the
power MOSFET 3 of the embodiment, thegate electrode 25 is provided via thegate insulating film 23 which is formed so that the region facing theNjfet region 40 is thicker than the other region. Thus, the amount of contribution to the gate-drain capacitance Qgd of the gate electrode can be further reduced. - (3) Third Embodiment
- FIG. 5 is a schematic cross section showing a third embodiment of a semiconductor device according to the invention. As obviously understood by comparison with FIG. 1, a
power MOSFET 5 of the third embodiment is characterized in that a portion facing theNjfet region 40 in thegate electrode 28 is selectively removed. - By employing the structure in which the
gate electrode 28 is divided as described above, the width L of theNjfet region 40 can be further narrowed, so that the gate-drain capacitance Qgd is further reduced and operation speed of the device is further increased. By implanting n-type impurities using thegate electrode 28 in the divisional structure as a mask, theNjfet region 40 can be formed in a self-aligned manner. - FIGS. 6 and 7 are diagrams for explaining reduction in the gate-drain capacitance Qgd according to the third embodiment. FIG. 6 shows electron density in the
conventional power MOSFET 100 illustrated in FIG. 26, and FIG. 7 shows electron density in the case where the gate electrode of thepower MOSFET 100 of FIG. 26 is simply divided without reducing the width L of the Njfet region. Each of FIGS. 6 and 7 shows electron density when 20V is applied as Vds. - As understood from comparison between FIG. 6 and FIG. 7, when the
gate electrode 94 of theconventional power MOSFET 100 is simply divided, the ratio of depletion by the gate remains high due to the wide region between neighboring p type base layers 14. As a result, depletion from the gate does not occur, a breakdown voltage decreases. - Referring again to FIG. 5, the
power MOSFET 5 of the embodiment further includes an LDD (Lightly Doped Drain)region 44 formed in the surface portion of theNifet region 40. TheLDD region 44 is formed in a self-aligned manner by shallowly implanting n-type impurity ions into theNjfet region 40 by using the dividedgate electrode 28 as a mask and, after that, performing thermal diffusion. - FIG. 8 is a graph showing an appropriate range of impurity concentration in the
LDD region 44 of thepower MOSFET 5 obtained by a simulation. It is understood from the graph that, when Xj=0.8 μm and L=0.4 μm, the value of RonQgd can be set to 10 [mΩnC] or less by setting the upper limit of the impurity concentration Cs of theLDD region 44 to about 5E17 [cm−3]. - Referring to FIGS. 9 through 14, some plane shapes of the gate electrode of the
power MOSFET 5 of the embodiment will be described. - FIG. 9 shows a plane shape of a gate electrode29 as a first example. The gate electrode 29 of the example is divided into two parts and each part is formed so as to have a stripe pattern similar to the plane shape of the gate electrode of a conventional power MOSFET. Such an electrode shape has a drawback such that resistance of the gate electrode itself might become high and it might disturb increase in the processing speed of the device.
- As a solution to such drawback, the
Njfet region 40 of thepower MOSFET 5 is not formed in stripes in the longitudinal direction of thegate electrode 28 in the surface portion of the n− type high-resistance epitaxial layer 50. For example, as shown in a second example of FIG. 10, divided gate electrodes each having a hollow rectangular plane shape are disposed at regular intervals in the longitudinal direction, eachNjfet region 40 just bellow the hollow rectangular is surrounded by the ptype base layer 14, and divided gate electrodes are connected to each other at regular intervals so as to form a plane shape like a ladder in a region where theNjfet region 40 does not exist in the lower layer. Since thegate electrodes 28 are formed so as to surround theNjfet regions 40 disposed at regular intervals from the top view, resistance of the gate electrodes can be largely reduced. Further, depletion of theNjfet region 40 develops only in the horizontal direction of the drawing sheet in the example shown in FIG. 9. By disposing theNjfet regions 40 at regular intervals as shown in FIG. 10, depletion develops omnidirectionally. Consequently, operation speed of the device is further improved. FIG. 11 shows a schematic cross section taken along line A-A of FIG. 10, and FIG. 12 shows a schematic cross section taken along line B-B of FIG. 10. - In the example shown in FIG. 10, the shape of the
Njfet region 40 surrounded by the ptype base layer 14 is a rectangular shape. However, the shape of theNjfet region 40 is not limited to the rectangular shape but may be, for example, acircular shape 32 as a third example shown in FIG. 13 or apolygonal shape 34 as a fourth example show in FIG. 14. - (4) Fourth Embodiment
- FIG. 15 is a schematic cross section showing a fourth embodiment of the semiconductor device according to the invention. A
power MOSFET 9 shown in FIG. 15 is obtained by applying the foregoing third embodiment to a lateral-type power MOSFET. Specifically, in a region outside of the ptype base layer 14, an n+ type low-resistance drain layer 68 is formed so as to extend from the surface of the n− type high-resistance epitaxial layer 50 to an n+ low-resistance semiconductor layer 70 just below thelayer 50. Adrain electrode 62 is provided on the surface of the n+ type low-resistance drain layer 68, thereby constructing a vertical-type power MOSFET. Thepower MOSFET 9 is substantially the same as thepower MOSFET 5 shown in FIG. 5 in that theNjfet region 40 sandwiched (or surrounded) by the ptype base layer 14 is formed so that its width L is narrow, in that theNjfet region 40 is formed at high concentration, in that thegate electrode 28 is provided in a divided form, and in that theLDD region 44 is formed in the surface portion of theNjfet region 40. - (5) Fifth Embodiment
- FIG. 16 is a schematic cross section showing a fifth embodiment of a semiconductor device according to the invention. A
power MOSFET 7 shown in FIG. 16 is characterized in that it further includes an insulatingfilm 52 formed in a trench TR2 provided with a depth which is approximately the same as diffusion depth of the ptype base layer 14 in an almost center portion in theNjfet region 46 and it further includes anelectrode 54 of a fixed potential provided in the insulatingfilm 52. - By providing the trench TR2 in the
Njfet region 46 sandwiched (or surrounded) by the ptype base layer 14 as described above, ions can be implanted obliquely to the surface of the wafer. Consequently, the highly-dopedNjfet region 46 can be formed in a fine structure on the side walls of the trench TR2. By providing theelectrode 54 via the insulatingfilm 52 in the trench TR2 and fixing the potential of theelectrode 54, the breakdown voltage can be further increased by about 5V and the gate-drain capacitance Qgd can be further reduced by about 20%. - A method of manufacturing the
power MOSFET 7 shown in FIG. 16 will be briefly described with reference to FIGS. 17 through 22. - First, as shown in FIG. 17, an n− type high-
resistance epitaxial layer 50 is formed on the top face of the n+ type low-resistance semiconductor substrate 10 having thedrain electrode 12 on its under face, and a ptype base layer 15 is formed on the top face of the n−type epitaxial layer 50. Subsequently, agate insulating film 26 and thegate electrode 28 are formed on the surface of the ptype base layer 15. After that, thegate electrode 28 is divided into at least two parts. Subsequently, aphotoresist 102 is formed, and n type impurities are selectively implanted between the dividedgate electrodes 28 a, thereby forming a shallow n-type lightly doped drain (LDD)region 48 so that its both ends face the dividedgate electrodes 28 a via the gate insulating film 26 (refer to FIG. 18). By making the ends of theLDD region 48 overlapped with thegate electrode 28 as described above, the gate-drain capacitance Qgd can be suppressed. - After removing the
photoresist 102, an insulating film is deposited on the whole wafer and RIE (Reactive Ion Etching) is executed. By the operation, as shown in FIG. 18, the deposited insulating film can be left only on the side walls of thegate insulating film 26 and thegate electrodes 28 a (side walls 104). As a material of theside walls 104, a conductive material such as polysilicon can be used in place of the insulating film. In this case, thegate electrode 28 a has to be oxidized so as to be insulated from the conductive material by post-oxidation or the like. - Next, as shown in FIG. 19, a
photoresist 106 is formed. By using thephotoresist 106 and theside walls 104 as a mask, the ptype base layer 15 is selectively removed by RIE, thereby forming the trench TR2 with the ends of theLDD region 48 being retained by widths each of which corresponds to that of theside wall 104. Subsequently, n-type impurities are implanted at oblique angles to the wafer as shown by arrows in FIG. 19. Thus, then type region 46 serving as an Njfet region is selectively formed only on the side walls of the trench TR2 (FIG. 20). - Subsequently, as shown in FIG. 21, the
oxide film 52 is formed on the silicon on the surface of the wafer with an oxidizing process. If ions implanted in the side walls of the trench TR2 are, for example, of arsenic, the extent of thermal diffusion is less than in a case of phosphorus and, by speed-increased oxidization, the oxide film in the surface portion of arsenic can be formed thicker than that of the other silicon surface portion. - Further, as shown in FIG. 22, the trench TR2 is buried with the insulating
film 52, or the insulatingfilm 52 and a conductive material. Finally, aninterlayer insulating film 72 and thesource electrode 20 are formed. - By the processes, the size of the gate-drain overlap region below the gate electrode is minimized by the
LDD region 48, and the highly-dopedNjfet region 46 can be formed on the side walls of the trench TR2. By filling the trench TR2 with the insulating film or the conductive material via the insulatingfilm 52 and connecting and fixing theelectrode 54 made of the conductive material to the source potential or other potential, a field plate effect can be expected in theNjfet region 46 of the side walls of the trench TR2. As a result, depletion is promoted. The concentration of theNjfet region 46 of the side walls of the trench TR2 can thus be made higher than that of the drift layer necessary to obtain a breakdown voltage for an ordinary purpose. With the structures, remarkable reduction in the gate-drain capacitance Qgd and the on-state resistance Ron can be realized. - The manufacturing method of the power MOSFET according to the embodiment is not limited to the above described method. For example, in place of the method of preliminarily forming the p
type base layer 15 before dividing thegate electrode 28, p type impurities may be diffused only from the source region after division of thegate electrode 28. Also with respect to the shallow n-type LDD region 48, in place of the method of implanting n type impurities in the self-alignment process so that both ends of theLDD region 48 face thegate electrode 28 a via thegate oxide film 26, theLDD region 48 may be formed by implanting after forming the trench TR or after forming theoxide film 52. In this case, the number of processes of thermal diffusion can be reduced, and the overlap of the gate and drain can be adjusted to the minimum amount. - (6) Sixth Embodiment
- FIG. 23 is a schematic cross section showing a sixth embodiment of a semiconductor device according to the invention. A
power MOSFET 11 shown in FIG. 23 is characterized in that theelectrode 56 formed in the insulatingfilm 52 in the trench TR2 is electrically connected to an upper part of thesource electrode 20. With such a structure, the potential of theelectrode 56 in the trench TR2 can be fixed to the potential of thesource electrode 20. - (7) Seventh Embodiment
- FIG. 24 is a schematic cross section showing a seventh embodiment of a semiconductor device according to the invention. A
power MOSFET 13 shown in the diagram is characterized in that a trench TR4 is formed so deep as to reach the n+type semiconductor substrate 10 so that the n-type highly-dopedregion 56 of the side walls of the trench TR4 is directly connected to the n+type semiconductor substrate 10 and in that the n type highly dopedregion 56 is sandwiched by the insulatingfilm 62 in the trench TR4 and the p− type region 30 on the outside of the trench TR4. - In the foregoing fifth and sixth embodiments, since the trench TR2 is formed with approximate same depth as that of the p-
type base layer 14, theNjfet region 46 on the side walls of the trench also has to be formed with approximate same depth as the depth of the p-type base layer 14 for the following reason. If the trench is too shallow, a current path between the source and the drain is interrupted. On the other hand, if the trench is too deep, the impurity concentration of the n− type drain layer increases. In this case, it is concerned that a depletion layer does not extend and the breakdown voltage decreases. - Since the
power MOSFET 13 of the seventh embodiment employs the structure in which the n type highly-dopedregion 56 serving as the Njfet region is sandwiched by the insulatingfilm 62 in the trench TR4 and the p−type region 30 on the outside of the trench TR4, a current can directly pass to the n+ type low-resistance semiconductor substrate 10 via no n−type drift layers, so that ON-state resistance can be decreased. With the configuration, the n-type highly-dopedregion 56 is therefore easily depleted and the depletion layer extends also to the p−type region 30. As a result, a desired breakdown voltage can be obtained. - FIG. 25 is a schematic cross section showing a modification of the seventh embodiment. A
power MOSFET 17 shown in the diagram has an insulatinglayer 80 formed on the outside of the trench TR4 in place of the p−type region 30 formed on the outside of the trench TR4 in thepower MOSFET 13 shown in FIG. 24. Even with such an insulatinglayer 80, the n type highly-dopedregion 56 on the side walls of the trench is depleted. - Since the third through seventh embodiments employ the structure in which the gate electrode is divided into two or more parts, there may occur a concern about increase in gate resistance. Examples of methods of eliminating such a concern include a method of metallizing the surface of a gate polysilicon electrode with a silicide process and a method of re-connecting the divided parts of the gate electrode in a terrace state in a wiring process to be performed after forming element regions.
- Although the embodiments of the invention have been described above, it is obvious that the invention is not limited to the embodiments but can be variously modified within the scope and the spirit of the invention. For example, the case of selecting the n type as a first conductivity type has been described in the foregoing embodiments. Also when the invention is applied to a p-type channel device in which n and p are opposite to those of the embodiments, similar effects can be obtained.
Claims (21)
1. A semiconductor device comprising:
a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type;
a first main electrode connected to the low-resistance drain layer;
a high-resistance epitaxial layer of the first conductivity type formed on the low-resistance drain layer;
a second-conductivity type base layer selectively formed in a surface portion of the high-resistance epitaxial layer;
a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer;
a jfet layer of the first conductivity type selectively formed in a region sandwiched by the second-conductivity type base layers in a surface portion of the high-resistance epitaxial layer and having impurity concentration higher than that of the high-resistance epitaxial layer;
a gate insulating film formed on at least a part of the surface of said first-conductivity type jfet layer, on the surfaces of the second-conductivity type base layers facing each other across said first-conductivity type jfet layer, and on the surfaces of end portions of the first-conductivity type source layers facing each other across said first-conductivity type jfet layer;
a control electrode formed on the gate insulating film; and
a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode,
wherein assuming that depth of the second-conductivity type base layer is Xj, width L of said first-conductivity type jfet layer in the direction orthogonal to the longitudinal direction of the control electrode is substantially equal to or less than that of an interval between neighboring control electrodes and satisfies the following expression.
L≦Xj×0.7
2. The semiconductor device according to claim 1 , wherein depth of said first-conductivity type jfet layer is substantially same as that of the second-conductivity type base layer.
3. The semiconductor device according to claim 1 , wherein impurity concentration N of said first-conductivity type jfet layer satisfies the following expression.
N≦4E12/L [cm−3]
4. The semiconductor device according to claim 1 , wherein a junction interface between the second-conductivity type base layer and said first-conductivity type jfet layer becomes perpendicular to the surface of the device as it comes close to the surface of the device.
5. The semiconductor device according to claim 1 , wherein at least a part of a region of the gate insulating film facing said first-conductivity type jfet layer is thicker than the other region of the gate insulating film.
6. The semiconductor device according to claim 1 , wherein the gate insulating film and the control electrode are formed by selectively removing a part of a region facing said first-conductivity type jfet layer.
7. The semiconductor device according to claim 6 , wherein said first-conductivity type jfet layer is formed in a self-aligned manner by using the control electrode as a mask.
8. The semiconductor device according to claim 6 , which further comprises a first-conductivity type LDD layer which is formed in a surface portion of said first-conductivity type jfet layer and impurity concentration of which is higher than that of the high-resistance epitaxial layer and is lower than that of said first-conductivity type jfet layer.
9. The semiconductor device according to claim 8 , wherein said first-conductivity type LDD layer is formed in a self-aligned manner by using the control electrode as a mask.
10. The semiconductor device according to claim 6 , wherein surface peak concentration of said first-conductivity type jfet layer is 5E17 [cm−3 ] or less.
11. The semiconductor device according to claim 6 , wherein said first-conductivity type jfet layers each having a rectangular plane shape are disposed at regular intervals in the longitudinal direction of the control electrode, and the second-conductivity type base layer is formed so as to surround each of said first-conductivity type jfet layers.
12. The semiconductor device according to claim 6 , wherein said first-conductivity type jfet layers each having a circular plane shape are disposed at regular intervals in the longitudinal direction of the control electrode, and the second-conductivity type base layer is formed so as to surround each of said first-conductivity type jfet layers.
13. The semiconductor device according to claim 6 , wherein said first-conductivity type jfet layers each having a polygonal plane shape are disposed at regular intervals in the longitudinal direction of the control electrode, and the second-conductivity type base layer is formed so as to surround each of said first-conductivity type jfet layers.
14. A semiconductor device comprising:
a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type;
a first main electrode connected to the low-resistance drain layer;
a high-resistance epitaxial layer of the first conductivity type formed on the low-resistance drain layer;
a second-conductivity type base layer selectively formed in a surface portion of the high-resistance epitaxial layer;
a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer;
a jfet layer of the first conductivity type selectively formed in a region sandwiched by the second-conductivity type base layer in the surface portion of the high-resistance epitaxial layer and having impurity concentration higher than that of the high-resistance epitaxial layer;
a gate insulating film formed on at least a part of the surface of said first-conductivity type jfet layer, on the surfaces of the second-conductivity type base layers facing each other across said first-conductivity type jfet layer, and on the surfaces of end portions of the first-conductivity type source layers facing each other across said first-conductivity type jfet layer;
a control electrode formed on the gate insulating film; and;
a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode,
wherein the second-conductivity type base layers sandwiching said first-conductivity type jfet layer are disposed close to each other so that depletion from the second-conductivity type base layer becomes dominant, and
the gate insulating film and the control electrode are formed by selectively removing a part of a region facing said first-conductivity type jfet layer.
15. The semiconductor device according to claim 14 , which further comprises an insulating layer formed in said first-conductivity type jfet layer.
16. The semiconductor device according to claim 15 , which further comprises an electrode which is formed in the insulating layer so as to be covered with the insulating layer and to which a potential is fixed.
17. The semiconductor device according to claim 16 , wherein an electrode in said first-conductivity type jfet layer is connected to the second main electrode.
18. A semiconductor device comprising:
a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type;
a first main electrode connected to the low-resistance drain layer;
a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer;
a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer;
a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer;
a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate;
a jfet layer of the first conductivity type formed on side walls of said trench;
an insulating layer formed in said trench;
an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to said first-conductivity type jfet layer around a top face of said trench;
a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of said LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across said trench, and on a region of the surface of the second-conductivity type base layer sandwiched by said LDD layer and the first-conductivity type source layer; and
a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.
19. The semiconductor device according to claim 18 , which further comprises an electrode which is formed in said trench so as to be covered with the insulating layer and to which a potential is fixed.
20. A semiconductor device comprising:
a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type;
a first main electrode connected to the low-resistance drain layer;
a first insulating layer formed on the low-resistance drain layer;
a second-conductivity type base layer formed on the first insulating layer;
a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer;
a trench formed so as to extend from the surface of the second-conductivity type base layer to the semiconductor substrate;
a jfet layer of the first conductivity type formed on side walls of said trench;
a second insulating layer formed in said trench;
an LDD layer of the first conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to said jfet layer of the first conductivity type around a top face of said trench;
a control electrode formed so as to be divided into a plurality of parts above the semiconductor substrate, and formed on a gate insulating film formed on a part of the surface of said LDD layer, on surfaces of end portions of the first-conductivity type source layer facing each other across said trench, and on a region of the second-conductivity type base layer sandwiched by said LDD layer and the first-conductivity type source layer; and
a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.
21. The semiconductor device according to claim 20 , which further comprises an electrode which is formed in the second insulating layer so as to be covered with the second insulating layer and to which a potential is fixed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/118,159 US7663186B2 (en) | 2002-03-29 | 2008-05-09 | Semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002-094361 | 2002-03-29 | ||
JP2002094361A JP3906105B2 (en) | 2002-03-29 | 2002-03-29 | Semiconductor device |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/118,159 Division US7663186B2 (en) | 2002-03-29 | 2008-05-09 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
US20030227052A1 true US20030227052A1 (en) | 2003-12-11 |
Family
ID=28786180
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/400,625 Abandoned US20030227052A1 (en) | 2002-03-29 | 2003-03-28 | Semiconductor device |
US12/118,159 Expired - Fee Related US7663186B2 (en) | 2002-03-29 | 2008-05-09 | Semiconductor device |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/118,159 Expired - Fee Related US7663186B2 (en) | 2002-03-29 | 2008-05-09 | Semiconductor device |
Country Status (3)
Country | Link |
---|---|
US (2) | US20030227052A1 (en) |
JP (1) | JP3906105B2 (en) |
CN (1) | CN1244160C (en) |
Cited By (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050116298A1 (en) * | 2003-11-07 | 2005-06-02 | Jenoe Tihanyi | MOS field effect transistor with small miller capacitance |
WO2005045937A3 (en) * | 2003-11-06 | 2005-08-11 | Koninkl Philips Electronics Nv | Insulated gate field-effect transistor |
US20060102908A1 (en) * | 2004-11-16 | 2006-05-18 | Seiji Imai | Semiconductor device |
US20060113614A1 (en) * | 2004-11-06 | 2006-06-01 | Yoo In-Kyeong | Nonvolatile memory device and method including resistor and transistor |
US20060192256A1 (en) * | 2005-01-21 | 2006-08-31 | Cooper James A | High-voltage power semiconductor device |
US20060220122A1 (en) * | 2005-03-17 | 2006-10-05 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20070072352A1 (en) * | 2005-09-29 | 2007-03-29 | Sanyo Electric Co., Ltd. | Insulated gate field effect transistor and manufacturing method thereof |
EP1770787A2 (en) * | 2005-10-03 | 2007-04-04 | AMI Semiconductor Belgium BVBA | Semiconductor device with a MOS transistor and method of manufacturing the same |
US20070134853A1 (en) * | 2005-12-09 | 2007-06-14 | Lite-On Semiconductor Corp. | Power semiconductor device having reduced on-resistance and method of manufacturing the same |
EP1703567A3 (en) * | 2005-03-17 | 2008-07-02 | Sanyo Electric Co., Ltd. | Insulated gate field-effect transistor and method of making the same |
US20080265291A1 (en) * | 2007-04-30 | 2008-10-30 | Freescale Semiconductor, Inc. | Mosfet device including a source with alternating p-type and n-type regions |
US20090050961A1 (en) * | 2005-04-13 | 2009-02-26 | Rohm Co., Ltd. | Semiconductor Device |
US20090085111A1 (en) * | 2007-09-27 | 2009-04-02 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
WO2011056407A1 (en) | 2009-11-03 | 2011-05-12 | Cree, Inc. | Power semiconductor devices having selectively doped jfet regions and related methods of forming such devices |
US20120248531A1 (en) * | 2011-03-31 | 2012-10-04 | Semiconductor Components Industries, L.L.C. | Insulated gate semiconductor device |
US20130020637A1 (en) * | 2008-12-10 | 2013-01-24 | Juame Roig-Guitart | Electronic device and a transistor including a trench and a sidewall doped region |
US20130299764A1 (en) * | 2012-05-11 | 2013-11-14 | Globalfoundries Singapore Pte. Ltd. | Localized device |
US20130320432A1 (en) * | 2012-06-01 | 2013-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical Power MOSFET and Methods of Forming the Same |
KR101430824B1 (en) * | 2012-06-01 | 2014-08-18 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Vertical power mosfet and methods of forming the same |
KR101469343B1 (en) * | 2012-06-01 | 2014-12-04 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Vertical power mosfet and methods of forming the same |
US20140367771A1 (en) * | 2013-06-18 | 2014-12-18 | Monolith Semiconductor, Inc. | High voltage semiconductor devices and methods of making the devices |
US20160093733A1 (en) * | 2013-09-20 | 2016-03-31 | Monolith Semiconductor Inc. | High voltage mosfet devices and methods of making the devices |
US20160104792A1 (en) * | 2013-09-20 | 2016-04-14 | Monolith Semiconductor Inc. | High voltage mosfet devices and methods of making the devices |
US9537002B2 (en) | 2012-03-30 | 2017-01-03 | Fuji Electric Co., Ltd. | Semiconductor device with SiC base layer |
EP3089216A4 (en) * | 2013-12-23 | 2017-10-11 | Zhongshan Hkg Technologies Limited | Split-gate power semiconductor field-effect transistor |
WO2017205437A1 (en) * | 2016-05-23 | 2017-11-30 | General Electric Company | Electric field shielding in silicon carbide metal-oxide-semiconductor (mos) devices having an optimization layer |
US10062759B2 (en) | 2013-03-29 | 2018-08-28 | Hitachi, Ltd. | Silicon carbide semiconductor device and method for manufacturing same |
DE102014116503B4 (en) | 2013-11-14 | 2021-11-18 | Infineon Technologies Ag | Transistor and tunable inductor |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6903421B1 (en) * | 2004-01-16 | 2005-06-07 | System General Corp. | Isolated high-voltage LDMOS transistor having a split well structure |
JP4620368B2 (en) * | 2004-03-08 | 2011-01-26 | 三菱電機株式会社 | Manufacturing method of semiconductor device |
JP4832731B2 (en) * | 2004-07-07 | 2011-12-07 | 株式会社東芝 | Power semiconductor device |
JP4620564B2 (en) * | 2005-10-03 | 2011-01-26 | 三菱電機株式会社 | Semiconductor device |
US7378317B2 (en) * | 2005-12-14 | 2008-05-27 | Freescale Semiconductor, Inc. | Superjunction power MOSFET |
EP2052414B1 (en) | 2006-08-17 | 2016-03-30 | Cree, Inc. | High power insulated gate bipolar transistors |
JP2008135474A (en) * | 2006-11-27 | 2008-06-12 | Rohm Co Ltd | Semiconductor device |
JP5098489B2 (en) * | 2007-07-27 | 2012-12-12 | 住友電気工業株式会社 | Manufacturing method of oxide field effect transistor |
US20100314695A1 (en) * | 2009-06-10 | 2010-12-16 | International Rectifier Corporation | Self-aligned vertical group III-V transistor and method for fabricated same |
JP2012156544A (en) * | 2012-04-11 | 2012-08-16 | Rohm Co Ltd | Semiconductor device and method for manufacturing the same |
CN106158665B (en) * | 2015-04-23 | 2019-06-11 | 北大方正集团有限公司 | The preparation method and field effect transistor of field effect transistor |
CN106298892A (en) * | 2015-05-27 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of VDMOS device |
JP6696166B2 (en) * | 2015-08-19 | 2020-05-20 | 富士電機株式会社 | Semiconductor device and manufacturing method |
JP6624300B2 (en) * | 2016-10-17 | 2019-12-25 | 富士電機株式会社 | Semiconductor device |
KR102554414B1 (en) | 2018-11-01 | 2023-07-11 | 삼성전자주식회사 | power device |
CN113506829A (en) * | 2021-07-05 | 2021-10-15 | 西安卫光科技有限公司 | Step gate dielectric layer structure and manufacturing method thereof |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4455565A (en) * | 1980-02-22 | 1984-06-19 | Rca Corporation | Vertical MOSFET with an aligned gate electrode and aligned drain shield electrode |
US4974059A (en) * | 1982-12-21 | 1990-11-27 | International Rectifier Corporation | Semiconductor high-power mosfet device |
US5814859A (en) * | 1995-03-20 | 1998-09-29 | General Electric Company | Self-aligned transistor device including a patterned refracting dielectric layer |
US6455892B1 (en) * | 1999-09-21 | 2002-09-24 | Denso Corporation | Silicon carbide semiconductor device and method for manufacturing the same |
US6693323B2 (en) * | 1999-10-21 | 2004-02-17 | Fuji Electric Co., Ltd. | Super-junction semiconductor device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59167066A (en) | 1983-03-14 | 1984-09-20 | Nissan Motor Co Ltd | Vertical type metal oxide semiconductor field effect transistor |
JPS645070U (en) | 1987-06-24 | 1989-01-12 | ||
JP2771172B2 (en) | 1988-04-01 | 1998-07-02 | 日本電気株式会社 | Vertical field-effect transistor |
JP3166148B2 (en) | 1995-07-11 | 2001-05-14 | 横河電機株式会社 | Semiconductor device |
JP3436220B2 (en) | 1999-12-08 | 2003-08-11 | 株式会社豊田中央研究所 | Vertical semiconductor device |
US6784486B2 (en) * | 2000-06-23 | 2004-08-31 | Silicon Semiconductor Corporation | Vertical power devices having retrograded-doped transition regions therein |
-
2002
- 2002-03-29 JP JP2002094361A patent/JP3906105B2/en not_active Expired - Lifetime
-
2003
- 2003-03-28 US US10/400,625 patent/US20030227052A1/en not_active Abandoned
- 2003-03-31 CN CNB031086152A patent/CN1244160C/en not_active Expired - Fee Related
-
2008
- 2008-05-09 US US12/118,159 patent/US7663186B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4455565A (en) * | 1980-02-22 | 1984-06-19 | Rca Corporation | Vertical MOSFET with an aligned gate electrode and aligned drain shield electrode |
US4974059A (en) * | 1982-12-21 | 1990-11-27 | International Rectifier Corporation | Semiconductor high-power mosfet device |
US5814859A (en) * | 1995-03-20 | 1998-09-29 | General Electric Company | Self-aligned transistor device including a patterned refracting dielectric layer |
US6455892B1 (en) * | 1999-09-21 | 2002-09-24 | Denso Corporation | Silicon carbide semiconductor device and method for manufacturing the same |
US6693323B2 (en) * | 1999-10-21 | 2004-02-17 | Fuji Electric Co., Ltd. | Super-junction semiconductor device |
Cited By (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070080379A1 (en) * | 2003-11-06 | 2007-04-12 | Koninklijke Philips Electronics N.V. | Insulated gate field effect transistor |
WO2005045937A3 (en) * | 2003-11-06 | 2005-08-11 | Koninkl Philips Electronics Nv | Insulated gate field-effect transistor |
US7642596B2 (en) * | 2003-11-06 | 2010-01-05 | Nxp B.V. | Insulated gate field effect transistor |
US20050116298A1 (en) * | 2003-11-07 | 2005-06-02 | Jenoe Tihanyi | MOS field effect transistor with small miller capacitance |
US20060113614A1 (en) * | 2004-11-06 | 2006-06-01 | Yoo In-Kyeong | Nonvolatile memory device and method including resistor and transistor |
US7821809B2 (en) | 2004-11-06 | 2010-10-26 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method including resistor and transistor |
US20060102908A1 (en) * | 2004-11-16 | 2006-05-18 | Seiji Imai | Semiconductor device |
US7569900B2 (en) * | 2004-11-16 | 2009-08-04 | Kabushiki Kaisha Toshiba | Silicon carbide high breakdown voltage semiconductor device |
US20060192256A1 (en) * | 2005-01-21 | 2006-08-31 | Cooper James A | High-voltage power semiconductor device |
US7498633B2 (en) * | 2005-01-21 | 2009-03-03 | Purdue Research Foundation | High-voltage power semiconductor device |
US8133788B2 (en) * | 2005-03-17 | 2012-03-13 | Semiconductor Components Industries, Llc | Method of manufacturing semiconductor device |
EP1703567A3 (en) * | 2005-03-17 | 2008-07-02 | Sanyo Electric Co., Ltd. | Insulated gate field-effect transistor and method of making the same |
US20100015772A1 (en) * | 2005-03-17 | 2010-01-21 | Sanyo Electric Co., Ltd. | Method of manufacturing semiconductor device |
US20060220122A1 (en) * | 2005-03-17 | 2006-10-05 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20090050961A1 (en) * | 2005-04-13 | 2009-02-26 | Rohm Co., Ltd. | Semiconductor Device |
US20070072352A1 (en) * | 2005-09-29 | 2007-03-29 | Sanyo Electric Co., Ltd. | Insulated gate field effect transistor and manufacturing method thereof |
EP1770787A2 (en) * | 2005-10-03 | 2007-04-04 | AMI Semiconductor Belgium BVBA | Semiconductor device with a MOS transistor and method of manufacturing the same |
EP1770787A3 (en) * | 2005-10-03 | 2008-06-04 | AMI Semiconductor Belgium BVBA | Semiconductor device with a MOS transistor and method of manufacturing the same |
US20070134853A1 (en) * | 2005-12-09 | 2007-06-14 | Lite-On Semiconductor Corp. | Power semiconductor device having reduced on-resistance and method of manufacturing the same |
WO2008137261A1 (en) * | 2007-04-30 | 2008-11-13 | Freescale Semiconductor Inc. | Mosfet device including a source with alternating p-type and n-type regions |
US20080265291A1 (en) * | 2007-04-30 | 2008-10-30 | Freescale Semiconductor, Inc. | Mosfet device including a source with alternating p-type and n-type regions |
US7851889B2 (en) | 2007-04-30 | 2010-12-14 | Freescale Semiconductor, Inc. | MOSFET device including a source with alternating P-type and N-type regions |
US20090085111A1 (en) * | 2007-09-27 | 2009-04-02 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US8648398B2 (en) * | 2008-12-10 | 2014-02-11 | Semiconductor Components Industries, Llc | Electronic device and a transistor including a trench and a sidewall doped region |
US20130020637A1 (en) * | 2008-12-10 | 2013-01-24 | Juame Roig-Guitart | Electronic device and a transistor including a trench and a sidewall doped region |
WO2011056407A1 (en) | 2009-11-03 | 2011-05-12 | Cree, Inc. | Power semiconductor devices having selectively doped jfet regions and related methods of forming such devices |
EP2497116A1 (en) * | 2009-11-03 | 2012-09-12 | Cree, Inc. | Power semiconductor devices having selectively doped jfet regions and related methods of forming such devices |
EP2497116A4 (en) * | 2009-11-03 | 2014-06-18 | Cree Inc | Power semiconductor devices having selectively doped jfet regions and related methods of forming such devices |
US20120248531A1 (en) * | 2011-03-31 | 2012-10-04 | Semiconductor Components Industries, L.L.C. | Insulated gate semiconductor device |
US8779507B2 (en) * | 2011-03-31 | 2014-07-15 | Semiconductor Components Industries, Llc | Insulated gate semiconductor device |
US9537002B2 (en) | 2012-03-30 | 2017-01-03 | Fuji Electric Co., Ltd. | Semiconductor device with SiC base layer |
US20130299764A1 (en) * | 2012-05-11 | 2013-11-14 | Globalfoundries Singapore Pte. Ltd. | Localized device |
US9673297B2 (en) | 2012-06-01 | 2017-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical power MOSFET and methods of forming the same |
KR101430824B1 (en) * | 2012-06-01 | 2014-08-18 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Vertical power mosfet and methods of forming the same |
US8884369B2 (en) | 2012-06-01 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical power MOSFET and methods of forming the same |
KR101469343B1 (en) * | 2012-06-01 | 2014-12-04 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Vertical power mosfet and methods of forming the same |
US10141421B2 (en) | 2012-06-01 | 2018-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical power MOSFET and methods of forming the same |
US9087920B2 (en) * | 2012-06-01 | 2015-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical power MOSFET and methods of forming the same |
US20130320432A1 (en) * | 2012-06-01 | 2013-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical Power MOSFET and Methods of Forming the Same |
US9892974B2 (en) | 2012-06-01 | 2018-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical power MOSFET and methods of forming the same |
DE102012109921B4 (en) * | 2012-06-01 | 2016-05-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vertical power MOSFET and method of making the same |
US10062759B2 (en) | 2013-03-29 | 2018-08-28 | Hitachi, Ltd. | Silicon carbide semiconductor device and method for manufacturing same |
DE112013006715B4 (en) | 2013-03-29 | 2022-10-13 | Hitachi Power Semiconductor Device, Ltd. | Silicon carbide semiconductor device and method of manufacturing the same |
US10062749B2 (en) * | 2013-06-18 | 2018-08-28 | Monolith Semiconductor Inc. | High voltage semiconductor devices and methods of making the devices |
US20140367771A1 (en) * | 2013-06-18 | 2014-12-18 | Monolith Semiconductor, Inc. | High voltage semiconductor devices and methods of making the devices |
US20160104792A1 (en) * | 2013-09-20 | 2016-04-14 | Monolith Semiconductor Inc. | High voltage mosfet devices and methods of making the devices |
US9991376B2 (en) * | 2013-09-20 | 2018-06-05 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
US20160093733A1 (en) * | 2013-09-20 | 2016-03-31 | Monolith Semiconductor Inc. | High voltage mosfet devices and methods of making the devices |
US9853147B2 (en) * | 2013-09-20 | 2017-12-26 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
US10361302B2 (en) | 2013-09-20 | 2019-07-23 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
US10692999B2 (en) | 2013-09-20 | 2020-06-23 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
DE102014116503B4 (en) | 2013-11-14 | 2021-11-18 | Infineon Technologies Ag | Transistor and tunable inductor |
EP3089216A4 (en) * | 2013-12-23 | 2017-10-11 | Zhongshan Hkg Technologies Limited | Split-gate power semiconductor field-effect transistor |
US10388737B2 (en) | 2016-05-23 | 2019-08-20 | General Electric Company | Electric field shielding in silicon carbide metal-oxide-semiconductor (MOS) devices having an optimization layer |
WO2017205437A1 (en) * | 2016-05-23 | 2017-11-30 | General Electric Company | Electric field shielding in silicon carbide metal-oxide-semiconductor (mos) devices having an optimization layer |
Also Published As
Publication number | Publication date |
---|---|
US20080251838A1 (en) | 2008-10-16 |
JP2003298052A (en) | 2003-10-17 |
US7663186B2 (en) | 2010-02-16 |
JP3906105B2 (en) | 2007-04-18 |
CN1244160C (en) | 2006-03-01 |
CN1449058A (en) | 2003-10-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7663186B2 (en) | Semiconductor device | |
EP0788659B1 (en) | High voltage lateral dmos device with enhanced drift region | |
EP0616372B1 (en) | Short channel trenched DMOS transistor | |
US9450091B2 (en) | Semiconductor device with enhanced mobility and method | |
EP0763259B1 (en) | Punch-through field effect transistor | |
US7361558B2 (en) | Method of manufacturing a closed cell trench MOSFET | |
US7858478B2 (en) | Method for producing an integrated circuit including a trench transistor and integrated circuit | |
US7635621B2 (en) | Lateral double-diffused metal oxide semiconductor (LDMOS) device with an enhanced drift region that has an improved Ron area product | |
JP4198469B2 (en) | Power device and manufacturing method thereof | |
EP2362423B1 (en) | Vertical power semiconductor device | |
EP0654173B1 (en) | High density power device structure and fabrication process | |
US6849900B2 (en) | Semiconductor device | |
US7276405B2 (en) | Power semiconductor device having high breakdown voltage, low on-resistance and small switching loss and method of forming the same | |
US20160211366A1 (en) | Lateral double diffused mos transistors | |
KR20010112439A (en) | A super-self-aligned trench-gate dmos with reduced on-resistance | |
JPH09219512A (en) | Mos field-effect transistor and manufacture thereof | |
JP2005510059A (en) | Field effect transistor semiconductor device | |
US20060240625A1 (en) | Power semiconductor device having improved performance and method | |
US9178054B2 (en) | Planar vertical DMOS transistor with reduced gate charge | |
EP0915509B1 (en) | Process for integrating, in a same semiconductor chip, MOS technology devices with different threshold voltages | |
KR20000051294A (en) | DMOS field effect transistor with improved electrical characteristics and fabricating method thereof | |
US5451536A (en) | Power MOSFET transistor | |
KR20000014215A (en) | Method for manufacturing the reliable lateral transistor | |
KR19990050418A (en) | Power Device with Double Field Plate Structure | |
US20020195654A1 (en) | DMOS transistor and fabricating method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ONO, SYOTARO;YAMAGUCHI, YOSHIHIRO;KAWAGUCHI, YUSUKE;AND OTHERS;REEL/FRAME:014304/0199;SIGNING DATES FROM 20030506 TO 20030507 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |