US20040056356A1 - Methods and apparatus for forming a film on a substrate - Google Patents

Methods and apparatus for forming a film on a substrate Download PDF

Info

Publication number
US20040056356A1
US20040056356A1 US10/618,636 US61863603A US2004056356A1 US 20040056356 A1 US20040056356 A1 US 20040056356A1 US 61863603 A US61863603 A US 61863603A US 2004056356 A1 US2004056356 A1 US 2004056356A1
Authority
US
United States
Prior art keywords
layer
etch stop
nitrogen
etch
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/618,636
Inventor
John MacNeil
Robert Wilby
Knut Beekman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US10/618,636 priority Critical patent/US20040056356A1/en
Publication of US20040056356A1 publication Critical patent/US20040056356A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/36—Carbonitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3148—Silicon Carbide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31633—Deposition of carbon doped silicon oxide, e.g. SiOC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1031—Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/931—Silicon carbide semiconductor

Definitions

  • This invention relates to methods and apparatus for forming films on a substrate and in particular, but not exclusively, to forming low k etch stop films and devices containing such films.
  • low k refers to dielectric constants of 3.5 or less.
  • Damascene and dual damascene processing is becoming more prevalent in the manufacture of semiconductor wafers and in particular where copper is used as the interconnect metal. This is because the plasma etching of copper is relatively difficult and it is therefore preferred to etch formations in the dielectric layer and then deposit copper into the etched structure to fill it. Any excess copper can then be removed from the surface for example by chemical mechanical polishing leaving an inlay of copper in the etched features.
  • a common approach to creating dual damascene features is to deposit an etch stop layer between the two layers of dielectric so that the etch stop layer gives a good “end point” signal to the automated etching equipment as it breaks through the first layer.
  • Such closed loop control is preferred because it enables more precise control of the etched features than an open loop timed etch.
  • the etch stop layer therefore tends to need to have a relatively high selectivity for the etch process relative to the upper layer so that it is etched significantly more slowly giving time for control to take place.
  • silicon nitride has been used as an etch stop layer in association with a silicon dioxide type layer, however such silicon nitride would usually have a k value of about 7.5 compared to a standard silicon dioxide k value of 4.1 and the perceived low k requirement that k is less than 3.5.
  • Silicon carbide has been proposed as an alternative etch stop material but its k value is 9 to 10 and this still results in significant increases in the k value of the dielectric stack.
  • Silicon nitride layers have also been found to be problematic in that they create a good water barrier and many low k processes rely on water being able to be forced out of the dielectric layer during processing.
  • the invention consists in a semiconductor device including a dual damascene structure formed in a dielectric stack, the stack comprising an upper layer having first formation etched therein, an intermediate etch stop layer and a lower layer having a second formation etch therein, the second formation being contiguous with the first, each of the layers having a dielectric constant k ⁇ 3.5 and more preferably below 3.0 and the etch stop layer having a selectivity of at east 2.5:1 relative to the upper layer.
  • the etch stop layer is integral with the lower layer and it is particularly preferred that the etch stop layer is formed of nitrogen doped silicon carbide.
  • the k value of the etch stop layer is substantially equal to that of the other layers in the stack. Surprisingly, it has been found that the k value of the nitrogen doped silicon carbide can be adjusted depending on the amount of nitrogen doping which takes place. It is therefore, at least to an extent, possible to match the k value of the etch stop layer, with that of the other dielectric layers.
  • the etch stop layer may be integral with the lower layer, because the k value of the nitrogen doped silicon carbide is sufficiently low to be a low k dielectric material in its own right.
  • the invention consists in a low k dielectric layer formed of nitrogen doped silicon carbide.
  • the invention consists in a method of forming a low k film on a substrate comprising:
  • the silicon containing organic compound may be an alkylsilane and more specifically it may be tetraalkylsilane. It is particularly preferred that the silicon containing organic compound is tetramethylsilane.
  • the film may be deposited on a substrate positioned at or below room temperature and RF power may be supplied during the deposition of the film.
  • FIG. 1 is a schematic view of an apparatus for use in the present invention
  • FIGS. 2 to 4 are graphs illustrating the detectability of etch stop layers formed in accordance with the invention when located in the dielectric stack.
  • FIGS. 5 ( a ) to ( e ) schematically illustrate the formation of a wiring channel and associated via.
  • FIG. 1 there is shown, generally indicated at 1 , an apparatus which includes a vacuum chamber 2 having a showerhead 3 and a wafer support or platen 4 .
  • the showerhead 3 is connected to an RF scurce (not shown) to form one electrode, whilst the support 4 may be earthed to form another electrode. Alternatively, the RF source could be connected to the support 4 and the showerhead 3 earthed.
  • the showerhead 3 is connected by pipes (not shown) to respective sources of tetramethylsilane and another gas or gases.
  • the apparatus is generally of the form disclosed in EP-A-0731982, which is incorporated herein by reference. However, a standard (non-duplex) showerhead is normally used.
  • the apparatus can in fact be arranged to deposit a variety of layers depending on the nature of the other gas supplied.
  • the other gas is oxygen or an oxygen containing gas, then a low k carbon doped silicon dioxide layer can be formed.
  • the other gas is nitrogen then depending on the flow rate of the nitrogen, anything from a pure silicon carbide layer (with virtually no nitrogen present) to a carbon doped silicon nitride layer (with a high nitrogen flow) can be formed.
  • nitrogen-doped silicon carbide films can be formed which have a k value similar to or equal to the carbon-doped silicon dioxide layer mentioned above.
  • a dielectric stack consisting of carbon doped silicon dioxide layer, a nitrogen doped silicon carbide layer and a carbon doped silicon dioxide layer.
  • the stack is therefore not only particularly desirable from a low k point of view, it can also be simply formed in a manner which allows high throughput.
  • etch stop layer in one experiment a particularly effective etch stop layer was developed by forming what may be considered as a methyl doped silicon carbide/nitride with a k value of approximately 2.6. It was found if the carbon to nitrogen ratio was reduced to form more of a carbon doped silicon nitride then the k value increased to approximately 4.6. There was no hard transition point between the two materials. Greater additions of nitrogen to the process gas increase the nitrogen to carbon ratio such that at one extreme (no nitrogen) material can be considered silicon carbide and at the other carbon containing silicon nitride. All films contained hydrogen.
  • the low k nitrogen doped silicon carbide had a k value precisely equal to the low k carbon doped silicon dioxide formed as described above.
  • the RF power was applied by 380 Khz generator to the showerhead electrode and the platen was maintained at room temperature or below. Temperatures below 0° C. may be useful to the process, but in general the process has been run at room temperature or between 0° C. and room temperature.
  • TMS tetramethylsilane
  • the nitrogen-doped SiC(N) material is preferable as a low k etch stop material to carbon-doped silicon nitride.
  • Stacked structures were then constructed using the deposition process essentially as set out above but including a hydrogen plasma treatment of the type disclosed in our co-pending British Patent Application No. 9922801.7 which is incorporated herein by reference.
  • This hydrogen plasma treatment improves the low k film properties, e.g. reducing BOE wet etch rate from over 10,000 ⁇ /min to the same order as that of a thermal oxide (about 550 ⁇ /min), reducing hydrogen and carbon content, apparently increasing density and reducing the film's water absorption properties whilst reducing the likelihood of cracking.
  • the resultant stacks consisted of two 7000 ⁇ layers of SiO 2 (C) separated by a 500 ⁇ layer of SiC(N). Each of the silicon dioxide layers had been hydrogen plasma treated.
  • Etch experiments were run for different times and the output of an end point detector was recorded. As is commonly used for such experiments, the end point detector monitored the light intensity on the 440 nm emission line. The output from the end point detector is shown in FIGS. 2 and 3 . (The vertical axis of FIGS. 3 to 4 indicate increasing signal intensity in arbitrary units).
  • the etching characteristics of the SiN are inferior to those of the low k SiC material. Patterning or the absence of patterning does not make a significant difference to the selectivity of the low k SiO 2 (C) to the SiC(N). In the case where there was no photoresist the ratio was 2.9:1, whilst in these two experiments values of 3.01:1 and 2.92:1 were obtained giving an approximate value of 3:1.
  • This etch selectivity combined with the very acceptable uniformity figures indicates that SiC(N) is a useful etch stop material and the figures indicate that end point signals of useful clarity are generated at the 440 nm line.
  • the SiC(N) material has desirable properties as a low k dielectric in its own right and this leads to the possibility of a two layer stack with no separate distinct “etch stop” layer. Indeed stacks can be built of layers of materials having similar k values but with sufficiently different etch characteristics that the transition between layers can be detected and automatic processing achieved.
  • a particular example of an application which can benefit from the use of two low k materials, without the use of an etch stop layer, is the formation of a low k bi-layer for dual damascene applications.
  • one layer is used for the formation of vias, whilst the other defines the overlying trenches.
  • a “trench first” scheme could use the faster etching SiO 2 (C) overlying slower etching layer in which the vias was formed.
  • the trench pattern could be formed upon its surface by lithography and the trench pattern etched.
  • An end point signal would be produced when the underlying material was reached and a timed over-etch carried out.
  • the etch mask e.g. a photoresist
  • the vias would then be etched in the underlying low-k layer.
  • FIG. 5 illustrates at (a) to (e) a method of forming a wiring channel and via combination which utilises the differences in etch rate that can be obtained for the materials discussed above, whilst utilising their good low k characteristics.
  • the method described is particularly advantageous in that it removes the need for lithography and mask formation for the vias at the bottom of the wiring channel. As the wiring becomes narrower and narrower the masking of the bottom of the channel becomes more and more challenging.
  • FIG. 5( a ) a first layer of low k insulating material 10 is deposited on a substrate 11 and a via is part etched in the surface of that material as indicated at 12 . At this time the etching of the via formation 11 is relatively straightforward because the whole surface of the layer 10 is exposed.
  • a second conformal layer 13 is deposited so that it fills the formation 12 but this formation is then reflected at the surface of the layer 13 as shown at 14 . The upper surface of 13 is then masked with the desired wiring pattern and FIG. 5( c ) shows the part etching of the wiring channel 15 .
  • Material 11 can conveniently also provide the etch stop signal in the manner postulated above.
  • the carbon-doped silicon nitride and carbon-doped silicon dioxide provide an etch rate ratio or selectivity of approximately 2:1 whereas, as has been mentioned before, the selectivity of silicon dioxide to nitrogen-doped silicon carbide is approximately 3:1. Adjustment of doping can provide other selectivities.

Abstract

This invention relates semiconductor devices incorporating an intermediate etch stop layer between two dielectric layers in which the dielectric constant of each of the layers is k≦3.5 and the etch stop layer has a selectivity of at least 2.5:1 relative to the upper layer. Methods and apparatus for forming nitrogen doped silicon carbide films, for example, for use as etch stop layers are described.

Description

  • This invention relates to methods and apparatus for forming films on a substrate and in particular, but not exclusively, to forming low k etch stop films and devices containing such films. For the purposes of this specification the term low k refers to dielectric constants of 3.5 or less. [0001]
  • Damascene and dual damascene processing is becoming more prevalent in the manufacture of semiconductor wafers and in particular where copper is used as the interconnect metal. This is because the plasma etching of copper is relatively difficult and it is therefore preferred to etch formations in the dielectric layer and then deposit copper into the etched structure to fill it. Any excess copper can then be removed from the surface for example by chemical mechanical polishing leaving an inlay of copper in the etched features. [0002]
  • In dual damascene processing two separate but connected features are etched in respective dielectric layers one line above the other. Thus a trench may be cut in the upper layer and vias may be formed in the lower layer to connect the trench to contact points in an underlying layer. Examples of such structures are discussed in an article entitled Dual Damascene Challenges, Dielectric Etch by Peter Singer in the August 1999 edition of Semiconductor International. [0003]
  • A common approach to creating dual damascene features is to deposit an etch stop layer between the two layers of dielectric so that the etch stop layer gives a good “end point” signal to the automated etching equipment as it breaks through the first layer. Such closed loop control is preferred because it enables more precise control of the etched features than an open loop timed etch. [0004]
  • The etch stop layer therefore tends to need to have a relatively high selectivity for the etch process relative to the upper layer so that it is etched significantly more slowly giving time for control to take place. [0005]
  • Commonly, these days, it is desirable that the whole dielectric structure has a low k value and this leads one to the desire to have an etch stop layer which also has a low k value. [0006]
  • Additionally a silane-based plasma-formed silicon nitride has been used as an etch stop layer in association with a silicon dioxide type layer, however such silicon nitride would usually have a k value of about 7.5 compared to a standard silicon dioxide k value of 4.1 and the perceived low k requirement that k is less than 3.5. Silicon carbide has been proposed as an alternative etch stop material but its k value is 9 to 10 and this still results in significant increases in the k value of the dielectric stack. Silicon nitride layers have also been found to be problematic in that they create a good water barrier and many low k processes rely on water being able to be forced out of the dielectric layer during processing. [0007]
  • Further, current silicon nitride technology is not necessarily compatible with the chemistry used to form the low k layers. [0008]
  • A discussion of these problems is contained in WO-A-99/41423, but the conclusion of that patent application is that a good etch stop layer for this situation should have a significant oxide content. A large number of proposed solutions are set out but they appear to require stacks of layers having significantly different k values. [0009]
  • From one aspect the invention consists in a semiconductor device including a dual damascene structure formed in a dielectric stack, the stack comprising an upper layer having first formation etched therein, an intermediate etch stop layer and a lower layer having a second formation etch therein, the second formation being contiguous with the first, each of the layers having a dielectric constant k ≦3.5 and more preferably below 3.0 and the etch stop layer having a selectivity of at east 2.5:1 relative to the upper layer. [0010]
  • Preferably the etch stop layer is integral with the lower layer and it is particularly preferred that the etch stop layer is formed of nitrogen doped silicon carbide. [0011]
  • In a particularly preferred arrangement the k value of the etch stop layer is substantially equal to that of the other layers in the stack. Surprisingly, it has been found that the k value of the nitrogen doped silicon carbide can be adjusted depending on the amount of nitrogen doping which takes place. It is therefore, at least to an extent, possible to match the k value of the etch stop layer, with that of the other dielectric layers. [0012]
  • As has already been indicated above, that the etch stop layer may be integral with the lower layer, because the k value of the nitrogen doped silicon carbide is sufficiently low to be a low k dielectric material in its own right. [0013]
  • Thus from a second aspect the invention consists in a low k dielectric layer formed of nitrogen doped silicon carbide. [0014]
  • From a further aspect the invention consists in a method of forming a low k film on a substrate comprising: [0015]
  • (a) positioning the substrate on a support in a chamber; and [0016]
  • (b) supplying to the chamber, in gaseous or vapour form, a silicon-containing organic compound and nitrogen in the presence of a plasma to deposit a nitrogen coped silicon carbide film on the substrate. [0017]
  • The silicon containing organic compound may be an alkylsilane and more specifically it may be tetraalkylsilane. It is particularly preferred that the silicon containing organic compound is tetramethylsilane. [0018]
  • The film may be deposited on a substrate positioned at or below room temperature and RF power may be supplied during the deposition of the film. [0019]
  • Although the invention has been defined above it is to be understood it includes any inventive combination of the features set out above or in the following description.[0020]
  • The invention may be performed in various ways and specific embodiments will now be described, by way of example, with reference to the following drawings in which; [0021]
  • FIG. 1 is a schematic view of an apparatus for use in the present invention; [0022]
  • FIGS. [0023] 2 to 4 are graphs illustrating the detectability of etch stop layers formed in accordance with the invention when located in the dielectric stack; and
  • FIGS. [0024] 5(a) to (e) schematically illustrate the formation of a wiring channel and associated via.
  • Referring to FIG. 1, there is shown, generally indicated at [0025] 1, an apparatus which includes a vacuum chamber 2 having a showerhead 3 and a wafer support or platen 4. The showerhead 3 is connected to an RF scurce (not shown) to form one electrode, whilst the support 4 may be earthed to form another electrode. Alternatively, the RF source could be connected to the support 4 and the showerhead 3 earthed. The showerhead 3 is connected by pipes (not shown) to respective sources of tetramethylsilane and another gas or gases. The apparatus is generally of the form disclosed in EP-A-0731982, which is incorporated herein by reference. However, a standard (non-duplex) showerhead is normally used.
  • In use, the apparatus can in fact be arranged to deposit a variety of layers depending on the nature of the other gas supplied. Thus if the other gas is oxygen or an oxygen containing gas, then a low k carbon doped silicon dioxide layer can be formed. If on the other hand the other gas is nitrogen then depending on the flow rate of the nitrogen, anything from a pure silicon carbide layer (with virtually no nitrogen present) to a carbon doped silicon nitride layer (with a high nitrogen flow) can be formed. The applicants have discovered that by suitable adjustment of the nitrogen flow rate, nitrogen-doped silicon carbide films can be formed which have a k value similar to or equal to the carbon-doped silicon dioxide layer mentioned above. It is thus possible in a single chamber to form a dielectric stack consisting of carbon doped silicon dioxide layer, a nitrogen doped silicon carbide layer and a carbon doped silicon dioxide layer. The stack is therefore not only particularly desirable from a low k point of view, it can also be simply formed in a manner which allows high throughput. [0026]
  • Thus, in one experiment a particularly effective etch stop layer was developed by forming what may be considered as a methyl doped silicon carbide/nitride with a k value of approximately 2.6. It was found if the carbon to nitrogen ratio was reduced to form more of a carbon doped silicon nitride then the k value increased to approximately 4.6. There was no hard transition point between the two materials. Greater additions of nitrogen to the process gas increase the nitrogen to carbon ratio such that at one extreme (no nitrogen) material can be considered silicon carbide and at the other carbon containing silicon nitride. All films contained hydrogen. [0027]
  • In this experiment the process conditions were as follows: [0028]
    Pressure TMS flow O2Flow N2Flow RF Power Temp
    low-k C doped SiO2k = 2.6 SiO2(C)
    A methyl doped silicon dioxide
    3000 mT 80 sccm 100 sccm 500 sccm  100 W 0˜25° C.
    low-k N doped SiC k = 2.6 SiC(N)
    A methyl doped silicon carbide/nitride
    1500 mT 80 sccm nil  50 sccm  200 W 0˜25° C.
    low-k C doped SiN k = 4.6 SiN(C)
    A methyl doped silicon nitride
     500 mT ˜20 sccm nil 500 sccm 1000 W 0˜25° C.
  • It will thus be seen that at the particular nitrogen flow selected the low k nitrogen doped silicon carbide had a k value precisely equal to the low k carbon doped silicon dioxide formed as described above. [0029]
  • The RF power was applied by 380 Khz generator to the showerhead electrode and the platen was maintained at room temperature or below. Temperatures below 0° C. may be useful to the process, but in general the process has been run at room temperature or between 0° C. and room temperature. [0030]
  • Further experiments were carried out at 13.56 mHz RF power. It was found that the SiO[0031] 2(C) and SiC(N) results differed markedly. In the case of SiO2(C) the deposition rate increased and the uniformity of thickness improved whereas for the SiC(N) material the rate decreased and the uniformity worsened. It is therefore further postulated that a low K etch stop layer of the invention could be formed from SiO2(C) deposited at high frequency (above 4 mHz) and SiC(N) at low frequency (below 4 mHz).
  • The spacing of the wafer from the showerhead and the electrode will affect film uniformity and should be experimentally derived to maximise that uniformity. The flow rates for the tetramethylsilane (TMS) are approximate because they are difficult to determine for reasons given in our co-pending British Patent Application No. 9922691.2. [0032]
  • Initial experiments were carried out on silicon wafers without resist coating where, using the same etch process, the etch rates were: [0033]
    Film type Precursors Etch rate
    SiO2 (C) TMS/02 9,377 Å/min
    SiC (N) TMS/N2 3,222 Å/min
    SiN (C) TMS/N2 4,787 Å/min
  • From these etch rates one can calculate that there is an etch selectivity of 2.9:1 (SiO[0034] 2:SiC) which compares favourably to standard etch stop layers with much higher k values.
  • Thus, contrary to expectations, the nitrogen-doped SiC(N) material is preferable as a low k etch stop material to carbon-doped silicon nitride. [0035]
  • Stacked structures were then constructed using the deposition process essentially as set out above but including a hydrogen plasma treatment of the type disclosed in our co-pending British Patent Application No. 9922801.7 which is incorporated herein by reference. This hydrogen plasma treatment improves the low k film properties, e.g. reducing BOE wet etch rate from over 10,000 Å/min to the same order as that of a thermal oxide (about 550 Å/min), reducing hydrogen and carbon content, apparently increasing density and reducing the film's water absorption properties whilst reducing the likelihood of cracking. [0036]
  • The resultant stacks consisted of two 7000 Å layers of SiO[0037] 2(C) separated by a 500 Å layer of SiC(N). Each of the silicon dioxide layers had been hydrogen plasma treated.
  • Etch experiments were run for different times and the output of an end point detector was recorded. As is commonly used for such experiments, the end point detector monitored the light intensity on the 440 nm emission line. The output from the end point detector is shown in FIGS. [0038] 2 and 3. (The vertical axis of FIGS. 3 to 4 indicate increasing signal intensity in arbitrary units).
  • A further experiment was carried out with SiC(N) layer over SiO[0039] 2(C) layer and the end point signal outout for this experiment is shown in FIG. 4.
  • Subsequently further experiments were carried out on patterned wafters. Two different patterns were used characterised, respectively, a small open area (as would by typical with a contact/via) and a large open area (which is comparable with to an interconnect). SiO[0040] 2(C) SiC(N) and SiN(C) materials as described above were used.
  • The results can be summarised as follows: [0041]
    Etch rate Non uniformity Selectivity
    Film type Å/min ′/−% to TMS/02 Si02
    Interconnect mask
    TMS/02 Si02(C) 10,611 8.3
    TMS/N2 SiC type 3,524 5.3 3.01
    TMS/N2 SiN type 4,224 6.6
    Contact/via mask
    TMS/02 Si02(C) 11,328 4.4
    TMS/N2 SiC type 3,875 5.9 2.92
    TMS/N2 SiN type 3,932 9.0
  • Thus it will be seen that, as well as having a much higher k value, the etching characteristics of the SiN are inferior to those of the low k SiC material. Patterning or the absence of patterning does not make a significant difference to the selectivity of the low k SiO[0042] 2(C) to the SiC(N). In the case where there was no photoresist the ratio was 2.9:1, whilst in these two experiments values of 3.01:1 and 2.92:1 were obtained giving an approximate value of 3:1. This etch selectivity combined with the very acceptable uniformity figures indicates that SiC(N) is a useful etch stop material and the figures indicate that end point signals of useful clarity are generated at the 440 nm line.
  • As has already been mentioned above, the SiC(N) material has desirable properties as a low k dielectric in its own right and this leads to the possibility of a two layer stack with no separate distinct “etch stop” layer. Indeed stacks can be built of layers of materials having similar k values but with sufficiently different etch characteristics that the transition between layers can be detected and automatic processing achieved. [0043]
  • A particular example of an application which can benefit from the use of two low k materials, without the use of an etch stop layer, is the formation of a low k bi-layer for dual damascene applications. Here one layer is used for the formation of vias, whilst the other defines the overlying trenches. As an example, a “trench first” scheme could use the faster etching SiO[0044] 2(C) overlying slower etching layer in which the vias was formed. The trench pattern could be formed upon its surface by lithography and the trench pattern etched. An end point signal would be produced when the underlying material was reached and a timed over-etch carried out. Then the etch mask (e.g. a photoresist) would be removed and the wafer patterned for the underlying vias. The vias would then be etched in the underlying low-k layer.
  • An alternative procedure is illustrated in FIG. 5. As can be seen FIG. 5 illustrates at (a) to (e) a method of forming a wiring channel and via combination which utilises the differences in etch rate that can be obtained for the materials discussed above, whilst utilising their good low k characteristics. The method described is particularly advantageous in that it removes the need for lithography and mask formation for the vias at the bottom of the wiring channel. As the wiring becomes narrower and narrower the masking of the bottom of the channel becomes more and more challenging. [0045]
  • Thus in FIG. 5([0046] a) a first layer of low k insulating material 10 is deposited on a substrate 11 and a via is part etched in the surface of that material as indicated at 12. At this time the etching of the via formation 11 is relatively straightforward because the whole surface of the layer 10 is exposed. In FIG. 5(b) a second conformal layer 13 is deposited so that it fills the formation 12 but this formation is then reflected at the surface of the layer 13 as shown at 14. The upper surface of 13 is then masked with the desired wiring pattern and FIG. 5(c) shows the part etching of the wiring channel 15. Simultaneously and inevitably the bottom of the formation 14 is also etched and so this progresses down into the formation 12 as shown at (c) and (d). At the point shown in (d) there will be a distance x left to etch in the layer 13, whereas there will be a distance y left to etch in the layer 11. Although not clearly shown in the schematic drawings y will usually be greater than x and the ratio y/x will determine the relative etch rates which should be selected for the materials of the layers 13 and 11. In the kind of arrangement illustrated in the figures, it is likely that in fact that y will approximately be twice x and so the etch rate of material 11 should be twice that of material 13.
  • [0047] Material 11 can conveniently also provide the etch stop signal in the manner postulated above. Thus looking at the etch rates set out above, it will be seen that the carbon-doped silicon nitride and carbon-doped silicon dioxide provide an etch rate ratio or selectivity of approximately 2:1 whereas, as has been mentioned before, the selectivity of silicon dioxide to nitrogen-doped silicon carbide is approximately 3:1. Adjustment of doping can provide other selectivities.

Claims (16)

1. A semiconductor device including a dual damascene structure formed in a dielectric stack, the stack comprising an upper layer having a first formation etched therein, an intermediate etch stop layer and a lower layer having a second formation etched therein, the second formation being contiguous with the first through the etch stop layer, each of the layers having a dielectric constant k≦3.5 and the etch stop layer has a selectivity of at least 2.5:1 relative to the upper layer.
2. A device as claimed in claim 1 wherein the etch stop layer is integral with the lower layer.
3. A device as claimed in claim 1 or claim 2 wherein the etch stop layer is formed of nitrogen-doped silicon carbide.
4. A method of forming a low k film on a substrate comprising:
(a) positioning the substrate on a support in a chamber.
(b) supplying to the chamber in gaseous or vapour from a silicon-containing organic compound and nitrogen in the presence of a plasma to deposit a nitrogen-doped silicon carbide film on the substrate.
5. A method as claimed in claim 5 where the nitrogen-doped silicon carbide is deposited by a plasma driven at frequencies below 4 mHz.
6. A method as claimed in claim 4 or claim 5 wherein the silicon-containing organic compound is an alkylsilane.
7. A method as claimed in any one of claims 4 to 6 wherein the silicon-containing compound is a tetraalkysilane.
8. A method as claimed in any one of claims 4 to 6 wherein the silicon-containing organic compound is tetramethylsilane.
9. An etch stop layer comprising nitrogen doped silicon carbide.
10. A stack of dielectric layers when in each layer is formed of a different material, the materials having detectably different etch characteristics but generally equal dielectric constants.
11. A stack as claimed in claim 10 wherein the selectivity between adjacent layers is at least 2.5:1.
12. A method of forming a dual damascene structure including depositing a layer of first insulating material having a first etch rate on a semiconductor wafer, part etching one or more vias in the first layer, subsequentially depositing a layer of second insulating material onto the first so that the part etched via is filled with the second material causing a corresponding formation to appear at the surface of the second layer, etching the second layer a channel to receive a wiring line such that the channel contains the corresponding formation, the relative etch rates of the materials being such that when the channel is etched to the surface of the first layer, the via is fully etched through the first layer.
13. A stack as claimed in claim 10 or claim 11 wherein the difference in the dielectric constants of the materials of adjacent layers varies by less than 10%
14. A method as claimed in claim 13 wherein the etch rate of the first layer is approximately twice that of the second layer.
15. A method as claimed in claim 12 wherein the first layer is carbon-doped SiO2 and the second layer is nitrogen-doped SiC or carbon-doped silicon nitride.
16. A method of forming a low k etch stop layer comprising depositing carbon-doped Si0 2 by a plasma based reaction at a frequency below 4 mHz and depositing a nitrogen-doped SiC by a plasma based reaction onto the SiO2 material at a frequency below 4 mHz.
US10/618,636 2000-01-19 2003-07-15 Methods and apparatus for forming a film on a substrate Abandoned US20040056356A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/618,636 US20040056356A1 (en) 2000-01-19 2003-07-15 Methods and apparatus for forming a film on a substrate

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB0001179.1 2000-01-19
GBGB0001179.1A GB0001179D0 (en) 2000-01-19 2000-01-19 Methods & apparatus for forming a film on a substrate
US09/760,820 US6627535B2 (en) 2000-01-19 2001-01-17 Methods and apparatus for forming a film on a substrate
US10/618,636 US20040056356A1 (en) 2000-01-19 2003-07-15 Methods and apparatus for forming a film on a substrate

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/760,820 Division US6627535B2 (en) 2000-01-19 2001-01-17 Methods and apparatus for forming a film on a substrate

Publications (1)

Publication Number Publication Date
US20040056356A1 true US20040056356A1 (en) 2004-03-25

Family

ID=9883946

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/760,820 Expired - Fee Related US6627535B2 (en) 2000-01-19 2001-01-17 Methods and apparatus for forming a film on a substrate
US10/618,636 Abandoned US20040056356A1 (en) 2000-01-19 2003-07-15 Methods and apparatus for forming a film on a substrate

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/760,820 Expired - Fee Related US6627535B2 (en) 2000-01-19 2001-01-17 Methods and apparatus for forming a film on a substrate

Country Status (6)

Country Link
US (2) US6627535B2 (en)
JP (1) JP2001244337A (en)
KR (1) KR20010076361A (en)
CN (1) CN1185693C (en)
DE (1) DE10101766A1 (en)
GB (2) GB0001179D0 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103107158A (en) * 2011-11-11 2013-05-15 中芯国际集成电路制造(上海)有限公司 Semiconductor device and forming method thereof

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7804115B2 (en) 1998-02-25 2010-09-28 Micron Technology, Inc. Semiconductor constructions having antireflective portions
US6274292B1 (en) 1998-02-25 2001-08-14 Micron Technology, Inc. Semiconductor processing methods
US6268282B1 (en) * 1998-09-03 2001-07-31 Micron Technology, Inc. Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks
US6828683B2 (en) * 1998-12-23 2004-12-07 Micron Technology, Inc. Semiconductor devices, and semiconductor processing methods
US7067414B1 (en) * 1999-09-01 2006-06-27 Micron Technology, Inc. Low k interlevel dielectric layer fabrication methods
US6440860B1 (en) * 2000-01-18 2002-08-27 Micron Technology, Inc. Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride
KR100533198B1 (en) * 2000-08-18 2005-12-05 동경 엘렉트론 주식회사 Low-dielectric silicon nitride film and method of forming the same, semiconductor device and fabrication process thereof
JP4698813B2 (en) * 2000-10-19 2011-06-08 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
GB0117600D0 (en) 2001-07-19 2001-09-12 Trikon Holdings Ltd Semiconductor structure
GB0129567D0 (en) * 2001-12-11 2002-01-30 Trikon Technologies Ltd Diffusion barrier
WO2003050870A1 (en) * 2001-12-11 2003-06-19 Trikon Technologies Limited Diffusion barrier
JP3716218B2 (en) * 2002-03-06 2005-11-16 富士通株式会社 Wiring structure and method for forming the same
US7749563B2 (en) * 2002-10-07 2010-07-06 Applied Materials, Inc. Two-layer film for next generation damascene barrier application with good oxidation resistance
US6991959B2 (en) * 2002-10-10 2006-01-31 Asm Japan K.K. Method of manufacturing silicon carbide film
JP4066332B2 (en) 2002-10-10 2008-03-26 日本エー・エス・エム株式会社 Method for manufacturing silicon carbide film
US6908846B2 (en) * 2002-10-24 2005-06-21 Lam Research Corporation Method and apparatus for detecting endpoint during plasma etching of thin films
US7238393B2 (en) * 2003-02-13 2007-07-03 Asm Japan K.K. Method of forming silicon carbide films
US6921978B2 (en) * 2003-05-08 2005-07-26 International Business Machines Corporation Method to generate porous organic dielectric
US7138332B2 (en) * 2003-07-09 2006-11-21 Asm Japan K.K. Method of forming silicon carbide films
US20050035455A1 (en) * 2003-08-14 2005-02-17 Chenming Hu Device with low-k dielectric in close proximity thereto and its method of fabrication
US6849561B1 (en) * 2003-08-18 2005-02-01 Asm Japan K.K. Method of forming low-k films
US20050074554A1 (en) * 2003-10-06 2005-04-07 Shiu-Ko Jangjian Method of forming inter-metal dielectric layer structure
KR100854809B1 (en) 2003-11-11 2008-08-27 도쿄엘렉트론가부시키가이샤 Method for processing substrate
US20050239284A1 (en) * 2004-04-21 2005-10-27 International Business Machines Corporation Wiring structure for integrated circuit with reduced intralevel capacitance
US7115974B2 (en) * 2004-04-27 2006-10-03 Taiwan Semiconductor Manfacturing Company, Ltd. Silicon oxycarbide and silicon carbonitride based materials for MOS devices
US7320945B2 (en) * 2004-06-30 2008-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient low k material
US7732342B2 (en) * 2005-05-26 2010-06-08 Applied Materials, Inc. Method to increase the compressive stress of PECVD silicon nitride films
KR100660890B1 (en) * 2005-11-16 2006-12-26 삼성전자주식회사 Method for forming silicon dioxide film using atomic layer deposition
JP2007165717A (en) * 2005-12-15 2007-06-28 Tokyo Electron Ltd Filming method and filming device
US7501355B2 (en) * 2006-06-29 2009-03-10 Applied Materials, Inc. Decreasing the etch rate of silicon nitride by carbon addition
CN102044414B (en) * 2009-10-13 2012-05-23 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and manufacturing method thereof
CN103137598B (en) * 2011-12-02 2016-01-06 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacture method thereof
JP7174634B2 (en) * 2019-01-18 2022-11-17 東京エレクトロン株式会社 Method for etching a film
CN112201570A (en) * 2020-09-24 2021-01-08 上海华力集成电路制造有限公司 Process method for reducing photoresist poisoning

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4647472A (en) * 1982-12-24 1987-03-03 Tokyo Shibaura Denki Kabushiki Kaisha Process of producing a semiconductor device
US5225032A (en) * 1991-08-09 1993-07-06 Allied-Signal Inc. Method of producing stoichiometric, epitaxial, monocrystalline films of silicon carbide at temperatures below 900 degrees centigrade
US5244698A (en) * 1985-02-21 1993-09-14 Canon Kabushiki Kaisha Process for forming deposited film
US5514604A (en) * 1993-12-08 1996-05-07 General Electric Company Vertical channel silicon carbide metal-oxide-semiconductor field effect transistor with self-aligned gate for microwave and power applications, and method of making
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US6255735B1 (en) * 1999-01-05 2001-07-03 Advanced Micro Devices, Inc. Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers
US6333255B1 (en) * 1997-08-21 2001-12-25 Matsushita Electronics Corporation Method for making semiconductor device containing low carbon film for interconnect structures
US6340435B1 (en) * 1998-02-11 2002-01-22 Applied Materials, Inc. Integrated low K dielectrics and etch stops
US6436824B1 (en) * 1999-07-02 2002-08-20 Chartered Semiconductor Manufacturing Ltd. Low dielectric constant materials for copper damascene

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291334B1 (en) * 1997-12-19 2001-09-18 Applied Materials, Inc. Etch stop layer for dual damascene process
US6303523B2 (en) 1998-02-11 2001-10-16 Applied Materials, Inc. Plasma processes for depositing low dielectric constant films
US6387819B1 (en) * 1998-04-29 2002-05-14 Applied Materials, Inc. Method for etching low K dielectric layers
US6974766B1 (en) 1998-10-01 2005-12-13 Applied Materials, Inc. In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4647472A (en) * 1982-12-24 1987-03-03 Tokyo Shibaura Denki Kabushiki Kaisha Process of producing a semiconductor device
US5244698A (en) * 1985-02-21 1993-09-14 Canon Kabushiki Kaisha Process for forming deposited film
US5225032A (en) * 1991-08-09 1993-07-06 Allied-Signal Inc. Method of producing stoichiometric, epitaxial, monocrystalline films of silicon carbide at temperatures below 900 degrees centigrade
US5514604A (en) * 1993-12-08 1996-05-07 General Electric Company Vertical channel silicon carbide metal-oxide-semiconductor field effect transistor with self-aligned gate for microwave and power applications, and method of making
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US6333255B1 (en) * 1997-08-21 2001-12-25 Matsushita Electronics Corporation Method for making semiconductor device containing low carbon film for interconnect structures
US6340435B1 (en) * 1998-02-11 2002-01-22 Applied Materials, Inc. Integrated low K dielectrics and etch stops
US6255735B1 (en) * 1999-01-05 2001-07-03 Advanced Micro Devices, Inc. Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers
US6436824B1 (en) * 1999-07-02 2002-08-20 Chartered Semiconductor Manufacturing Ltd. Low dielectric constant materials for copper damascene

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103107158A (en) * 2011-11-11 2013-05-15 中芯国际集成电路制造(上海)有限公司 Semiconductor device and forming method thereof

Also Published As

Publication number Publication date
CN1309418A (en) 2001-08-22
JP2001244337A (en) 2001-09-07
US20010030369A1 (en) 2001-10-18
GB0101160D0 (en) 2001-02-28
CN1185693C (en) 2005-01-19
GB2361808B (en) 2004-08-11
KR20010076361A (en) 2001-08-11
US6627535B2 (en) 2003-09-30
GB2361808A (en) 2001-10-31
GB0001179D0 (en) 2000-03-08
DE10101766A1 (en) 2001-07-26

Similar Documents

Publication Publication Date Title
US6627535B2 (en) Methods and apparatus for forming a film on a substrate
US20210020432A1 (en) Method of forming topology-controlled amorphous carbon polymer film
US7226853B2 (en) Method of forming a dual damascene structure utilizing a three layer hard mask structure
US7125792B2 (en) Dual damascene structure and method
US6812043B2 (en) Method for forming a carbon doped oxide low-k insulating layer
JP5500810B2 (en) Method for forming voids in a multilayer wiring structure
KR100801369B1 (en) Method of depositing dielectric films
US7311852B2 (en) Method of plasma etching low-k dielectric materials
TWI528454B (en) Semiconductor device and method of manufacturing semiconductor device
US20090104774A1 (en) Method of manufacturing a semiconductor device
US20020177322A1 (en) Method of plasma etching of silicon carbide
US20030068582A1 (en) Method of manufacturing semiconductor device having silicon carbide film
JP2001110789A (en) Integrated low-k dielectric and etching stop layer
KR100817350B1 (en) Dual plasma treatment of silicon carbide films
JP2002270586A (en) Etching method of organic based insulating film and dual damascene process
US5451435A (en) Method for forming dielectric
US7091612B2 (en) Dual damascene structure and method
US7129164B2 (en) Method for forming a multi-layer low-K dual damascene
US9679802B2 (en) Method of etching a porous dielectric material
JP2003109940A (en) Method of manufacturing semiconductor device with silicon-containing insulating film
TW201916368A (en) Semiconductor device
JP3986674B2 (en) Semiconductor device, method for manufacturing the same, and method for forming interlayer insulating film
JP2004522315A (en) Semiconductor structure
GB2399453A (en) Methods and apparatus for forming a film on a substrate
KR100447322B1 (en) Method of forming a metal line in semiconductor device

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION