US20040057269A1 - Arrangement of integrated circuits in a memory module - Google Patents
Arrangement of integrated circuits in a memory module Download PDFInfo
- Publication number
- US20040057269A1 US20040057269A1 US10/674,240 US67424003A US2004057269A1 US 20040057269 A1 US20040057269 A1 US 20040057269A1 US 67424003 A US67424003 A US 67424003A US 2004057269 A1 US2004057269 A1 US 2004057269A1
- Authority
- US
- United States
- Prior art keywords
- integrated circuits
- memory module
- row
- circuit board
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09409—Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.
Description
- This application is a divisional of U.S. patent application Ser. No. 10/094,512, filed Mar. 7, 2002, the disclosures of which are hereby incorporated in their entirety by reference herein. This application is related to U.S. patent application Ser. No. ______ (Attorney Docket NETL.001DV2) filed on even date herewith, which is a divisional of U.S. patent application Ser. No. 10/094,512, filed Mar. 7, 2002.
- 1. Field of the Invention
- The present invention relates to memory modules for use in computers. More specifically, the invention relates to the layout and organization of SDRAM memory modules to achieve 1-Gigabyte (i.e., 1,073,741,824 bytes) or more capacity using standard TSOP integrated circuits.
- 2. Description of the Related Art
- The demand for high speed, high capacity memory modules for use in the computer industry has grown rapidly. The average base memory capacity of servers recently increased from 512 Megabytes to 1.2 Gigabytes. The cost of dynamic random access memory (DRAM) modules declined by more than 75%.
- To successfully operate in a computer, a memory module must meet standard timing and interface requirements for the type of memory module intended for use in the particular computer. These requirements are defined in design specification documents that are published by either the original initiator of the standard (e.g., Intel or IBM) or a standards issuing body such as JEDEC (formerly, the Joint Electron Device Engineering Council). Among the most important design guidelines for memory module manufactures are those for PC SDRAM, PC133 SDRAM, and DDR SDRAM. The requirements documents also provide design guidelines which, if followed, will result in a memory module that meets the necessary timing requirements.
- To meet the requirements defined in the SDRAM design guidelines and respond to consumer demand for higher capacity memory modules, manufacturers of memory modules have attempted to place a higher density of memory integrated circuits on boards that meet the 1.75″ board height guideline found in the design specifications. Achieving the effective memory density on the printed circuit board has presented a substantial challenge to memory module manufacturers. High memory density on the memory module board has been achieved via the use of stacked integrated circuits and the use of more compact integrated circuit connector designs, such as micro-BGA (Ball Grid Array).
- Use of non-standard integrated circuits, such as micro-BGA integrated circuits increases costs. Micro-BGA integrated circuits use a connection technique that places the connections for the integrated circuit between the body of the integrated circuit and the printed circuit board. Consequently, micro-BGA integrated circuits can be placed closer to one another on a board than can integrated circuits using the more prevalent TSOP (Thin Small Outline Package) packaging techniques. However, integrated circuits using micro-BGA connectors typically cost twice as much as comparable capacity TSOP integrated circuits.
- Stacking a second layer of integrated circuits on top of the integrated circuits directly on the surface of the printed circuit board allows the manufacturer to double the memory density on the circuit board. However, the stacking of integrated circuits results in twice as much heat generation as with single layers of integrated circuits, with no corresponding increase in surface area. Consequently, memory modules using stacked integrated circuits have substantial disadvantages over memory modules using a single layer of integrated circuits. Operating at higher temperatures increases the incidence of bit failure. Greater cooling capacity is needed to avoid the problems of high temperature operation. Thermal fatigue and physical failure of the connections between the circuit board and the integrated circuit can result from ongoing heating and cooling cycles.
- A first aspect of the present invention is a memory module comprising a printed circuit board and a plurality of identical integrated circuits. The integrated circuits are mounted on one or both sides of the printed circuit board in first and second rows. The integrated circuits in the first row on a side are oriented in an opposite orientation from the integrated circuits in the second row on the same side. The orientation of the integrated circuits are indicated by an orientation indicia contained on each integrated circuit.
- Another aspect of the present invention is a memory module comprising a printed circuit board. A plurality of identical integrated circuits are mounted in two rows on at least one side of the printed circuit board. The memory module also includes a control logic bus, a first register and a second register. The control logic bus is connected to the integrated circuits. The first register and the second register are connected to the control logic bus. Each row of integrated circuits is divided into a first lateral half and a second lateral half. The first register addresses the integrated circuits in the first lateral half of both rows. The second register addresses the integrated circuits in the second lateral half of both rows.
- Another aspect of the present invention is a memory module comprising a printed circuit board. A plurality of identical integrated circuits are mounted in two rows on at least one side of the printed circuit board. The memory module includes a control logic bus, a first register and a second register. The control logic bus is connected to the integrated circuits. The first register and the second register are connected to the control logic bus. The first register accesses a first range of data bits and a second range of data bits. The second register accesses a third range of data bits and a fourth range of data bits. The first range of data bits and the second range of data bits are non-contiguous subsets of a data word. The third range of data bits and the fourth range of data bits are also non-contiguous subsets of a data word.
- A further aspect of the present invention is a method for arranging integrated circuit locations on a printed circuit board. The method comprises placing locations for the integrated circuits in a first row and a second row onto at least one surface of a printed circuit board. The integrated circuit locations in the second row are oriented 180 degrees relative to an orientation of the integrated circuit locations in the first row.
- Another aspect of the present invention is a method for the manufacture of memory modules. The method comprises placing the locations for the integrated circuits on a printed circuit board in a first row and a second row on at least one side of the printed circuit board, and orienting the integrated circuit locations in the first row 180 degrees relative to the orientation of the integrated circuits in the second row. The method further comprises interconnecting the integrated circuit locations in a first half of the first row of integrated circuits and the first half of the second row of integrated circuits to a first register location, and interconnecting the integrated circuit locations in a second half of the first row of integrated circuit locations and the second half of the second row of integrated circuit locations to a second register location. The method also comprises placing identical integrated circuits at the integrated circuit locations in the printed circuit board.
- Another aspect of the present invention is a 1-Gigabyte capacity memory module comprising 36 integrated circuits. The integrated circuits are 256-Megabit (i.e., 268,435,456 bits) SDRAM organized as 64 Meg by 4 bits (i.e., 67,108,864 addressed locations with 4 bits per location). The integrated circuits are in a Thin Small Outline Package (TSOP). The memory module has an approximate width of 5.25 inches (133.350 mm) and an approximate height of 2.05 inches (52.073 mm).
- Another aspect of the present invention is a 2-Gigabyte capacity memory module comprises 36 integrated circuits. The integrated circuits are 512-Megabit (i.e., 536,870,912 bits) SDRAM organized as 128 Meg by 4 bits (i.e., 134,217,728 addressed locations with 4 bits per location). The integrated circuits are in a Thin Small Outline Package (TSOP). The memory module has an approximate width of 5.25 inches (133.350 mm) and an approximate height of 2.05 inches (52.073 mm).
- The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the invention.
- FIG. 1A illustrates a view of the primary side of a memory module in an embodiment of a PC133 SDRAM memory module
- FIG. 1B illustrates a view of the secondary side of the memory module of FIG. 1A.
- FIG. 2A illustrates a view of the primary side of a memory module in an embodiment of a DDR SDRAM memory module.
- FIG. 2B illustrates a view of the secondary side of the memory module of FIG. 2A.
- FIG. 3A is a block diagram of an embodiment of a PC 133 SDRAM memory module.
- FIG. 3B is an enlargement of one half of the block diagram of FIG. 3A
- FIG. 4A illustrates a portion of the primary signal layer of a printed circuit board in an embodiment of a memory module.
- FIG. 4B illustrates a portion of the MIDI layer of a printed circuit board in an embodiment of a memory module.
- FIG. 4C illustrates a portion of the MID2 layer of a printed circuit board in an embodiment of a memory module.
- In the following description, reference is made to the accompanying drawings, which show, by way of illustration, specific embodiments in which the invention may be practiced. Numerous specific details of these embodiments are set forth in order to provide a thorough understanding of the invention. However, it will be obvious to one skilled in the art that the invention may be practiced without the specific details or with certain alternative components and methods to those described herein.
- FIG. 1A illustrates the primary side of an embodiment of a
memory module 100. Themodule 100 comprises two rows of memory integratedcircuits 102 mounted onto a printedcircuit board 104. Thememory module 100 meets the timing standards for and is compatible with J-EDEC requirements for a PC133 SDRAM module, but departs from the design guidelines contained in the PC133 design specification. In particular, thememory module 100 meets the timing and interface requirements of the PC133 standard notwithstanding themodule 100 having a height (H) of approximately two inches. This height exceeds the 1.75″ height guideline recommended in the PC133 Design Specification, but allows a single layer of conventional TSOPintegrated circuits 102 to be placed in two rows on each side of the printedcircuit board 104, thus avoiding the negative characteristics caused by stacking of integrated circuits and also avoiding the use of more expensive micro-BGA integrated circuits. The printed circuit board maintains a width (W) of 5.25″ as defined in the PC133 Design Specification. - The
memory module 100 is compatible with the timing requirements while using a greater printed circuit board height through the unique layout and arrangement of theintegrated circuits 102 on the printed circuit board and the arrangement of integrated circuit interconnections. As illustrated in FIG. 1A, the upper row of integrated circuits 102 (designated U1 through U10) are oriented in the opposite direction from the lower row of integrated circuits 102 (designated U11 through U18). FIG. 1B illustrates the second side of the embodiment of amemory module 100. The upper row of integrated circuits 102 (designated U24 through U33) on the second side of the printedcircuit board 104 are placed in an orientation opposite that of the lower row of integrated circuits 102 (designated U34 through U41). The orientation of eachintegrated circuit 102 can be advantageously determined from anorientation indicia 106. For example in the illustrated embodiment, the orientation indicia is a smallcircular mark 106 on the surface of theintegrated circuit 102. - The different orientations of the upper row of
integrated circuits 102 and the lower row ofintegrated circuits 102 allow the traces on the signal layer of thememory module 100 to be placed such that the trace lengths to the data pins on theintegrated circuits 102 in the first (upper) row have substantially the same length as the signal traces to the data pins on theintegrated circuits 102 in the second (lower) row. - FIG. 4A illustrates a portion of a
primary signal layer 400 of the printedcircuit board 104 of the embodiment of amemory module 100 illustrated in FIGS. 1A and 1B. FIG. 4B illustrates a portion of aMID1 signal layer 430 of the printedcircuit board 104 of the embodiment of a memory module illustrated in FIGS. 1A and 1B. FIG. 4C illustrates a portion of aMID2 signal layer 460 of the embodiment of a memory module illustrated in FIGS. 1A and 1B. - The illustrated portion of the
primary signal layer 400 connects to theintegrated circuits 102 designated U1 and U11. Asignal trace 404 to one of the data pins of the U1 integrated circuit is designed to have substantially the same length from the data pin of the U1 integrated circuit to the primarymemory module connector 420 as the length of asignal trace 414 from the corresponding data pin in the U11 integrated circuit to the primarymemory module connector 420. Thesignal trace 404 from the U1 integrated circuit to the primarymemory module connector 420 and thesignal trace 414 from the U11 integrated circuit to the primarymemory module connector 420 each include a respective portion of signal trace located on theMID2 layer 460 of the printedcircuit board 104, as illustrated in FIG. 4C. Similarly, asignal trace 408 from a second data pin on the U1 integrated circuit to the primarymemory module connector 420 is designed to be of substantially the same length as the length of asignal trace 418 from the corresponding pin on the U11 integrated circuit to the primarymemory module connector 420. As illustrated in FIG. 4C, the signal traces 408, 418 also include respective portions of the traces located on theMID2 layer 460 of the printedcircuit board 104. - A
signal trace 402 and asignal trace 406 from third and fourth data pins on the U1 integrated circuit to the primarymemory module connector 420 are designed to be substantially the same lengths as the lengths of asignal trace 412 and asignal trace 416 from the corresponding data pins on the U11 integrated circuit to the primarymemory module connector 420. As illustrated in FIG. 4B, the signal traces 402, 406, 412, 416 include a portion of the signal trace located on theMID1 layer 430 of the printedcircuit board 104. - As shown in FIG. 1A, four signal traces404, 408, 416, 418 include
respective resistors 107 affixed to a first set of connection points 407 (FIG. 4A) on theprimary signal layer 400 of the printedcircuit board 104. As further shown in FIG. 1A, the four signal traces 402, 406, 418, 414 include respective resistors 109 (FIG. 4A) affixed to a second set of connection points 409 on theprimary signal layer 400 of the printedcircuit board 104. Theresistors connector 420 and also provide impedance matching required in the JEDEC standards. - The substantially equal signal trace lengths are repeated for each pair of integrated circuit locations in the first and the second row. By reversing the orientation of the
integrated circuits 102 from the first row to the second row, the portions of the signal traces on theprimary signal layer 400 serving an integrated circuit in the first row have substantially the same lengths as the signal traces serving a corresponding integrated circuit in the second row. The overall lengths of the traces are configured to be substantially equal (to within 10% of the total trace length) by varying the lengths of the portions of the traces located on theMID1 layer 430 and theMID2 layer 460. In addition to the data signal trace lengths, the data mask trace lengths and the clock trace lengths advantageously are maintained to be substantially equal. - Unlike known memory module circuit board designs, the substantial equality of trace lengths is achieved without requiring the addition of repetitious back-and-forth (i.e., serpentine) trace portions to the signal traces of the physically closer
integrated circuits 102 to equalize the trace lengths of the signal lines of the closerintegrated circuits 102 with the trace lengths of the signal lines of theintegrated circuits 102 that are located physically farther from a common signaltrace connector area 420. Since printedcircuit board 104 space is not consumed with serpentine signal traces, the signal traces are advantageously wider, and the spacing between signal traces is advantageously greater. The greater width and spacing of the signal traces advantageously results in decreased signal noise and interference. The absence of serpentine signal traces advantageously results in amemory module 100 that produces less radio frequency interference and is less susceptible to radio frequency interference. - The timing requirements for the
memory module 100 are advantageously met through the use of a second level of symmetry in addition to the use of substantially equal trace lengths. As shown in the block diagram FIG. 3A, the address signals to theintegrated circuits 102 in the top and bottom row (integrated circuits designated U1-U5, U24 - U28, U11- U14, and U34-U37) on one half of thememory module 100 are routed from acommon register 302 via aset 303 of signal paths. The address signals to theintegrated circuits 102 on the second half of the memory module 100 (designated U6-U10, U29-U33, U15-U18, and U38-U41) are routed from acommon register 304 via asecond set 305 of signal paths. The use of the bilateral symmetry allows closer matching of timing performance for the signals from theintegrated circuits 102, improves the timing performance, and provides greater performance timing margins than traditional design guidelines in which each integrated circuit in a row ofintegrated circuits 102 is connected to a single register. The operation of thememory module 100 is synchronized with an external clock signal (not shown) from a computer (not shown) by aclock generator circuit 309, which is discussed in more detail below in connection with FIG. 3B. - FIG. 3B illustrates a
half 310 of the block diagram shown in FIG. 3A. As shown in FIG. 3B, the bilateral symmetry utilizes non-contiguous ranges of data bits for each addressing register. Rather than handling the bits in contiguous ranges such as bits 0-31 addressed in a first register and bits 32-63 addressed in a second register, as described in the JEDEC design guidelines, thefirst register 302 addresses data bits 0-15 (designated D0 through D15) and data bits 32-47 (designated D32 through D47). Thesecond register 304 addresses theintegrated circuits 102 on the second half of the board (not shown in FIG. 3B), which store data bits 16-31 and bits 48-63. Each data bit (designated D0 through D63) and each check bit (designated CB0 through CB7) connects to the memorymodule connection interface 314 via arespective signal trace 311 which contains a respectiveresistive element 312. Theresistive elements 312 in FIG. 3B correspond to theresistors memory module 100 that complies with memory module timing requirements on a physically larger board than envisioned in the design guidelines. The use of bilateral symmetry in the board layout and the use of non-contiguous bit ranges is advantageously usable for larger data word lengths than the 64-bit word length given in this embodiment. - The operation of the memory integrated circuits U1-U18, U24-U41 and the operation of the
common registers clock generator circuit 309. Theclock generator circuit 309 includes a phase locked loop (PLL) (not shown) that operates in a conventional manner to synchronize the clock signals with an input clock signal (CKIN) from the computer (not shown) or other system into which the memory module is inserted. Each of the clock signals PCK0-PCK8 is connected to four memory integrated circuits, and the clock signal PCK9 is connected to thecommon registers PCK0 U11, U12, U34, U35 (D0-D3, D4-D7) PCK1 U13, U14, U36, U37 (D8-D11, D12-D15) PCK2 U15, U16, U38, U39 (D16-D19, D20-D23) PCK3 U17, U18, U40, U41 (D24-D27, D28-D31) PCK4 U1, U2, U24, U25 (D32-D35, D40-D43) PCK5 U3, U4, U26, U27 (D36-D39, D44-D47) PCK6 U1, U2, U24, U25 (D48-D51, D52-D55) PCK7 U9, U10, U32, U33 (D56-D59, D60-D63) PCK8 U5, U6, U28, U29 (CB0-CB3, CB4-CB7) PCK9 control registers 302, 304 - As shown in FIG. 1B, the
integrated circuits 102 are advantageously mounted on both sides of the printedcircuit board 104. The mounting ofintegrated circuits 102 on both sides of the printed circuit board, and the use of bilateral symmetry of the signal traces on the printed circuit board advantageously permits the use of a larger printed circuit board and standard memory integratedcircuits 102. Theintegrated circuits 102 used are advantageously commercially available 64 Meg by 4-bit (67,108,864 address locations with 4 bits per location) memory integrated circuits for a 1-Gigabytecapacity memory module 100 and are advantageously commercially available 128 Meg by 4-bit (134,217,728 addressed locations with 4 bits per location) memory integrated circuits for a 2-Gigabytecapacity memory module 100. Because of the location of the data pins of theintegrated circuits 102, the four data pins of theintegrated circuits 102 on the second side of the printedcircuit board 104 are directly opposite the four data pins of theintegrated circuits 102 on the first side of the printed circuit board. Thus, the data pins of the integrated circuit on the opposite side are serviced by the signal traces shown in FIG. 4A using a via between the two sides for each signal trace. - An embodiment of a
memory module 200 that is compatible with the timing requirements for Double Data Rate (DDR) SDRAM is shown in FIG. 2A and FIG. 2B. TheDDR SDRAM module 200 comprises memory integratedcircuits 202 utilizing standard TSOP packaging that are compatible with the JEDEC DDR timing requirements. TheDDR SDRAM module 200 advantageously utilizes bilateral symmetry to achieve the timing requirements specified in the DDR SDRAM requirements on aboard 204 having a height (H) of approximately 2 inches and a width (W) of 5.25 inches. - In FIGS. 2A and 2B, the
integrated circuits 202 are oriented, as advantageously indicated by anorientation indicia 106, in opposite orientations in a first and a second row, respectively. The trace lengths of signal traces to theintegrated circuits 202 in the first (upper) row are maintained to be substantially the same as the signal traces tointegrated circuits 202 in the second (lower) row. Theintegrated circuits 202 mounted to a first half of thememory module 200 are routed to afirst register 210 and theintegrated circuits 202 mounted to a second half of thememory module 200 are routed to a second register 220. As with thePC133 SDRAM module 100, each data register stores non-contiguous portions of the data word. - Although the invention has been described in terms of certain preferred embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments which do not provide all of the features and advantages set forth herein, are also within the scope of this invention. Accordingly, the scope of the invention is defined by the claims that follow.
Claims (4)
1. A 1-Gigabyte capacity memory module comprising 36 integrated circuits of type 256-Megabit SDRAM organized as 64 Meg by 4 bits in a TSOP package having an approximate dimension of 5.25 inches wide by 2.05 inches high, the integrated circuits arranged in two rows on each of two surfaces of a printed circuit board.
2. The memory module of claim 1 , wherein the integrated circuits are Double Data Rate SDRAM.
3. A 2-Gigabyte capacity memory module comprising 36 integrated circuits of type 512-Megabit SDRAM organized as 128 Meg by 4 bits in a TSOP package having an approximate dimension of 5.25 inches wide by 2.05 inches high, the integrated circuits arranged in two rows on each of two surfaces of a printed circuit board.
4. The memory module of claim 3 , wherein the integrated circuits are Double Data Rate SDRAM.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/674,240 US20040057269A1 (en) | 2002-03-07 | 2003-09-29 | Arrangement of integrated circuits in a memory module |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/094,512 US6751113B2 (en) | 2002-03-07 | 2002-03-07 | Arrangement of integrated circuits in a memory module |
US10/674,240 US20040057269A1 (en) | 2002-03-07 | 2003-09-29 | Arrangement of integrated circuits in a memory module |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/094,512 Division US6751113B2 (en) | 2002-03-07 | 2002-03-07 | Arrangement of integrated circuits in a memory module |
Publications (1)
Publication Number | Publication Date |
---|---|
US20040057269A1 true US20040057269A1 (en) | 2004-03-25 |
Family
ID=27788121
Family Applications (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/094,512 Expired - Lifetime US6751113B2 (en) | 2002-03-07 | 2002-03-07 | Arrangement of integrated circuits in a memory module |
US10/674,082 Abandoned US20040136229A1 (en) | 2002-03-07 | 2003-09-26 | Arrangement of integrated circuits in a memory module |
US10/674,240 Abandoned US20040057269A1 (en) | 2002-03-07 | 2003-09-29 | Arrangement of integrated circuits in a memory module |
US10/765,420 Expired - Lifetime US6930900B2 (en) | 2002-03-07 | 2004-01-27 | Arrangement of integrated circuits in a memory module |
US10/765,488 Expired - Lifetime US6930903B2 (en) | 2002-03-07 | 2004-01-27 | Arrangement of integrated circuits in a memory module |
US10/768,534 Expired - Lifetime US6873534B2 (en) | 2002-03-07 | 2004-01-30 | Arrangement of integrated circuits in a memory module |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/094,512 Expired - Lifetime US6751113B2 (en) | 2002-03-07 | 2002-03-07 | Arrangement of integrated circuits in a memory module |
US10/674,082 Abandoned US20040136229A1 (en) | 2002-03-07 | 2003-09-26 | Arrangement of integrated circuits in a memory module |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/765,420 Expired - Lifetime US6930900B2 (en) | 2002-03-07 | 2004-01-27 | Arrangement of integrated circuits in a memory module |
US10/765,488 Expired - Lifetime US6930903B2 (en) | 2002-03-07 | 2004-01-27 | Arrangement of integrated circuits in a memory module |
US10/768,534 Expired - Lifetime US6873534B2 (en) | 2002-03-07 | 2004-01-30 | Arrangement of integrated circuits in a memory module |
Country Status (3)
Country | Link |
---|---|
US (6) | US6751113B2 (en) |
AU (1) | AU2003213767A1 (en) |
WO (1) | WO2003077132A1 (en) |
Families Citing this family (113)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050280155A1 (en) * | 2004-06-21 | 2005-12-22 | Sang-Yun Lee | Semiconductor bonding and layer transfer method |
US8058142B2 (en) | 1996-11-04 | 2011-11-15 | Besang Inc. | Bonded semiconductor structure and method of making the same |
US7656678B2 (en) | 2001-10-26 | 2010-02-02 | Entorian Technologies, Lp | Stacked module systems |
US6956284B2 (en) * | 2001-10-26 | 2005-10-18 | Staktek Group L.P. | Integrated circuit stacking system and method |
US6751113B2 (en) * | 2002-03-07 | 2004-06-15 | Netlist, Inc. | Arrangement of integrated circuits in a memory module |
US7200024B2 (en) * | 2002-08-02 | 2007-04-03 | Micron Technology, Inc. | System and method for optically interconnecting memory devices |
US7117316B2 (en) * | 2002-08-05 | 2006-10-03 | Micron Technology, Inc. | Memory hub and access method having internal row caching |
US7254331B2 (en) * | 2002-08-09 | 2007-08-07 | Micron Technology, Inc. | System and method for multiple bit optical data transmission in memory systems |
US7149874B2 (en) * | 2002-08-16 | 2006-12-12 | Micron Technology, Inc. | Memory hub bypass circuit and method |
US7836252B2 (en) | 2002-08-29 | 2010-11-16 | Micron Technology, Inc. | System and method for optimizing interconnections of memory devices in a multichip module |
US7102907B2 (en) * | 2002-09-09 | 2006-09-05 | Micron Technology, Inc. | Wavelength division multiplexed memory module, memory system and method |
US20100133695A1 (en) * | 2003-01-12 | 2010-06-03 | Sang-Yun Lee | Electronic circuit with embedded memory |
US7799675B2 (en) * | 2003-06-24 | 2010-09-21 | Sang-Yun Lee | Bonded semiconductor structure and method of fabricating the same |
US7245145B2 (en) | 2003-06-11 | 2007-07-17 | Micron Technology, Inc. | Memory module and method having improved signal routing topology |
US7120727B2 (en) | 2003-06-19 | 2006-10-10 | Micron Technology, Inc. | Reconfigurable memory module and method |
US7260685B2 (en) * | 2003-06-20 | 2007-08-21 | Micron Technology, Inc. | Memory hub and access method having internal prefetch buffers |
US7863748B2 (en) * | 2003-06-24 | 2011-01-04 | Oh Choonsik | Semiconductor circuit and method of fabricating the same |
US20100190334A1 (en) * | 2003-06-24 | 2010-07-29 | Sang-Yun Lee | Three-dimensional semiconductor structure and method of manufacturing the same |
US7867822B2 (en) | 2003-06-24 | 2011-01-11 | Sang-Yun Lee | Semiconductor memory device |
US8071438B2 (en) * | 2003-06-24 | 2011-12-06 | Besang Inc. | Semiconductor circuit |
US7120743B2 (en) * | 2003-10-20 | 2006-10-10 | Micron Technology, Inc. | Arbitration system and method for memory responses in a hub-based memory system |
US7023719B1 (en) * | 2003-10-23 | 2006-04-04 | Lsi Logic Corporation | Memory module having mirrored placement of DRAM integrated circuits upon a four-layer printed circuit board |
KR100574951B1 (en) * | 2003-10-31 | 2006-05-02 | 삼성전자주식회사 | Memory module having improved register architecture |
US20050018495A1 (en) * | 2004-01-29 | 2005-01-27 | Netlist, Inc. | Arrangement of integrated circuits in a memory module |
US7366864B2 (en) | 2004-03-08 | 2008-04-29 | Micron Technology, Inc. | Memory hub architecture having programmable lane widths |
US7120723B2 (en) * | 2004-03-25 | 2006-10-10 | Micron Technology, Inc. | System and method for memory hub-based expansion bus |
US7590797B2 (en) | 2004-04-08 | 2009-09-15 | Micron Technology, Inc. | System and method for optimizing interconnections of components in a multichip memory module |
DE102004021226A1 (en) * | 2004-04-30 | 2005-11-24 | Infineon Technologies Ag | Semiconductor circuit module, e.g. for memory chips, has chips in two groups aligned at 180 degrees to each other so that each branch of signal line ends lies in y-direction |
US7222213B2 (en) * | 2004-05-17 | 2007-05-22 | Micron Technology, Inc. | System and method for communicating the synchronization status of memory modules during initialization of the memory modules |
US7392331B2 (en) | 2004-08-31 | 2008-06-24 | Micron Technology, Inc. | System and method for transmitting data packets in a computer system having a memory hub architecture |
US7324352B2 (en) * | 2004-09-03 | 2008-01-29 | Staktek Group L.P. | High capacity thin module system and method |
US20060049513A1 (en) * | 2004-09-03 | 2006-03-09 | Staktek Group L.P. | Thin module system and method with thermal management |
US7760513B2 (en) | 2004-09-03 | 2010-07-20 | Entorian Technologies Lp | Modified core for circuit module system and method |
US7443023B2 (en) | 2004-09-03 | 2008-10-28 | Entorian Technologies, Lp | High capacity thin module system |
US20060050492A1 (en) * | 2004-09-03 | 2006-03-09 | Staktek Group, L.P. | Thin module system and method |
US7423885B2 (en) | 2004-09-03 | 2008-09-09 | Entorian Technologies, Lp | Die module system |
US7511968B2 (en) * | 2004-09-03 | 2009-03-31 | Entorian Technologies, Lp | Buffered thin module system and method |
US7606050B2 (en) * | 2004-09-03 | 2009-10-20 | Entorian Technologies, Lp | Compact module system and method |
US7289327B2 (en) * | 2006-02-27 | 2007-10-30 | Stakick Group L.P. | Active cooling methods and apparatus for modules |
US7606049B2 (en) * | 2004-09-03 | 2009-10-20 | Entorian Technologies, Lp | Module thermal management system and method |
US7606040B2 (en) * | 2004-09-03 | 2009-10-20 | Entorian Technologies, Lp | Memory module system and method |
US7468893B2 (en) * | 2004-09-03 | 2008-12-23 | Entorian Technologies, Lp | Thin module system and method |
US20060053345A1 (en) * | 2004-09-03 | 2006-03-09 | Staktek Group L.P. | Thin module system and method |
US20060261449A1 (en) * | 2005-05-18 | 2006-11-23 | Staktek Group L.P. | Memory module system and method |
KR100665840B1 (en) * | 2004-12-10 | 2007-01-09 | 삼성전자주식회사 | Memory module of daisy-chain structure and method for fabricating the same |
US20060136658A1 (en) * | 2004-12-16 | 2006-06-22 | Simpletech, Inc. | DDR2 SDRAM memory module |
JP4754235B2 (en) * | 2005-02-21 | 2011-08-24 | Ntn株式会社 | Rotation transmission device |
US7212424B2 (en) * | 2005-03-21 | 2007-05-01 | Hewlett-Packard Development Company, L.P. | Double-high DIMM with dual registers and related methods |
US8455978B2 (en) | 2010-05-27 | 2013-06-04 | Sang-Yun Lee | Semiconductor circuit structure and method of making the same |
US8367524B2 (en) * | 2005-03-29 | 2013-02-05 | Sang-Yun Lee | Three-dimensional integrated circuit structure |
US20110143506A1 (en) * | 2009-12-10 | 2011-06-16 | Sang-Yun Lee | Method for fabricating a semiconductor memory device |
US7457978B2 (en) * | 2005-05-09 | 2008-11-25 | Micron Technology, Inc. | Adjustable byte lane offset for memory module to reduce skew |
US7414312B2 (en) * | 2005-05-24 | 2008-08-19 | Kingston Technology Corp. | Memory-module board layout for use with memory chips of different data widths |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US7580312B2 (en) * | 2006-07-31 | 2009-08-25 | Metaram, Inc. | Power saving system and method for use with a plurality of memory circuits |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US20080082763A1 (en) * | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US7472220B2 (en) | 2006-07-31 | 2008-12-30 | Metaram, Inc. | Interface circuit system and method for performing power management operations utilizing power management signals |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US7609567B2 (en) * | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US8619452B2 (en) | 2005-09-02 | 2013-12-31 | Google Inc. | Methods and apparatus of stacking DRAMs |
KR101318116B1 (en) * | 2005-06-24 | 2013-11-14 | 구글 인코포레이티드 | An integrated memory core and memory interface circuit |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US7392338B2 (en) * | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US7386656B2 (en) | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
DE102005051497B3 (en) * | 2005-10-26 | 2006-12-07 | Infineon Technologies Ag | Memory module e.g. registered dual in-line memory module, has two groups of semiconductor chips connected by two separate line buses, respectively, where conducting paths of line buses branch out to all semiconductor chips of groups |
DE102005051998B3 (en) * | 2005-10-31 | 2007-01-11 | Infineon Technologies Ag | Semiconductor memory module has two rows of DRAM chips arranged to give leads of equal length that are as short as possible |
US7511969B2 (en) * | 2006-02-02 | 2009-03-31 | Entorian Technologies, Lp | Composite core circuit module system and method |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
KR100715287B1 (en) * | 2006-04-26 | 2007-05-08 | 삼성전자주식회사 | Semiconductor memory module |
US7663939B2 (en) * | 2006-05-30 | 2010-02-16 | Kingston Technology Corporation | Voltage stabilizer memory module |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US20080028135A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Multiple-component memory interface system and method |
KR100834826B1 (en) | 2007-01-25 | 2008-06-03 | 삼성전자주식회사 | Mounting structure in integrated circuit module and layout method of termination resistance therefor |
US8040710B2 (en) * | 2007-05-31 | 2011-10-18 | Qimonda Ag | Semiconductor memory arrangement |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US7839712B2 (en) * | 2007-08-03 | 2010-11-23 | Qimonda Ag | Semiconductor memory arrangement |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
JP4372189B2 (en) | 2007-12-27 | 2009-11-25 | 株式会社東芝 | Information processing apparatus and nonvolatile semiconductor memory drive |
US20100195277A1 (en) * | 2009-02-05 | 2010-08-05 | Trident Microsystems, Inc. | Dual Layer Printed Circuit Board |
EP2441007A1 (en) | 2009-06-09 | 2012-04-18 | Google, Inc. | Programming of dimm termination resistance values |
US8723335B2 (en) | 2010-05-20 | 2014-05-13 | Sang-Yun Lee | Semiconductor circuit structure and method of forming the same using a capping layer |
US8289727B2 (en) | 2010-06-11 | 2012-10-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package substrate |
KR101796116B1 (en) | 2010-10-20 | 2017-11-10 | 삼성전자 주식회사 | Semiconductor device, memory module and memory system having the same and operating method thereof |
US9158546B1 (en) | 2011-04-06 | 2015-10-13 | P4tents1, LLC | Computer program product for fetching from a first physical memory between an execution of a plurality of threads associated with a second physical memory |
US9176671B1 (en) | 2011-04-06 | 2015-11-03 | P4tents1, LLC | Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system |
US9170744B1 (en) | 2011-04-06 | 2015-10-27 | P4tents1, LLC | Computer program product for controlling a flash/DRAM/embedded DRAM-equipped system |
US9164679B2 (en) | 2011-04-06 | 2015-10-20 | Patents1, Llc | System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class |
US8930647B1 (en) | 2011-04-06 | 2015-01-06 | P4tents1, LLC | Multiple class memory systems |
US8437164B1 (en) * | 2011-07-27 | 2013-05-07 | Apple Inc. | Stacked memory device for a configurable bandwidth memory interface |
US9417754B2 (en) | 2011-08-05 | 2016-08-16 | P4tents1, LLC | User interface system, method, and computer program product |
WO2013177310A2 (en) | 2012-05-22 | 2013-11-28 | Xockets IP, LLC | Offloading of computation for rack level servers and corresponding methods and systems |
US20140165196A1 (en) | 2012-05-22 | 2014-06-12 | Xockets IP, LLC | Efficient packet handling, redirection, and inspection using offload processors |
US9378161B1 (en) | 2013-01-17 | 2016-06-28 | Xockets, Inc. | Full bandwidth packet handling with server systems including offload processors |
US9250954B2 (en) | 2013-01-17 | 2016-02-02 | Xockets, Inc. | Offload processor modules for connection to system memory, and corresponding methods and systems |
Citations (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4280176A (en) * | 1978-12-26 | 1981-07-21 | International Business Machines Corporation | Memory configuration, address interleaving, relocation and access control system |
US4679167A (en) * | 1983-07-29 | 1987-07-07 | Hewlett-Packard Company | Apparatus for locating a memory module within a memory space |
US5012389A (en) * | 1988-12-14 | 1991-04-30 | Hand Held Products, Inc. | Board wiring pattern for a high density memory module |
US5164916A (en) * | 1992-03-31 | 1992-11-17 | Digital Equipment Corporation | High-density double-sided multi-string memory module with resistor for insertion detection |
US5191404A (en) * | 1989-12-20 | 1993-03-02 | Digital Equipment Corporation | High density memory array packaging |
US5226136A (en) * | 1986-05-06 | 1993-07-06 | Nintendo Company Limited | Memory cartridge bank selecting apparatus |
US5303123A (en) * | 1992-12-21 | 1994-04-12 | Alcatel Network Systems, Inc. | Retainer for removable circuit board components |
US5383148A (en) * | 1992-05-19 | 1995-01-17 | Sun Microsystems, Inc. | Single in-line memory module |
US5412538A (en) * | 1993-07-19 | 1995-05-02 | Cordata, Inc. | Space-saving memory module |
US5428762A (en) * | 1992-03-11 | 1995-06-27 | International Business Machines Corporation | Expandable memory having plural memory cards for distributively storing system data |
US5495435A (en) * | 1993-11-18 | 1996-02-27 | Nec Corporation | Synchronous DRAM memory module |
US5513135A (en) * | 1994-12-02 | 1996-04-30 | International Business Machines Corporation | Synchronous memory packaged in single/dual in-line memory module and method of fabrication |
US5541448A (en) * | 1991-10-16 | 1996-07-30 | Texas Instruments Inc. | Electronic circuit card |
US5572691A (en) * | 1993-04-21 | 1996-11-05 | Gi Corporation | Apparatus and method for providing multiple data streams from stored data using dual memory buffers |
US5631807A (en) * | 1995-01-20 | 1997-05-20 | Minnesota Mining And Manufacturing Company | Electronic circuit structure with aperture suspended component |
US5642323A (en) * | 1993-06-17 | 1997-06-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit with a data transmission circuit |
US5652861A (en) * | 1993-02-24 | 1997-07-29 | Digital Equipment Corporation | System for interleaving memory modules and banks |
US5652462A (en) * | 1993-04-05 | 1997-07-29 | Matsushita Electric Industrial Co., Ltd. | Multilevel semiconductor integrated circuit device |
US5661339A (en) * | 1992-09-16 | 1997-08-26 | Clayton; James E. | Thin multichip module |
US5691946A (en) * | 1996-12-03 | 1997-11-25 | International Business Machines Corporation | Row redundancy block architecture |
US5712811A (en) * | 1995-05-17 | 1998-01-27 | Lg Semicon Co., Ltd. | IC memory card |
US5737192A (en) * | 1993-04-30 | 1998-04-07 | The United States Of America As Represented By The Secretary Of The Air Force | Density improvement in integration modules |
US5743408A (en) * | 1996-05-16 | 1998-04-28 | Hill; Mark Langdon | Leather automobile trim |
US5835932A (en) * | 1997-03-13 | 1998-11-10 | Silicon Aquarius, Inc. | Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM |
US5847985A (en) * | 1997-03-24 | 1998-12-08 | Mitsubishi Denki Kabushiki Kaisha | Memory modules |
US5867448A (en) * | 1997-06-11 | 1999-02-02 | Cypress Semiconductor Corp. | Buffer for memory modules with trace delay compensation |
US5953738A (en) * | 1997-07-02 | 1999-09-14 | Silicon Aquarius, Inc | DRAM with integral SRAM and arithmetic-logic units |
US6021048A (en) * | 1998-02-17 | 2000-02-01 | Smith; Gary W. | High speed memory module |
US6072744A (en) * | 1998-07-21 | 2000-06-06 | Hyundai Electronics Industries Co., Ltd. | Memory device having data bus lines of uniform length |
US6097619A (en) * | 1998-06-19 | 2000-08-01 | Compaq Computer Corp. | Symmetric memory board |
US6151235A (en) * | 1998-09-22 | 2000-11-21 | Nucore Technology Inc. | Card type semiconductor memory device for storing analog image signals in separate analog memory card units |
US6157538A (en) * | 1998-12-07 | 2000-12-05 | Intel Corporation | Heat dissipation apparatus and method |
US6181004B1 (en) * | 1999-01-22 | 2001-01-30 | Jerry D. Koontz | Digital signal processing assembly and test method |
US6215718B1 (en) * | 1998-06-11 | 2001-04-10 | Texas Instruments Incorporated | Architecture for large capacity high-speed random access memory |
US6222739B1 (en) * | 1998-01-20 | 2001-04-24 | Viking Components | High-density computer module with stacked parallel-plane packaging |
US6222737B1 (en) * | 1999-04-23 | 2001-04-24 | Dense-Pac Microsystems, Inc. | Universal package and method of forming the same |
US6353539B1 (en) * | 1998-07-21 | 2002-03-05 | Intel Corporation | Method and apparatus for matched length routing of back-to-back package placement |
US20020048616A1 (en) * | 1999-10-07 | 2002-04-25 | Moore Geoffrey H. | Apparatus for making pipe insulation |
US20020088633A1 (en) * | 2001-01-08 | 2002-07-11 | Kong Eun Youp | Multi-chip memory devices, modules and control methods including independent control of memory chips |
US6502161B1 (en) * | 2000-01-05 | 2002-12-31 | Rambus Inc. | Memory system including a point-to-point linked memory subsystem |
US20030009879A1 (en) * | 2000-03-17 | 2003-01-16 | Allan Draisey | Capsules |
US20030014578A1 (en) * | 2001-07-11 | 2003-01-16 | Pax George E. | Routability for memeory devices |
US6532158B1 (en) * | 1999-08-25 | 2003-03-11 | Smartdata Sa | Electronic apparatus comprising a group of chipcards |
US20030051091A1 (en) * | 1991-11-05 | 2003-03-13 | Leung Wing Yu | Latched sense amplifiers as high speed memory in a memory system |
US20030057564A1 (en) * | 1997-04-04 | 2003-03-27 | Elm Technology Corporation | Three dimensional structure memory |
US6545895B1 (en) * | 2002-04-22 | 2003-04-08 | High Connection Density, Inc. | High capacity SDRAM memory module with stacked printed circuit boards |
US6705877B1 (en) * | 2003-01-17 | 2004-03-16 | High Connection Density, Inc. | Stackable memory module with variable bandwidth |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6034054A (en) | 1983-08-04 | 1985-02-21 | Nec Corp | Module of memory integrated circuit |
US5452231A (en) * | 1988-10-05 | 1995-09-19 | Quickturn Design Systems, Inc. | Hierarchically connected reconfigurable logic assembly |
IL96808A (en) * | 1990-04-18 | 1996-03-31 | Rambus Inc | Integrated circuit i/o using a high performance bus interface |
US5465435A (en) * | 1995-02-21 | 1995-11-14 | Malvaez; Laura A. | Shower step for shaving legs |
IN188196B (en) * | 1995-05-15 | 2002-08-31 | Silicon Graphics Inc | |
US5754408A (en) * | 1995-11-29 | 1998-05-19 | Mitsubishi Semiconductor America, Inc. | Stackable double-density integrated circuit assemblies |
US5994997A (en) * | 1997-11-24 | 1999-11-30 | Motorola, Inc. | Thick-film resistor having concentric terminals and method therefor |
JP3718039B2 (en) * | 1997-12-17 | 2005-11-16 | 株式会社日立製作所 | Semiconductor device and electronic device using the same |
US5912507A (en) * | 1998-02-04 | 1999-06-15 | Motorola, Inc. | Solderable pad with integral series termination resistor |
US6225035B1 (en) * | 1998-03-18 | 2001-05-01 | Motorola, Inc. | Method for forming a thick-film resistor |
US6446184B2 (en) | 1998-04-28 | 2002-09-03 | International Business Machines Corporation | Address re-mapping for memory module using presence detect data |
US6108212A (en) * | 1998-06-05 | 2000-08-22 | Motorola, Inc. | Surface-mount device package having an integral passive component |
US6171921B1 (en) * | 1998-06-05 | 2001-01-09 | Motorola, Inc. | Method for forming a thick-film resistor and thick-film resistor formed thereby |
US6232042B1 (en) * | 1998-07-07 | 2001-05-15 | Motorola, Inc. | Method for manufacturing an integral thin-film metal resistor |
US6185654B1 (en) * | 1998-07-17 | 2001-02-06 | Compaq Computer Corporation | Phantom resource memory address mapping system |
JP2000148656A (en) * | 1998-11-09 | 2000-05-30 | Mitsubishi Electric Corp | Memory system |
US6103134A (en) * | 1998-12-31 | 2000-08-15 | Motorola, Inc. | Circuit board features with reduced parasitic capacitance and method therefor |
US6349456B1 (en) | 1998-12-31 | 2002-02-26 | Motorola, Inc. | Method of manufacturing photodefined integral capacitor with self-aligned dielectric and electrodes |
US6194990B1 (en) * | 1999-03-16 | 2001-02-27 | Motorola, Inc. | Printed circuit board with a multilayer integral thin-film metal resistor and method therefor |
US6256866B1 (en) | 1999-05-11 | 2001-07-10 | Motorola, Inc. | Polymer thick-film resistor printed on planar circuit board surface |
JP2001053243A (en) * | 1999-08-06 | 2001-02-23 | Hitachi Ltd | Semiconductor memory device and memory module |
JP2001084754A (en) * | 1999-09-16 | 2001-03-30 | Mitsubishi Electric Corp | Semiconductor integrated circuit and memory module provided therewith |
US6353867B1 (en) * | 2000-01-14 | 2002-03-05 | Insilicon Corporation | Virtual component on-chip interface |
JP2001339043A (en) * | 2000-05-30 | 2001-12-07 | Mitsubishi Electric Corp | Semiconductor device and semiconductor module using the same |
JP4480855B2 (en) * | 2000-06-08 | 2010-06-16 | 富士通マイクロエレクトロニクス株式会社 | Module including semiconductor device and system including module |
US6342164B1 (en) | 2000-07-31 | 2002-01-29 | Motorola, Inc. | Pinhole-free dielectric films |
US6757751B1 (en) * | 2000-08-11 | 2004-06-29 | Harrison Gene | High-speed, multiple-bank, stacked, and PCB-mounted memory module |
US6625685B1 (en) * | 2000-09-20 | 2003-09-23 | Broadcom Corporation | Memory controller with programmable configuration |
US6594712B1 (en) * | 2000-10-20 | 2003-07-15 | Banderacom, Inc. | Inifiniband channel adapter for performing direct DMA between PCI bus and inifiniband link |
US20030090879A1 (en) * | 2001-06-14 | 2003-05-15 | Doblar Drew G. | Dual inline memory module |
KR100429878B1 (en) * | 2001-09-10 | 2004-05-03 | 삼성전자주식회사 | Memory module and printed circuit board for the same |
US6766433B2 (en) * | 2001-09-21 | 2004-07-20 | Freescale Semiconductor, Inc. | System having user programmable addressing modes and method therefor |
US6751113B2 (en) * | 2002-03-07 | 2004-06-15 | Netlist, Inc. | Arrangement of integrated circuits in a memory module |
-
2002
- 2002-03-07 US US10/094,512 patent/US6751113B2/en not_active Expired - Lifetime
-
2003
- 2003-03-06 WO PCT/US2003/006978 patent/WO2003077132A1/en not_active Application Discontinuation
- 2003-03-06 AU AU2003213767A patent/AU2003213767A1/en not_active Abandoned
- 2003-09-26 US US10/674,082 patent/US20040136229A1/en not_active Abandoned
- 2003-09-29 US US10/674,240 patent/US20040057269A1/en not_active Abandoned
-
2004
- 2004-01-27 US US10/765,420 patent/US6930900B2/en not_active Expired - Lifetime
- 2004-01-27 US US10/765,488 patent/US6930903B2/en not_active Expired - Lifetime
- 2004-01-30 US US10/768,534 patent/US6873534B2/en not_active Expired - Lifetime
Patent Citations (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4280176A (en) * | 1978-12-26 | 1981-07-21 | International Business Machines Corporation | Memory configuration, address interleaving, relocation and access control system |
US4679167A (en) * | 1983-07-29 | 1987-07-07 | Hewlett-Packard Company | Apparatus for locating a memory module within a memory space |
US5226136A (en) * | 1986-05-06 | 1993-07-06 | Nintendo Company Limited | Memory cartridge bank selecting apparatus |
US5012389A (en) * | 1988-12-14 | 1991-04-30 | Hand Held Products, Inc. | Board wiring pattern for a high density memory module |
US5191404A (en) * | 1989-12-20 | 1993-03-02 | Digital Equipment Corporation | High density memory array packaging |
US5541448A (en) * | 1991-10-16 | 1996-07-30 | Texas Instruments Inc. | Electronic circuit card |
US20030051091A1 (en) * | 1991-11-05 | 2003-03-13 | Leung Wing Yu | Latched sense amplifiers as high speed memory in a memory system |
US5428762A (en) * | 1992-03-11 | 1995-06-27 | International Business Machines Corporation | Expandable memory having plural memory cards for distributively storing system data |
US5164916A (en) * | 1992-03-31 | 1992-11-17 | Digital Equipment Corporation | High-density double-sided multi-string memory module with resistor for insertion detection |
US5383148A (en) * | 1992-05-19 | 1995-01-17 | Sun Microsystems, Inc. | Single in-line memory module |
US5465229A (en) * | 1992-05-19 | 1995-11-07 | Sun Microsystems, Inc. | Single in-line memory module |
US5532954A (en) * | 1992-05-19 | 1996-07-02 | Sun Microsystems, Inc. | Single in-line memory module |
US5973951A (en) * | 1992-05-19 | 1999-10-26 | Sun Microsystems, Inc. | Single in-line memory module |
US5661339A (en) * | 1992-09-16 | 1997-08-26 | Clayton; James E. | Thin multichip module |
US5303123A (en) * | 1992-12-21 | 1994-04-12 | Alcatel Network Systems, Inc. | Retainer for removable circuit board components |
US5652861A (en) * | 1993-02-24 | 1997-07-29 | Digital Equipment Corporation | System for interleaving memory modules and banks |
US5652462A (en) * | 1993-04-05 | 1997-07-29 | Matsushita Electric Industrial Co., Ltd. | Multilevel semiconductor integrated circuit device |
US5572691A (en) * | 1993-04-21 | 1996-11-05 | Gi Corporation | Apparatus and method for providing multiple data streams from stored data using dual memory buffers |
US5737192A (en) * | 1993-04-30 | 1998-04-07 | The United States Of America As Represented By The Secretary Of The Air Force | Density improvement in integration modules |
US5642323A (en) * | 1993-06-17 | 1997-06-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit with a data transmission circuit |
US5412538A (en) * | 1993-07-19 | 1995-05-02 | Cordata, Inc. | Space-saving memory module |
US5495435A (en) * | 1993-11-18 | 1996-02-27 | Nec Corporation | Synchronous DRAM memory module |
US5513135A (en) * | 1994-12-02 | 1996-04-30 | International Business Machines Corporation | Synchronous memory packaged in single/dual in-line memory module and method of fabrication |
US5631807A (en) * | 1995-01-20 | 1997-05-20 | Minnesota Mining And Manufacturing Company | Electronic circuit structure with aperture suspended component |
US5712811A (en) * | 1995-05-17 | 1998-01-27 | Lg Semicon Co., Ltd. | IC memory card |
US5743408A (en) * | 1996-05-16 | 1998-04-28 | Hill; Mark Langdon | Leather automobile trim |
US5691946A (en) * | 1996-12-03 | 1997-11-25 | International Business Machines Corporation | Row redundancy block architecture |
US5835932A (en) * | 1997-03-13 | 1998-11-10 | Silicon Aquarius, Inc. | Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM |
US5847985A (en) * | 1997-03-24 | 1998-12-08 | Mitsubishi Denki Kabushiki Kaisha | Memory modules |
US20030057564A1 (en) * | 1997-04-04 | 2003-03-27 | Elm Technology Corporation | Three dimensional structure memory |
US5867448A (en) * | 1997-06-11 | 1999-02-02 | Cypress Semiconductor Corp. | Buffer for memory modules with trace delay compensation |
US5953738A (en) * | 1997-07-02 | 1999-09-14 | Silicon Aquarius, Inc | DRAM with integral SRAM and arithmetic-logic units |
US6222739B1 (en) * | 1998-01-20 | 2001-04-24 | Viking Components | High-density computer module with stacked parallel-plane packaging |
US6021048A (en) * | 1998-02-17 | 2000-02-01 | Smith; Gary W. | High speed memory module |
US6215718B1 (en) * | 1998-06-11 | 2001-04-10 | Texas Instruments Incorporated | Architecture for large capacity high-speed random access memory |
US6097619A (en) * | 1998-06-19 | 2000-08-01 | Compaq Computer Corp. | Symmetric memory board |
US6353539B1 (en) * | 1998-07-21 | 2002-03-05 | Intel Corporation | Method and apparatus for matched length routing of back-to-back package placement |
US6072744A (en) * | 1998-07-21 | 2000-06-06 | Hyundai Electronics Industries Co., Ltd. | Memory device having data bus lines of uniform length |
US6151235A (en) * | 1998-09-22 | 2000-11-21 | Nucore Technology Inc. | Card type semiconductor memory device for storing analog image signals in separate analog memory card units |
US6157538A (en) * | 1998-12-07 | 2000-12-05 | Intel Corporation | Heat dissipation apparatus and method |
US6181004B1 (en) * | 1999-01-22 | 2001-01-30 | Jerry D. Koontz | Digital signal processing assembly and test method |
US6222737B1 (en) * | 1999-04-23 | 2001-04-24 | Dense-Pac Microsystems, Inc. | Universal package and method of forming the same |
US6532158B1 (en) * | 1999-08-25 | 2003-03-11 | Smartdata Sa | Electronic apparatus comprising a group of chipcards |
US20020048616A1 (en) * | 1999-10-07 | 2002-04-25 | Moore Geoffrey H. | Apparatus for making pipe insulation |
US6502161B1 (en) * | 2000-01-05 | 2002-12-31 | Rambus Inc. | Memory system including a point-to-point linked memory subsystem |
US20030061447A1 (en) * | 2000-01-05 | 2003-03-27 | Perego Richard E. | Memory system including a point-to-point linked memory subsystem |
US20030009879A1 (en) * | 2000-03-17 | 2003-01-16 | Allan Draisey | Capsules |
US20020088633A1 (en) * | 2001-01-08 | 2002-07-11 | Kong Eun Youp | Multi-chip memory devices, modules and control methods including independent control of memory chips |
US20030014578A1 (en) * | 2001-07-11 | 2003-01-16 | Pax George E. | Routability for memeory devices |
US6545895B1 (en) * | 2002-04-22 | 2003-04-08 | High Connection Density, Inc. | High capacity SDRAM memory module with stacked printed circuit boards |
US6705877B1 (en) * | 2003-01-17 | 2004-03-16 | High Connection Density, Inc. | Stackable memory module with variable bandwidth |
Also Published As
Publication number | Publication date |
---|---|
US20030169614A1 (en) | 2003-09-11 |
US6930903B2 (en) | 2005-08-16 |
US20040184301A1 (en) | 2004-09-23 |
US6751113B2 (en) | 2004-06-15 |
US20040184300A1 (en) | 2004-09-23 |
AU2003213767A1 (en) | 2003-09-22 |
US20040136229A1 (en) | 2004-07-15 |
US6930900B2 (en) | 2005-08-16 |
US6873534B2 (en) | 2005-03-29 |
US20040184299A1 (en) | 2004-09-23 |
WO2003077132A1 (en) | 2003-09-18 |
WO2003077132A8 (en) | 2003-12-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6930900B2 (en) | Arrangement of integrated circuits in a memory module | |
US20050018495A1 (en) | Arrangement of integrated circuits in a memory module | |
US7053478B2 (en) | Pitch change and chip scale stacking system | |
KR100235222B1 (en) | Single in-line memory module | |
TW387131B (en) | Dual-bank memory module with shared capacitors and R-C elements integrated into the module substrate | |
US7606040B2 (en) | Memory module system and method | |
US6705877B1 (en) | Stackable memory module with variable bandwidth | |
US7405471B2 (en) | Carrier-based electronic module | |
US6891729B2 (en) | Memory module | |
US7522425B2 (en) | High capacity thin module system and method | |
US7233501B1 (en) | Interleaved memory heat sink | |
US6597062B1 (en) | Short channel, memory module with stacked printed circuit boards | |
US20030090879A1 (en) | Dual inline memory module | |
US20060048385A1 (en) | Minimized profile circuit module systems and methods | |
US20060050496A1 (en) | Thin module system and method | |
CN101232009B (en) | Mounting structures for integrated circuit modules | |
JPH10173122A (en) | Memory module | |
JP2007525769A (en) | Interchangeable connection array for double-sided DIMM placement | |
US7738259B2 (en) | Shared via decoupling for area arrays components | |
ATE208124T1 (en) | MULTI-LAYER PRINTED CIRCUIT BOARD AND SPACE SAVING MEMORY MODULE | |
US7863091B2 (en) | Planar array contact memory cards | |
US20070258278A1 (en) | Memory module and methods for making and using the same | |
US20080266778A1 (en) | Memory module routing | |
JP2004524628A (en) | Multi-bank memory subsystem with multiple memory modules arranged | |
US20070224854A1 (en) | Memory module, method of manufacturing a memory module and computer system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |