US20040071227A1 - Apparatus for generating quadrature phase signals and data recovery circuit using the same - Google Patents
Apparatus for generating quadrature phase signals and data recovery circuit using the same Download PDFInfo
- Publication number
- US20040071227A1 US20040071227A1 US10/647,476 US64747603A US2004071227A1 US 20040071227 A1 US20040071227 A1 US 20040071227A1 US 64747603 A US64747603 A US 64747603A US 2004071227 A1 US2004071227 A1 US 2004071227A1
- Authority
- US
- United States
- Prior art keywords
- phase
- clock signals
- signals
- base
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000011084 recovery Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000000630 rising effect Effects 0.000 description 6
- 230000007704 transition Effects 0.000 description 5
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010587 phase diagram Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0025—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal
Definitions
- This invention relates to a data recovery circuit, and more particularly to a controllable quadrature phase generator in a half-rate data recovery circuit for generating two clock signals that are 90 degrees out of phase with each other.
- FIG. 1 shows a schematic block diagram of a conventional data recovery circuit.
- a data recovery circuit 10 mainly comprises a clock source 12 , a phase detector 14 and a loop filter 16 .
- the clock source 12 is for example a voltage-controlled oscillator for generating a reference clock signal CLK having the same frequency as the incoming data signal.
- the phase detector 14 compares the phase of the incoming data signal to the phase of the reference clock signal CLK, determining whether or not these two signals are synchronous with each other. If the incoming data signal leads or lags the reference clock signal CLK, then the phase detector 14 generates a phase error signal which is a function of the phase difference between these two signals.
- the phase error signal is then applied to the loop filter 16 so as to eliminate the undesired high frequency noise and to output a control signal for feedback to the clock source 12 .
- the clock source 12 is controlled based on the control signal to adjust the phase of the reference clock signal CLK. In this way, the reference clock signal CLK can be synchronized with the incoming data signal and thus may be used for retiming the incoming data signal to thereby produce the correctly recovered data.
- an object of the present invention is to provide an apparatus for generating two quadrature clock signals, i.e., two clock signals being 90 degrees out of phase with each other, by using a plurality of reference clock signals.
- the phase of the generated clock signals can be digitally controlled and adjustable through the whole cycle.
- Another object of the present invention is to provide a half-rate data recovery circuit using the above apparatus for generating two quadrature clock signals being 90 degrees out of phase with each other and having a frequency equal to half the incoming data rate.
- an apparatus for generating quadrature phase signals comprises a base selector, a first phase interpolator and a second phase interpolator.
- the base selector generates a first, a second, a third and a fourth base clock signals in accordance with a region control signal by using a plurality of reference clock signals of the same frequency and different phases.
- the first and the second base clock signals are used as boundaries for defining a phase region for a first clock signal while the third and the fourth base clock signals are used as boundaries for defining a phase region for a second clock signal.
- the phase difference between the first and the second base clock signals is substantially equal to the phase difference between the third and the fourth base clock signals, and the phase difference between the first and the third base clock signals and the phase difference between the second and the fourth base clock signals are both substantially 90 degrees.
- the first phase interpolator operates in accordance with a position control signal to generate a first clock signal, the phase of which is a weighted average of the phases of the first and the second base clock signals.
- the second phase interpolator operates in accordance with the same position control signal to generate a second clock signal, the phase of which is a weighted average of the third and the fourth base clock signals.
- the first and the second clock signals both have the same frequency and are substantially 90 degrees out of phase with each other.
- a data recovery circuit is designed to incorporate the above apparatus for generating two quadrature clock signals including a first and a second clock signals having a frequency equal to half the frequency of an incoming data signal received by the data recovery circuit.
- the clock signals are fed into a phase detector for phase comparison with the incoming data, which in turn generates a phase error signal.
- a digital loop filter operates on the basis of the phase error signal to digitally control the apparatus for generating two quadrature clock signals, adjusting the phases of the generated clock signals so that the second clock signal is synchronous with the incoming data signal and the first clock signal is always maintained 90 degrees out of phase with the second clock signal.
- FIG. 1 depicts a schematic block diagram of a conventional data recovery circuit
- FIG. 2 depicts a schematic block diagram of a half-rate data recovery circuit according to the present invention
- FIG. 3 depicts a timing diagram showing the incoming data signal received by the data recovery circuit and the first and the second clock signals
- FIG. 4 depicts a schematic block diagram of a preferred embodiment of the quadrature phase generator according to the present invention
- FIGS. 5 ( a ) and 5 ( b ) respectively show a phase diagram and a phase region table for the quadrature phase generator
- FIG. 6 depicts a circuit for implementing the base selector in the quadrature phase generator
- FIG. 7 is a table showing the relation among the control bits, the mediate clock signals, and the base clock signals;
- FIG. 8 illustrates the relation between the weight represented by the position control signal and the clock signal generated by the weighted average process
- FIG. 9 depicts a phase rotation state machine for the quadrature clock signals
- FIG. 10 is a table illustrating the relation between the control signal and the phase rotation of the quadrature clock signals.
- the data recovery circuit 20 mainly comprises a multiphase source 22 , a quadrature phase generator 23 , a phase detector 24 and a digital loop filter 26 .
- the multiphase source 22 generates a plurality of reference clock signals of the same frequency and different phases from an external reference clock.
- the multiphase source 22 generates four reference clock signals with phases separated by 45 degrees, i.e., 0-degree, 45-degree, 90-degree and 135-degree, respectively.
- the quadrature phase generator 23 receives the four reference clock signals from the multiphase source 22 and generates therefrom a first clock signal CKI (in-phase) and a second clock signal CKQ (quadrature) for outputting to the phase detector 24 .
- the first and the second clock signals CKI and CKQ are of the same frequency, which is equal to half the frequency of an incoming data signal received by the data recovery circuit 20 , and are substantially 90 degrees out of phase with each other.
- the phase detector 24 compares the incoming data signal and the second clock signal CKQ to determine whether or not a phase difference exists therebetween, that is, to determine whether or not the rising edge/falling edge of the second clock signal CKQ is aligned with the transition portion between two adjacent data bits.
- a rising edge of the clock signal 32 is aligned with the transition portion 33 between two data bits D 0 and D 1
- a rising edge of the clock signal 32 a leads the transition portion 33 between two data bits D 0 and D 1
- a rising edge of the clock signal 32 b lags the transition portion 33 between two data bits D 0 and D 1 .
- each rising edge/falling edge of the first clock signal CKI can be maintain in the central portion 34 of each incoming data bit since the first clock signal CKI is offset from the second clock signal CKQ by 90 degrees. In this way, the most correct result can be obtained in data recovery when the first clock signal CKI is employed for sampling the incoming data signal.
- the phase detector 24 If there is a phase difference between the incoming data signal and the second clock signal CKQ, for example, in the cases of the clock signals 32 a and 32 b, the phase detector 24 generates a phase error signal based on the lead/lag conditions.
- the digital loop filter 26 operates to filter out undesired high frequency noise, as well as to generate a digital control signal on the basis of the phase error signal generated by the phase detector 24 .
- the digital control signal is fed back to the quadrature phase generator 23 to adjust the phases of the first and the second clock signals CKI and CKQ, so that the phase difference between the incoming data signal and the second clock signal CKQ can be minimized.
- the digital control signal comprises a region control signal and a position control signal, which will be better described below.
- the quadrature phase generator 23 comprises a base selector 28 , a first phase interpolator 29 a and a second phase interpolator 29 b.
- the base selector 28 is provided with a control input terminal for receiving the region control signal from the digital loop filter 26 , and four reference clock input terminals for receiving the four reference clock signals from the multiphase source 22 .
- These four reference clock signals i.e., the 0-degree, 45-degree, 90-degree and 135-degree signals, and their inverted signals, i.e., the 180-degree, 225-degree, 270-degree and 315-degree signals, together form eight different phasesbeing evenly spaced apart from one another by 45 degrees to divide the phase plane into eight regions.
- the base selector 28 selects a first and a second base clock signals B 1 and B 2 from the four reference clock signals (the 0-degree, 45-degree, 90-degree and 135-degree signals) and their inverted signals (the 180-degree, 225-degree, 270-degree and 315-degree signals) in accordance with the region control signal.
- the first and the second base clock signals B 1 and B 2 which are for example separated by 45 degrees, serve as a pair of boundaries for defining the phase region of the first clock signal CKI.
- the base selector 28 also selects a third and a fourth base clock signals B 3 and B 4 , which are also for example separated by 45 degrees, as a pair of boundaries for defining the phase region of the second clock signal CKQ.
- FIGS. 5 ( a ) and 5 ( b ) respectively show a phase diagram and a phase region table for explaining phase region selection of the first and the second clock signals CKI and CKQ. For instance, as shown in FIG.
- FIG. 6 illustrates a circuit for implementing the base selector 28 .
- the base selector 28 includes a buffer/inverter unit 281 and a bypass/cross unit 282 and is controlled by a region control signal having six control bits CA-CF.
- the buffer/inverter unit 281 consists of, for example, four exclusive-or (XOR) gates 281 a ⁇ 281 d.
- Each of the XOR gates 281 a ⁇ 281 d has two input terminals for receiving one of the reference clock signals and one of the control bits CA ⁇ CD, respectively, and has an output terminal for outputting one of four mediate clock signals M 1 ⁇ M 4 .
- the buffer/inverter unit 281 is able to selectively output four mediate clock signals, the phases of which are 0-degree/180-degree, 45-degree/225-degree, 90-degree/270-degree and 135-degree/315-degree, respectively.
- the bypass/cross unit 282 consists of a first bypass/cross multiplexer 282 a and a second bypass/cross multiplexer 282 b, each of which is provided with two input terminals and two output terminals and is respectively controlled by a control bit CE or CF.
- Each of the first and the second bypass/cross multiplexers 282 a and 282 b operates to direct-connect signals at its two input terminals to its two output terminals upon receiving a control bit “0” and to cross-connect signals at its two input terminals to its two output terminals upon receiving a control bit “1”.
- the first bypass/cross multiplexer 282 a receives at its two input terminals the first and the third mediate clock signals M 1 and M 3 generated by the buffer/inverter unit 281 , and outputs at its two output terminals two output signals to serve as the first and the third base clock signals B 1 and B 3 , respectively. That is, the first bypass/cross multiplexer 282 a outputs a 0-degree/180-degree signal and a 90-degree/270-degree signal respectively as the first base clock signal B 1 and as the third base clock signal B 3 .
- the second bypass/cross multiplexer 282 b receives at its the two input terminals the second and the fourth mediate clock signals M 2 and M 4 generated by the buffer/inverter unit 281 , and outputs at its two output terminals two output signals to serve as the second and the fourth base clock signals B 2 and B 4 , respectively. Therefore, the second bypass/cross multiplexer 282 b outputs a 45-degree/225-degree degrees signal and a 135-degree/315-degree signal respectively as the second base clock signal B 2 and as the fourth base clock signal B 4 .
- the table in FIG. 7 shows the relation among the control bits CA ⁇ CF, the mediate clock signals M 1 ⁇ M 4 and the base clock signals B 1 ⁇ B 4 .
- the first and the second base clock signals B 1 and B 2 i.e., the boundaries for defining the phase region of the first clock signal CKI, selected by the base selector 28 are subsequently fed into the first phase interpolator 29 a to generate the first clock signal CKI by a weighted average process.
- the third and the fourth base clock signals B 3 and B 4 i.e., the boundaries for defining the phase region of the second clock signal CKQ selected by the base selector 28 are subsequently fed into the second phase interpolator 29 b to generate the second clock signal CKQ by a weighted average process.
- the weighted average process is carried out by the first or the second phase interpolator 29 a or 29 b to obtain a weighted average of two boundary phases, based on a “weight” given by the position control signal from the digital loop filter 26 .
- the first clock signal CKI generated at the output terminal of the first phase interpolator 29 a has a phase which is a weighted average of the phases of the first and the second base clock signals B 1 and B 2 . That is, the phase of the first clock signal CKI (weight) ⁇ (the phase of the first base clock signal B 1 )+(1 ⁇ weight) ⁇ (the phase of the second base clock signal B 2 ).
- the second clock signal CKQ generated at the output terminal of the second phase interpolator 29 b has a phase which is a weighted average of the phases of the third and the fourth base clock signals B 3 and B 4 .
- phase of the second clock signal CKQ (weight) ⁇ (the phase of the third base clock signal B 3 )+(1 ⁇ weight) ⁇ (the phase of the fourth base clock signal B 4 ).
- the phases of the first and the third base clock signals B 1 and B 3 are selected to be separated by 90 degrees and the second and the fourth base clock signals B 2 and B 4 are also selected to be separated by 90 degrees. Therefore, by controlling weighted average processes in the first and the second phase interpolators 29 a and 29 b at the same weight, two clock signals CKI and CKQ having a phase difference of 90 degrees can be obtained.
- FIG. 8 shows the relation between the weight represented by the position control signal and the clock signal generated by the weighted average process.
- the first and the second phase interpolators 29 a and 29 b can be digitally controlled by the position control signal (weight) to vary the phases of the first and the second clock signals CKI and CKQ, which are thereby adjustable in those 45-degree regions respectively defined by the boundaries B 1 and B 2 and by the boundaries B 3 and B 4 selected by the base selector 28 .
- weight the weight values of 0.75, 0.5 and 0.25 set forth here are for illustrative purpose only.
- FIG. 9 shows a phase rotation state machine for the first and the second clock signals CKI and CKQ, in which the clockwise rotation path is represented by solid arrows while the counterclockwise rotation path is represented by dotted arrows.
- the quadrature phase generator 23 of the invention for each of the phase values falling in any regions other than the boundaries, there is only one setting. However, for each of the phase values falling exactly on the boundaries, there are dual settings.
- 0-degree and 45-degree signals may be selected respectively for the first and the second base clock signals B 1 and B 2 as the phase region boundaries, and the weight is set to 1 (state “0A” in FIG. 9).
- 0-degree and 315-degree signals may be selected respectively for the first and the second base clock signals B 1 and B 2 as the phase region boundaries, and the weight is set to 1 (state “0H” in FIG. 9). Accordingly, the setting of a phase value falling on the boundary depends on the previous steady state of the clock signal.
- the setting of “0A” is adopted; contrarily, if the previous steady state of the first clock signal CKI falls in region H, then the setting of “0H” is adopted.
- FIG. 10 shows a table for illustrating how the region control signal CA ⁇ CF and the position control signal (weight) vary to make the phase rotate, taking the clockwise rotation from region A to region H as an example.
- the quadrature phase generator according to the invention can be digitally controlled to generate two adjustable quadrature clock signals, the phases of which are allowed to be adjusted thought the whole cycle
Abstract
Description
- This application is based upon and claims the benefit of U.S. provisional application No. 60/417,180 filed Oct. 10, 2002, the contents of which are incorporated herein by reference.
- 1. Field of the Invention
- This invention relates to a data recovery circuit, and more particularly to a controllable quadrature phase generator in a half-rate data recovery circuit for generating two clock signals that are 90 degrees out of phase with each other.
- 2. Description of the Related Art
- In digital data processing, all digital data is clocked by an associated clock signal, the period of which is equal to that of the digital data, so that a digital circuit is allowed to process digital data and to function properly. When digital data is transmitted serially, the associated clock signal is not transmitted along with the digital data for the consideration of transmission efficiency. Therefore, the receiving end must be able to extract clock signal from the incoming data so that the received data can be correctly recovered. Phase locked loop (PLL) circuits are generally used in circuits for data recovery. FIG. 1 shows a schematic block diagram of a conventional data recovery circuit. As shown, a
data recovery circuit 10 mainly comprises aclock source 12, aphase detector 14 and aloop filter 16. Theclock source 12 is for example a voltage-controlled oscillator for generating a reference clock signal CLK having the same frequency as the incoming data signal. Thephase detector 14 compares the phase of the incoming data signal to the phase of the reference clock signal CLK, determining whether or not these two signals are synchronous with each other. If the incoming data signal leads or lags the reference clock signal CLK, then thephase detector 14 generates a phase error signal which is a function of the phase difference between these two signals. The phase error signal is then applied to theloop filter 16 so as to eliminate the undesired high frequency noise and to output a control signal for feedback to theclock source 12. Theclock source 12 is controlled based on the control signal to adjust the phase of the reference clock signal CLK. In this way, the reference clock signal CLK can be synchronized with the incoming data signal and thus may be used for retiming the incoming data signal to thereby produce the correctly recovered data. - Recently, the demand for higher transmission speed has been rapidly increasing. However, the maximum data rate allowed by the phase detector in the above full-rate data recovery circuit is approaching the limit. Therefore, such circuit can hardly satisfy the speed demand in high speed serial communication. A half-rate data recovery circuit has been developed to solve this issue. This half-rate data recovery circuit, which operates at a frequency equal to half the rate of the incoming data stream, approximately doubles the maximum data rate allowed to be processed by the circuit at the receiving end.
- Therefore, an object of the present invention is to provide an apparatus for generating two quadrature clock signals, i.e., two clock signals being 90 degrees out of phase with each other, by using a plurality of reference clock signals. The phase of the generated clock signals can be digitally controlled and adjustable through the whole cycle.
- Another object of the present invention is to provide a half-rate data recovery circuit using the above apparatus for generating two quadrature clock signals being 90 degrees out of phase with each other and having a frequency equal to half the incoming data rate.
- To achieve the above objects, according to one aspect of the present invention, an apparatus for generating quadrature phase signals comprises a base selector, a first phase interpolator and a second phase interpolator. The base selector generates a first, a second, a third and a fourth base clock signals in accordance with a region control signal by using a plurality of reference clock signals of the same frequency and different phases. The first and the second base clock signals are used as boundaries for defining a phase region for a first clock signal while the third and the fourth base clock signals are used as boundaries for defining a phase region for a second clock signal. The phase difference between the first and the second base clock signals is substantially equal to the phase difference between the third and the fourth base clock signals, and the phase difference between the first and the third base clock signals and the phase difference between the second and the fourth base clock signals are both substantially 90 degrees. The first phase interpolator operates in accordance with a position control signal to generate a first clock signal, the phase of which is a weighted average of the phases of the first and the second base clock signals. Similarly, the second phase interpolator operates in accordance with the same position control signal to generate a second clock signal, the phase of which is a weighted average of the third and the fourth base clock signals. The first and the second clock signals both have the same frequency and are substantially 90 degrees out of phase with each other.
- According to another aspect of the present invention, a data recovery circuit is designed to incorporate the above apparatus for generating two quadrature clock signals including a first and a second clock signals having a frequency equal to half the frequency of an incoming data signal received by the data recovery circuit. The clock signals are fed into a phase detector for phase comparison with the incoming data, which in turn generates a phase error signal. A digital loop filter operates on the basis of the phase error signal to digitally control the apparatus for generating two quadrature clock signals, adjusting the phases of the generated clock signals so that the second clock signal is synchronous with the incoming data signal and the first clock signal is always maintained 90 degrees out of phase with the second clock signal.
- Objects and advantages of the present invention will be fully understood from the detailed description to follow taken in conjunction with the embodiments as illustrated in the accompanying drawings, wherein:
- FIG. 1 depicts a schematic block diagram of a conventional data recovery circuit;
- FIG. 2 depicts a schematic block diagram of a half-rate data recovery circuit according to the present invention;
- FIG. 3 depicts a timing diagram showing the incoming data signal received by the data recovery circuit and the first and the second clock signals;
- FIG. 4 depicts a schematic block diagram of a preferred embodiment of the quadrature phase generator according to the present invention;
- FIGS.5(a) and 5(b) respectively show a phase diagram and a phase region table for the quadrature phase generator;
- FIG. 6 depicts a circuit for implementing the base selector in the quadrature phase generator;
- FIG. 7 is a table showing the relation among the control bits, the mediate clock signals, and the base clock signals;
- FIG. 8 illustrates the relation between the weight represented by the position control signal and the clock signal generated by the weighted average process;
- FIG. 9 depicts a phase rotation state machine for the quadrature clock signals; and
- FIG. 10 is a table illustrating the relation between the control signal and the phase rotation of the quadrature clock signals.
- Please refer to FIG. 2, which shows the schematic block diagram of a half-rate data recovery circuit according to the present invention. As shown, the
data recovery circuit 20 mainly comprises amultiphase source 22, aquadrature phase generator 23, aphase detector 24 and adigital loop filter 26. Themultiphase source 22 generates a plurality of reference clock signals of the same frequency and different phases from an external reference clock. In the preferred embodiment, themultiphase source 22 generates four reference clock signals with phases separated by 45 degrees, i.e., 0-degree, 45-degree, 90-degree and 135-degree, respectively. Thequadrature phase generator 23 receives the four reference clock signals from themultiphase source 22 and generates therefrom a first clock signal CKI (in-phase) and a second clock signal CKQ (quadrature) for outputting to thephase detector 24. Please refer now to the timing diagram in FIG. 3. The first and the second clock signals CKI and CKQ are of the same frequency, which is equal to half the frequency of an incoming data signal received by thedata recovery circuit 20, and are substantially 90 degrees out of phase with each other. Thephase detector 24 compares the incoming data signal and the second clock signal CKQ to determine whether or not a phase difference exists therebetween, that is, to determine whether or not the rising edge/falling edge of the second clock signal CKQ is aligned with the transition portion between two adjacent data bits. In FIG. 3, a rising edge of theclock signal 32 is aligned with thetransition portion 33 between two data bits D0 and D1, a rising edge of theclock signal 32 a leads thetransition portion 33 between two data bits D0 and D1, and a rising edge of theclock signal 32 b lags thetransition portion 33 between two data bits D0 and D1. If there is no phase difference between the incoming data signal and the second clock signal CKQ, i.e., the rising edge/falling edge of the second clock signal CKQ is aligned with the transition portion between two adjacent data bits, then each rising edge/falling edge of the first clock signal CKI can be maintain in thecentral portion 34 of each incoming data bit since the first clock signal CKI is offset from the second clock signal CKQ by 90 degrees. In this way, the most correct result can be obtained in data recovery when the first clock signal CKI is employed for sampling the incoming data signal. If there is a phase difference between the incoming data signal and the second clock signal CKQ, for example, in the cases of the clock signals 32 a and 32 b, thephase detector 24 generates a phase error signal based on the lead/lag conditions. Thedigital loop filter 26 operates to filter out undesired high frequency noise, as well as to generate a digital control signal on the basis of the phase error signal generated by thephase detector 24. The digital control signal is fed back to thequadrature phase generator 23 to adjust the phases of the first and the second clock signals CKI and CKQ, so that the phase difference between the incoming data signal and the second clock signal CKQ can be minimized. In the preferred embodiment, the digital control signal comprises a region control signal and a position control signal, which will be better described below. - A preferred embodiment of the
quadrature phase generator 23 is shown in FIG. 4. Thequadrature phase generator 23 comprises abase selector 28, afirst phase interpolator 29 a and asecond phase interpolator 29 b. - The
base selector 28 is provided with a control input terminal for receiving the region control signal from thedigital loop filter 26, and four reference clock input terminals for receiving the four reference clock signals from themultiphase source 22. These four reference clock signals, i.e., the 0-degree, 45-degree, 90-degree and 135-degree signals, and their inverted signals, i.e., the 180-degree, 225-degree, 270-degree and 315-degree signals, together form eight different phasesbeing evenly spaced apart from one another by 45 degrees to divide the phase plane into eight regions. Thebase selector 28 selects a first and a second base clock signals B1 and B2 from the four reference clock signals (the 0-degree, 45-degree, 90-degree and 135-degree signals) and their inverted signals (the 180-degree, 225-degree, 270-degree and 315-degree signals) in accordance with the region control signal. The first and the second base clock signals B1 and B2, which are for example separated by 45 degrees, serve as a pair of boundaries for defining the phase region of the first clock signal CKI. Thebase selector 28 also selects a third and a fourth base clock signals B3 and B4, which are also for example separated by 45 degrees, as a pair of boundaries for defining the phase region of the second clock signal CKQ. Since the first and the second clock signals CKI and CKQ must be 90 degrees out of phase with each other, the first and the third base clock signals B1 and B3 are selected to have phases separated by 90 degrees and the second and the fourth base clock signal B2 and B4 are also selected to have phases separated by 90 degrees. FIGS. 5(a) and 5(b) respectively show a phase diagram and a phase region table for explaining phase region selection of the first and the second clock signals CKI and CKQ. For instance, as shown in FIG. 5(a), when the phase of the first clock signal CKI falls in the region B bounded by two base clock signals having phases of 45-degree and 90-degree respectively, the phase of the second clock signal CKQ falls in the region H bounded by two base clock signals having phases of 0-degree and 315-degree respectively. The discussion here assumes that the first clock signal CKI leads the second clock signal CKQ. However, in practice the first clock signal CKI can also be set to lag the second clock signal CKQ. - FIG. 6 illustrates a circuit for implementing the
base selector 28. As shown, thebase selector 28 includes a buffer/inverter unit 281 and a bypass/cross unit 282 and is controlled by a region control signal having six control bits CA-CF. The buffer/inverter unit 281 consists of, for example, four exclusive-or (XOR)gates 281 a˜281 d. Each of theXOR gates 281 a˜281 d has two input terminals for receiving one of the reference clock signals and one of the control bits CA˜CD, respectively, and has an output terminal for outputting one of four mediate clock signals M1˜M4. When an XOR gate receives a control bit “0” at one is input terminal, the output mediate clock signal will be the same as the reference clock signal at the other input terminal. In this way, the XOR gate acts like a buffer. When an XOR gate receives a control bit “1” at one input terminal, the output mediate clock signal will be the inverted signal of the reference clock signal at the other input terminal. In this way, the XOR gate acts like an inverter. Thereby, the buffer/inverter unit 281 is able to selectively output four mediate clock signals, the phases of which are 0-degree/180-degree, 45-degree/225-degree, 90-degree/270-degree and 135-degree/315-degree, respectively. The bypass/cross unit 282 consists of a first bypass/cross multiplexer 282 a and a second bypass/cross multiplexer 282 b, each of which is provided with two input terminals and two output terminals and is respectively controlled by a control bit CE or CF. Each of the first and the second bypass/cross multiplexers cross multiplexer 282 a receives at its two input terminals the first and the third mediate clock signals M1 and M3 generated by the buffer/inverter unit 281, and outputs at its two output terminals two output signals to serve as the first and the third base clock signals B1 and B3, respectively. That is, the first bypass/cross multiplexer 282 a outputs a 0-degree/180-degree signal and a 90-degree/270-degree signal respectively as the first base clock signal B1 and as the third base clock signal B3. Similarly, the second bypass/cross multiplexer 282b receives at its the two input terminals the second and the fourth mediate clock signals M2 and M4 generated by the buffer/inverter unit 281, and outputs at its two output terminals two output signals to serve as the second and the fourth base clock signals B2 and B4, respectively. Therefore, the second bypass/cross multiplexer 282 b outputs a 45-degree/225-degree degrees signal and a 135-degree/315-degree signal respectively as the second base clock signal B2 and as the fourth base clock signal B4. The table in FIG. 7 shows the relation among the control bits CA˜CF, the mediate clock signals M1˜M4 and the base clock signals B1˜B4. - Referring back to FIG. 4, the first and the second base clock signals B1 and B2, i.e., the boundaries for defining the phase region of the first clock signal CKI, selected by the
base selector 28 are subsequently fed into thefirst phase interpolator 29 a to generate the first clock signal CKI by a weighted average process. Similarly, the third and the fourth base clock signals B3 and B4, i.e., the boundaries for defining the phase region of the second clock signal CKQ selected by thebase selector 28 are subsequently fed into thesecond phase interpolator 29 b to generate the second clock signal CKQ by a weighted average process. The weighted average process is carried out by the first or thesecond phase interpolator digital loop filter 26. - More specifically, the first clock signal CKI generated at the output terminal of the
first phase interpolator 29 a has a phase which is a weighted average of the phases of the first and the second base clock signals B1 and B2. That is, the phase of the first clock signal CKI (weight)×(the phase of the first base clock signal B1)+(1−weight) ×(the phase of the second base clock signal B2). Similarly, the second clock signal CKQ generated at the output terminal of thesecond phase interpolator 29 b has a phase which is a weighted average of the phases of the third and the fourth base clock signals B3 and B4. That is, the phase of the second clock signal CKQ=(weight)×(the phase of the third base clock signal B3)+(1−weight)×(the phase of the fourth base clock signal B4). As discussed above, the phases of the first and the third base clock signals B1 and B3 are selected to be separated by 90 degrees and the second and the fourth base clock signals B2 and B4 are also selected to be separated by 90 degrees. Therefore, by controlling weighted average processes in the first and thesecond phase interpolators second phase interpolators base selector 28. It should be noted that the weight values of 0.75, 0.5 and 0.25 set forth here are for illustrative purpose only. - The phase control of the first and the second clock signals generated by the
quadrature phase generator 23 is now explained more specifically with reference to FIG. 9. FIG. 9 shows a phase rotation state machine for the first and the second clock signals CKI and CKQ, in which the clockwise rotation path is represented by solid arrows while the counterclockwise rotation path is represented by dotted arrows. According to thequadrature phase generator 23 of the invention, for each of the phase values falling in any regions other than the boundaries, there is only one setting. However, for each of the phase values falling exactly on the boundaries, there are dual settings. For example, to generate a first clock signal CKI with a 0-degree phase, 0-degree and 45-degree signals may be selected respectively for the first and the second base clock signals B1 and B2 as the phase region boundaries, and the weight is set to 1 (state “0A” in FIG. 9). Alternatively, 0-degree and 315-degree signals may be selected respectively for the first and the second base clock signals B1 and B2 as the phase region boundaries, and the weight is set to 1 (state “0H” in FIG. 9). Accordingly, the setting of a phase value falling on the boundary depends on the previous steady state of the clock signal. Taking the above 0-degree phase setting as an example, if the previous steady state of the first clock signal CKI falls in region A, then the setting of “0A” is adopted; contrarily, if the previous steady state of the first clock signal CKI falls in region H, then the setting of “0H” is adopted. In some situations, it takes a two-step setting for the phase of a clock signal to rotate out of a boundary. For example, if the present state of the first clock signal CKI is “0A”, then only one step is needed for the phase to rotate from the boundary to region A; however, if the present state of the first clock signal CKI is “0H”, then two steps are needed for the phase to first pass through a transient state “0A” and subsequently proceed to region A. All rotations across two adjacent regions require passing through a transient state. FIG. 10 shows a table for illustrating how the region control signal CA˜CF and the position control signal (weight) vary to make the phase rotate, taking the clockwise rotation from region A to region H as an example. - With the above structure, the quadrature phase generator according to the invention can be digitally controlled to generate two adjustable quadrature clock signals, the phases of which are allowed to be adjusted thought the whole cycle
- While the present invention has been described with reference to the preferred embodiments thereof, it is to be understood that the invention should not be considered as limited thereby. Various modifications and changes could be conceived of by those skilled in the art without departuring from the scope of the present invention, which is indicated by the appended claims.
Claims (14)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/647,476 US6801066B2 (en) | 2002-10-10 | 2003-08-26 | Apparatus for generating quadrature phase signals and data recovery circuit using the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US41718002P | 2002-10-10 | 2002-10-10 | |
US10/647,476 US6801066B2 (en) | 2002-10-10 | 2003-08-26 | Apparatus for generating quadrature phase signals and data recovery circuit using the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20040071227A1 true US20040071227A1 (en) | 2004-04-15 |
US6801066B2 US6801066B2 (en) | 2004-10-05 |
Family
ID=37400779
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/647,476 Expired - Lifetime US6801066B2 (en) | 2002-10-10 | 2003-08-26 | Apparatus for generating quadrature phase signals and data recovery circuit using the same |
Country Status (2)
Country | Link |
---|---|
US (1) | US6801066B2 (en) |
TW (1) | TWI248259B (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050265487A1 (en) * | 2004-05-27 | 2005-12-01 | Xyratex Technology Limited | Method of sampling data and a circuit for sampling data |
US20060077752A1 (en) * | 2003-10-02 | 2006-04-13 | Broadcom Corporation | Phase controlled high speed interfaces |
US7227393B1 (en) * | 2004-06-03 | 2007-06-05 | Marvell International Ltd. | Method and apparatus for adaptive delay cancellation in high-speed wireline transmitters |
US20070146035A1 (en) * | 2005-12-28 | 2007-06-28 | Intel Corporation | Receive clock deskewing method, apparatus, and system |
EP2779434A1 (en) * | 2013-03-15 | 2014-09-17 | Analog Devices, Inc. | Apparatus and methods for invertible sine-shaping for phase interpolation |
US8873606B2 (en) * | 2012-11-07 | 2014-10-28 | Broadcom Corporation | Transceiver including a high latency communication channel and a low latency communication channel |
WO2019009968A1 (en) * | 2017-07-07 | 2019-01-10 | Qualcomm Incorporated | Serializer-deserializer with frequency doubler |
US11005479B2 (en) * | 2019-04-16 | 2021-05-11 | SK Hynix Inc. | Phase detection circuit, and clock generating circuit and semiconductor apparatus using the phase detection circuit |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7323917B2 (en) * | 2003-09-15 | 2008-01-29 | Texas Instruments Incorporated | Method and apparatus for synthesizing a clock signal having a frequency near the frequency of a source clock signal |
US7403584B2 (en) * | 2003-12-31 | 2008-07-22 | Intel Corporation | Programmable phase interpolator adjustment for ideal data eye sampling |
TWI278735B (en) * | 2005-03-21 | 2007-04-11 | Realtek Semiconductor Corp | Multi-phase clock generator and method thereof |
US8116418B2 (en) * | 2008-05-08 | 2012-02-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fast locking clock and data recovery |
KR100992000B1 (en) * | 2008-12-11 | 2010-11-04 | 주식회사 하이닉스반도체 | Multi-Phase Clock Generation Circuit And Controlling Method Thereof |
CN103107796B (en) * | 2011-11-09 | 2016-02-03 | 群联电子股份有限公司 | Clock data recovery circuit |
WO2015161431A1 (en) * | 2014-04-22 | 2015-10-29 | 京微雅格(北京)科技有限公司 | Lvds data recovering method and circuit |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5554945A (en) * | 1994-02-15 | 1996-09-10 | Rambus, Inc. | Voltage controlled phase shifter with unlimited range |
US6122336A (en) * | 1997-09-11 | 2000-09-19 | Lsi Logic Corporation | Digital clock recovery circuit with phase interpolation |
US6564359B2 (en) * | 2000-11-29 | 2003-05-13 | Nec Electronics Corporation | Clock control circuit and method |
US6570944B2 (en) * | 2001-06-25 | 2003-05-27 | Rambus Inc. | Apparatus for data recovery in a synchronous chip-to-chip system |
-
2003
- 2003-07-23 TW TW092120139A patent/TWI248259B/en not_active IP Right Cessation
- 2003-08-26 US US10/647,476 patent/US6801066B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5554945A (en) * | 1994-02-15 | 1996-09-10 | Rambus, Inc. | Voltage controlled phase shifter with unlimited range |
US6122336A (en) * | 1997-09-11 | 2000-09-19 | Lsi Logic Corporation | Digital clock recovery circuit with phase interpolation |
US6564359B2 (en) * | 2000-11-29 | 2003-05-13 | Nec Electronics Corporation | Clock control circuit and method |
US6570944B2 (en) * | 2001-06-25 | 2003-05-27 | Rambus Inc. | Apparatus for data recovery in a synchronous chip-to-chip system |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080101526A1 (en) * | 2003-10-02 | 2008-05-01 | Broadcom Corporation | Phase Controlled High Speed Interfaces |
US20060077752A1 (en) * | 2003-10-02 | 2006-04-13 | Broadcom Corporation | Phase controlled high speed interfaces |
US7515504B2 (en) | 2003-10-02 | 2009-04-07 | Broadcom Corporation | Phase controlled high speed interfaces |
US7333390B2 (en) * | 2003-10-02 | 2008-02-19 | Broadcom Corporation | Phase controlled high speed interfaces |
US20050265487A1 (en) * | 2004-05-27 | 2005-12-01 | Xyratex Technology Limited | Method of sampling data and a circuit for sampling data |
US7227393B1 (en) * | 2004-06-03 | 2007-06-05 | Marvell International Ltd. | Method and apparatus for adaptive delay cancellation in high-speed wireline transmitters |
US7439788B2 (en) | 2005-12-28 | 2008-10-21 | Intel Corporation | Receive clock deskewing method, apparatus, and system |
GB2447362A (en) * | 2005-12-28 | 2008-09-10 | Intel Corp | Receive clock deskewing method,apparatus and system |
WO2007078700A1 (en) * | 2005-12-28 | 2007-07-12 | Intel Corporation | Receive clock deskewing method, apparatus and system |
US20070146035A1 (en) * | 2005-12-28 | 2007-06-28 | Intel Corporation | Receive clock deskewing method, apparatus, and system |
GB2447362B (en) * | 2005-12-28 | 2010-09-01 | Intel Corp | Receive clock deskewing method,apparatus,and system |
DE112006003551B4 (en) * | 2005-12-28 | 2013-04-18 | Intel Corporation | Method, device and system for time equalization of the reception clock |
US8873606B2 (en) * | 2012-11-07 | 2014-10-28 | Broadcom Corporation | Transceiver including a high latency communication channel and a low latency communication channel |
US20150010044A1 (en) * | 2012-11-07 | 2015-01-08 | Broadcom Corporation | Transceiver including a high latency communication channel and a low latency communication channel |
US9306621B2 (en) * | 2012-11-07 | 2016-04-05 | Broadcom Corporation | Transceiver including a high latency communication channel and a low latency communication channel |
EP2779434A1 (en) * | 2013-03-15 | 2014-09-17 | Analog Devices, Inc. | Apparatus and methods for invertible sine-shaping for phase interpolation |
WO2019009968A1 (en) * | 2017-07-07 | 2019-01-10 | Qualcomm Incorporated | Serializer-deserializer with frequency doubler |
US10419204B2 (en) | 2017-07-07 | 2019-09-17 | Qualcomm Incorporated | Serializer-deserializer with frequency doubler |
US11005479B2 (en) * | 2019-04-16 | 2021-05-11 | SK Hynix Inc. | Phase detection circuit, and clock generating circuit and semiconductor apparatus using the phase detection circuit |
Also Published As
Publication number | Publication date |
---|---|
TWI248259B (en) | 2006-01-21 |
US6801066B2 (en) | 2004-10-05 |
TW200406093A (en) | 2004-04-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8903031B2 (en) | Low jitter clock recovery circuit | |
US6801066B2 (en) | Apparatus for generating quadrature phase signals and data recovery circuit using the same | |
US7319345B2 (en) | Wide-range multi-phase clock generator | |
US6683930B1 (en) | Digital phase/frequency detector, and clock generator and data recovery PLL containing the same | |
US6008680A (en) | Continuously adjustable delay-locked loop | |
US6307413B1 (en) | Reference-free clock generator and data recovery PLL | |
JP5269387B2 (en) | Signal interleaving for serial clock and data recovery | |
US8559578B2 (en) | Data reproduction circuit | |
US8138798B2 (en) | Symmetric phase detector | |
US7602869B2 (en) | Methods and apparatus for clock synchronization and data recovery in a receiver | |
US5457718A (en) | Compact phase recovery scheme using digital circuits | |
US20100091927A1 (en) | Clock and Data Recovery (CDR) Using Phase Interpolation | |
US6937685B2 (en) | Apparatus and method for counting high-speed early/late pulses from a high speed phase detector using a pulse accumulator | |
US20100090733A1 (en) | Generating Multiple Clock Phases | |
US11190191B2 (en) | Correction signaling between lanes in multi-chip-modules | |
WO2007019339A2 (en) | Clock-and-data-recovery system | |
Yang | Delay-locked loops-an overview | |
US20210111859A1 (en) | Clock data recovery circuit with improved phase interpolation | |
US6028462A (en) | Tunable delay for very high speed | |
US7561653B2 (en) | Method and apparatus for automatic clock alignment | |
US8269533B2 (en) | Digital phase-locked loop | |
US7545193B2 (en) | Voltage-controlled delay circuit using second-order phase interpolation | |
JP3973149B2 (en) | Data recovery circuit and data recovery method | |
WO2003079554A2 (en) | Phase detector for clock and data recovery at half clock frequency | |
CN114884504A (en) | Clock correction method, clock data recovery circuit, chip, receiving end and terminal |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MSTAR SEMICONDUCTOR, INC., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, JIUNN-YIH;REEL/FRAME:014432/0332 Effective date: 20030718 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAT HOLDER NO LONGER CLAIMS SMALL ENTITY STATUS, ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: STOL); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: MEDIATEK INC., TAIWAN Free format text: MERGER;ASSIGNOR:MSTAR SEMICONDUCTOR, INC.;REEL/FRAME:052931/0468 Effective date: 20190115 |