US20040090828A1 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit Download PDFInfo
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- US20040090828A1 US20040090828A1 US10/333,010 US33301003A US2004090828A1 US 20040090828 A1 US20040090828 A1 US 20040090828A1 US 33301003 A US33301003 A US 33301003A US 2004090828 A1 US2004090828 A1 US 2004090828A1
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- 238000006243 chemical reaction Methods 0.000 claims 1
- 230000008878 coupling Effects 0.000 abstract description 7
- 238000010168 coupling process Methods 0.000 abstract description 7
- 238000005859 coupling reaction Methods 0.000 abstract description 7
- 230000003111 delayed effect Effects 0.000 description 17
- 238000000034 method Methods 0.000 description 11
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0231—Astable circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
- H03K3/0315—Ring oscillators
- H03K3/0322—Ring oscillators with differential cells
Definitions
- the present invention relates generally to a semiconductor integrated circuit and more particularly to a semiconductor integrated circuit including a differential ring multiphase oscillator.
- a parallel-serial converter is required on a transmit side which converter converts parallel data into serial data by using sub-clock signals having multiple phases (hereinafter, such clock signals are referred to as multiphase clock signals).
- the multiphase clock signals are synchronous with a base clock signal and have the same phase difference.
- a multiphase clock generator is required which generates the multiphase clock signals and supplies them to the parallel-serial converter.
- An example of the multiphase clock generator is a voltage-controlled or current-controlled differential ring oscillator having multiple stages of delayed differential inverted amplifiers connected in a ring form.
- a ring oscillator By using such a ring oscillator, it is possible to easily draw multiphase clock signals having the same phase difference out of the multi-staged amplifiers.
- the influences of electrostatic coupling between different wirings must be made uniform.
- FIG. 1 shows a voltage-controlled differential ring oscillator used in conventional semiconductor integrated circuits.
- the output amplifiers 102 a - 102 j buffer oscillation signals output from every other delayed differential inverted amplifiers 101 a - 101 j connected in a ring form and supply them as multiphase clock signals R 1 -R 10 to the parallel-serial converter.
- FIG. 2 shows voltage waveforms of the multiphase clock signals R 1 -R 10 output from the voltage-controlled differential ring oscillator as shown in FIG. 1.
- an abscissa represents time and an ordinate represents voltage.
- FIG. 3A shows wirings or interconnects for three clock signals R 1 , R 2 , R 3 formed in a semiconductor integrated circuit and capacitors C p equivalently representing stray capacities between these wirings.
- FIG. 3B shows how crosstalks due to stray capacities degrade the voltage waveforms of the clock signals.
- a clock signal R 2 undergoes voltage variations under the influence of crosstalks due to stray capacities each time the adjacent clock signals R 1 and R 3 change their voltage levels.
- An amount of voltage variation ⁇ V increases with the stray capacity C p .
- information at the transition point is important, and therefore, crosstalk near the transition point has great effects on precision of the clock signals.
- the stray capacities C p can be reduced, for example, by increasing the distance between the multiphase clock signal wirings as shown in FIG. 4A.
- FIG. 4A shows an example in which an interval of the multiphase clock signal wirings is increased by two times to halve the stray capacities. This method, however, increases a wiring area for the multiphase clock signals.
- FIG. 4B shows the new wiring added between adjacent two clock signal wirings and the new wiring is grounded.
- the new wiring may be supplied with a stable voltage.
- Such a technique can shield the adjacent two clock signal wirings electrostatically from one another and prevent possible degradations of clock signal waveforms which would otherwise be caused by level transitions of the adjacent clock signals.
- This technique requires an additional area for laying the new wirings, increasing the wiring area for the multiphase clock signals.
- a semiconductor integrated circuit comprises: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.
- FIG. 1 is a circuit diagram showing a configuration of a voltage-controlled differential ring oscillator used in conventional semiconductor integrated circuits.
- FIG. 2 is a waveform diagram showing voltage waveforms of multiphase clock signals output from the voltage controlled differential ring oscillator as shown in FIG. 1.
- FIG. 3A is a schematic diagram showing multiphase clock signal wirings in a conventional semiconductor integrated circuits and equivalents of stray capacities between these wirings
- FIG. 3B is a waveform diagram showing how the voltage waveform of a clock signal is degraded by crosstalk due to the stray capacity.
- FIGS. 4A and 4B show wirings in the conventional semiconductor integrated circuit which are modified to prevent degradations of waveforms of the multiphase clock signals.
- FIG. 5 shows a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.
- FIG. 6 is a waveform diagram showing voltage waveforms of multiphase clock signals output from a voltage-controlled differential ring oscillator as shown in FIG. 5.
- FIG. 7A shows an example arrangement of wirings in the semiconductor integrated circuit according to the first embodiment of the present invention
- FIG. 7B shows voltage waveforms of clock signals in the example arrangement of wirings as shown in FIG. 7A.
- FIG. 8A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to the first embodiment of the present invention
- FIG. 8B shows an example arrangement of multiphase clock signal wirings in a conventional semiconductor integrated circuit.
- FIG. 9 is a waveform diagram showing voltage waveforms of multiphase clock signals output from a voltage-controlled differential ring oscillator in a semiconductor integrated circuit according to a second embodiment of the present invention.
- FIG. 10A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to the second embodiment of the present invention
- FIG. 10B shows voltage waveforms of the multiphase clock signals in the arrangement as shown in FIG. 10A.
- FIG. 11 is a waveform diagram showing voltage waveforms of multiphase clock signals output from a voltage-controlled differential ring oscillator in a semiconductor integrated circuit according to a third embodiment of the present invention.
- FIG. 12A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to the third embodiment of the present invention
- FIG. 12B shows voltage waveforms of the multiphase clock signals in the wiring arrangement as shown in FIG. 12A.
- FIG. 5 shows a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.
- this semiconductor integrated circuit includes a voltage-controlled differential ring oscillator 500 for outputting multiphase clock signals and a parallel-serial converter 600 for converting received parallel data into serial data on the basis of the multiphase clock signals.
- the parallel-serial converter 600 may be provided on the outside of the semiconductor integrated circuit.
- the voltage-controlled differential ring oscillator 500 includes N stages of delayed differential inverted amplifiers 101 a , 101 b , . . . for performing oscillating operation and logic circuits 502 a , 502 b , . . . for performing logic operation on the basis of output signals of the delayed differential inverted amplifiers 101 a , 101 b , . . . to output clock signals having M phases.
- N is a positive even number and M is an even number within a range from 2 to N.
- Each of the delayed differential inverted amplifiers 101 a - 101 j amplifies a difference between a signal applied to a non-inverted input terminal and a signal applied to an inverted input terminal and supplies the amplified differential signal to a non-inverted output terminal and an inverted output terminal.
- the delayed differential inverted amplifiers 101 a - 101 j are connected in a ring form so that a non-inverted output terminal of the previous stage is connected to an inverted input terminal of the subsequent stage and an inverted output terminal of the previous stage is connected to a non-inverted input terminal of the subsequent stage.
- a non-inverted output terminal of a delayed differential inverted amplifier 101 j is connected to a non-inverted input terminal of a delayed differential inverted amplifier 101 a and that an inverted output terminal of the delayed differential inverted amplifier 101 j is connected to an inverted input terminal of the delayed differential inverted amplifier 101 a .
- a signal phase is inverted after passing through the ring once.
- the delay time of each of the delayed differential inverted amplifiers 101 a - 101 j is controlled by an applied control voltage or control current, allowing the oscillation frequency of the voltage-controlled differential ring oscillator 500 to be adjusted.
- the logic circuits include M AND gates 502 a - 502 j .
- An AND gate 502 a has one input terminal connected to the inverted output terminal of the delayed differential inverted amplifier 101 a and the other input terminal connected to the non-inverted output terminal of the delayed differential inverted amplifier 11 e .
- One input terminal of an AND gate 502 b is connected to the inverted output terminal of the delayed differential inverted amplifier 101 c and the other input terminal is connected to the non-inverted output terminal of the delayed differential inverted amplifier 101 g .
- the subsequent AND gates 502 c - 502 j are connected in the similar manner.
- the AND gates 502 a - 502 j produce multiphase clock signals S 1 -S 10 as shown in FIG. 6.
- FIG. 7A a set of clock signal wirings (S 1 , S 6 ) is shown in FIG. 7A as an example of wiring arrangement.
- a wiring for a clock signal S 1 and a wiring for a clock signal S 6 are arranged in parallel on a semiconductor substrate.
- ground wirings GND are arranged for electrostatic shielding.
- FIG. 7B shows voltage waveforms of the clock signals S 1 and S 6 in the wiring arrangement as shown in FIG. 7A.
- the set of clock signal wirings (S 1 , S 6 ) is so arranged that one clock signal changes its level when another clock signal is maintained at a low level (at a ground voltage level).
- the clock signal wiring at the ground voltage level has a sufficiently small impedance compared with an impedance of a crosstalk source, and therefore, it has a function of electrostatic shield in the same way as a ground wiring GND.
- a wiring for the clock signal S 1 is shielded by a ground wiring GND and a wiring for the clock signal S 6 . Therefore, as shown in FIG. 7B, if the clock signal S 1 changes its level in this period, its waveform is protected against being deformed at that time.
- FIG. 8A shows an arrangement of multiphase clock signal wirings according to this embodiment and, for comparison, FIG. 8B shows an example of conventional arrangement of multiphase clock signal wirings.
- the sets of clock signal wirings S 1 , S 6 ), (S 2 , S 7 ), (S 3 , S 8 ), (S 4 , S 9 ) and (S 5 , S 10 ) each has two clock signal wirings arranged parallel to each other on the semiconductor substrate are arranged with ground wirings GND inserted between respective two sets of clock signal wirings.
- clock signal wirings R 1 -R 10 and ground wirings GND are alternately arranged on the semiconductor substrate.
- FIG. 8A and FIG. 8B shows that the wiring area of the semiconductor substrate in this embodiment is about 25% less than that in the conventional technique.
- FIG. 9 shows voltage waveforms of multiphase clock signals S 1 -S 12 output from the 12-stage voltage-controlled differential ring oscillator.
- clock signal wirings are grouped into plural sets of three clock signal wirings and, in each set of three clock signal wirings, it is possible that when one clock signal changes its level, both of the other two clock signals are maintained at a low level.
- clock signals are grouped into plural sets of three clock signals by using plural sets of clock signal wirings (S 1 , 5 , S 9 ), (S 2 , S 6 , S 10 ), (S 3 , S 7 , S 11 ) and (S 4 , S 8 , S 12 ).
- each set of clock signal wirings when one of the three clock signals changes its level, the other two clock signals can be certainly maintained at a low level.
- FIG. 10A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to this embodiment.
- the sets of clock signal wirings S 1 , S 5 , S 9 ), (S 2 , S 6 , S 10 ), (S 3 , S 7 , S 11 ) and (S 4 , S 8 , S 12 )
- three clock signal wirings are arranged parallel to each other on the semiconductor substrate, with ground wirings GND interposed between respective two sets of clock signal wirings.
- FIG. 10B shows voltage waveforms of clock signals S 1 , S 5 , S 9 in the semiconductor integrated circuit of this embodiment.
- the clock signal S 5 performs a voltage level transition
- the clock signals S 1 and S 9 are certainly maintained at a low level. Therefore, the wiring for the clock signal S 5 is virtually shielded by the wirings for the clock signals S 1 and S 9 and no voltage waveform deformation is observed with the clock signal S 5 at that time.
- the clock signal S 1 or S 9 changes its voltage level, the clock signal S 5 is certainly maintained at a low level, so that wiring for the clock signal S 1 or S 9 is virtually shielded by wiring for the clock signal S 5 and a ground wiring GND.
- the wiring area of the semiconductor substrate can be reduced by approximately 36% compared with that of the conventional arrangement in which clock signal wirings and ground wirings are alternately arranged.
- FIG. 11 shows voltage waveforms of multiphase clock signals S 1 -S 16 output from the 16-stage voltage-controlled differential ring oscillator.
- clock signal wirings are grouped into plural sets of four clock signal wirings and, in each set of four clock signal wirings, it is possible that when one clock signal changes its level, the remaining three clock signals are maintained at a low level.
- clock signals are grouped into plural sets of four clock signals by using plural sets of four clock signal wirings (S 1 , S 5 , S 9 , S 13 ), (S 2 , S 6 , S 10 , S 14 ), (S 3 , S 7 , S 11 , S 15 ) and (S 4 , S 8 , S 12 , S 16 ).
- FIG. 12A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to this embodiment.
- each set of clock signal wirings S 1 , S 5 , S 9 , S 13 ), (S 2 , S 6 , S 10 , S 14 ), (S 3 , S 7 , S 11 , S 15 ) and (S 4 , S 8 , S 12 , S 16 )
- four clock signal wirings are arranged parallel to each other on the semiconductor substrate, with ground wirings GND interposed between respective two sets of clock signal wirings.
- FIG. 12B shows voltage waveforms of clock signals S 1 , S 5 , S 9 , S 13 in the semiconductor integrated circuit according to this embodiment.
- the remaining three clock signals are certainly maintained at a low level. Therefore, wiring of the level-changing clock signal is virtually shielded by wirings of the adjacent clock signal wirings and no voltage waveform deformation is observed with the level-changing clock signal at that time.
- the wiring area of the semiconductor substrate can be reduced by approximately 37% compared with that of the conventional arrangement in which clock signal wirings and ground wirings are alternately arranged.
- a ground wiring for electrostatic shielding is arranged between respective two set of clock signal wirings as a technique for preventing degradation of signals due to electrostatic coupling between respective two sets of clock signal wirings in the above embodiments
- a technique for preventing degradation of signals between respective two sets of clock signal wirings is not limited to this arrangement.
- the present invention can also be realized by employing other techniques.
- An example of such techniques involves increasing a distance between respective two sets of clock signal wirings to reduce stray capacities between adjacent two sets of clock signal wirings.
- the present invention can be applied to and implemented by any oscillator as long as it generates multiphase clock signals having the same phase difference.
- the present invention is not limited to the voltage-controlled differential ring oscillator and can be modified within a scope of claims.
- the present invention can be applied to semiconductor integrated circuits having a multi-stage ring oscillator that generates multiphase clock signals having the same phase difference.
Abstract
Description
- The present invention relates generally to a semiconductor integrated circuit and more particularly to a semiconductor integrated circuit including a differential ring multiphase oscillator.
- For signal transmission among devices, a technique employing high-speed and small-amplitude serial signals has been in use in recent years. Compared with a technique that transmits digital signals in parallel, this technique needs only a small number of cables and also can minimize electromagnetic interference (EMI) caused by the digital signal transmission.
- To realize a high-speed serial communication, a parallel-serial converter is required on a transmit side which converter converts parallel data into serial data by using sub-clock signals having multiple phases (hereinafter, such clock signals are referred to as multiphase clock signals). The multiphase clock signals are synchronous with a base clock signal and have the same phase difference. Further, a multiphase clock generator is required which generates the multiphase clock signals and supplies them to the parallel-serial converter.
- An example of the multiphase clock generator is a voltage-controlled or current-controlled differential ring oscillator having multiple stages of delayed differential inverted amplifiers connected in a ring form. By using such a ring oscillator, it is possible to easily draw multiphase clock signals having the same phase difference out of the multi-staged amplifiers. However, in the case of designing wiring layout for the multiphase clock signals having precisely equal phase differences from the high-speed ring oscillator to the parallel-serial converter, the influences of electrostatic coupling between different wirings must be made uniform.
- FIG. 1 shows a voltage-controlled differential ring oscillator used in conventional semiconductor integrated circuits. As shown in FIG. 1, the voltage-controlled
differential ring oscillator 100 includes N stages of delayed differential inverted amplifiers 101 a-101 j which perform oscillating operation and output amplifiers 102 a-102 j which buffer output signals of the delayed differential inverted amplifiers 101 a-101 j to output multiphase clock signals. Shown here is a case of N=10. The output amplifiers 102 a-102 j buffer oscillation signals output from every other delayed differential inverted amplifiers 101 a-101 j connected in a ring form and supply them as multiphase clock signals R1-R10 to the parallel-serial converter. - FIG. 2 shows voltage waveforms of the multiphase clock signals R1-R10 output from the voltage-controlled differential ring oscillator as shown in FIG. 1. In FIG. 2, an abscissa represents time and an ordinate represents voltage. When we let “A” stand for a duration in which each clock signal is a high level and “B” for a cycle of the clock signal, a duty of each clock signal is set at D=A/B=0.5.
- FIG. 3A shows wirings or interconnects for three clock signals R1, R2, R3 formed in a semiconductor integrated circuit and capacitors Cp equivalently representing stray capacities between these wirings. FIG. 3B shows how crosstalks due to stray capacities degrade the voltage waveforms of the clock signals. As shown in FIG. 3B, a clock signal R2 undergoes voltage variations under the influence of crosstalks due to stray capacities each time the adjacent clock signals R1 and R3 change their voltage levels. An amount of voltage variation ΔV increases with the stray capacity Cp. In clock signals, information at the transition point is important, and therefore, crosstalk near the transition point has great effects on precision of the clock signals.
- To generate high-speed and small-amplitude serial signals, it is necessary to use multiphase clock signals having high frequencies. The use of multiphase clock signals having increased frequencies, however, results in that the phase difference to between the multiphase clock signals as shown in FIG. 3B becomes shorter, which in turn makes a transition waveform of the clock signal R2 more likely to be degraded by voltage variations due to the crosstalk induced when the adjacent clock signals R1 and R3 perform voltage level transitions. It is therefore desired that the circuit for generating high-speed and small-amplitude serial signals be designed to have as small stray capacities Cp as possible.
- The stray capacities Cp can be reduced, for example, by increasing the distance between the multiphase clock signal wirings as shown in FIG. 4A. FIG. 4A shows an example in which an interval of the multiphase clock signal wirings is increased by two times to halve the stray capacities. This method, however, increases a wiring area for the multiphase clock signals.
- Another technique for reducing the electrostatic coupling between adjacent two clock signal wirings may involve arranging another wiring between the adjacent two clock signal wirings as shown in FIG. 4B. FIG. 4B shows the new wiring added between adjacent two clock signal wirings and the new wiring is grounded. Alternatively, the new wiring may be supplied with a stable voltage. Such a technique can shield the adjacent two clock signal wirings electrostatically from one another and prevent possible degradations of clock signal waveforms which would otherwise be caused by level transitions of the adjacent clock signals. This technique, however, requires an additional area for laying the new wirings, increasing the wiring area for the multiphase clock signals.
- On the other hand, a number of multiphase clock signals having the same phase difference tends to increase at an accelerating rate in the future for a higher-speed serial communication. Hence, arranging wirings for the multiphase clock signals using the above-mentioned conventional technique requires a large wiring area, giving rise to a problem of an increased semiconductor substrate area. Under these circumstances, there are growing demands for a semiconductor integrated circuit that can prevent degradation of waveforms of multiphase clock signals without increasing the wiring area.
- It is therefore an object of the present invention to provide a semiconductor integrated circuit that can prevent multiphase clock signals having the same phase difference, which signals are generated by a multi-stage differential ring oscillator and transmitted to other circuits, from being degraded in waveform due to electrostatic coupling between wirings thereof and that enables the multiphase clock signals to be wired in as small an area as possible.
- To achieve the above object, a semiconductor integrated circuit according to the present invention comprises: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.
- According to the present invention, it is possible to prevent degradations of multiphase clock signal waveforms due to stray capacities without increasing the wiring area of the multiphase clock signals.
- Advantages and features of the present invention will become apparent when taken in conjunction with the following detailed description and the accompanying drawings. In these drawings, the same reference number represents identical constitutional elements.
- FIG. 1 is a circuit diagram showing a configuration of a voltage-controlled differential ring oscillator used in conventional semiconductor integrated circuits.
- FIG. 2 is a waveform diagram showing voltage waveforms of multiphase clock signals output from the voltage controlled differential ring oscillator as shown in FIG. 1.
- FIG. 3A is a schematic diagram showing multiphase clock signal wirings in a conventional semiconductor integrated circuits and equivalents of stray capacities between these wirings, and FIG. 3B is a waveform diagram showing how the voltage waveform of a clock signal is degraded by crosstalk due to the stray capacity.
- FIGS. 4A and 4B show wirings in the conventional semiconductor integrated circuit which are modified to prevent degradations of waveforms of the multiphase clock signals.
- FIG. 5 shows a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.
- FIG. 6 is a waveform diagram showing voltage waveforms of multiphase clock signals output from a voltage-controlled differential ring oscillator as shown in FIG. 5.
- FIG. 7A shows an example arrangement of wirings in the semiconductor integrated circuit according to the first embodiment of the present invention, and FIG. 7B shows voltage waveforms of clock signals in the example arrangement of wirings as shown in FIG. 7A.
- FIG. 8A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to the first embodiment of the present invention, and FIG. 8B shows an example arrangement of multiphase clock signal wirings in a conventional semiconductor integrated circuit.
- FIG. 9 is a waveform diagram showing voltage waveforms of multiphase clock signals output from a voltage-controlled differential ring oscillator in a semiconductor integrated circuit according to a second embodiment of the present invention.
- FIG. 10A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to the second embodiment of the present invention, and FIG. 10B shows voltage waveforms of the multiphase clock signals in the arrangement as shown in FIG. 10A.
- FIG. 11 is a waveform diagram showing voltage waveforms of multiphase clock signals output from a voltage-controlled differential ring oscillator in a semiconductor integrated circuit according to a third embodiment of the present invention.
- FIG. 12A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to the third embodiment of the present invention, and FIG. 12B shows voltage waveforms of the multiphase clock signals in the wiring arrangement as shown in FIG. 12A.
- FIG. 5 shows a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. As shown in FIG. 5, this semiconductor integrated circuit includes a voltage-controlled
differential ring oscillator 500 for outputting multiphase clock signals and a parallel-serial converter 600 for converting received parallel data into serial data on the basis of the multiphase clock signals. The parallel-serial converter 600 may be provided on the outside of the semiconductor integrated circuit. - The voltage-controlled
differential ring oscillator 500 includes N stages of delayed differentialinverted amplifiers logic circuits amplifiers - Each of the delayed differential inverted amplifiers101 a-101 j amplifies a difference between a signal applied to a non-inverted input terminal and a signal applied to an inverted input terminal and supplies the amplified differential signal to a non-inverted output terminal and an inverted output terminal. The delayed differential inverted amplifiers 101 a-101 j are connected in a ring form so that a non-inverted output terminal of the previous stage is connected to an inverted input terminal of the subsequent stage and an inverted output terminal of the previous stage is connected to a non-inverted input terminal of the subsequent stage. It is noted, however, that a non-inverted output terminal of a delayed differential
inverted amplifier 101 j is connected to a non-inverted input terminal of a delayed differentialinverted amplifier 101 a and that an inverted output terminal of the delayed differentialinverted amplifier 101 j is connected to an inverted input terminal of the delayed differentialinverted amplifier 101 a. With this arrangement, a signal phase is inverted after passing through the ring once. The delay time of each of the delayed differential inverted amplifiers 101 a-101 j is controlled by an applied control voltage or control current, allowing the oscillation frequency of the voltage-controlleddifferential ring oscillator 500 to be adjusted. - In this embodiment, the logic circuits include M AND gates502 a-502 j. An AND
gate 502 a has one input terminal connected to the inverted output terminal of the delayed differentialinverted amplifier 101 a and the other input terminal connected to the non-inverted output terminal of the delayed differential inverted amplifier 11 e. One input terminal of an ANDgate 502 b is connected to the inverted output terminal of the delayed differentialinverted amplifier 101 c and the other input terminal is connected to the non-inverted output terminal of the delayed differentialinverted amplifier 101 g. The subsequent ANDgates 502 c-502 j are connected in the similar manner. Thus, the AND gates 502 a-502 j produce multiphase clock signals S1-S10 as shown in FIG. 6. - In FIG. 6, when a duration in which the clock signal is high is denoted as “A” and a cycle of the clock signal as “B”, then a duty of the clock signal D=A/B is expressed as follows:
- D=(0.5−2/N) (1)
- If N=10, equation (1) results in D=0.3<0.5. Hence, two clock signal wirings can be combined such that one clock signal transits from a low level to a high level or from the high level to the low level when another clock signal is maintained at the low level (in this embodiment, ground potential). In this embodiment, sets of combined clock signal wirings (S1, S6), (S2, S7), (S3, S8), (S4, S9), and (S5, S10) are used.
- Among the above sets of clock signal wirings, a set of clock signal wirings (S1, S6) is shown in FIG. 7A as an example of wiring arrangement. In FIG. 7A, a wiring for a clock signal S1 and a wiring for a clock signal S6 are arranged in parallel on a semiconductor substrate. On the outside of these wirings, ground wirings GND are arranged for electrostatic shielding. FIG. 7B shows voltage waveforms of the clock signals S1 and S6 in the wiring arrangement as shown in FIG. 7A.
- As described above, the set of clock signal wirings (S1, S6) is so arranged that one clock signal changes its level when another clock signal is maintained at a low level (at a ground voltage level). The clock signal wiring at the ground voltage level has a sufficiently small impedance compared with an impedance of a crosstalk source, and therefore, it has a function of electrostatic shield in the same way as a ground wiring GND. For example, when the clock signal S6 has the ground voltage level, a wiring for the clock signal S1 is shielded by a ground wiring GND and a wiring for the clock signal S6. Therefore, as shown in FIG. 7B, if the clock signal S1 changes its level in this period, its waveform is protected against being deformed at that time.
- Similarly, as to other sets of clock signal wirings, in a period when one of the two clock signal wirings is at a low level, the other of the two clock signal wirings is virtually shielded. Therefore, by arranging clock signal wirings with ground wirings for shielding every set of clock signal wirings as described above, it is possible to prevent waveform deformations of multiphase clock signals that would otherwise be caused by electrostatic coupling between the wirings.
- FIG. 8A shows an arrangement of multiphase clock signal wirings according to this embodiment and, for comparison, FIG. 8B shows an example of conventional arrangement of multiphase clock signal wirings. In this embodiment as shown in FIG. 8A, the sets of clock signal wirings (S1, S6), (S2, S7), (S3, S8), (S4, S9) and (S5, S10) each has two clock signal wirings arranged parallel to each other on the semiconductor substrate are arranged with ground wirings GND inserted between respective two sets of clock signal wirings. On the other hand, in the conventional arrangement as shown in FIG. 8B, clock signal wirings R1-R10 and ground wirings GND are alternately arranged on the semiconductor substrate. Comparison between FIG. 8A and FIG. 8B shows that the wiring area of the semiconductor substrate in this embodiment is about 25% less than that in the conventional technique.
- Next, a semiconductor integrated circuit according to a second embodiment of the present invention will be described. The second embodiment uses the N-stage voltage-controlled differential ring oscillator as shown in FIG. 5 in a condition of N=12.
- FIG. 9 shows voltage waveforms of multiphase clock signals S1-S12 output from the 12-stage voltage-controlled differential ring oscillator. In this embodiment, the duty D of each clock signal is obtained from equation (1) as D=0.167. Hence, clock signal wirings are grouped into plural sets of three clock signal wirings and, in each set of three clock signal wirings, it is possible that when one clock signal changes its level, both of the other two clock signals are maintained at a low level. For example, in this embodiment, clock signals are grouped into plural sets of three clock signals by using plural sets of clock signal wirings (S1, 5, S9), (S2, S6, S10), (S3, S7, S11) and (S4, S8, S12). In each set of clock signal wirings, when one of the three clock signals changes its level, the other two clock signals can be certainly maintained at a low level.
- FIG. 10A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to this embodiment. As shown in FIG. 10A, in each of the sets of clock signal wirings (S1, S5, S9), (S2, S6, S10), (S3, S7, S11) and (S4, S8, S12), three clock signal wirings are arranged parallel to each other on the semiconductor substrate, with ground wirings GND interposed between respective two sets of clock signal wirings.
- FIG. 10B shows voltage waveforms of clock signals S1, S5, S9 in the semiconductor integrated circuit of this embodiment. As shown in FIG. 10B, when the clock signal S5 performs a voltage level transition, the clock signals S1 and S9 are certainly maintained at a low level. Therefore, the wiring for the clock signal S5 is virtually shielded by the wirings for the clock signals S1 and S9 and no voltage waveform deformation is observed with the clock signal S5 at that time. Further, when the clock signal S1 or S9 changes its voltage level, the clock signal S5 is certainly maintained at a low level, so that wiring for the clock signal S1 or S9 is virtually shielded by wiring for the clock signal S5 and a ground wiring GND.
- As described above, according to this embodiment, the wiring area of the semiconductor substrate can be reduced by approximately 36% compared with that of the conventional arrangement in which clock signal wirings and ground wirings are alternately arranged.
- Next, a semiconductor integrated circuit according to a third embodiment of the present invention will be described. The third embodiment uses the N-stage voltage-controlled differential ring oscillator as shown in FIG. 5 in a condition of N=16.
- FIG. 11 shows voltage waveforms of multiphase clock signals S1-S16 output from the 16-stage voltage-controlled differential ring oscillator. In this embodiment, the duty D of each clock signal is obtained from equation (1) as D=0.125. Hence, clock signal wirings are grouped into plural sets of four clock signal wirings and, in each set of four clock signal wirings, it is possible that when one clock signal changes its level, the remaining three clock signals are maintained at a low level. For example, in this embodiment, clock signals are grouped into plural sets of four clock signals by using plural sets of four clock signal wirings (S1, S5, S9, S13), (S2, S6, S10, S14), (S3, S7, S11, S15) and (S4, S8, S12, S16).
- FIG. 12A shows an arrangement of multiphase clock signal wirings in the semiconductor integrated circuit according to this embodiment. As shown in FIG. 12A, in each set of clock signal wirings (S1, S5, S9, S13), (S2, S6, S10, S14), (S3, S7, S11, S15) and (S4, S8, S12, S16), four clock signal wirings are arranged parallel to each other on the semiconductor substrate, with ground wirings GND interposed between respective two sets of clock signal wirings.
- FIG. 12B shows voltage waveforms of clock signals S1, S5, S9, S13 in the semiconductor integrated circuit according to this embodiment. As shown in FIG. 12B, when one of the clock signals in each set performs a voltage level transition, the remaining three clock signals are certainly maintained at a low level. Therefore, wiring of the level-changing clock signal is virtually shielded by wirings of the adjacent clock signal wirings and no voltage waveform deformation is observed with the level-changing clock signal at that time.
- As described above, according to this embodiment, the wiring area of the semiconductor substrate can be reduced by approximately 37% compared with that of the conventional arrangement in which clock signal wirings and ground wirings are alternately arranged.
- Although a ground wiring for electrostatic shielding is arranged between respective two set of clock signal wirings as a technique for preventing degradation of signals due to electrostatic coupling between respective two sets of clock signal wirings in the above embodiments, a technique for preventing degradation of signals between respective two sets of clock signal wirings is not limited to this arrangement. The present invention can also be realized by employing other techniques. An example of such techniques involves increasing a distance between respective two sets of clock signal wirings to reduce stray capacities between adjacent two sets of clock signal wirings.
- Although the voltage-controlled differential ring oscillator has been employed in the above embodiments, the present invention can be applied to and implemented by any oscillator as long as it generates multiphase clock signals having the same phase difference. Thus, the present invention is not limited to the voltage-controlled differential ring oscillator and can be modified within a scope of claims.
- According to the present invention, it is possible to prevent degradations of signal waveforms due to electrostatic coupling between multiphase clock signal wirings while reducing the wiring area of a semiconductor substrate for the multiphase clock signal wirings.
- The present invention can be applied to semiconductor integrated circuits having a multi-stage ring oscillator that generates multiphase clock signals having the same phase difference.
Claims (20)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000-226825 | 2000-07-27 | ||
JP2000226825A JP3615692B2 (en) | 2000-07-27 | 2000-07-27 | Multiphase clock oscillator |
PCT/JP2001/006204 WO2002011284A1 (en) | 2000-07-27 | 2001-07-18 | Semiconductor integrated circuit |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/008,957 Continuation US7158441B2 (en) | 2000-07-27 | 2004-12-13 | Semiconductor integrated circuit |
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US20040090828A1 true US20040090828A1 (en) | 2004-05-13 |
Family
ID=18720372
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US10/333,010 Abandoned US20040090828A1 (en) | 2000-07-27 | 2001-07-18 | Semiconductor integrated circuit |
US11/008,957 Expired - Lifetime US7158441B2 (en) | 2000-07-27 | 2004-12-13 | Semiconductor integrated circuit |
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Application Number | Title | Priority Date | Filing Date |
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US11/008,957 Expired - Lifetime US7158441B2 (en) | 2000-07-27 | 2004-12-13 | Semiconductor integrated circuit |
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US (2) | US20040090828A1 (en) |
JP (1) | JP3615692B2 (en) |
KR (1) | KR100706041B1 (en) |
CN (1) | CN1252922C (en) |
TW (1) | TW498539B (en) |
WO (1) | WO2002011284A1 (en) |
Families Citing this family (13)
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US20080043545A1 (en) * | 2004-04-29 | 2008-02-21 | Jan Vink | Multiple Data Rate Ram Memory Controller |
WO2008149981A1 (en) | 2007-06-08 | 2008-12-11 | Nec Corporation | Modulation device and pulse wave generation device |
JP2009021870A (en) * | 2007-07-12 | 2009-01-29 | Sony Corp | Signal-generating apparatus, filter apparatus, signal-generating method, and filtering method |
CN102265349B (en) * | 2008-11-05 | 2014-06-18 | 奈克斯特生物测定学公司 | Non-binary decoder architecture and control signal logic for reducing circuit complexity |
CN115051705A (en) | 2016-04-22 | 2022-09-13 | 康杜实验室公司 | High performance phase locked loop |
US10193716B2 (en) | 2016-04-28 | 2019-01-29 | Kandou Labs, S.A. | Clock data recovery with decision feedback equalization |
US10411922B2 (en) | 2016-09-16 | 2019-09-10 | Kandou Labs, S.A. | Data-driven phase detector element for phase locked loops |
US10693473B2 (en) | 2017-05-22 | 2020-06-23 | Kandou Labs, S.A. | Multi-modal data-driven clock recovery circuit |
US10554380B2 (en) | 2018-01-26 | 2020-02-04 | Kandou Labs, S.A. | Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation |
US10958251B2 (en) | 2019-04-08 | 2021-03-23 | Kandou Labs, S.A. | Multiple adjacent slicewise layout of voltage-controlled oscillator |
US11463092B1 (en) | 2021-04-01 | 2022-10-04 | Kanou Labs Sa | Clock and data recovery lock detection circuit for verifying lock condition in presence of imbalanced early to late vote ratios |
US11563605B2 (en) | 2021-04-07 | 2023-01-24 | Kandou Labs SA | Horizontal centering of sampling point using multiple vertical voltage measurements |
US11496282B1 (en) | 2021-06-04 | 2022-11-08 | Kandou Labs, S.A. | Horizontal centering of sampling point using vertical vernier |
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US5668505A (en) * | 1996-03-13 | 1997-09-16 | Symbol Technologies, Inc. | Ring oscillator having two rings whose outputs are combined |
US6426662B1 (en) * | 2001-11-12 | 2002-07-30 | Pericom Semiconductor Corp. | Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays |
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US4494021A (en) * | 1982-08-30 | 1985-01-15 | Xerox Corporation | Self-calibrated clock and timing signal generator for MOS/VLSI circuitry |
JPH0739240B2 (en) * | 1992-05-06 | 1995-05-01 | 雅子 山上 | Luminous decorative fabric |
JP3240713B2 (en) * | 1992-11-13 | 2001-12-25 | 日本電気株式会社 | Polyphase clock generation circuit |
US5596302A (en) * | 1996-01-17 | 1997-01-21 | Lucent Technologies Inc. | Ring oscillator using even numbers of differential stages with current mirrors |
US5777567A (en) * | 1996-06-14 | 1998-07-07 | Sun Microsystems, Inc. | System and method for serial to parallel data conversion using delay line |
DE19736857C1 (en) * | 1997-08-23 | 1999-01-07 | Philips Patentverwaltung | Ring oscillator |
US6152347A (en) * | 1998-01-30 | 2000-11-28 | Acco Brands, Inc. | Vertical Stapler |
-
2000
- 2000-07-27 JP JP2000226825A patent/JP3615692B2/en not_active Expired - Lifetime
-
2001
- 2001-07-18 CN CNB018133215A patent/CN1252922C/en not_active Expired - Lifetime
- 2001-07-18 WO PCT/JP2001/006204 patent/WO2002011284A1/en active Application Filing
- 2001-07-18 US US10/333,010 patent/US20040090828A1/en not_active Abandoned
- 2001-07-18 KR KR1020037000996A patent/KR100706041B1/en active IP Right Grant
- 2001-07-19 TW TW090117672A patent/TW498539B/en not_active IP Right Cessation
-
2004
- 2004-12-13 US US11/008,957 patent/US7158441B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US5668505A (en) * | 1996-03-13 | 1997-09-16 | Symbol Technologies, Inc. | Ring oscillator having two rings whose outputs are combined |
US6426662B1 (en) * | 2001-11-12 | 2002-07-30 | Pericom Semiconductor Corp. | Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays |
Also Published As
Publication number | Publication date |
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KR20030047994A (en) | 2003-06-18 |
US7158441B2 (en) | 2007-01-02 |
US20050104673A1 (en) | 2005-05-19 |
KR100706041B1 (en) | 2007-04-11 |
JP3615692B2 (en) | 2005-02-02 |
CN1444797A (en) | 2003-09-24 |
JP2002043905A (en) | 2002-02-08 |
WO2002011284A1 (en) | 2002-02-07 |
CN1252922C (en) | 2006-04-19 |
TW498539B (en) | 2002-08-11 |
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