US20040119169A1 - Radio frequency integrated circuit having increased substrate resistance enabling three dimensional interconnection with feedthroughs - Google Patents
Radio frequency integrated circuit having increased substrate resistance enabling three dimensional interconnection with feedthroughs Download PDFInfo
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- US20040119169A1 US20040119169A1 US10/328,213 US32821302A US2004119169A1 US 20040119169 A1 US20040119169 A1 US 20040119169A1 US 32821302 A US32821302 A US 32821302A US 2004119169 A1 US2004119169 A1 US 2004119169A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Abstract
Description
- These teachings relate generally to integrated circuits (ICs) and, more specifically, relate to radio frequency (RF) ICs and to techniques for stacking ICs in three dimensional (3D) packaging arrangements.
- In order to reduce the size of devices certain IC stacking structures have been developed. The stacking structures rely on a through-hole interconnection structure, also referred to in the art as a feedthrough or as a via, for making vertical connections between ICs that are stacked one upon another. In combination with the horizontal connections made within the ICs themselves, this technique provides a 3D IC packaging structure, thereby increasing the density and reducing the required package area. As compared with conventional wire-bond interconnections, the 3D packaging structure has a much greater potential for miniaturization.
- A problem exists, however, when one of the ICs to be stacked is an IC that handles RF signals, such as those of about one GHz (109 Hertz) and greater, as the electrical performance is degraded due at least in part to insertion losses experienced by the RF signals at the through-hole interconnection structures. This problem relates to the fact that, in conventional 3D IC packaging approaches, the IC substrates (Si) typically have a resistivity of about 10 ohms-centimeter (10 ohms-cm) in order to enable the substrate to function as a ground. A result of the use of such low resistivity substrate material is that the substrate can appear as a capacitor to a high frequency signal, and can thereby deteriorate the signal.
- At present, the application of through-hole interconnections in 3D IC structures is assumed for low-speed digital, or low frequency applications such as memory modules. Reference may be had to K.Kondo et al., “High Aspect Ratio Copper Via Fill used for Three Dimensional Chip Stacking”, 2002 ICEP Proceedings, pp. 327, for a description of current state-of-the-art through-hole technology in the context of 3D IC stacking.
- General reference with regard to a wafer stacking technique that can involve an RF circuit may be made to U.S. Pat. No.: 6,489,217B1, Method of Forming an Integrated Circuit on a Low Loss Substrate, A. Kalnitsky et al., Dec. 03, 2002 (Maxim Integrated Products, Inc.), such as FIG. 9 and col. 4, lines 43-53. This patent discloses in part varying the dopant concentration of a silicon substrate or an epitaxial layer in order to increase the resistivity thereof to several thousand ohms-cm (col. 3, line 62 to col. 4, line6).
- The foregoing and other problems are overcome, and other advantages are realized, in accordance with the presently preferred embodiments of these teachings.
- This invention provides for the use of the through-hole interconnection structure for not only low-speed and low frequency ICs, but also for RF and other high-speed application ICs. By the use of this invention an RF IC, or other type of high-speed IC, can be stacked with other types of ICs to thereby benefit from the advantages inherent in miniaturized devices, such as SiP (System in Package) solutions.
- This invention provides a method for forming a three dimensional integrated circuit stacked structure, as well as a stacked structure formed in accordance with the method. The method includes placing a first integrated circuit atop a second integrated circuit, and electrically connecting the first and the second integrated circuits at connection points. At least some of the connection points correspond to electrically conductive through-hole structures made through a silicon substrate of the first integrated circuit. The first one of the integrated circuits contains circuitry operating at frequencies equal to or greater than about 1 GHz, and the silicon substrate has a resistivity of at least about 100 ohms-cm. The result is that the electrical performance is not degraded, as the RF signal insertion loss at the through-hole interconnection structures is significantly reduced.
- In an exemplary embodiment the first integrated circuit contains RF circuitry and the second integrated circuit contains baseband circuitry. The second integrated circuit has a second silicon substrate that may also have a resistivity of at least about 100 ohms-cm. In the preferred embodiment the first and the second integrated circuits form a part of a wireless communications device, such as a cellular telephone.
- The foregoing and other aspects of these teachings are made more evident in the following Detailed Description of the Preferred Embodiments, when read in conjunction with the attached Drawing Figures, wherein:
- FIG. 1 is an enlarged, cross-sectional view of a silicon substrate that contains a through-hole structure;
- FIG. 2 is a chart showing insertion loss a function of frequency for substrates of different resistivities;
- FIG. 3 is a chart that plots substrate resistivity versus insertion loss at 10 GHz;
- FIG. 4A is a block diagram of a wireless communications device showing three exemplary functional units, i.e., an RF unit, a baseband (BB) unit and an energy management (EM) unit, each embodied in an IC; and
- FIG. 4B shows a 3D stacked IC arrangement corresponding to the wireless communications device shown in FIG. 4A.
- FIG. 1 is an enlarged, cross-sectional view of an
IC substrate 10 that contains a through-hole structure 12. TheIC substrate 10 is assumed to contain or support RF or other high speed circuitry. Thesubstrate 10 includes asilicon body 14 through which the through-hole structure 12 is made by any conventional process, such as masking and etching. In accordance with conventional practice there is at least one layer ofdielectric material 16 overlying a surface of thesubstrate 10, such as a layer of native silicon dioxide (SiO2). In other embodiments other types of oxides can be employed, as can layers of polymeric materials. In the preferred embodiment the dielectric material also forms aninsulating sleeve 16A within the through-hole structure 12. Electrical conductivity is established from the top-side surface 10A to the bottom-side surface 10B of thesubstrate 10 by an electrically conductive material such as, but not limited to,metal 18, that fills the through-hole structure 12 within thesleeve 16A. Themetal 18 may be copper, or aluminum, or any suitable low resistivity metal, or alloy, or multi-layered metal system. An electricallyconductive contact 20, such as a solder ball, is formed on the exposedmetal 18 at the bottom-side surface 10B of thesubstrate 10. Thecontact 20 may be used to form an electrical contact to a corresponding electrical contact, such as a planar pad, on another IC (not shown in FIG. 1) upon which thesubstrate 10 is stacked. - In accordance with this invention, the
silicon body 14 is comprised of silicon having a resistivity of at least about 100 ohms-cm. As is well known in the art, the resistivity of a silicon substrate can be changed by changing the concentration of dopants. Reference in this regard can be made, as one example, to U.S. Pat. No. 6,478,883 B1, Silicon Single Crystal Wafer, Epitaxial Silicon Wafer, and Methods for Producing Them, M. Tamatsuka et al. Nov. 12, 2002, (Shin-Etsu Handotai Co., Ltd). This particular patent shows the use of boron-doped single crystal silicon having a resistivity of from 10-100 million ohms-cm, as well as antimony-doped and phosphorus-doped single crystal silicon wafers. - Reference is made to the graphs of FIGS. 2 and 3 for showing simulation results of insertion loss of the through-
hole interconnection structure 12, where the resistivity of thesilicon body 14 portion of thesubstrate 10 is varied. In FIG. 2 “Metal” means that thesilicon body 14 portion is assumed to be a perfect electrical conductor, and “Insulator” means that thesilicon body 14 portion is assumed to have infinite resistivity. As is shown in FIGS. 2 and 3, if the resistivity of thesilicon body 14 portion is about at least 100 ohm-cm, or larger, the insertion loss of the through-hole interconnection structure 12 is small, at least up to 10 GHz, and is thus suitable for use with current RF and other high speed ICs. - Exemplary and non-limiting dimensions and other parameters relating to the results shown in FIGS. 2 and 3 are as follows: thickness of the substrate (silicon body14): 50 micrometers; diameter of the through-hole structure 12: 50 micrometers; thickness of the dielectric material (oxide) 16: 0.5 micrometers; and boron as the dopant for the
Si substrate 14. In this non-limiting example a boron concentration of the 1015 atoms/cm3 results in a substrate resistivity of 10 ohms-cm, while reducing the boron concentration to about 1014 atoms/cm3 results in the desired substrate resistivity of about 100 ohms-cm. - FIG. 4A illustrates an example of a system containing several integrated circuits (ICs)1, 2 and 3 with various signal types in a wireless communication terminal or device, such as a cellular telephone or a personal communicator. Signaling between the
ICs cells 4 contained within each IC. In the illustrated example, IC 1 is an RF IC containing high speed analog circuitry with low level signals, such as RF amplifiers, RF mixers, and RF oscillators,IC 2 is baseband (BB) IC characterized by high speed digital signals and circuits, such as a digital signal processor (DSP), andIC 3 is an energy management (EM) device employing mixed low speed analog and digital circuitry. - FIG. 4B is an enlarged cross-sectional view showing a non-limiting example of a 3D stacked
IC structure 5 corresponding to the wireless communications device shown in FIG. 4A. In this example thestructure 5 has, from top to bottom, theRF IC 1, theBB IC 2 and theEM IC 3. Note that some of the through-hole structures 12 connect only theRF IC 1 to theBB IC 2, some of the through-hole structures 12 connect only theBB IC 2 to theEM IC 3, while some others of the through-hole structures 12 connect theRF IC 1 to theEM IC 3, via through-hole structures 12 that pass through theBB IC 2. After stacking theintegrated circuits solder balls 20 can be melted for providing electrical contacts between the ICs. - In accordance with this invention, the
silicon body 14 of at least the RF IC 1 (and possible also theBB IC 2, depending on the clock frequencies used for the digital circuits) is comprised of silicon having a resistivity of at least about 100 ohms-cm. Note that it may be desirable to provide the at least 100 ohm-cm resistivity Si substrate, even if theBB IC 2 does not operate with high frequency signals, if theBB IC 2 is required to conduct high frequency signals between theRF IC 1 and another IC below theBB IC 2. - In any event, the use of the at least 100 ohm-cm resistivity substrate material results in the electrical performance not being degraded, as in the prior art low resistivity (e.g., 10 ohms-cm) silicon substrates used in stacked IC structures, as the RF signal insertion loss at the through-
hole interconnections 12 is significantly reduced, as was shown above in FIGS. 2 and 3. - Furthermore, the use of the at least 100 ohm-cm resistivity substrate material is advantageous in that the use of (unnecessarily) higher resistivity substrates (e.g., at least several thousands of ohms-cm) can result in unstable electrical potentials and interference between ICs. In addition, unnecessarily higher resistivity substrates may be more costly. The use of the at least 100 ohm-cm resistivity substrate material is presently preferred, as is a substrate having a resistivity of less that about 1000 ohms-cm, or more preferably less than about 500 ohms-cm, or even more preferably less than about 250 ohms-cm.
- While at first glance it might appear that the similar results may be obtained by using thicker layers of the
dielectric material 16, in practice the growth of thick dielectric films is expensive and time consuming. Furthermore, a reliable process for growing a thick layer of dielectric on the edges of a sidewall, to form the insulatingsleeve 16A, is not generally available. However, increasing the resistivity of thesubstrate 14 by varying the dopant concentration so as to reach the threshold resistivity of about 100 ohms-cm is a much more cost effective approach, and is currently preferred. - If grounding structures or layers are desired they can be provided using metallization, and contacted using the through-
hole structures 12. - While described in the context of presently preferred embodiments thereof, those skilled in the art should appreciate that a number of modifications may be made thereto, and that all such modifications will fall within the scope of this invention.
Claims (13)
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US10/328,213 US6756681B1 (en) | 2002-12-23 | 2002-12-23 | Radio frequency integrated circuit having increased substrate resistance enabling three dimensional interconnection with feedthroughs |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110175223A1 (en) * | 2005-05-19 | 2011-07-21 | Wood Alan G | Stacked Semiconductor Components Having Conductive Interconnects |
US20120193782A1 (en) * | 2011-01-31 | 2012-08-02 | Fujitsu Limited | Semiconductor device, method of manufacturing semiconductor device, and electronic device |
US8581387B1 (en) | 2006-04-24 | 2013-11-12 | Micron Technology, Inc. | Through wire interconnect (TWI) having bonded connection and encapsulating polymer layer |
US9013044B2 (en) | 2005-12-07 | 2015-04-21 | Micron Technology, Inc. | Through wire interconnect (TWI) for semiconductor components having wire in via and bonded connection with substrate contact |
US10945647B2 (en) * | 2006-02-28 | 2021-03-16 | Abbott Diabetes Care Inc. | Analyte sensor transmitter unit configuration for a data monitoring and management system |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5526320A (en) | 1994-12-23 | 1996-06-11 | Micron Technology Inc. | Burst EDO memory device |
JP2004095849A (en) * | 2002-08-30 | 2004-03-25 | Fujikura Ltd | Method for manufacturing semiconductor substrate with through electrode, and method for manufacturing semiconductor device with through electrode |
US6934199B2 (en) * | 2002-12-11 | 2005-08-23 | Micron Technology, Inc. | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency |
US6961259B2 (en) * | 2003-01-23 | 2005-11-01 | Micron Technology, Inc. | Apparatus and methods for optically-coupled memory systems |
KR100543729B1 (en) * | 2004-03-24 | 2006-01-20 | 아바고테크놀로지스코리아 주식회사 | RF IC package for improving heat transfer rate and for reducing height and size of package and assembly method thereof |
US7768113B2 (en) * | 2005-05-26 | 2010-08-03 | Volkan Ozguz | Stackable tier structure comprising prefabricated high density feedthrough |
US7919844B2 (en) * | 2005-05-26 | 2011-04-05 | Aprolase Development Co., Llc | Tier structure with tier frame having a feedthrough structure |
TWI287273B (en) * | 2006-01-25 | 2007-09-21 | Advanced Semiconductor Eng | Three dimensional package and method of making the same |
TWI293499B (en) | 2006-01-25 | 2008-02-11 | Advanced Semiconductor Eng | Three dimensional package and method of making the same |
US7474005B2 (en) * | 2006-05-31 | 2009-01-06 | Alcatel-Lucent Usa Inc. | Microelectronic element chips |
TWI422009B (en) * | 2010-07-08 | 2014-01-01 | Nat Univ Tsing Hua | Multi-chip stacked structure |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5063177A (en) * | 1990-10-04 | 1991-11-05 | Comsat | Method of packaging microwave semiconductor components and integrated circuits |
US5882997A (en) * | 1996-09-30 | 1999-03-16 | Vlsi Technology, Inc. | Method for making devices having thin load structures |
US6185107B1 (en) * | 1998-12-23 | 2001-02-06 | Raytheon Company | MEMS based tile assemblies and methods of fabrication |
US20030119308A1 (en) * | 2001-12-20 | 2003-06-26 | Geefay Frank S. | Sloped via contacts |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6478883B1 (en) | 1998-08-31 | 2002-11-12 | Shin-Etsu Handotai Co., Ltd. | Silicon single crystal wafer, epitaxial silicon wafer, and methods for producing them |
US6489217B1 (en) | 2001-07-03 | 2002-12-03 | Maxim Integrated Products, Inc. | Method of forming an integrated circuit on a low loss substrate |
-
2002
- 2002-12-23 US US10/328,213 patent/US6756681B1/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5063177A (en) * | 1990-10-04 | 1991-11-05 | Comsat | Method of packaging microwave semiconductor components and integrated circuits |
US5882997A (en) * | 1996-09-30 | 1999-03-16 | Vlsi Technology, Inc. | Method for making devices having thin load structures |
US6185107B1 (en) * | 1998-12-23 | 2001-02-06 | Raytheon Company | MEMS based tile assemblies and methods of fabrication |
US20030119308A1 (en) * | 2001-12-20 | 2003-06-26 | Geefay Frank S. | Sloped via contacts |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110175223A1 (en) * | 2005-05-19 | 2011-07-21 | Wood Alan G | Stacked Semiconductor Components Having Conductive Interconnects |
US8546931B2 (en) * | 2005-05-19 | 2013-10-01 | Micron Technology, Inc. | Stacked semiconductor components having conductive interconnects |
US9013044B2 (en) | 2005-12-07 | 2015-04-21 | Micron Technology, Inc. | Through wire interconnect (TWI) for semiconductor components having wire in via and bonded connection with substrate contact |
US10945647B2 (en) * | 2006-02-28 | 2021-03-16 | Abbott Diabetes Care Inc. | Analyte sensor transmitter unit configuration for a data monitoring and management system |
US11179072B2 (en) | 2006-02-28 | 2021-11-23 | Abbott Diabetes Care Inc. | Analyte sensor transmitter unit configuration for a data monitoring and management system |
US11179071B2 (en) | 2006-02-28 | 2021-11-23 | Abbott Diabetes Care Inc | Analyte sensor transmitter unit configuration for a data monitoring and management system |
US8581387B1 (en) | 2006-04-24 | 2013-11-12 | Micron Technology, Inc. | Through wire interconnect (TWI) having bonded connection and encapsulating polymer layer |
US8741667B2 (en) | 2006-04-24 | 2014-06-03 | Micron Technology, Inc. | Method for fabricating a through wire interconnect (TWI) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer |
US9018751B2 (en) | 2006-04-24 | 2015-04-28 | Micron Technology, Inc. | Semiconductor module system having encapsulated through wire interconnect (TWI) |
US20120193782A1 (en) * | 2011-01-31 | 2012-08-02 | Fujitsu Limited | Semiconductor device, method of manufacturing semiconductor device, and electronic device |
US8692386B2 (en) * | 2011-01-31 | 2014-04-08 | Fujitsu Limited | Semiconductor device, method of manufacturing semiconductor device, and electronic device |
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US6756681B1 (en) | 2004-06-29 |
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