US20040119531A1 - Dc offset canceling circuit applied in a variable gain amplifier - Google Patents
Dc offset canceling circuit applied in a variable gain amplifier Download PDFInfo
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- US20040119531A1 US20040119531A1 US10/327,473 US32747302A US2004119531A1 US 20040119531 A1 US20040119531 A1 US 20040119531A1 US 32747302 A US32747302 A US 32747302A US 2004119531 A1 US2004119531 A1 US 2004119531A1
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- amplifier
- variable gain
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- chopper circuit
- circuit
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- 238000001914 filtration Methods 0.000 claims 2
- 230000001131 transforming effect Effects 0.000 claims 1
- 238000001228 spectrum Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/38—Dc amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers
- H03F3/387—Dc amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
- H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
- H03F3/45973—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using a feedback circuit
- H03F3/45977—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using a feedback circuit using switching means, e.g. sample and hold
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/168—Two amplifying stages are coupled by means of a filter circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45212—Indexing scheme relating to differential amplifiers the differential amplifier being designed to have a reduced offset
Definitions
- the present invention relates to a DC offset canceling circuit applied in a variable gain amplifier, and particularly to a DC offset canceling circuit which utilizes a chopper stabilization method to cancel DC offset of output stage.
- VGA Variable gain amplifiers
- a differential input end of an internal operational amplifier has the problem of intrinsic offset, and the intrinsic offset is always in the range of several mV to tens of mV.
- the maximum gain of variable gain amplification is up to tens of dB; therefore, the intrinsic offset after amplification will affect the recovery ability of the received signal, the characteristics of parameters of a dynamic range, and signal-to-noise ratio.
- a DC offset canceling circuit is shown in FIG. 1, disclosed by Yao et al., in “DC offset canceling circuit applied in a variable gain amplifier” U.S. Pat. No. 6,407,630 B1.
- a DC offset circuit 26 applied in a variable gain amplifier 25 .
- the variable gain amplifier 25 includes a first amplifier 21 , a second amplifier 22 , a plurality of switches 201 ⁇ 208 , and a plurality of resistors.
- the DC offset canceling circuit 26 includes a transconductance amplifier 23 and at least one internal capacitor 24 .
- the switches 201 ⁇ 204 adjust the variable gain of the first amplifier 21 .
- the switch 201 For example, if the switch 201 is closed, the gain is raised; and if the switch 202 is closed, the gain is reduced.
- the switches 205 ⁇ 208 adjust the variable gain of the first amplifier 22 . For example, if the switch 205 is closed, the gain is raised; and if the switch 207 is closed, the gain is reduced.
- the transconductance amplifier 23 is used to transform the output voltage of the second amplifier 22 to an output current based on a ratio.
- the output of the transconductance amplifier 23 is coupled to at least one internal capacitor 24 , and is then fed back to the input of the first amplifier 21 to cancel the DC offset of the variable gain amplifier 25 .
- the transconductance amplifier 23 cooperates with the internal capacitor 24 , only about 10 pF or even under 10 pF, as a Gm-C filter. Since the capacitance of the internal capacitor 24 is small, the internal capacitor 24 can be manufactured easily inside an IC, and does not occupy I/O pin.
- the present invention provides a DC offset canceling circuit including a transconductance amplifier, at least one internal capacitor, and chopper circuits.
- a first chopper circuit 30 is inserted between the output of the variable gain amplifier and the input of the transconductance amplifier.
- a second chopper circuit is inserted between the output of the transconductance amplifier and the capacitor.
- the first chopper circuit and the second chopper circuit are controlled by a non-overlap clock signal having a chopping frequency.
- the first chopper circuit can be merged into the input of transconductance amplifier.
- the second chopper circuit can be merged into the output of transconductance amplifier.
- the DC offset and low frequency noise of the transconductance amplifier, the undesired signal is translated up to the chopping frequency.
- the spectrum of the undesired signal is folded back around the chopping frequency.
- the chopping frequency is much higher than the desired signal bandwidth, thus the size of the undesired signal in the passband of the signal is greatly reduced.
- the transconductance amplifier and capacitor serve the same function, canceling the DC offset of the variable gain amplifier.
- the chopper circuit cancels the DC offset of the transconductance amplifier.
- FIG. 1 shows a DC offset canceling circuit in the prior art.
- FIG. 2 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the first embodiment.
- FIG. 3 is a block diagram of the chopper circuit applied in the variable gain amplifier.
- FIG. 4A ⁇ 4 D show the spectra of the desired and undesired signals.
- FIG. 5A is a schematic of the chopper circuit applied in the present invention.
- FIG. 5B is a schematic of the transconductance amplifier applied in the present invention.
- FIGS. 6 A ⁇ 6 B shows the operation of the chopper circuits.
- FIG. 7 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the second embodiment.
- FIG. 8 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the third embodiment.
- FIG. 9 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the fourth embodiment.
- FIG. 2 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the first embodiment.
- the first chopper circuit 30 is inserted between the second amplifier 22 and the transconductance amplifier 23 .
- the second chopper circuit 35 is inserted between the transconductance amplifier 23 and capacitor 24 .
- FIG. 3 is a block diagram of the chopper circuit applied in the variable gain amplifier.
- the chopper circuit 30 and 35 are controlled by non-overlap clock signals CK and CKB.
- the undesired signal Vu represents the DC offset or the low frequency noise of the transconductance amplifier 23 .
- the signal Vu′ is an undesired signal modulated by the chopper circuit 35 .
- FIGS. 4 A ⁇ 4 D show the spectra of the desired and undesired signals.
- the desired signal Vin comes from the second amplifier 22 . After the first chopper circuit 30 , the desired signal Vin is shifted up to the signal Vin′, at the clock frequency fc and the harmonic frequencies of the clock while the undesired signal Vu is unaffected.
- the signal Vin′ is shifted back to the signal Vin′′ in the original band and the undesired signal Vu is shifted up to the undesired Vu′, at the clock frequency fc and the harmonic frequencies of the clock.
- the spectrum of the undesired signal Vu′ has been folded back around the clock frequency fc.
- the clock frequency fc is much higher than the desired signal bandwidth, so the amount of the undesired signal Vu′ in the desired signal bandwidth is greatly reduced. Since the undesired signal Vu includes the DC offset and 1/f noise of the transconductance amplifier 23 , the influence of the undesired signal is mixed out the range of the desired signal.
- FIG. 5A is a schematic of the transconductance amplifier applied in the present invention.
- FIG. 5B is a schematic of the chopper circuit applied in the present invention.
- the first chopper circuit 30 and the second chopper circuit 35 are both implemented by two cross-coupled switches.
- FIGS. 6 A ⁇ 6 B shows the operation of the chopper circuits. When CK is on and CKB is off, the first chopper circuit 30 and the second chopper circuit 35 are in the state shown in FIG. 6A.
- the equivalent undesired signal Vueq at the input of the transconductance amplifier 23 is equal to the undesired signal Vu.
- the equivalent signal Vueq is equal to the negative of the undesired signal ⁇ Vu.
- the average of the equivalent signal approximates zero, that is, the undesired signal Vu is averaged out.
- FIG. 7 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the second embodiment.
- the first chopper circuit 30 is merged into the input of the transconductance amplifier 23 to form the transconductance amplifier 502 .
- the second chopper circuit 35 is inserted between output of the transconductance amplifier 502 and capacitor 24 .
- FIG. 8 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the third embodiment.
- the second chopper circuit 35 is merged into the output of the transconductance amplifier 23 to form the transconductance amplifier 504 .
- the first chopper circuit 30 is inserted between the second amplifier 22 and input to the transconductance amplifier 504 .
- FIG. 9 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the fourth embodiment.
- the chopper circuit 30 and 35 are merged into input and output of the transconductance amplifier 23 to form the transconductance amplifier 506 .
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a DC offset canceling circuit applied in a variable gain amplifier, and particularly to a DC offset canceling circuit which utilizes a chopper stabilization method to cancel DC offset of output stage.
- 2. Description of the Related Art
- Variable gain amplifiers (VGA), which amplify input signal to necessary voltage levels in a system in demodulation process, are widely used in home network transceivers which transmit signals via cable. When the variable gain amplifier is used, a differential input end of an internal operational amplifier has the problem of intrinsic offset, and the intrinsic offset is always in the range of several mV to tens of mV. For wireless or wired communication, the maximum gain of variable gain amplification is up to tens of dB; therefore, the intrinsic offset after amplification will affect the recovery ability of the received signal, the characteristics of parameters of a dynamic range, and signal-to-noise ratio.
- A DC offset canceling circuit is shown in FIG. 1, disclosed by Yao et al., in “DC offset canceling circuit applied in a variable gain amplifier” U.S. Pat. No. 6,407,630 B1. In FIG. 1, a
DC offset circuit 26 applied in avariable gain amplifier 25. Thevariable gain amplifier 25 includes afirst amplifier 21, asecond amplifier 22, a plurality ofswitches 201˜208, and a plurality of resistors. The DCoffset canceling circuit 26 includes atransconductance amplifier 23 and at least oneinternal capacitor 24. Theswitches 201˜204 adjust the variable gain of thefirst amplifier 21. For example, if theswitch 201 is closed, the gain is raised; and if theswitch 202 is closed, the gain is reduced. Theswitches 205˜208 adjust the variable gain of thefirst amplifier 22. For example, if theswitch 205 is closed, the gain is raised; and if theswitch 207 is closed, the gain is reduced. Thetransconductance amplifier 23 is used to transform the output voltage of thesecond amplifier 22 to an output current based on a ratio. - The output of the
transconductance amplifier 23 is coupled to at least oneinternal capacitor 24, and is then fed back to the input of thefirst amplifier 21 to cancel the DC offset of thevariable gain amplifier 25. The transconductance amplifier 23 cooperates with theinternal capacitor 24, only about 10 pF or even under 10 pF, as a Gm-C filter. Since the capacitance of theinternal capacitor 24 is small, theinternal capacitor 24 can be manufactured easily inside an IC, and does not occupy I/O pin. - The DC offset of the
first amplifier 21 and thesecond amplifier 22 is canceled by thetransconductance amplifier 23 andcapacitor 24, the Gm-C filter, but the DC offset of thetransconductance amplifier 23 is not. There is a need for a novel canceling circuit to cancel the DC offset of the final stage. - According to the prior art, an extremely large chip area is required for implementing the transconductance amplifier so as to reduce the DC offset. However, the DC offset can be reduced by a chopper to saving the chip area according to the present invention described as follows.
- It is therefore an object of the present invention to provide a DC offset canceling circuit of a variable gain amplifier.
- To achieve the above objects, the present invention provides a DC offset canceling circuit including a transconductance amplifier, at least one internal capacitor, and chopper circuits.
- A
first chopper circuit 30 is inserted between the output of the variable gain amplifier and the input of the transconductance amplifier. A second chopper circuit is inserted between the output of the transconductance amplifier and the capacitor. The first chopper circuit and the second chopper circuit are controlled by a non-overlap clock signal having a chopping frequency. The first chopper circuit can be merged into the input of transconductance amplifier. The second chopper circuit can be merged into the output of transconductance amplifier. - The DC offset and low frequency noise of the transconductance amplifier, the undesired signal, is translated up to the chopping frequency. The spectrum of the undesired signal is folded back around the chopping frequency. The chopping frequency is much higher than the desired signal bandwidth, thus the size of the undesired signal in the passband of the signal is greatly reduced.
- Being chopper-stabilized, the transconductance amplifier and capacitor serve the same function, canceling the DC offset of the variable gain amplifier. The chopper circuit cancels the DC offset of the transconductance amplifier.
- The aforementioned objects, features and advantages of this invention will become apparent by referring to the following detailed description of the preferred embodiment with reference to the accompanying drawings, wherein:
- FIG. 1 shows a DC offset canceling circuit in the prior art.
- FIG. 2 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the first embodiment.
- FIG. 3 is a block diagram of the chopper circuit applied in the variable gain amplifier.
- FIG. 4A˜4D show the spectra of the desired and undesired signals.
- FIG. 5A is a schematic of the chopper circuit applied in the present invention.
- FIG. 5B is a schematic of the transconductance amplifier applied in the present invention.
- FIGS.6A˜6B shows the operation of the chopper circuits.
- FIG. 7 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the second embodiment.
- FIG. 8 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the third embodiment.
- FIG. 9 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the fourth embodiment.
- FIG. 2 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the first embodiment. The
first chopper circuit 30 is inserted between thesecond amplifier 22 and thetransconductance amplifier 23. Thesecond chopper circuit 35 is inserted between thetransconductance amplifier 23 andcapacitor 24. - FIG. 3 is a block diagram of the chopper circuit applied in the variable gain amplifier. The
chopper circuit transconductance amplifier 23. The signal Vu′ is an undesired signal modulated by thechopper circuit 35. FIGS. 4A˜4D show the spectra of the desired and undesired signals. The desired signal Vin comes from thesecond amplifier 22. After thefirst chopper circuit 30, the desired signal Vin is shifted up to the signal Vin′, at the clock frequency fc and the harmonic frequencies of the clock while the undesired signal Vu is unaffected. After thesecond chopper circuit 35, the signal Vin′ is shifted back to the signal Vin″ in the original band and the undesired signal Vu is shifted up to the undesired Vu′, at the clock frequency fc and the harmonic frequencies of the clock. - The spectrum of the undesired signal Vu′ has been folded back around the clock frequency fc. The clock frequency fc is much higher than the desired signal bandwidth, so the amount of the undesired signal Vu′ in the desired signal bandwidth is greatly reduced. Since the undesired signal Vu includes the DC offset and 1/f noise of the
transconductance amplifier 23, the influence of the undesired signal is mixed out the range of the desired signal. - FIG. 5A is a schematic of the transconductance amplifier applied in the present invention. FIG. 5B is a schematic of the chopper circuit applied in the present invention. The
first chopper circuit 30 and thesecond chopper circuit 35 are both implemented by two cross-coupled switches. FIGS. 6A˜6B shows the operation of the chopper circuits. When CK is on and CKB is off, thefirst chopper circuit 30 and thesecond chopper circuit 35 are in the state shown in FIG. 6A. The equivalent undesired signal Vueq at the input of thetransconductance amplifier 23 is equal to the undesired signal Vu. When CK is off and CKB is on, thefirst chopper circuit 30 and thesecond chopper circuit 35 are in the state shown in FIG. 6B. The equivalent signal Vueq is equal to the negative of the undesired signal −Vu. The average of the equivalent signal approximates zero, that is, the undesired signal Vu is averaged out. - FIG. 7 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the second embodiment. The
first chopper circuit 30 is merged into the input of thetransconductance amplifier 23 to form thetransconductance amplifier 502. Thesecond chopper circuit 35 is inserted between output of thetransconductance amplifier 502 andcapacitor 24. - FIG. 8 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the third embodiment. The
second chopper circuit 35 is merged into the output of thetransconductance amplifier 23 to form thetransconductance amplifier 504. Thefirst chopper circuit 30 is inserted between thesecond amplifier 22 and input to thetransconductance amplifier 504. - FIG. 9 is a schematic of a DC offset canceling circuit applied in the variable gain amplifier in the fourth embodiment. The
chopper circuit transconductance amplifier 23 to form thetransconductance amplifier 506. - Although the present invention has been described in its preferred embodiments, it is not intended to limit the invention to the precise embodiments disclosed herein. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.
Claims (9)
Priority Applications (1)
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US10/327,473 US6750703B1 (en) | 2002-12-24 | 2002-12-24 | DC offset canceling circuit applied in a variable gain amplifier |
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US10/327,473 US6750703B1 (en) | 2002-12-24 | 2002-12-24 | DC offset canceling circuit applied in a variable gain amplifier |
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US6750703B1 US6750703B1 (en) | 2004-06-15 |
US20040119531A1 true US20040119531A1 (en) | 2004-06-24 |
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US10/327,473 Expired - Lifetime US6750703B1 (en) | 2002-12-24 | 2002-12-24 | DC offset canceling circuit applied in a variable gain amplifier |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US20060222117A1 (en) * | 2005-04-04 | 2006-10-05 | Mahibur Rahman | DC offset correction system for a receiver with baseband gain control |
US20110001515A1 (en) * | 2009-07-02 | 2011-01-06 | Robert Bosch Gmbh | Comparator with self-limiting positive feedback |
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US6961385B2 (en) * | 2003-01-21 | 2005-11-01 | Cirrus Logic, Inc. | Signal processing system with baseband noise modulation chopper circuit timing to reduce noise |
DE112005002091T5 (en) | 2004-09-10 | 2007-07-19 | Quantum Applied Science & Research Inc., San Diego | Amplifier circuit and method for reducing voltage and current noise |
US20090115518A1 (en) * | 2006-03-23 | 2009-05-07 | Nxp B.V. | Differential amplifier with input stage inverting common-mode signals |
TW200931795A (en) * | 2008-01-08 | 2009-07-16 | Richtek Technology Corp | Apparatus and method for improving the feedback linearity of a 1.5-bit Σ-Δ class-D amplifier |
CN101494440B (en) * | 2008-01-21 | 2013-09-11 | 立锜科技股份有限公司 | Device and method for improving feedback linearity of 1.5 bit Sigma-Delta modulation D type amplifier |
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US8344797B2 (en) * | 2009-11-20 | 2013-01-01 | Conexant Systems, Inc. | Systems and methods for offset cancellation method for DC-coupled audio drivers |
US10644664B2 (en) * | 2017-09-26 | 2020-05-05 | Texas Instruments Incorporated | Offset cancellation scheme |
CN108336974B (en) * | 2018-02-02 | 2021-08-31 | 中国科学院微电子研究所 | Adjustable in-band noise cancellation loop circuit |
CN114533087B (en) * | 2022-04-28 | 2022-08-26 | 之江实验室 | Method and system for eliminating direct current offset between electrodes based on chopping technology |
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US5206602A (en) * | 1992-04-30 | 1993-04-27 | Hewlett-Packard Company | Biomedical amplifier circuit |
US5293169A (en) * | 1992-04-30 | 1994-03-08 | Hewlett-Packard Company | Switched capacitor circuit for precision resistance |
US6262626B1 (en) * | 1998-11-12 | 2001-07-17 | U.S. Philips Corporation | Circuit comprising means for reducing the DC-offset and the noise produced by an amplifier |
US6407630B1 (en) * | 2001-01-04 | 2002-06-18 | Silicon Integrated Systems Corporation | DC offset cancelling circuit applied in a variable gain amplifier |
-
2002
- 2002-12-24 US US10/327,473 patent/US6750703B1/en not_active Expired - Lifetime
Patent Citations (4)
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US5206602A (en) * | 1992-04-30 | 1993-04-27 | Hewlett-Packard Company | Biomedical amplifier circuit |
US5293169A (en) * | 1992-04-30 | 1994-03-08 | Hewlett-Packard Company | Switched capacitor circuit for precision resistance |
US6262626B1 (en) * | 1998-11-12 | 2001-07-17 | U.S. Philips Corporation | Circuit comprising means for reducing the DC-offset and the noise produced by an amplifier |
US6407630B1 (en) * | 2001-01-04 | 2002-06-18 | Silicon Integrated Systems Corporation | DC offset cancelling circuit applied in a variable gain amplifier |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060222117A1 (en) * | 2005-04-04 | 2006-10-05 | Mahibur Rahman | DC offset correction system for a receiver with baseband gain control |
US7899431B2 (en) | 2005-04-04 | 2011-03-01 | Freescale Semiconductor, Inc. | DC offset correction system for a receiver with baseband gain control |
US20110001515A1 (en) * | 2009-07-02 | 2011-01-06 | Robert Bosch Gmbh | Comparator with self-limiting positive feedback |
US8476935B2 (en) * | 2009-07-02 | 2013-07-02 | Robert Bosch Gmbh | Comparator with self-limiting positive feedback |
US8786316B2 (en) | 2009-07-02 | 2014-07-22 | Robert Bosch Gmbh | Comparator with self-limiting positive feedback |
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