US20040159955A1 - Semiconductor chip module - Google Patents

Semiconductor chip module Download PDF

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Publication number
US20040159955A1
US20040159955A1 US10/776,139 US77613904A US2004159955A1 US 20040159955 A1 US20040159955 A1 US 20040159955A1 US 77613904 A US77613904 A US 77613904A US 2004159955 A1 US2004159955 A1 US 2004159955A1
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Prior art keywords
semiconductor chip
chip
mounting member
circuit traces
contact pads
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US10/776,139
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Ming-Tung Shen
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Priority to US10/776,139 priority Critical patent/US20040159955A1/en
Publication of US20040159955A1 publication Critical patent/US20040159955A1/en
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    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Definitions

  • the invention relates to a semiconductor chip module, more particularly to semiconductor chip modules that can be stacked one on top of the other in a fully automated manner.
  • the object of the present invention is to provide semiconductor chip modules that can be stacked one on top of the other in a fully automated manner.
  • a semiconductor chip module comprises:
  • a chip-mounting member having opposite first and second surfaces, a set of circuit traces, and a plurality of plated through holes that extend through the first and second surfaces and that are connected to the circuit traces;
  • a semiconductor chip having a pad mounting surface with a plurality of contact pads provided thereon;
  • a dielectric tape member for bonding adhesively the semiconductor chip on the chip-mounting member
  • each of the solder balls being aligned with and being connected to a respective one of the plated through holes in the chip-mounting member.
  • a semiconductor chip module stack comprises upper and lower semiconductor chip modules, each including:
  • a chip-mounting member having upper and lower surfaces, a set of circuit traces, and a plurality of plated through holes that extend through the upper and lower surfaces and that are connected to the circuit traces;
  • a semiconductor chip having a pad mounting surface with a plurality of contact pads provided thereon;
  • a dielectric tape member for bonding adhesively the semiconductor chip on the chip-mounting member
  • each of the solder balls being aligned with and being connected to a respective one of the plated through holes in the chip-mounting member.
  • solder balls of the upper semiconductor chip module are aligned with and are connected to the plated through holes in the chip-mounting member of the lower semiconductor chip module at the upper surface of the latter.
  • FIG. 1 is a fragmentary schematic partly sectional view of the first preferred embodiment of a semiconductor chip module according to the present invention
  • FIG. 2 is a fragmentary perspective view of a chip-mounting member of the first preferred embodiment
  • FIG. 3 is a perspective view illustrating a semiconductor chip of the first preferred embodiment
  • FIG. 4 is a perspective view illustrating a dielectric tape member of the first preferred embodiment
  • FIG. 5 is a fragmentary schematic partly sectional view illustrating how a plurality of the semiconductor chip modules of the first preferred embodiment can be interconnected to form a stack;
  • FIG. 6 is a fragmentary schematic partly sectional view of the second preferred embodiment of a semiconductor chip module according to the present invention.
  • FIG. 7 is a fragmentary schematic partly sectional view illustrating how a plurality of the semiconductor chip modules of the second preferred embodiment can be interconnected to form a stack;
  • FIG. 8 is a fragmentary schematic partly sectional view of the third preferred embodiment of a semiconductor chip module according to the present invention.
  • FIG. 9 is a fragmentary schematic partly sectional view illustrating how a plurality of the semiconductor chip modules of the third preferred embodiment can be interconnected to form a stack;
  • FIG. 10 is a fragmentary schematic partly sectional view of the fourth preferred embodiment of a semiconductor chip module according to the present invention.
  • FIG. 11 is a fragmentary schematic partly sectional view illustrating how a plurality of the semiconductor chip modules of the fourth preferred embodiment can be interconnected to form a stack.
  • FIG. 12 is a fragmentary schematic partly sectional view of the fifth preferred embodiment of a semiconductor chip module according to the present invention.
  • the first preferred embodiment of a semiconductor chip module according to the present invention is shown to comprise a chip-mounting member 1 , at least two semiconductor chips 2 , and a plurality of solder balls 3 .
  • the chip-mounting member 1 is a board body having opposite first and second chip mounting surfaces 10 , 11 that are respectively formed with circuit traces 12 (see FIG. 2).
  • the chip-mounting member 1 is further formed with a plurality of plated through holes 14 that extend through the first and second chip mounting surfaces 10 , 11 and that are connected electrically to the circuit traces 12 on the surfaces 10 , 11 .
  • Each of the semiconductor chips 2 has a pad mounting surface 20 with a plurality of contact pads 21 provided thereon (see FIG. 3).
  • the pad mounting surface 20 of each of the semiconductor chips 2 is bonded adhesively on one of the first and second chip mounting surfaces 10 , 11 via a dielectric tape member 4 .
  • the dielectric tape member 4 has a first adhesive surface adhered onto the pad mounting surface 20 of the semiconductor chip 2 , and an opposite second adhesive surface adhered onto the first or second chip mounting surface 10 , 11 .
  • the dielectric tape member 4 is formed with a plurality of holes 40 at positions registered with the contact pads 21 of the semiconductor chip 2 (see FIG. 4).
  • Conductive contact balls 5 are received in the holes 40 to establish electrical connection between the contact pads 21 of the semiconductor chip 2 and the circuit traces 12 on the first or second chip mounting surface 10 , 11 .
  • each semiconductor chip 2 has a peripheral portion that is provided with an epoxy resin layer 23 to strengthen bonding of the semiconductor chip 2 with the first or second chip mounting surface 10 , 11 .
  • each semiconductor chip 2 has a heat dissipating surface that is opposite to the pad mounting surface and that has a heat dissipating plate 24 secured thereon for heat dissipating and chip protection purposes.
  • Each of the solder balls 3 (only two are shown in FIG. 1) is made from tin and is disposed on the second chip mounting surface 11 of the chip-mounting member 1 .
  • Each of the solder balls 3 is aligned with and is connected to a respective one of the plated through holes 14 in the chip-mounting member 1 .
  • electrical connection between the solder balls 3 and the contact pads 21 of the semiconductor chips 2 can be established via the circuit traces 12 on the surfaces 10 , 11 of the chip-mounting member 1 .
  • FIG. 1 shows only one semiconductor chip 2 mounted on each of the surfaces 10 , 11 of the chip-mounting member 1 , it should be clear to one skilled in the art that two or more semiconductor chips 2 may be mounted on each of the surfaces 10 , 11 .
  • two or more semiconductor chip modules of the first preferred embodiment can be interconnected to form a semiconductor chip module stack.
  • the solder balls 3 on an upper one of the semiconductor chip modules are aligned with and are connected to the plated through holes 14 in the chip-mounting member 1 of a lower one of the semiconductor chip modules at the first chip mounting surface 10 of the latter.
  • the solder balls 3 of a lowermost one of the semiconductor chip modules in the semiconductor chip module stack can be mounted on a printed circuit board (not shown) for establishing electrical connection with circuit traces on the latter.
  • FIG. 6 illustrates the second preferred embodiment of a semiconductor chip module according to the present invention.
  • the chip-mounting member 1 is a three-layer board body having opposite first and second chip mounting surfaces 10 , 11 that are respectively formed with circuit traces similar to those shown in FIG. 2.
  • the chip-mounting member 1 is further formed with a plurality of plated through holes 14 that extend through the first and second chip mounting surfaces 10 , 12 and that are connected electrically to the circuit traces on the surfaces 10 , 11 .
  • Each of the surfaces 10 , 11 is formed with at least one chip receiving cavity 13 having an open end and a closed end opposite to the open end.
  • Each of the semiconductor chips 2 has a pad mounting surface 20 with a plurality of contact pads 21 provided thereon, and an opposite chip fixing surface.
  • Each of the semiconductor chips 2 is received in a respective one of the chip receiving cavities 13 in the chip-mounting member 1 with the pad mounting surface 20 being accessible from the first or second chip mounting surface 10 , 11 via the open end of the respective one of the chip receiving cavities 13 .
  • the chip fixing surface of each of the semiconductor chips 2 is bonded adhesively on the closed end of the respective one of the chip receiving cavities 13 via a dielectric tape member 4 a.
  • the dielectric tape member 4 a has a first adhesive surface adhered onto the chip fixing surface of the semiconductor chip 2 , and an opposite second adhesive surface adhered onto the closed end of the respective one of the chip receiving cavities 13 .
  • wires 22 interconnect the contact pads 21 of the semiconductor chip 2 and the circuit traces on the first or second chip mounting surface 10 , 11 .
  • an encapsulation layer 6 made of epoxy resin, is provided on each of the first and second chip mounting surfaces 10 , 11 to enclose the pad mounting surface 20 of each semiconductor chip 2 and the wires 22 that are connected to the semiconductor chip 2 for protection purposes.
  • each of the solder balls 3 is disposed on the second chip mounting surface 11 of the chip-mounting member 1 , and is aligned with and is connected to a respective one of the plated through holes 14 in the chip-mounting member 1 .
  • electrical connection between the solder balls 3 and the contact pads 21 of the semiconductor chips 2 can be established via the wires 22 and the circuit traces on the surfaces 10 , 11 of the chip-mounting member 1 .
  • two or more semiconductor chip modules of the second preferred embodiment can be interconnected to form a semiconductor chip module stack.
  • the solder balls 3 on an upper one of the semiconductor chip modules are aligned with and are connected to the plated through holes 14 in the chip-mounting member 1 of a lower one of the semiconductor chip modules at the first chip mounting surface 10 of the latter.
  • the solder balls 3 of a lowermost one of the semiconductor chip modules in the semiconductor chip module stack can be mounted on a printed circuit board (not shown) for establishing electrical connection with circuit traces on the latter.
  • FIG. 8 illustrates the third preferred embodiment of a semiconductor chip module according to the present invention.
  • the chip-mounting member 1 is a three-layer board body having opposite first and second chip mounting surfaces 10 , 11 formed with at least one chip receiving cavity 13 a having an open end and a closed end opposite to the open end.
  • the chip-mounting member 1 is further formed with a plurality of plated through holes 14 that extend through the surfaces 10 , 12 .
  • the first and second chip mounting surfaces 10 , 11 and the closed end of each chip receiving cavity 13 a are respectively formed with circuit traces similar to those shown in FIG. 2 and connected electrically to the plated through holes 14 .
  • Each of the chip receiving cavities 13 receives two semiconductor chips 2 a, 2 b therein.
  • Each of the semiconductor chips 2 a, 2 b has a pad mounting surface 20 with a plurality of contact pads 21 provided thereon, and an opposite chip fixing surface.
  • the pad mounting surface 20 of each of the semiconductor chips 2 a is bonded adhesively on the closed end of the respective one of the chip receiving cavities 13 a via a dielectric tape layer 4 .
  • the dielectric tape layer 4 has a first adhesive surface adhered onto the pad mounting surface 20 of the semiconductor chip 2 a, and an opposite second adhesive surface adhered onto the closed end of the respective one of the chip receiving cavities 13 a.
  • the dielectric tape layer 4 is formed with a plurality of holes 40 at positions registered with the contact pads 21 of the semiconductor chip 2 a.
  • Conductive contact balls 5 are received in the holes 40 to establish electrical connection between the contact pads 21 of the semiconductor chip 2 a and the circuit traces on the closed end of the respective one of the chip receiving cavities 13 a.
  • Each of the semiconductor chips 2 b is received in the respective one of the chip receiving cavities 13 a with the pad mounting surface 20 thereof being accessible from the first or second chip mounting surface 10 , 11 via the open end of the respective one of the chip receiving cavities 13 a.
  • the chip fixing surface of each of the semiconductor chips 2 b is bonded adhesively on the chip fixing surface of the semiconductor chip 2 a that is disposed in the same one of the chip receiving cavities 13 a via another dielectric tape layer 4 a.
  • the dielectric tape layer 4 a has a first adhesive surface adhered onto the chip fixing surface of the semiconductor chip 2 b, and an opposite second adhesive surface adhered onto the chip fixing surface of the semiconductor chip 2 a.
  • wires 22 interconnect the contact pads 21 of the semiconductor chip 2 b and the circuit traces on the first or second chip mounting surface 10 , 11 .
  • an encapsulation layer 6 made of epoxy resin, is provided on each of the surfaces 10 , 11 of the chip-mounting member 1 to enclose the pad mounting surface 20 of each semiconductor chip 2 b and the wires 22 that are connected to the semiconductor chip 2 b for protection purposes.
  • each of the solder balls 3 is disposed on the second chip mounting surface 11 , and is aligned with and is connected to a respective one of the plated through holes 14 in the chip-mounting member 1 .
  • electrical connection between the solder balls 3 and the contact pads 21 of the semiconductor chips 2 a can be established via the circuit traces on the closed ends of the chip receiving cavities 13 a, while electrical connection between the solder balls 3 and the contact pads 21 of the semiconductor chips 2 b can be established via the wires 22 and the circuit traces on the surfaces 10 , 11 of the chip-mounting member 1 .
  • two or more semiconductor chip modules of the third preferred embodiment can be interconnected to form a semiconductor chip module stack.
  • the solder balls 3 on an upper one of the semiconductor chip modules are aligned with and are connected to the plated through holes 14 in the chip-mounting member 1 of a lower one of the semiconductor chip modules at the first chip mounting surface 10 of the latter.
  • the solder balls 3 of a lowermost one of the semiconductor chip modules in the semiconductor chip module stack can be mounted on a printed circuit board (not shown) for establishing electrical connection with circuit traces on the latter.
  • the fourth preferred embodiment of a a semiconductor chip module according to the present invention is shown to comprise first and second chip-mounting members 1 a, 1 b, a first semiconductor chip 2 a , a second semiconductor chip 2 b , a plurality of first solder balls 3 a, and a plurality of second solder balls 3 b.
  • the first chip-mounting member 1 a is a board body having an upper chip mounting surface 15 a and a lower circuit layout surface 16 a formed with circuit traces similar to those shown in FIG. 2.
  • the first chip-mounting member 1 a is further formed with an opening 17 a and a plurality of plated through holes 14 a that extend through the surfaces 15 a, 16 a and that are connected electrically to the circuit traces on the circuit layout surface 16 a.
  • the first semiconductor chip 2 a has a pad mounting surface 20 a with a plurality of contact pads 21 a provided thereon.
  • the pad mounting surface 20 a is bonded adhesively on the chip mounting surface 15 a using a dielectric tape member 7 .
  • the dielectric tape member 7 has a first adhesive surface adhered onto the pad mounting surface 20 a, and an opposite second adhesive surface adhered onto the chip mounting surface 15 a.
  • the dielectric tape member 7 is formed with an opening 70 that is registered with the opening 17 a such that the contact pads 21 a are accessible from the circuit layout surface 16 a via the openings 17 a, 70 .
  • Wires 22 a interconnect the contact pads 21 a and the circuit traces on the circuit layout surface 16 a.
  • a peripheral portion of the first semiconductor chip 2 a is provided with an epoxy resin layer 23 a to strengthen bonding of the first semiconductor chip 2 a with the chip mounting surface 15 a.
  • the first semiconductor chip 2 a has a heat dissipating surface that is opposite to the pad mounting surface 20 a and that has a heat dissipating plate 24 a secured thereon for heat dissipating and chip protection purposes.
  • an encapsulation layer 6 a made of epoxy resin is provided on the circuit layout surface 16 a to enclose the pad mounting surface 20 a and the wires 22 a for protection purposes.
  • Each of the first solder balls 3 a (only two are shown in FIG. 10) is made from tin and is disposed on the circuit layout surface 16 a.
  • Each of the first solder balls 3 a is aligned with and is connected to a respective one of the plated through holes 14 a in the first chip-mounting member 1 a.
  • electrical connection between the first solder balls 3 a and the contact pads 21 a of the first semiconductor chip 2 a can be established via the circuit traces on the circuit layout surface 16 a and the wires 22 a.
  • the second chip-mounting member 1 b is a board body having a lower chip mounting surface 15 b and an upper circuit layout surface 16 b formed with circuit traces similar to those shown in FIG. 2.
  • the second chip-mounting member 1 b is further formed with an opening 17 b and a plurality of plated through holes 14 b that extend through the surfaces 15 b, 16 b and that are connected electrically to the circuit traces on the circuit layout surface 16 b .
  • the second semiconductor chip 2 b has a pad mounting surface 20 b with a plurality of contact pads 21 b provided thereon.
  • the pad mounting surface 20 b is bonded adhesively on the chip mounting surface 15 b using a dielectric tape member 8 .
  • the dielectric tape member 8 has a first adhesive surface adhered onto the pad mounting surface 20 b , and an opposite second adhesive surface adhered onto the chip mounting surface 15 b.
  • the dielectric tape member 8 is formed with an opening 80 that is registered with the opening 17 b such that the contact pads 21 b are accessible from the circuit layout surface 16 b via the openings 17 b , 80 .
  • Wires 22 b interconnect the contact pads 21 b and the circuit traces on the circuit layout surface 16 b .
  • a peripheral portion of the second semiconductor chip 2 b is provided with an epoxy resin layer 23 b to strengthen bonding of the second semiconductor chip 2 b with the chip mounting surface 15 b .
  • the second semiconductor chip 2 b has a heat dissipating surface that is opposite to the pad mounting surface 20 b and that has a heat dissipating plate 24 b secured thereon for heat dissipating and chip protection purposes.
  • an encapsulation layer 6 b made of epoxy resin is provided on the circuit layout surface 16 b to enclose the pad mounting surface 20 b and the wires 22 b for protection purposes.
  • Each of the second solder balls 3 b (only two are shown in FIG. 10) is made from tin and is disposed on the chip mounting surface 15 b .
  • Each of the second solder balls 3 b is aligned with and is connected to a respective one of the plated through holes 14 b in the second chip-mounting member 1 b .
  • electrical connection between the second solder balls 3 b and the contact pads 21 b of the second semiconductor chip 2 b can be established via the circuit traces on the circuit layout surface 16 b and the wires 22 b.
  • the second chip-mounting member 1 b is disposed below the first chip-mounting member 1 a, and each of the first solder balls 3 a on the circuit layout surface 16 a of the first chip-mounting member 1 a is aligned with and is connected to a respective one of the plated through holes 14 b at the circuit layout surface 16 a of the second chip-mounting member 1 b.
  • two or more semiconductor chip modules of the fourth preferred embodiment can be interconnected to form a semiconductor chip module stack.
  • the second solder balls 3 b on an upper one of the semiconductor chip modules are aligned with and are connected to the plated through holes 14 a at the chip mounting surface 15 a of the first chip-mounting member 1 a of a lower one of the semiconductor chip modules.
  • the second solder balls 3 b of a lowermost one of the semiconductor chip modules in the semiconductor chip module stack can be mounted on a printed circuit board (not shown) for establishing electrical connection with circuit traces on the latter.
  • FIG. 12 illustrates the fifth preferred embodiment of a semiconductor chip module according to the present invention.
  • each of the first and second chip-mounting members 1 a, 1 b has at least two first and second semiconductor chips 2 a , 2 b mounted respectively thereon.
  • the semiconductor chip module of this invention does not require the use of connector clips to establish electrical connection with other semiconductor chip modules.
  • the semiconductor chip module can be manufactured in a fully automated manner to result in lower production costs.
  • the semiconductor chips are memory chips, a significant increase in memory capacity is possible without incurring a significant increase in board penalty. The object of the present invention is thus met.

Abstract

A semiconductor chip module includes a chip-mounting member having opposite first and second surfaces, a set of circuit traces, and a plurality of plated through holes that extend through the first and second surfaces and that are connected to the circuit traces. A dielectric tape member bonds adhesively a semiconductor chip on the chip-mounting member. A first conductor unit connects electrically contact pads on a pad mounting surface of the semiconductor chip and the circuit traces. A plurality of solder balls are disposed on one of the first and second surfaces of the chip-mounting member, are aligned with and are connected to the plated through holes in the chip-mounting member, respectively.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The invention relates to a semiconductor chip module, more particularly to semiconductor chip modules that can be stacked one on top of the other in a fully automated manner. [0002]
  • 2. Description of the Related Art [0003]
  • In this age of computer technology, there is an ever-growing need to increase the speed and functionality of computers, thereby resulting in a corresponding need to increase the memory capacity. However, due to limitations in the size of a computer main board, the number of on-board memory devices that can be installed is severely limited. There is thus a need to develop a memory device having a capacity that can be expanded without incurring a substantial increase in board penalty. [0004]
  • In U.S. Pat. No. 4,996,587, there is disclosed an integrated semiconductor chip package that includes a plurality of chip carriers arranged in a stack, and a plurality of semiconductor chips mounted on the chip carriers. However, due to the need for S-shaped connector clips mounted on the chip carriers to establish electrical connection among the semiconductor chips, the integrated semiconductor chip package according to the aforesaid U.S. patent cannot be manufactured in a fully automated manner, thereby resulting in increased production costs. [0005]
    • SUMMARY OF THE INVENTION
  • Therefore, the object of the present invention is to provide semiconductor chip modules that can be stacked one on top of the other in a fully automated manner. [0006]
  • According to one aspect of the invention, a semiconductor chip module comprises: [0007]
  • a chip-mounting member having opposite first and second surfaces, a set of circuit traces, and a plurality of plated through holes that extend through the first and second surfaces and that are connected to the circuit traces; [0008]
  • a semiconductor chip having a pad mounting surface with a plurality of contact pads provided thereon; [0009]
  • a dielectric tape member for bonding adhesively the semiconductor chip on the chip-mounting member; [0010]
  • a conductor unit for connecting electrically the contact pads of the semiconductor chip and the circuit traces; and [0011]
  • a plurality of solder balls disposed on one of the first and second surfaces of the chip-mounting member, each of the solder balls being aligned with and being connected to a respective one of the plated through holes in the chip-mounting member. [0012]
  • According to another aspect of the invention, a semiconductor chip module stack comprises upper and lower semiconductor chip modules, each including: [0013]
  • a chip-mounting member having upper and lower surfaces, a set of circuit traces, and a plurality of plated through holes that extend through the upper and lower surfaces and that are connected to the circuit traces; [0014]
  • a semiconductor chip having a pad mounting surface with a plurality of contact pads provided thereon; [0015]
  • a dielectric tape member for bonding adhesively the semiconductor chip on the chip-mounting member; [0016]
  • a conductor unit for connecting electrically the contact pads of the semiconductor chip and the circuit traces; and [0017]
  • a plurality of solder balls disposed on the lower surface of the chip-mounting member, each of the solder balls being aligned with and being connected to a respective one of the plated through holes in the chip-mounting member. [0018]
  • The solder balls of the upper semiconductor chip module are aligned with and are connected to the plated through holes in the chip-mounting member of the lower semiconductor chip module at the upper surface of the latter. [0019]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments with reference to the accompanying drawings, of which: [0020]
  • FIG. 1 is a fragmentary schematic partly sectional view of the first preferred embodiment of a semiconductor chip module according to the present invention; [0021]
  • FIG. 2 is a fragmentary perspective view of a chip-mounting member of the first preferred embodiment; [0022]
  • FIG. 3 is a perspective view illustrating a semiconductor chip of the first preferred embodiment; [0023]
  • FIG. 4 is a perspective view illustrating a dielectric tape member of the first preferred embodiment; [0024]
  • FIG. 5 is a fragmentary schematic partly sectional view illustrating how a plurality of the semiconductor chip modules of the first preferred embodiment can be interconnected to form a stack; [0025]
  • FIG. 6 is a fragmentary schematic partly sectional view of the second preferred embodiment of a semiconductor chip module according to the present invention; [0026]
  • FIG. 7 is a fragmentary schematic partly sectional view illustrating how a plurality of the semiconductor chip modules of the second preferred embodiment can be interconnected to form a stack; [0027]
  • FIG. 8 is a fragmentary schematic partly sectional view of the third preferred embodiment of a semiconductor chip module according to the present invention; [0028]
  • FIG. 9 is a fragmentary schematic partly sectional view illustrating how a plurality of the semiconductor chip modules of the third preferred embodiment can be interconnected to form a stack; [0029]
  • FIG. 10 is a fragmentary schematic partly sectional view of the fourth preferred embodiment of a semiconductor chip module according to the present invention; [0030]
  • FIG. 11 is a fragmentary schematic partly sectional view illustrating how a plurality of the semiconductor chip modules of the fourth preferred embodiment can be interconnected to form a stack; and [0031]
  • FIG. 12 is a fragmentary schematic partly sectional view of the fifth preferred embodiment of a semiconductor chip module according to the present invention.[0032]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Before the present invention is described in greater detail, it should be noted that like elements are denoted by the same reference numerals throughout the disclosure. [0033]
  • Referring to FIG. 1, the first preferred embodiment of a semiconductor chip module according to the present invention is shown to comprise a chip-[0034] mounting member 1, at least two semiconductor chips 2, and a plurality of solder balls 3.
  • In this embodiment, the chip-[0035] mounting member 1 is a board body having opposite first and second chip mounting surfaces 10, 11 that are respectively formed with circuit traces 12 (see FIG. 2). The chip-mounting member 1 is further formed with a plurality of plated through holes 14 that extend through the first and second chip mounting surfaces 10, 11 and that are connected electrically to the circuit traces 12 on the surfaces 10, 11.
  • Each of the [0036] semiconductor chips 2 has a pad mounting surface 20 with a plurality of contact pads 21 provided thereon (see FIG. 3). The pad mounting surface 20 of each of the semiconductor chips 2 is bonded adhesively on one of the first and second chip mounting surfaces 10, 11 via a dielectric tape member 4. Particularly, the dielectric tape member 4 has a first adhesive surface adhered onto the pad mounting surface 20 of the semiconductor chip 2, and an opposite second adhesive surface adhered onto the first or second chip mounting surface 10, 11. The dielectric tape member 4 is formed with a plurality of holes 40 at positions registered with the contact pads 21 of the semiconductor chip 2 (see FIG. 4). Conductive contact balls 5 are received in the holes 40 to establish electrical connection between the contact pads 21 of the semiconductor chip 2 and the circuit traces 12 on the first or second chip mounting surface 10, 11. Preferably, each semiconductor chip 2 has a peripheral portion that is provided with an epoxy resin layer 23 to strengthen bonding of the semiconductor chip 2 with the first or second chip mounting surface 10, 11. Moreover, each semiconductor chip 2 has a heat dissipating surface that is opposite to the pad mounting surface and that has a heat dissipating plate 24 secured thereon for heat dissipating and chip protection purposes.
  • Each of the solder balls [0037] 3 (only two are shown in FIG. 1) is made from tin and is disposed on the second chip mounting surface 11 of the chip-mounting member 1. Each of the solder balls 3 is aligned with and is connected to a respective one of the plated through holes 14 in the chip-mounting member 1. Thus, electrical connection between the solder balls 3 and the contact pads 21 of the semiconductor chips 2 can be established via the circuit traces 12 on the surfaces 10, 11 of the chip-mounting member 1.
  • While FIG. 1 shows only one [0038] semiconductor chip 2 mounted on each of the surfaces 10, 11 of the chip-mounting member 1, it should be clear to one skilled in the art that two or more semiconductor chips 2 may be mounted on each of the surfaces 10, 11.
  • Referring to FIG. 5, two or more semiconductor chip modules of the first preferred embodiment can be interconnected to form a semiconductor chip module stack. As shown, the [0039] solder balls 3 on an upper one of the semiconductor chip modules are aligned with and are connected to the plated through holes 14 in the chip-mounting member 1 of a lower one of the semiconductor chip modules at the first chip mounting surface 10 of the latter. The solder balls 3 of a lowermost one of the semiconductor chip modules in the semiconductor chip module stack can be mounted on a printed circuit board (not shown) for establishing electrical connection with circuit traces on the latter.
  • FIG. 6 illustrates the second preferred embodiment of a semiconductor chip module according to the present invention. As shown, the chip-[0040] mounting member 1 is a three-layer board body having opposite first and second chip mounting surfaces 10, 11 that are respectively formed with circuit traces similar to those shown in FIG. 2. The chip-mounting member 1 is further formed with a plurality of plated through holes 14 that extend through the first and second chip mounting surfaces 10, 12 and that are connected electrically to the circuit traces on the surfaces 10, 11. Each of the surfaces 10, 11 is formed with at least one chip receiving cavity 13 having an open end and a closed end opposite to the open end. Each of the semiconductor chips 2 has a pad mounting surface 20 with a plurality of contact pads 21 provided thereon, and an opposite chip fixing surface. Each of the semiconductor chips 2 is received in a respective one of the chip receiving cavities 13 in the chip-mounting member 1 with the pad mounting surface 20 being accessible from the first or second chip mounting surface 10, 11 via the open end of the respective one of the chip receiving cavities 13. The chip fixing surface of each of the semiconductor chips 2 is bonded adhesively on the closed end of the respective one of the chip receiving cavities 13 via a dielectric tape member 4 a. Particularly, the dielectric tape member 4 a has a first adhesive surface adhered onto the chip fixing surface of the semiconductor chip 2, and an opposite second adhesive surface adhered onto the closed end of the respective one of the chip receiving cavities 13. In addition, wires 22 interconnect the contact pads 21 of the semiconductor chip 2 and the circuit traces on the first or second chip mounting surface 10, 11. Preferably, an encapsulation layer 6, made of epoxy resin, is provided on each of the first and second chip mounting surfaces 10, 11 to enclose the pad mounting surface 20 of each semiconductor chip 2 and the wires 22 that are connected to the semiconductor chip 2 for protection purposes. Like the previous embodiment, each of the solder balls 3 is disposed on the second chip mounting surface 11 of the chip-mounting member 1, and is aligned with and is connected to a respective one of the plated through holes 14 in the chip-mounting member 1. Thus, electrical connection between the solder balls 3 and the contact pads 21 of the semiconductor chips 2 can be established via the wires 22 and the circuit traces on the surfaces 10, 11 of the chip-mounting member 1.
  • Referring to FIG. 7, two or more semiconductor chip modules of the second preferred embodiment can be interconnected to form a semiconductor chip module stack. As shown, the [0041] solder balls 3 on an upper one of the semiconductor chip modules are aligned with and are connected to the plated through holes 14 in the chip-mounting member 1 of a lower one of the semiconductor chip modules at the first chip mounting surface 10 of the latter. The solder balls 3 of a lowermost one of the semiconductor chip modules in the semiconductor chip module stack can be mounted on a printed circuit board (not shown) for establishing electrical connection with circuit traces on the latter.
  • FIG. 8 illustrates the third preferred embodiment of a semiconductor chip module according to the present invention. As shown, the chip-mounting [0042] member 1 is a three-layer board body having opposite first and second chip mounting surfaces 10, 11 formed with at least one chip receiving cavity 13 a having an open end and a closed end opposite to the open end. The chip-mounting member 1 is further formed with a plurality of plated through holes 14 that extend through the surfaces 10, 12. The first and second chip mounting surfaces 10, 11 and the closed end of each chip receiving cavity 13 a are respectively formed with circuit traces similar to those shown in FIG. 2 and connected electrically to the plated through holes 14. Each of the chip receiving cavities 13 receives two semiconductor chips 2 a, 2 b therein. Each of the semiconductor chips 2 a, 2 b has a pad mounting surface 20 with a plurality of contact pads 21 provided thereon, and an opposite chip fixing surface. The pad mounting surface 20 of each of the semiconductor chips 2 a is bonded adhesively on the closed end of the respective one of the chip receiving cavities 13 a via a dielectric tape layer 4. Particularly, the dielectric tape layer 4 has a first adhesive surface adhered onto the pad mounting surface 20 of the semiconductor chip 2 a, and an opposite second adhesive surface adhered onto the closed end of the respective one of the chip receiving cavities 13 a. Like the first preferred embodiment, the dielectric tape layer 4 is formed with a plurality of holes 40 at positions registered with the contact pads 21 of the semiconductor chip 2 a. Conductive contact balls 5 are received in the holes 40 to establish electrical connection between the contact pads 21 of the semiconductor chip 2 a and the circuit traces on the closed end of the respective one of the chip receiving cavities 13 a. Each of the semiconductor chips 2 b is received in the respective one of the chip receiving cavities 13 a with the pad mounting surface 20 thereof being accessible from the first or second chip mounting surface 10, 11 via the open end of the respective one of the chip receiving cavities 13 a. The chip fixing surface of each of the semiconductor chips 2 b is bonded adhesively on the chip fixing surface of the semiconductor chip 2 a that is disposed in the same one of the chip receiving cavities 13 a via another dielectric tape layer 4 a. Particularly, the dielectric tape layer 4 a has a first adhesive surface adhered onto the chip fixing surface of the semiconductor chip 2 b, and an opposite second adhesive surface adhered onto the chip fixing surface of the semiconductor chip 2 a. In addition, like the second preferred embodiment, wires 22 interconnect the contact pads 21 of the semiconductor chip 2 b and the circuit traces on the first or second chip mounting surface 10, 11. Moreover, an encapsulation layer 6, made of epoxy resin, is provided on each of the surfaces 10, 11 of the chip-mounting member 1 to enclose the pad mounting surface 20 of each semiconductor chip 2 b and the wires 22 that are connected to the semiconductor chip 2 b for protection purposes. As with the previous embodiments, each of the solder balls 3 is disposed on the second chip mounting surface 11, and is aligned with and is connected to a respective one of the plated through holes 14 in the chip-mounting member 1. Thus, electrical connection between the solder balls 3 and the contact pads 21 of the semiconductor chips 2 a can be established via the circuit traces on the closed ends of the chip receiving cavities 13 a, while electrical connection between the solder balls 3 and the contact pads 21 of the semiconductor chips 2 b can be established via the wires 22 and the circuit traces on the surfaces 10, 11 of the chip-mounting member 1.
  • Referring to FIG. 9, two or more semiconductor chip modules of the third preferred embodiment can be interconnected to form a semiconductor chip module stack. As shown, the [0043] solder balls 3 on an upper one of the semiconductor chip modules are aligned with and are connected to the plated through holes 14 in the chip-mounting member 1 of a lower one of the semiconductor chip modules at the first chip mounting surface 10 of the latter. The solder balls 3 of a lowermost one of the semiconductor chip modules in the semiconductor chip module stack can be mounted on a printed circuit board (not shown) for establishing electrical connection with circuit traces on the latter.
  • Referring to FIG. 10, the fourth preferred embodiment of a a semiconductor chip module according to the present invention is shown to comprise first and second chip-mounting members [0044] 1 a, 1 b, a first semiconductor chip 2 a, a second semiconductor chip 2 b, a plurality of first solder balls 3 a, and a plurality of second solder balls 3 b.
  • In this embodiment, the first chip-mounting member [0045] 1 a is a board body having an upper chip mounting surface 15 a and a lower circuit layout surface 16 a formed with circuit traces similar to those shown in FIG. 2. The first chip-mounting member 1 a is further formed with an opening 17 a and a plurality of plated through holes 14 a that extend through the surfaces 15 a, 16 a and that are connected electrically to the circuit traces on the circuit layout surface 16 a. The first semiconductor chip 2 a has a pad mounting surface 20 a with a plurality of contact pads 21 a provided thereon. The pad mounting surface 20 a is bonded adhesively on the chip mounting surface 15 a using a dielectric tape member 7. Particularly, the dielectric tape member 7 has a first adhesive surface adhered onto the pad mounting surface 20 a, and an opposite second adhesive surface adhered onto the chip mounting surface 15 a. The dielectric tape member 7 is formed with an opening 70 that is registered with the opening 17 a such that the contact pads 21 a are accessible from the circuit layout surface 16 a via the openings 17 a, 70. Wires 22 a interconnect the contact pads 21 a and the circuit traces on the circuit layout surface 16 a. Preferably, a peripheral portion of the first semiconductor chip 2 a is provided with an epoxy resin layer 23 a to strengthen bonding of the first semiconductor chip 2 a with the chip mounting surface 15 a. Moreover, the first semiconductor chip 2 a has a heat dissipating surface that is opposite to the pad mounting surface 20 a and that has a heat dissipating plate 24 a secured thereon for heat dissipating and chip protection purposes. In addition, an encapsulation layer 6 a made of epoxy resin is provided on the circuit layout surface 16 a to enclose the pad mounting surface 20 a and the wires 22 a for protection purposes. Each of the first solder balls 3 a (only two are shown in FIG. 10) is made from tin and is disposed on the circuit layout surface 16 a. Each of the first solder balls 3 a is aligned with and is connected to a respective one of the plated through holes 14 a in the first chip-mounting member 1 a. Thus, electrical connection between the first solder balls 3 a and the contact pads 21 a of the first semiconductor chip 2 a can be established via the circuit traces on the circuit layout surface 16 a and the wires 22 a.
  • Unlike the first chip-mounting member [0046] 1 a, the second chip-mounting member 1 b is a board body having a lower chip mounting surface 15 b and an upper circuit layout surface 16 b formed with circuit traces similar to those shown in FIG. 2. The second chip-mounting member 1 b is further formed with an opening 17 b and a plurality of plated through holes 14 b that extend through the surfaces 15 b, 16 b and that are connected electrically to the circuit traces on the circuit layout surface 16 b. The second semiconductor chip 2 b has a pad mounting surface 20 b with a plurality of contact pads 21 b provided thereon. The pad mounting surface 20 b is bonded adhesively on the chip mounting surface 15 b using a dielectric tape member 8. Particularly, the dielectric tape member 8 has a first adhesive surface adhered onto the pad mounting surface 20 b, and an opposite second adhesive surface adhered onto the chip mounting surface 15 b. The dielectric tape member 8 is formed with an opening 80 that is registered with the opening 17 b such that the contact pads 21 b are accessible from the circuit layout surface 16 b via the openings 17 b, 80. Wires 22 b interconnect the contact pads 21 b and the circuit traces on the circuit layout surface 16 b. Like the first semiconductor chip 2 a, a peripheral portion of the second semiconductor chip 2 b is provided with an epoxy resin layer 23 b to strengthen bonding of the second semiconductor chip 2 b with the chip mounting surface 15 b. Moreover, the second semiconductor chip 2 b has a heat dissipating surface that is opposite to the pad mounting surface 20 b and that has a heat dissipating plate 24 b secured thereon for heat dissipating and chip protection purposes. In addition, an encapsulation layer 6 b made of epoxy resin is provided on the circuit layout surface 16 b to enclose the pad mounting surface 20 b and the wires 22 b for protection purposes. Each of the second solder balls 3 b (only two are shown in FIG. 10) is made from tin and is disposed on the chip mounting surface 15 b. Each of the second solder balls 3 b is aligned with and is connected to a respective one of the plated through holes 14 b in the second chip-mounting member 1 b. Thus, electrical connection between the second solder balls 3 b and the contact pads 21 b of the second semiconductor chip 2 b can be established via the circuit traces on the circuit layout surface 16 b and the wires 22 b.
  • In this embodiment, the second chip-mounting member [0047] 1 b is disposed below the first chip-mounting member 1 a, and each of the first solder balls 3 a on the circuit layout surface 16 a of the first chip-mounting member 1 a is aligned with and is connected to a respective one of the plated through holes 14 b at the circuit layout surface 16 a of the second chip-mounting member 1 b.
  • Referring to FIG. 11, two or more semiconductor chip modules of the fourth preferred embodiment can be interconnected to form a semiconductor chip module stack. As shown, the [0048] second solder balls 3 b on an upper one of the semiconductor chip modules are aligned with and are connected to the plated through holes 14 a at the chip mounting surface 15 a of the first chip-mounting member 1 a of a lower one of the semiconductor chip modules. The second solder balls 3 b of a lowermost one of the semiconductor chip modules in the semiconductor chip module stack can be mounted on a printed circuit board (not shown) for establishing electrical connection with circuit traces on the latter.
  • FIG. 12 illustrates the fifth preferred embodiment of a semiconductor chip module according to the present invention. In contrast with the fourth preferred embodiment, each of the first and second chip-mounting members [0049] 1 a, 1 b has at least two first and second semiconductor chips 2 a, 2 b mounted respectively thereon.
  • It has thus been shown that the semiconductor chip module of this invention does not require the use of connector clips to establish electrical connection with other semiconductor chip modules. The semiconductor chip module can be manufactured in a fully automated manner to result in lower production costs. When the semiconductor chips are memory chips, a significant increase in memory capacity is possible without incurring a significant increase in board penalty. The object of the present invention is thus met. [0050]
  • While the present invention has been described in connection with what is considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements. [0051]

Claims (19)

I claim:
1. A semiconductor chip module comprising:
a chip-mounting member having opposite first and second surfaces, a set of first circuit traces, and a plurality of plated through holes that extend through said first and second surfaces and that are connected to said first circuit traces;
a first semiconductor chip having a pad mounting surface with a plurality of contact pads provided thereon;
a first dielectric tape member for bonding adhesively said first semiconductor chip on said chip-mounting member;
a first conductor unit for connecting electrically said contact pads of said first semiconductor chip and said first circuit traces; and
a plurality of solder balls disposed on one of said first and second surfaces of said chip-mounting member, each of said solder balls being aligned with and being connected to a respective one of said plated through holes in said chip-mounting member.
2. The semiconductor chip module as claimed in claim 1, wherein:
said first circuit traces and said first semiconductor chip are disposed on a same one of said first and second surfaces of said chip-mounting member;
said first dielectric tape member bonds adhesively said pad mounting surface of said first semiconductor chip on said same one of said first and second surfaces of said chip-mounting member, and is formed with a plurality of holes at positions registered with said contact pads of said first semiconductor chip; and
said first conductor unit includes a plurality of conductive contact balls that are received in said holes in said first dielectric tape member to establish electrical connection between said contact pads of said first semiconductor chip and said first circuit traces.
3. The semiconductor chip module as claimed in claim 2, wherein said chip-mounting member further has a set of second circuit traces accessible from the other one of said first and second surfaces opposite to said first circuit traces and connected to said plated through holes, said semiconductor chip module further comprising:
a second semiconductor chip having a pad mounting surface with a plurality of contact pads provided thereon;
a second dielectric tape member for bonding adhesively said second semiconductor chip on said chip-mounting member; and
a second conductor unit for connecting electrically said contact pads of said second semiconductor chip and said second circuit traces.
4. The semiconductor chip module as claimed in claim 3, wherein:
said second dielectric tape member bonds adhesively said pad mounting surface of said second semiconductor chip on the other one of said first and second surfaces of said chip-mounting member, and is formed with a plurality of holes at positions registered with said contact pads of said second semiconductor chip; and
said second conductor unit includes a plurality of conductive contact balls that are received in said holes in said second dielectric tape member to establish electrical connection between said contact pads of said second semiconductor chip and said second circuit traces.
5. The semiconductor chip module as claimed in claim 2, wherein said first semiconductor chip has a peripheral portion that is provided with an epoxy resin layer to strengthen bonding of said first semiconductor chip with said same one of said first and second surfaces of said chip-mounting member.
6. The semiconductor chip module as claimed in claim 2, wherein said first semiconductor chip has a heat dissipating surface that is opposite to said pad mounting surface and that has a heat dissipating plate secured thereon.
7. The semiconductor chip module as claimed in claim 1, wherein:
said chip-mounting member has a first chip receiving cavity formed in one of said first and second surfaces thereof, said first chip receiving cavity having an open end and a closed end opposite to said open end, said first circuit traces and said first chip receiving cavity being provided on a same one of said first and second surfaces of said chip-mounting member;
said first semiconductor chip is received in said first chip receiving cavity with said pad mounting surface thereof being accessible from said same one of said first and second surfaces of said chip-mounting member via said open end of said first chip receiving cavity; and
said first conductor unit includes a plurality of conductive wires that interconnect said contact pads of said first semiconductor chip and said first circuit traces.
8. The semiconductor chip module as claimed in claim 7, wherein said first semiconductor chip has a chip fixing surface opposite to said pad mounting surface, said first dielectric tape member bonding adhesively said chip fixing surface of said first semiconductor chip on said closed end of said first chip receiving cavity.
9. The semiconductor chip module as claimed in claim 7, wherein said chip-mounting member further has a set of second circuit traces accessible from the other one of said first and second surfaces opposite to said first circuit traces and connected to said plated through holes, said semiconductor chip module further comprising:
a second semiconductor chip having a pad mounting surface with a plurality of contact pads provided thereon;
a second dielectric tape member for bonding adhesively said second semiconductor chip on said chip-mounting member; and
a second conductor unit for connecting electrically said contact pads of said second semiconductor chip and said second circuit traces.
10. The semiconductor chip module as claimed in claim 9, wherein:
said chip-mounting member has a second chip receiving cavity formed in the other one of said first and second surfaces thereof, said second chip receiving cavity having an open end and a closed end opposite to said open end;
said second semiconductor chip is received in said second chip receiving cavity with said pad mounting surface thereof being accessible from the other one of said first and second surfaces of said chip-mounting member via said open end of said second chip receiving cavity; and
said second conductor unit includes a plurality of conductive wires that interconnect said contact pads of said second semiconductor chip and said second circuit traces.
11. The semiconductor chip module as claimed in claim 10, wherein said second semiconductor chip has a chip fixing surface opposite to said pad mounting surface, said second dielectric tape member bonding adhesively said chip fixing surface of said second semiconductor chip on said closed end of said second chip receiving cavity.
12. The semiconductor chip module as claimed in claim 7, further comprising an encapsulation layer provided on said same one of said first and second surfaces of said chip-mounting member to enclose said pad mounting surface of said first semiconductor chip and said first conductor unit.
13. The semiconductor chip module as claimed in claim 7, wherein said closed end of said first chip receiving cavity is formed with a set of second circuit traces that are connected to said plated through holes, said first semiconductor chip having a chip fixing surface opposite to said pad mounting surface, said semiconductor chip module further comprising:
a second semiconductor chip having a pad mounting surface with a plurality of contact pads provided thereon, and a chip fixing surface opposite to said pad mounting surface, said second semiconductor chip being received in said first chip receiving cavity between said first semiconductor chip and said closed end of said first chip receiving cavity;
said first dielectric tape member including a first dielectric tape layer for bonding together said chip fixing surfaces of said first and second semiconductor chips, and a second dielectric tape layer for bonding adhesively said pad mounting surface of said second semiconductor chip on said closed end of said first chip receiving cavity, said second dielectric tape layer being formed with a plurality of holes at positions registered with said contact pads of said second semiconductor chip; and
a second conductor unit including a plurality of conductive contact balls that are received in said holes in said second dielectric tape layer to establish electrical connection between said contact pads of said second semiconductor chip and said second circuit traces.
14. The semiconductor chip module as claimed in claim 13, wherein said chip-mounting member further has a set of third circuit traces accessible from the other one of said first and second surfaces opposite to said first circuit traces and connected to said plated through holes, said semiconductor chip module further comprising:
a third semiconductor chip having a pad mounting surface with a plurality of contact pads provided thereon;
a third dielectric tape member for bonding adhesively said third semiconductor chip on said chip-mounting member; and
a third conductor unit for connecting electrically said contact pads of said third semiconductor chip and said third circuit traces.
15. The semiconductor chip module as claimed in claim 1, wherein said first circuit traces are disposed on one of said first and second surfaces of said chip-mounting member, said first dielectric tape member bonding adhesively said pad mounting surface of said first semiconductor chip on the other one of said first and second surfaces of said chip-mounting member, said chip-mounting member being formed with a first opening that extends through said first and second surfaces thereof, said first dielectric tape member being formed with a second opening that is registered with said first opening for access to said contact pads of said first semiconductor chip, said first conductor unit including a plurality of wires that interconnect said contact pads of said first semiconductor chip and said first circuit traces.
16. The semiconductor chip module as claimed in claim 15, wherein said first semiconductor chip has a peripheral portion that is provided with an epoxy resin layer to strengthen bonding of said first semiconductor chip with the other one of said first and second surfaces of said chip-mounting member.
17. The semiconductor chip module as claimed in claim 15, wherein said first semiconductor chip has a heat dissipating surface that is opposite to said pad mounting surface and that has a heat dissipating plate secured thereon.
18. The semiconductor chip module as claimed in claim 15, further comprising an encapsulation layer provided on said one of said first and second surfaces of said chip-mounting member to enclose said pad mounting surface of said first semiconductor chip and said first conductor unit.
19. A semiconductor chip module stack, comprising:
upper and lower semiconductor chip modules, each including
a chip-mounting member having upper and lower surfaces, a set of circuit traces, and a plurality of plated through holes that extend through said upper and lower surfaces and that are connected to said circuit traces,
a semiconductor chip having a pad mounting surface with a plurality of contact pads provided thereon,
a dielectric tape member for bonding adhesively said semiconductor chip on said chip-mounting member,
a conductor unit for connecting electrically said contact pads of said semiconductor chip and said circuit traces, and
a plurality of solder balls disposed on said lower surface of said chip-mounting member, each of said solder balls being aligned with and being connected to a respective one of said plated through holes in said chip-mounting member;
wherein said solder balls of said upper semiconductor chip module are aligned with and are connected to said plated through holes in said chip-mounting member of said lower semiconductor chip module at said upper surface of said chip-mounting member of said lower semiconductor chip module.
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TW088212813U TW417839U (en) 1999-07-30 1999-07-30 Stacked memory module structure and multi-layered stacked memory module structure using the same
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