US20040161910A1 - Semiconductor apparatus and semiconductor apparatus manufacturing method - Google Patents
Semiconductor apparatus and semiconductor apparatus manufacturing method Download PDFInfo
- Publication number
- US20040161910A1 US20040161910A1 US10/778,116 US77811604A US2004161910A1 US 20040161910 A1 US20040161910 A1 US 20040161910A1 US 77811604 A US77811604 A US 77811604A US 2004161910 A1 US2004161910 A1 US 2004161910A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor
- semiconductor device
- wire
- resin
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 157
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000011347 resin Substances 0.000 claims abstract description 45
- 229920005989 resin Polymers 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 230000002093 peripheral effect Effects 0.000 claims abstract description 24
- 238000007789 sealing Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 description 14
- 230000035882 stress Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000005498 polishing Methods 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3178—Coating or filling in grooves made in the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
Definitions
- the present invention relates to a semiconductor apparatus and a semiconductor apparatus manufacturing method, in particular to a package of a semiconductor apparatus.
- FIG. 6 shows a conventional chip size package.
- the semiconductor device shown in FIG. 6 is structured as follows.
- An electrode pad 2 is formed on a semiconductor substrate 1 .
- a wire 3 made of Cu or the like to be electrically connected to the electrode pad 2 is also formed on the semiconductor substrate 1 .
- the surface of the semiconductor substrate 1 and the wire 3 are sealed with a resin 4 .
- a bump 5 made of solder is formed on the wire 3 that is exposed on the surface of the resin 4 .
- FIG. 7-A a wire 71 made of Cu or the like is formed on a wafer 70 that is a semiconductor substrate.
- the entire wafer 70 is filled with a resin 72 .
- the entire surface of the resin covering the wafer 70 is polished to expose the wire 71 on the surface.
- a bump electrode 73 made of solder or the like is formed on the surface of the wire 72 .
- the wafer is cut into individual semiconductor devices. In this way, individual semiconductor devices are formed, which completes the semiconductor device manufacturing process.
- the conventional semiconductor device manufacturing method has the following problems. First, when the wafer is divided into multiple individual semiconductor devices, a stress is created on the interface between the surface of each of the semiconductor devices and the resin. This stress often causes some of the semiconductor devices to be chipped. Second, the thermal stress generated when the semiconductor device is packaged causes the resin to be peeled off from the semiconductor device.
- a semiconductor device has a semiconductor substrate containing a central portion having a first thickness and a peripheral portion having a second thickness that is smaller than the first thickness, an electrode pad formed on the semiconductor substrate, a sealing resin for sealing the semiconductor substrate, a protruded electrode formed on the sealing resin, and a wire which electrically connects the electrode pad to the protruded electrode.
- a semiconductor device manufacturing method has the following steps. First, an electrode pad is formed on a semiconductor wafer. Second, a wire to be connected to the electrode pad is formed. Third, a groove having a first width that varies between a first value as a lower limit and a second value as an upper limit is formed on a prescribed region of the semiconductor wafer. Fourth, in the semiconductor wafer and the wire are sealed with a resin. Fifth, a protruded electrode that is electrically connected to the wire is formed on the resin. Finally, the semiconductor wafer is divided into multiple semiconductor devices by cutting the prescribed region using a blade having a thickness that is smaller than the first width.
- FIG. 1 shows the structure of a semiconductor device according to the first embodiment of the present invention.
- FIG. 2 is a process diagram showing the process of the semiconductor device manufacturing method according to the first embodiment of the present invention.
- FIG. 3 shows the structure of a semiconductor device according to the second embodiment of the present invention.
- FIG. 4 is a process diagram showing the process of the semiconductor device manufacturing method according to the second embodiment of the present invention.
- FIG. 5 shows the shape of the groove formed in the process of the semiconductor device manufacturing method according to the second embodiment of the present invention.
- FIG. 6 shows the structure of a conventional semiconductor device.
- FIG. 7 is a process diagram showing a conventional semiconductor device manufacturing method.
- FIG. 1 shows the structure of a semiconductor device according to the first embodiment of the present invention.
- FIG. 1-A is a back-view of the semiconductor apparatus according to the first embodiment of the present invention.
- FIG. 1-B is a cross sectional view of what is shown in FIG. 1-A across the line AB.
- the first embodiment of the present invention will be explained with reference to FIG. 1. The same reference numerals are used for the components that are already used in FIG. 6.
- the semiconductor substrate 1 has a prescribed thickness at the central portion 11 .
- the thickness of the peripheral portion 12 of the semiconductor device in the semiconductor substrate 1 is smaller than the thickness of the central portion 11 .
- the peripheral portion 12 of the semiconductor device thus forms a step unit 6 as shown inside the circle in FIG. 1-B.
- This step unit 6 is formed on the surface of the side on which the semiconductor substrate is sealed with the resin. It is desirable that the depth of this step unit 6 , that is, the distance from the surface of the central portion 11 to the top portion of the peripheral portion 12 be larger than 10 ⁇ m (this distance is indicated by Y in FIG. 1-B).
- the distance from the edge portion of the semiconductor device to the central portion of the semiconductor device that is, the width of the step unit 6 be larger than 3 ⁇ m (this distance is indicated by X in FIG. 1-B).
- Aluminum electrode pads 2 are formed at prescribed positions on the surface of the semiconductor substrate 1 .
- a wire 3 made of Cu is formed on the semiconductor substrate 1 .
- the wire 3 is electrically connected to the aluminum pad 2 .
- the surface of the semiconductor substrate 1 and the wire 3 are sealed with a resin 4 .
- Protruded electrodes 5 are formed over the resin 4 . In the present embodiment, these protruded electrodes 5 are bump electrodes made of solder or the like that are formed over the wire 3 exposed on the surface of the resin 4 .
- the peripheral portion 12 of the semiconductor substrate 1 is thinner than the central portion 11 , forming the step unit 6 .
- This step unit 6 is formed on four sides surrounding the central portion 11 as shown in FIG. 1-A.
- step unit 6 Due to the presence of this step unit 6 , the area of contact increases in the peripheral portion 12 of the semiconductor device between the resin 4 and the semiconductor substrate 1 . As a result, the strength of the anchor effect is increased.
- the semiconductor device of the present invention is stable since the resin is harder to be peeled off from the semiconductor substrate by the thermal stress that is generated when the semiconductor device is packaged.
- FIG. 2 is a process diagram showing the process of the semiconductor device manufacturing method according to the first embodiment of the present invention.
- a wire 21 made of Cu is formed on a semiconductor wafer 20 by an electric plating process or the like. This wire is electrically connected to an electrode pad formed on a wafer not shown in the drawing.
- a groove 23 is formed on the surface of the semiconductor wafer 20 using a peripheral blade 22 that rotates at high speed. This groove is formed in the portion that is to be the peripheral portion of each individual semiconductor device.
- the thickness of the peripheral blade 22 used to form the groove is between 35 ⁇ m and 150 ⁇ m.
- the width of the groove 23 is made larger than the thickness of the peripheral blade 22 by 1 ⁇ m to 5 ⁇ m.
- the depth of the groove 23 is set larger than 10 ⁇ m as shown in FIG. 2-B. By making the groove 23 deeper than 10 ⁇ m, the groove can be formed with a stable width without depending very much on the shape of the tip of the blade 22 .
- the surface of the semiconductor wafer 20 is filled with the resin 24 .
- the groove 23 is also filled with the resin 24 as shown in FIG. 2-C.
- the portion in which the groove 23 has been formed in the previous process is cut with a high speed rotating peripheral blade 27 .
- the semiconductor wafer 20 is divided into multiple semiconductor devices.
- the semiconductor wafer 20 is divided into multiple semiconductor devices by forming the groove 23 on the surface of the semiconductor wafer 20 , sealing with a resin the surface of the semiconductor wafer 20 , and cutting the semiconductor wafer 20 along the groove 23 .
- the semiconductor wafer 20 is cut to a small depth. Therefore, in this case, the length of time the blade 22 stays in contact with the surface of the semiconductor wafer 20 is shorter compared with the case in which the semiconductor wafer 20 is cut into multiple semiconductor devices. Therefore, the stress applied to the surface of the semiconductor wafer 20 in this case is small. As a result, the surface of each of the multiple semiconductor devices is less likely to be broken or cracked. Even if the surface of the semiconductor wafer 20 is chipped when the groove 23 is formed, the chipped portion is filed with the resin 24 . Therefore, the chipped portion does not get corroded.
- semiconductor devices are provided without having the resin portion peeled off from the semiconductor substrate while reducing the amount the surface of the semiconductor device is chipped.
- FIG. 3 shows the structure of a semiconductor device according to the second embodiment of the present invention.
- FIG. 3-A is a back view of the semiconductor device according to the second embodiment of the present invention.
- FIG. 3-B is a cross sectional view of what is shown in FIG. 3-A across the line A-O-B.
- the second embodiment of the present invention will be explained with reference to FIG. 3. The same reference numerals are used for the components that are already used in FIG. 1.
- the second embodiment is identical with the first embodiment in that a step unit 6 is formed on the semiconductor substrate 1 .
- the width of the step unit 6 is varied periodically like a pule wave form (this width is shown by X in the drawing).
- the degree of the anchor effect of the step unit 6 is further increased.
- the step is formed in two directions along each side of the semiconductor device. The step consists of step portions 31 that are parallel to the side of the semiconductor device and step portions 32 that are perpendicular to the side of the semiconductor device.
- the resultant semiconductor device has an anchor effect that is superior to the anchor effect achieved in the first embodiment.
- FIG. 4 is a process diagram showing the process of the semiconductor device manufacturing method according to the second embodiment of the present invention.
- FIG. 5 shows the shape of the groove formed in the process of the semiconductor device manufacturing method according to the second embodiment of the present invention.
- a wire 21 made of Cu is formed on a semiconductor wafer 20 by an electric plating process as shown in FIG. 4-A.
- a groove 23 is formed on the surface of the semiconductor wafer 20 by illuminating a laser light onto the surface of the semiconductor wafer 20 .
- This groove 23 is formed in each of those portions that are to become the peripheral portions of the multiple semiconductor devices to be formed.
- the width of the groove 23 is varied periodically between the lower limit of X1 ⁇ m and the upper limit X2 ⁇ m.
- the depth of the groove 23 is set to 10 ⁇ m as shown in FIG. 4-B.
- FIG. 5 is a magnified top view of the shape of the groove 23 .
- the surface of the semiconductor wafer 20 is filled with a resin 24 .
- the groove 23 is also filled with the resin 24 .
- the surface of the resin 24 is polished using a polishing blade 25 until the wire 21 embedded in the resin 24 is exposed.
- a bump electrode 26 made of a solder ball or the like is formed on the exposed wire 20 .
- the semiconductor wafer 20 is cut and divided into multiple semiconductor devices using a high speed rotating peripheral blade 27 .
- the thickness of the peripheral blade 27 be made smaller than the minimum width X1 of the groove. If possible, the thickness of the peripheral blade 27 should be made smaller than the minimum width X1 of the groove by at least 6 ⁇ m
- the amount of stress applied to the surface of the semiconductor wafer can be reduced.
- the step unit is formed in the shape of a pulse wave form. As a result, the stress that is generated when the resin 24 hardens and contracts is absorbed by the step unit.
- stable semiconductor devices are provided without having the resin portion peeled off from the semiconductor substrate.
- the wire was exposed by polishing the sealing resin.
- the shape of the step unit need not be like a pulse wave form.
- the same effect can be achieved by varying the width of the step unit within a range between a prescribed upper limit and a prescribed lower limit and by dividing the semiconductor substrate into individual devices using a blade whose thickness is smaller than the lower limit width of the step unit.
Abstract
The sealing resin of a semiconductor device is prevented from being peeled off from the substrate of the semiconductor device. A semiconductor device according to the present invention has a semiconductor substrate containing a central portion having a first thickness and a peripheral portion having a second thickness that is smaller than the first thickness, an electrode pad formed on the semiconductor substrate, a sealing resin for sealing the semiconductor substrate, a protruded electrode formed on the sealing resin, and a wire which electrically connects the electrode pad to the protruded electrode.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor apparatus and a semiconductor apparatus manufacturing method, in particular to a package of a semiconductor apparatus.
- 2. Description of Related Art
- In recent years, semiconductor apparatuses are getting packaged with an increasingly higher density, and semiconductor devices such as chip size packages are receiving attention.
- FIG. 6 shows a conventional chip size package. The semiconductor device shown in FIG. 6 is structured as follows. An
electrode pad 2 is formed on asemiconductor substrate 1. Awire 3 made of Cu or the like to be electrically connected to theelectrode pad 2 is also formed on thesemiconductor substrate 1. The surface of thesemiconductor substrate 1 and thewire 3 are sealed with aresin 4. Abump 5 made of solder is formed on thewire 3 that is exposed on the surface of theresin 4. - In what follows, a conventional semiconductor device manufacturing method will be explained with reference to FIG. 7. First, as shown in FIG. 7-A, a
wire 71 made of Cu or the like is formed on awafer 70 that is a semiconductor substrate. Second, as shown in FIG. 7-B, theentire wafer 70 is filled with aresin 72. Third, as shown in FIG. 7-C, the entire surface of the resin covering thewafer 70 is polished to expose thewire 71 on the surface. Fourth, as shown in FIG. 7-D, abump electrode 73 made of solder or the like is formed on the surface of thewire 72. Fifth, as shown in FIG. 7-E, the wafer is cut into individual semiconductor devices. In this way, individual semiconductor devices are formed, which completes the semiconductor device manufacturing process. - However, the conventional semiconductor device manufacturing method has the following problems. First, when the wafer is divided into multiple individual semiconductor devices, a stress is created on the interface between the surface of each of the semiconductor devices and the resin. This stress often causes some of the semiconductor devices to be chipped. Second, the thermal stress generated when the semiconductor device is packaged causes the resin to be peeled off from the semiconductor device.
- Given these problems, it is an object of the present invention to provide a semiconductor apparatus and a semiconductor apparatus manufacturing method capable of solving these problems.
- A semiconductor device according to the present invention has a semiconductor substrate containing a central portion having a first thickness and a peripheral portion having a second thickness that is smaller than the first thickness, an electrode pad formed on the semiconductor substrate, a sealing resin for sealing the semiconductor substrate, a protruded electrode formed on the sealing resin, and a wire which electrically connects the electrode pad to the protruded electrode.
- A semiconductor device manufacturing method according to the present invention has the following steps. First, an electrode pad is formed on a semiconductor wafer. Second, a wire to be connected to the electrode pad is formed. Third, a groove having a first width that varies between a first value as a lower limit and a second value as an upper limit is formed on a prescribed region of the semiconductor wafer. Fourth, in the semiconductor wafer and the wire are sealed with a resin. Fifth, a protruded electrode that is electrically connected to the wire is formed on the resin. Finally, the semiconductor wafer is divided into multiple semiconductor devices by cutting the prescribed region using a blade having a thickness that is smaller than the first width.
- FIG. 1 shows the structure of a semiconductor device according to the first embodiment of the present invention.
- FIG. 2 is a process diagram showing the process of the semiconductor device manufacturing method according to the first embodiment of the present invention.
- FIG. 3 shows the structure of a semiconductor device according to the second embodiment of the present invention.
- FIG. 4 is a process diagram showing the process of the semiconductor device manufacturing method according to the second embodiment of the present invention.
- FIG. 5 shows the shape of the groove formed in the process of the semiconductor device manufacturing method according to the second embodiment of the present invention.
- FIG. 6 shows the structure of a conventional semiconductor device.
- FIG. 7 is a process diagram showing a conventional semiconductor device manufacturing method.
- FIG. 1 shows the structure of a semiconductor device according to the first embodiment of the present invention. FIG. 1-A is a back-view of the semiconductor apparatus according to the first embodiment of the present invention. FIG. 1-B is a cross sectional view of what is shown in FIG. 1-A across the line AB. In what follows, the first embodiment of the present invention will be explained with reference to FIG. 1. The same reference numerals are used for the components that are already used in FIG. 6.
- The
semiconductor substrate 1 has a prescribed thickness at thecentral portion 11. The thickness of theperipheral portion 12 of the semiconductor device in thesemiconductor substrate 1 is smaller than the thickness of thecentral portion 11. Theperipheral portion 12 of the semiconductor device thus forms astep unit 6 as shown inside the circle in FIG. 1-B. Thisstep unit 6 is formed on the surface of the side on which the semiconductor substrate is sealed with the resin. It is desirable that the depth of thisstep unit 6, that is, the distance from the surface of thecentral portion 11 to the top portion of theperipheral portion 12 be larger than 10 μm (this distance is indicated by Y in FIG. 1-B). It is desirable that the distance from the edge portion of the semiconductor device to the central portion of the semiconductor device, that is, the width of thestep unit 6 be larger than 3 μm (this distance is indicated by X in FIG. 1-B).Aluminum electrode pads 2 are formed at prescribed positions on the surface of thesemiconductor substrate 1. Awire 3 made of Cu is formed on thesemiconductor substrate 1. Thewire 3 is electrically connected to thealuminum pad 2. The surface of thesemiconductor substrate 1 and thewire 3 are sealed with aresin 4. Protrudedelectrodes 5 are formed over theresin 4. In the present embodiment, theseprotruded electrodes 5 are bump electrodes made of solder or the like that are formed over thewire 3 exposed on the surface of theresin 4. - In the semiconductor device of the present invention, the
peripheral portion 12 of thesemiconductor substrate 1 is thinner than thecentral portion 11, forming thestep unit 6. Thisstep unit 6 is formed on four sides surrounding thecentral portion 11 as shown in FIG. 1-A. - Due to the presence of this
step unit 6, the area of contact increases in theperipheral portion 12 of the semiconductor device between theresin 4 and thesemiconductor substrate 1. As a result, the strength of the anchor effect is increased. - Since the anchor effect has been increased, the
resin 4 becomes harder to be peeled off from thesemiconductor substrate 1. - The semiconductor device of the present invention is stable since the resin is harder to be peeled off from the semiconductor substrate by the thermal stress that is generated when the semiconductor device is packaged.
- FIG. 2 is a process diagram showing the process of the semiconductor device manufacturing method according to the first embodiment of the present invention.
- Next, the manufacturing method of the semiconductor device according to the first embodiment of the present invention will be explained with reference to FIG. 2.
- First, as shown in FIG. 2-A, a
wire 21 made of Cu is formed on asemiconductor wafer 20 by an electric plating process or the like. This wire is electrically connected to an electrode pad formed on a wafer not shown in the drawing. - After this, a
groove 23 is formed on the surface of thesemiconductor wafer 20 using aperipheral blade 22 that rotates at high speed. This groove is formed in the portion that is to be the peripheral portion of each individual semiconductor device. The thickness of theperipheral blade 22 used to form the groove is between 35 μm and 150 μm. The width of thegroove 23 is made larger than the thickness of theperipheral blade 22 by 1 μm to 5 μm. The depth of thegroove 23 is set larger than 10 μm as shown in FIG. 2-B. By making thegroove 23 deeper than 10 μm, the groove can be formed with a stable width without depending very much on the shape of the tip of theblade 22. - After this, the surface of the
semiconductor wafer 20 is filled with theresin 24. As a result, thegroove 23 is also filled with theresin 24 as shown in FIG. 2-C. - Next, as shown in FIG. 2-D, the surface of the
resin 24 is polished with thepolishing blade 25 until thewire 21 embedded in theresin 24 is exposed. After this, as shown in FIG. 2-E, abump electrode 26 made of a solder ball is formed on thewire 21. - After this, the portion in which the
groove 23 has been formed in the previous process is cut with a high speed rotatingperipheral blade 27. As a result, thesemiconductor wafer 20 is divided into multiple semiconductor devices. In this case, it is desirable that the thickness of theperipheral blade 27 be smaller than that of theblade 22, preferably by more than 6 μm as shown in FIG. 2-F. - According to the manufacturing method of the present invention, the
semiconductor wafer 20 is divided into multiple semiconductor devices by forming thegroove 23 on the surface of thesemiconductor wafer 20, sealing with a resin the surface of thesemiconductor wafer 20, and cutting thesemiconductor wafer 20 along thegroove 23. - When the blade directly hits the surface of the
semiconductor wafer 20, a stress is applied to the surface of thesemiconductor wafer 20. Theblade 27 used to divide thesemiconductor wafer 20 into multiple semiconductor devices dose not directly hit the surface of thesemiconductor wafer 20. Instead, theblade 27 hits the bottom of thegroove 23. Hence, the stress is applied to the surface of thesemiconductor wafer 20 when thegroove 23 is formed but not when thesemiconductor wafer 20 is cut into multiple semiconductor devices. - When the
groove 23 is formed, thesemiconductor wafer 20 is cut to a small depth. Therefore, in this case, the length of time theblade 22 stays in contact with the surface of thesemiconductor wafer 20 is shorter compared with the case in which thesemiconductor wafer 20 is cut into multiple semiconductor devices. Therefore, the stress applied to the surface of thesemiconductor wafer 20 in this case is small. As a result, the surface of each of the multiple semiconductor devices is less likely to be broken or cracked. Even if the surface of thesemiconductor wafer 20 is chipped when thegroove 23 is formed, the chipped portion is filed with theresin 24. Therefore, the chipped portion does not get corroded. - Thus, according to the semiconductor device and semiconductor device manufacturing method of the first embodiment of the present invention, semiconductor devices are provided without having the resin portion peeled off from the semiconductor substrate while reducing the amount the surface of the semiconductor device is chipped.
- FIG. 3 shows the structure of a semiconductor device according to the second embodiment of the present invention.
- FIG. 3-A is a back view of the semiconductor device according to the second embodiment of the present invention. FIG. 3-B is a cross sectional view of what is shown in FIG. 3-A across the line A-O-B. In what follows, the second embodiment of the present invention will be explained with reference to FIG. 3. The same reference numerals are used for the components that are already used in FIG. 1.
- The second embodiment is identical with the first embodiment in that a
step unit 6 is formed on thesemiconductor substrate 1. - As shown in FIG. 3-A with the broken line, the width of the
step unit 6 is varied periodically like a pule wave form (this width is shown by X in the drawing). By forming thestep unit 6 in this shape, the degree of the anchor effect of thestep unit 6 is further increased. Moreover, as shown in FIG. 3-A, the step is formed in two directions along each side of the semiconductor device. The step consists ofstep portions 31 that are parallel to the side of the semiconductor device andstep portions 32 that are perpendicular to the side of the semiconductor device. - Therefore, regardless of the direction from which a shear stress or thermal stress is applied to the semiconductor device, it is possible to prevent the resin from getting peeled off from the semiconductor substrate.
- Hence, according to the second embodiment, the resultant semiconductor device has an anchor effect that is superior to the anchor effect achieved in the first embodiment.
- FIG. 4 is a process diagram showing the process of the semiconductor device manufacturing method according to the second embodiment of the present invention. FIG. 5 shows the shape of the groove formed in the process of the semiconductor device manufacturing method according to the second embodiment of the present invention.
- Next, the semiconductor device manufacturing method of the second embodiment of the present invention will be explained with reference to FIG. 4. The same reference numerals are used for the components that are already used in FIG. 2.
- First, a
wire 21 made of Cu is formed on asemiconductor wafer 20 by an electric plating process as shown in FIG. 4-A. - Second, a
groove 23 is formed on the surface of thesemiconductor wafer 20 by illuminating a laser light onto the surface of thesemiconductor wafer 20. Thisgroove 23 is formed in each of those portions that are to become the peripheral portions of the multiple semiconductor devices to be formed. The width of thegroove 23 is varied periodically between the lower limit of X1 μm and the upper limit X2 μm. The depth of thegroove 23 is set to 10 μm as shown in FIG. 4-B. FIG. 5 is a magnified top view of the shape of thegroove 23. - Third, as shown in FIG. 4-C, the surface of the
semiconductor wafer 20 is filled with aresin 24. In this case, thegroove 23 is also filled with theresin 24. - Fourth, as shown in FIG. 4-D, the surface of the
resin 24 is polished using apolishing blade 25 until thewire 21 embedded in theresin 24 is exposed. - Fifth, as shown in FIG. 4-E, a
bump electrode 26 made of a solder ball or the like is formed on the exposedwire 20. - Finally, as shown in FIG. 4-F, the
semiconductor wafer 20 is cut and divided into multiple semiconductor devices using a high speed rotatingperipheral blade 27. In this case, it is desirable that the thickness of theperipheral blade 27 be made smaller than the minimum width X1 of the groove. If possible, the thickness of theperipheral blade 27 should be made smaller than the minimum width X1 of the groove by at least 6 μm - As in the first embodiment, the amount of stress applied to the surface of the semiconductor wafer can be reduced. In the present embodiment, the step unit is formed in the shape of a pulse wave form. As a result, the stress that is generated when the
resin 24 hardens and contracts is absorbed by the step unit. Thus, according to the semiconductor device manufacturing method of the second embodiment, stable semiconductor devices are provided without having the resin portion peeled off from the semiconductor substrate. - In the embodiments of the present invention, the wire was exposed by polishing the sealing resin. However, it is not necessary to polish the sealing resin if the amount of the resin is controlled so that the wire will be exposed in sealing the semiconductor surface with the resin.
- It should be noted that the shape of the step unit need not be like a pulse wave form. The same effect can be achieved by varying the width of the step unit within a range between a prescribed upper limit and a prescribed lower limit and by dividing the semiconductor substrate into individual devices using a blade whose thickness is smaller than the lower limit width of the step unit.
Claims (12)
1. A semiconductor device, comprising:
a semiconductor substrate having a central portion with a first thickness and a peripheral portion with a second thickness that is smaller than said first thickness;
an electrode pad formed on said semiconductor substrate;
a sealing resin for sealing said semiconductor substrate;
a protruded electrode formed on said sealing resin; and
a wire which electrically connects said electrode pad to said protruded electrode.
2. A semiconductor device as claimed in claim 1 , wherein said first thickness is less than said second thickness by more than 10 μm.
3. A semiconductor device, comprising:
a semiconductor substrate having a central portion and a peripheral portion that is formed with a step of prescribed height that is measured with respect to a surface of said central portion;
an electrode pad formed on said central portion of said semiconductor substrate;
a protruded electrode that is electrically connected to said electrode pad via a wire; and
a sealing resin for sealing said central portion, said peripheral portion, and said wire of said semiconductor substrate.
4. A semiconductor device as claimed in claim 3 , wherein said peripheral portion of said semiconductor substrate has a width that is equal to a distance from an edge portion of said semiconductor device to said central portion, and wherein a width of said peripheral portion is varied between a first value and a second value.
5. A semiconductor device as claimed in claim 3 , wherein said peripheral portion of said semiconductor substrate has a width that is equal to a distance from an edge portion of said semiconductor device to said central portion, and said width of said peripheral portion is over 3 μm.
6. A semiconductor device as claimed in claim 3 , wherein said prescribed height of said step is over 10 μm.
7. A semiconductor device manufacturing method comprising the steps of:
forming an electrode pad on a semiconductor wafer;
forming a wire to be connected to said electrode pad;
forming on a prescribed region of said semiconductor wafer a groove having a first width that is varied between a first value as a lower limit and a second value as an upper limit;
sealing with a resin said semiconductor wafer and said wire;
forming on said resin a protruded electrode that is electrically connected to said wire; and
dividing said semiconductor wafer into a plurality of semiconductor devices by cutting said prescribed region using a blade having a thickness that is smaller than said first width.
8. A semiconductor device manufacturing method as claimed in claim 7 , wherein a depth of said groove having said first width is over 10 μm.
9. A semiconductor device manufacturing method as claimed in claim 7 , wherein a difference between said first width and said second width is over 6 μm.
10. A semiconductor device manufacturing method comprising the steps of:
forming an electrode pad on a semiconductor wafer;
forming a wire to be connected to said electrode pad;
forming on a prescribed region of said semiconductor wafer a groove having a first width that varies between a first value as a lower limit and a second value as an upper limit;
sealing with a resin said semiconductor wafer and said wire;
forming on said resin a protruded electrode that is electrically connected to said wire; and
dividing said semiconductor wafer into a plurality of semiconductor devices by cutting said prescribed region using a blade having a third thickness that is smaller than said second value.
11. A semiconductor device manufacturing method as claimed in claim 10 , wherein a depth of said groove is over 10 μm.
12. A semiconductor device manufacturing method as claimed in claim 10 , wherein a difference between said second value and said third width is over 6 μm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/778,116 US20040161910A1 (en) | 1999-03-11 | 2004-02-17 | Semiconductor apparatus and semiconductor apparatus manufacturing method |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11065157A JP3128548B2 (en) | 1999-03-11 | 1999-03-11 | Semiconductor device and method of manufacturing semiconductor device |
JP065157/99 | 1999-03-11 | ||
US09/519,662 US6281591B1 (en) | 1999-03-11 | 2000-03-06 | Semiconductor apparatus and semiconductor apparatus manufacturing method |
US09/897,090 US6770543B2 (en) | 1999-03-11 | 2001-07-03 | Semiconductor apparatus and semiconductor apparatus manufacturing method |
US10/778,116 US20040161910A1 (en) | 1999-03-11 | 2004-02-17 | Semiconductor apparatus and semiconductor apparatus manufacturing method |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/897,090 Continuation US6770543B2 (en) | 1999-03-11 | 2001-07-03 | Semiconductor apparatus and semiconductor apparatus manufacturing method |
Publications (1)
Publication Number | Publication Date |
---|---|
US20040161910A1 true US20040161910A1 (en) | 2004-08-19 |
Family
ID=13278777
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/519,662 Expired - Lifetime US6281591B1 (en) | 1999-03-11 | 2000-03-06 | Semiconductor apparatus and semiconductor apparatus manufacturing method |
US09/897,090 Expired - Fee Related US6770543B2 (en) | 1999-03-11 | 2001-07-03 | Semiconductor apparatus and semiconductor apparatus manufacturing method |
US10/778,116 Abandoned US20040161910A1 (en) | 1999-03-11 | 2004-02-17 | Semiconductor apparatus and semiconductor apparatus manufacturing method |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/519,662 Expired - Lifetime US6281591B1 (en) | 1999-03-11 | 2000-03-06 | Semiconductor apparatus and semiconductor apparatus manufacturing method |
US09/897,090 Expired - Fee Related US6770543B2 (en) | 1999-03-11 | 2001-07-03 | Semiconductor apparatus and semiconductor apparatus manufacturing method |
Country Status (4)
Country | Link |
---|---|
US (3) | US6281591B1 (en) |
JP (1) | JP3128548B2 (en) |
KR (1) | KR100659954B1 (en) |
TW (1) | TW445589B (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040238926A1 (en) * | 2003-03-20 | 2004-12-02 | Seiko Epson Corporation | Semiconductor wafer, semiconductor device and method for manufacturing same, circuit board, and electronic apparatus |
US20060258051A1 (en) * | 2005-05-10 | 2006-11-16 | Texas Instruments Incorporated | Method and system for solder die attach |
WO2008077659A1 (en) * | 2006-12-21 | 2008-07-03 | Robert Bosch Gmbh | Electrical component |
US20130309865A1 (en) * | 2012-05-16 | 2013-11-21 | Samsung Electronics Co., Ltd. | Method of manufacturing substrate for mounting electronic device |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3446825B2 (en) * | 1999-04-06 | 2003-09-16 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
JP4691787B2 (en) * | 2001-01-15 | 2011-06-01 | パナソニック株式会社 | SAW device |
JP4856328B2 (en) * | 2001-07-13 | 2012-01-18 | ローム株式会社 | Manufacturing method of semiconductor device |
US6734568B2 (en) * | 2001-08-29 | 2004-05-11 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
JP4439151B2 (en) | 2001-10-31 | 2010-03-24 | 株式会社リコー | IC socket |
JP3775499B2 (en) | 2002-01-08 | 2006-05-17 | 株式会社リコー | Semiconductor device, manufacturing method thereof, and DC-DC converter |
US20030218246A1 (en) * | 2002-05-22 | 2003-11-27 | Hirofumi Abe | Semiconductor device passing large electric current |
US20040023439A1 (en) | 2002-07-03 | 2004-02-05 | Kazunari Kimino | Apparatus and method for manufacturing semiconductor device |
JP3639272B2 (en) * | 2002-08-30 | 2005-04-20 | 株式会社東芝 | Semiconductor device and method for manufacturing semiconductor device |
US7042065B2 (en) | 2003-03-05 | 2006-05-09 | Ricoh Company, Ltd. | Semiconductor device and method of manufacturing the same |
JP4537702B2 (en) * | 2003-12-26 | 2010-09-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
JP4290088B2 (en) | 2004-07-14 | 2009-07-01 | 株式会社リコー | IC socket |
JP4653447B2 (en) * | 2004-09-09 | 2011-03-16 | Okiセミコンダクタ株式会社 | Manufacturing method of semiconductor device |
JP2006196701A (en) | 2005-01-13 | 2006-07-27 | Oki Electric Ind Co Ltd | Manufacturing method for semiconductor device |
CN101278394B (en) * | 2005-10-03 | 2010-05-19 | 罗姆股份有限公司 | Semiconductor device |
JP5116250B2 (en) * | 2006-04-11 | 2013-01-09 | キヤノン株式会社 | Multilayer piezoelectric element, method for manufacturing the same, and vibration wave driving device |
US7569422B2 (en) | 2006-08-11 | 2009-08-04 | Megica Corporation | Chip package and method for fabricating the same |
JP5081037B2 (en) | 2008-03-31 | 2012-11-21 | ラピスセミコンダクタ株式会社 | Semiconductor device |
US7517726B1 (en) * | 2008-04-25 | 2009-04-14 | Shanghai Kaihong Technology Co., Ltd | Wire bonded chip scale package fabrication methods |
US8421201B2 (en) | 2009-06-22 | 2013-04-16 | Stats Chippac Ltd. | Integrated circuit packaging system with underfill and methods of manufacture thereof |
JP5475363B2 (en) * | 2009-08-07 | 2014-04-16 | ラピスセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
JP5003802B2 (en) * | 2010-07-22 | 2012-08-15 | パナソニック株式会社 | SAW device and manufacturing method thereof |
US9358580B1 (en) * | 2013-03-12 | 2016-06-07 | BTD Wood Powder Coating, Inc. | Method for preparing and top coating a powder coated wood substrate |
TWI581676B (en) * | 2016-04-27 | 2017-05-01 | 矽品精密工業股份有限公司 | Electronic package and substrate structure |
JP7433020B2 (en) | 2019-11-07 | 2024-02-19 | ローム株式会社 | Chip parts and their manufacturing method |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5379187A (en) * | 1993-03-25 | 1995-01-03 | Vlsi Technology, Inc. | Design for encapsulation of thermally enhanced integrated circuits |
US5393711A (en) * | 1991-10-12 | 1995-02-28 | Robert Bosch Gmbh | Process for manufacturing semiconductor components |
US5604372A (en) * | 1994-08-30 | 1997-02-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor pressure sensor apparatus |
US5701034A (en) * | 1994-05-03 | 1997-12-23 | Amkor Electronics, Inc. | Packaged semiconductor die including heat sink with locking feature |
US5757078A (en) * | 1995-04-27 | 1998-05-26 | Nec Corporation | Semiconductor device with increased multi-bumps and adhered multilayered insulating films and method for installing same |
US5786266A (en) * | 1994-04-12 | 1998-07-28 | Lsi Logic Corporation | Multi cut wafer saw process |
US5786631A (en) * | 1995-10-04 | 1998-07-28 | Lsi Logic Corporation | Configurable ball grid array package |
US5801435A (en) * | 1995-02-27 | 1998-09-01 | Seiko Epson Corporation | Resin sealing type semiconductor device and method of making the same |
US5883440A (en) * | 1996-09-30 | 1999-03-16 | Sony Corporation | Outline forming method for semiconductor device and semiconductor manufacturing device used in this method |
US5886415A (en) * | 1996-01-19 | 1999-03-23 | Shinko Electric Industries, Co., Ltd. | Anisotropic conductive sheet and printed circuit board |
US5939778A (en) * | 1996-07-09 | 1999-08-17 | International Business Machines Corporation | Integrated circuit chip package |
US5977641A (en) * | 1997-05-14 | 1999-11-02 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US5989982A (en) * | 1997-10-08 | 1999-11-23 | Oki Electric Industry Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20010003049A1 (en) * | 1996-07-12 | 2001-06-07 | Norio Fukasawa | Method and mold for manufacturing semiconductor device, semiconductor device, and method for mounting the device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51137378A (en) | 1975-05-22 | 1976-11-27 | Mitsubishi Electric Corp | Semi conductor wafer |
KR0178255B1 (en) * | 1995-11-17 | 1999-03-20 | 황인길 | Pcb carrier frame of bag semiconductor package and method of making the same |
JP3137322B2 (en) * | 1996-07-12 | 2001-02-19 | 富士通株式会社 | Semiconductor device manufacturing method, semiconductor device manufacturing mold, and semiconductor device |
JP3143081B2 (en) * | 1996-07-31 | 2001-03-07 | シャープ株式会社 | Chip support substrate for semiconductor package, semiconductor device, and method of manufacturing semiconductor device |
JP3152180B2 (en) | 1997-10-03 | 2001-04-03 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
JPH11224890A (en) | 1997-12-01 | 1999-08-17 | Mitsui High Tec Inc | Semiconductor device and its manufacturing |
-
1999
- 1999-03-11 JP JP11065157A patent/JP3128548B2/en not_active Expired - Fee Related
-
2000
- 2000-03-06 US US09/519,662 patent/US6281591B1/en not_active Expired - Lifetime
- 2000-03-07 KR KR1020000011292A patent/KR100659954B1/en active IP Right Grant
- 2000-03-10 TW TW089104363A patent/TW445589B/en not_active IP Right Cessation
-
2001
- 2001-07-03 US US09/897,090 patent/US6770543B2/en not_active Expired - Fee Related
-
2004
- 2004-02-17 US US10/778,116 patent/US20040161910A1/en not_active Abandoned
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5393711A (en) * | 1991-10-12 | 1995-02-28 | Robert Bosch Gmbh | Process for manufacturing semiconductor components |
US5379187A (en) * | 1993-03-25 | 1995-01-03 | Vlsi Technology, Inc. | Design for encapsulation of thermally enhanced integrated circuits |
US5786266A (en) * | 1994-04-12 | 1998-07-28 | Lsi Logic Corporation | Multi cut wafer saw process |
US5701034A (en) * | 1994-05-03 | 1997-12-23 | Amkor Electronics, Inc. | Packaged semiconductor die including heat sink with locking feature |
US5604372A (en) * | 1994-08-30 | 1997-02-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor pressure sensor apparatus |
US5801435A (en) * | 1995-02-27 | 1998-09-01 | Seiko Epson Corporation | Resin sealing type semiconductor device and method of making the same |
US5757078A (en) * | 1995-04-27 | 1998-05-26 | Nec Corporation | Semiconductor device with increased multi-bumps and adhered multilayered insulating films and method for installing same |
US5786631A (en) * | 1995-10-04 | 1998-07-28 | Lsi Logic Corporation | Configurable ball grid array package |
US5886415A (en) * | 1996-01-19 | 1999-03-23 | Shinko Electric Industries, Co., Ltd. | Anisotropic conductive sheet and printed circuit board |
US5939778A (en) * | 1996-07-09 | 1999-08-17 | International Business Machines Corporation | Integrated circuit chip package |
US20010003049A1 (en) * | 1996-07-12 | 2001-06-07 | Norio Fukasawa | Method and mold for manufacturing semiconductor device, semiconductor device, and method for mounting the device |
US5883440A (en) * | 1996-09-30 | 1999-03-16 | Sony Corporation | Outline forming method for semiconductor device and semiconductor manufacturing device used in this method |
US5977641A (en) * | 1997-05-14 | 1999-11-02 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
US5989982A (en) * | 1997-10-08 | 1999-11-23 | Oki Electric Industry Co., Ltd. | Semiconductor device and method of manufacturing the same |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040238926A1 (en) * | 2003-03-20 | 2004-12-02 | Seiko Epson Corporation | Semiconductor wafer, semiconductor device and method for manufacturing same, circuit board, and electronic apparatus |
US20060258051A1 (en) * | 2005-05-10 | 2006-11-16 | Texas Instruments Incorporated | Method and system for solder die attach |
WO2008077659A1 (en) * | 2006-12-21 | 2008-07-03 | Robert Bosch Gmbh | Electrical component |
US20130309865A1 (en) * | 2012-05-16 | 2013-11-21 | Samsung Electronics Co., Ltd. | Method of manufacturing substrate for mounting electronic device |
Also Published As
Publication number | Publication date |
---|---|
KR100659954B1 (en) | 2006-12-22 |
JP2000260910A (en) | 2000-09-22 |
TW445589B (en) | 2001-07-11 |
JP3128548B2 (en) | 2001-01-29 |
US20010039110A1 (en) | 2001-11-08 |
KR20000071421A (en) | 2000-11-25 |
US6281591B1 (en) | 2001-08-28 |
US6770543B2 (en) | 2004-08-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6281591B1 (en) | Semiconductor apparatus and semiconductor apparatus manufacturing method | |
US7763528B2 (en) | Method for manufacturing semiconductor device | |
JP4183375B2 (en) | Semiconductor device and manufacturing method thereof | |
US6699735B2 (en) | Semiconductor device and method for manufacturing the semiconductor device | |
KR100297451B1 (en) | Semiconductor package and method for manufacturing thereof | |
US6495916B1 (en) | Resin-encapsulated semiconductor device | |
EP1043772A2 (en) | Method for packaging and mounting semiconductor device and device obtained thereby | |
JP2000353766A (en) | Semiconductor device and manufacture thereof | |
US20100301464A1 (en) | Asterisk pad | |
US20210134685A1 (en) | Semiconductor structure and method of fabricating the same | |
EP1202343A2 (en) | Semiconductor device and fabrication process therefor | |
JP2009246251A (en) | Semiconductor device and its manufacturing method | |
US20200365408A1 (en) | Semiconductor packages with die including cavities and related methods | |
TW452873B (en) | Manufacturing method of wafer scale semiconductor package structure | |
JP2003086762A (en) | Semiconductor device and manufacturing method therefor | |
US11894234B2 (en) | Semiconductor packages with die support structure for thin die | |
US20200273767A1 (en) | Electronic chip package | |
JP2003124392A (en) | Semiconductor device and manufacturing method therefor | |
US20120168947A1 (en) | Methods and Designs for Localized Wafer Thinning | |
EP1154475A1 (en) | Semiconductor device and semiconductor device manufacturing method | |
US10283483B2 (en) | Packaging method and package structure for image sensing chip | |
US20200258750A1 (en) | Die support structures and related methods | |
JP2007311575A (en) | Semiconductor device | |
US20060270163A1 (en) | Semiconductor chip with flip chip contacts, and method for producing semiconductor chip with flip chip contacts | |
KR20000066097A (en) | Chip scale package and method of fabricating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |