US20040164886A1 - Data driver - Google Patents
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- US20040164886A1 US20040164886A1 US10/459,479 US45947903A US2004164886A1 US 20040164886 A1 US20040164886 A1 US 20040164886A1 US 45947903 A US45947903 A US 45947903A US 2004164886 A1 US2004164886 A1 US 2004164886A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
- G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
- G09G3/3283—Details of drivers for data electrodes in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
Definitions
- the present invention relates to a data driver for an active matrix organic light emitting display (AMOLED), which is configured to convert digital voltage signals into analog current signals to drive pixels in the display to emit light.
- AMOLED active matrix organic light emitting display
- Pixels in an AMOLED are driven by analog current signals; however, the signals that control the pixels to emit light are digital voltage signals. Therefore, each AMOLED needs a data driver (or source driver) to convert digital control voltage signals into analog current signals.
- FIG. 1 illustrates a data driver 1 of the prior art.
- the data driver 1 includes a first shift register 101 , a data register 103 , a voltage latch 105 , a converter 107 , a current latch 109 , a current source 111 , and a second shift register 113 .
- the converter 107 is configured to receive the digital voltage signals 110 , which will later drive pixels to emit light, from the voltage latch 105 , and to convert the digital voltage signals 110 into analog current signals 112 based on the reference currents provided by the current source 111 .
- the second shift register 113 is configured to switch on or off each cell in the current latch 109 in order to store the analog current signals 112 sent by the converter 107 .
- an enabling signal 108 enables the current latch 109 so that all the analog current signals 114 , identical to the analog current signals 112 , are able to reach all pixels of the AMOLED to present a transient frame.
- the framework of the converter 107 is basically a current mirror.
- FIG. 2 illustrates one kind of current mirror of the prior art.
- a reference current I s generated by the current source 111 shown in FIG. 1, mirrors I p1 , I p2 , I p3 , etc. through a transistor MP 1 .
- the values of the mirrored currents e.g. I p1 , I p2 , I p3 , etc., are associated with the characteristics, i.e. aspect ratio, threshold voltage, and mobility, of MP 2 , MP 3 , MP 4 , etc.
- the present invention discloses a data driver for an active matrix organic light emitting display (AMOLED), which converts digital voltage signals into analog current signals in order to drive all pixels in the display to emit light.
- AMOLED active matrix organic light emitting display
- the data driver includes a first shift register, a data register, a data latch, a second shift register, and N converters.
- the first shift register is configured to provide an N-bit first control signal.
- the data register is configured to store N M-bit digital voltage signals by switching on the cells in it in turn in response to the first control signal, and to send the N digital voltage signals to the data latch.
- the data latch is configured to receive the N digital voltage signals and respectively transmit them to the N converters in response to an enabling signal.
- the second shift register is configured to provide an (M+1)-bit second control signal to control the procedure of converting the digital voltage signals into analog current signals.
- Each converter of the data driver of the present invention is a digital-voltage-to-analog-current converter with M units regarded as current sources.
- Each current source (or each unit) includes two control signals to enable or disable the transistors within so as to control the generation timing of mirrored currents.
- the current source can overcome the drawbacks of the prior art and, therefore, the mirrored current does not deviate even if the characteristics of the transistors within have been changed during fabricating.
- FIG. 1 illustrates a data driver of the prior art.
- FIG. 2 is the exemplary circuitry of a current mirror of the prior art.
- FIG. 3 illustrates the data driver of the present invention.
- FIG. 4 illustrates the converter of the present invention.
- FIG. 5 is the circuitry of a current mirror of the present invention.
- the data driver 2 disclosed by the present invention includes a first shift register 201 , a data register 203 , a data latch 205 , a second shift register 207 , and N converters 209 .
- the first shift register 201 is configured to receive a data shift signal 202 and provide an N-bit first control signal 204 .
- the first control signal 204 is transmitted to the data register 203 to switch on the cells in the data register 203 so that N M-bit digital voltage signals 206 are stored in turn.
- the digital voltage signals 206 are the signals that need to be converted into analog current signals 218 , which are then respectively transmitted through data lines to drive pixels and make pixels emit light.
- the data register 203 After receiving and storing all of the digital voltage signals 206 , the data register 203 will send these signals 206 to the data latch 205 .
- the data latch 205 is switched on by an enabling signal 210 at a particular timing so that the digital voltage signals 208 , identical to the digital voltage signals 206 , are able to be transmitted to N converters 209 respectively.
- the second shift register 207 is configured to provide an (M+1)-bit second control signal 216 in response to a signal 214 to activate the procedure of converting digital voltage signals 212 , identical to the digital voltage signals 208 , to analog current signals 218 in N converters 209 .
- the converters 209 are digital-voltage-to-analog-current converters with the same function that the current latch 109 shown in FIG. 1 has. Each of the converters 209 is capable of seizing the converted analog current signals 218 and does not release them to pixels until all of the digital voltage signals 212 have been converted.
- each digital voltage signal is assumed to be a 6-bit signal.
- each of the N converters 209 responsive to a 6-bit input, is required to have 6 first devices 301 and 6 second devices 303 .
- Each first device 301 responsive to one of the preceding 6 bits SW 0 ⁇ SW 5 of the second control signal 216 , is configured to generate one of the 6 first mirrored currents I m0 ⁇ I m5 respectively, and to transmit it to the corresponding second device 303 .
- Each second device 303 responsive to both a last bit SW 6 of the second control signal 216 and one of the 6 first mirrored currents I m0 ⁇ I m5 , is configured to generate one of the 6 second mirrored currents I 10 ⁇ I 15 . Finally, the specific digital voltage signal 212 is converted into an analog current signal 218 when all of the 6 second mirrored currents I 10 ⁇ I 15 are added together.
- the first device 301 converts the reference current I ref1 provided by the current source 211 into a first mirrored current I m1 after receiving the second bit SW 1 of the second control signal 216 .
- the second device 303 then converts the first mirrored current I m1 into a second mirrored current I 11 , according to the value of the second bit D 1 of the specific digital voltage signal 206 while receiving the last bit SW 6 of the second control signal 216 .
- the current source 211 of the embodiment has at least 6 outputs so that it provides 6 different reference currents I ref0 ⁇ I ref5 for the 6 first devices 301 to respectively generate the 6 first mirrored currents I m0 ⁇ I m5 .
- FIG. 5 illustrates the circuitry of the unit 3 shown in FIG. 4.
- the converter 209 can provide a high level voltage source VDD and a low level voltage source VSS externally or internally.
- the first device 301 includes a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , and a first capacitor C 1 .
- the first transistor M 1 and the second transistor M 2 are n-channel TFTs, and the third transistor M 3 is a p-channel TFT. All of the transistors M 1 , M 2 , and M 3 include a source, a drain, and a gate respectively.
- the first capacitor C 1 includes a first end 1 st and a second end 2 nd.
- the interconnections within the first device 301 include: the gate G of the first transistor M 1 is configured to input the second bit SW 1 of the second control signal 216 , the second terminal 2 nd of the first transistor M 1 is connected to the second output I ref1 of the current source 211 , the first terminal 1 st of the first transistor M 1 is respectively connected to the first terminal 1 st of the second transistor M 2 and the second terminal 2 nd of the third transistor M 3 , the gate G of the second transistor M 2 is connected to the gate G of the first transistor M 1 , the second terminal 2 nd of the second transistor M 2 is respectively connected to the gate G of the third transistor M 3 and the second end 2 nd of the first capacitor C 1 , and the first end 1 st of the first capacitor C 1 is respectively connected to the first terminal 1 st of the third transistor M 3 and the high level voltage source VDD.
- the second device 303 includes a fourth transistor M 4 , a fifth transistor M 5 , a sixth transistor M 6 , a seventh transistor M 7 , and a second capacitor C 2 .
- the transistors M 4 ⁇ M 7 are all n-channel TFTs having a first terminal 1 st, a second terminal 2 nd, and a gate G.
- the second capacitor C 2 includes a first end 1 st and a second end 2 nd.
- the interconnections within the second device 303 include: the gate G of the fourth transistor M 4 is configured to input the last bit SW 6 of the second control signal 216 , the second terminal 2 nd of the fourth transistor M 4 is connected to the second terminal 2 nd of the third transistor M 3 of the first device 301 , the first terminal 1 st of the fourth transistor M 4 is respectively connected to the first terminal 1 st of the fifth transistor M 5 and the second terminal 2 nd of the sixth transistor M 6 , the gate G of the fifth transistor M 5 is connected to the gate G of the fourth transistor M 4 , the second terminal 2 nd of the fifth transistor M 5 is respectively connected to the gate G of the sixth transistor M 6 and the second end 2 nd of the second capacitor C 2 , the first end 1 st of the second capacitor C 2 is respectively connected to the first terminal 1 st of the sixth transistor M 6 and the low level voltage source VSS, the first terminal 1 st of the seventh transistor M 7 is connected to the second terminal 2 nd of the sixth transistor M 6 , and the gate
- the second bit SW 1 of the second control signal 216 is used to enable or disable the first transistor M 1 and the second transistor M 2 .
- the first transistor M 1 and the second transistor M 2 are enabled so that the second reference current I ref1 provided by the current source 211 is able to flow through the first transistor M 1 and the third transistor M 3 and hence charge the first capacitor C 1 .
- the second reference current I ref1 is converted into a corresponding first voltage stored in the first capacitor C 1 .
- SW 1 will switch to a low level so that the first transistor M 1 and the second transistor M 2 are disabled and, therefore, the first voltage is saved in the first capacitor C 1 .
- the last bit SW 6 of the second control signal 216 is used herein to enable or disable the fourth transistor M 4 and the fifth transistor M 5 .
- the fourth transistor M 4 and the fifth transistor M 5 are enabled so that the first voltage stored in the first capacitor C 1 is able to convert into a second voltage stored in the second capacitor C 2 .
- SW 6 switches to a low level to disable the fourth transistor M 4 and the fifth transistor M 5 and, therefore, the second voltage is saved in the second capacitor C 2 .
- the second bit D 1 of the digital voltage signal 212 transmitted to the converter 209 shown in FIG. 4 is high, the second voltage will be converted into the second mirrored current I 11 flowing through the sixth transistor M 6 and the seventh transistor M 7 . Otherwise, the transistor M 7 will be off and the second mirrored current I 11 will not appear.
- the second reference current I ref1 can be converted into a corresponding V GS stored in the first capacitor C 1 regardless of the practical aspect ratio, threshold voltage, or mobility of the third transistor M 3 .
- the V GS stored in the first capacitor C 1 is converted into the first mirrored current I m1 to charge the second capacitor C 2 through the transistors M 3 , M 4 , and M 6 .
- the value of the second mirrored current I 11 is substantially equal to that of the first mirrored current I m1 , i.e. equal to the reference current I ref1 .
- the unit 3 is a current mirror.
- SW 1 is regarded as a first control signal for enabling or disabling the first transistor M 1 and the second transistor M 2 ; SW 1 also assures that the reference current I ref1 be converted into the first voltage stored in the first capacitor C 1 .
- SW 6 is regarded as a second control signal for enabling or disabling the fourth transistor M 4 and the fifth transistor M 5 ; SW 6 assures that the first voltage be converted into the corresponding second voltage stored in the second capacitor C 2 .
- the second mirrored current I 11 is then generated in reference to the second voltage, i.e. in reference to the reference current I ref1 .
- the framework of the current mirror of the present invention has an advantage of generating a steady mirrored current without respect to the characteristics of the transistors within.
- FIG. 4 The frameworks and functions of other units shown in FIG. 4 are identical to those of the unit 3 .
- the second terminals of all the seventh transistors M 7 of the second device 303 are respectively connected to a common node n 1 .
- a sum I TOTAL of all the currents flowing through the common node n 1 is one of the analog current signals 218 , which drives one pixel in an AMOLED to emit light.
- N converters 209 provided by the present invention to drive N pixels in an AMOLED to emit light simultaneously.
- the data driver of the present invention is capable of converting digital voltage control signals for controlling pixels to emit light into analog current signals that can drive OLEDs directly. Moreover, the data driver of the present invention is capable of generating steady analog current signals even if the characteristics of the transistors within deviate from theoretical values during fabricating.
Abstract
Description
- This Application claims priority to Taiwan Patent Application No. 092103685 filed on Feb. 21, 2003.
- The present invention relates to a data driver for an active matrix organic light emitting display (AMOLED), which is configured to convert digital voltage signals into analog current signals to drive pixels in the display to emit light.
- Pixels in an AMOLED are driven by analog current signals; however, the signals that control the pixels to emit light are digital voltage signals. Therefore, each AMOLED needs a data driver (or source driver) to convert digital control voltage signals into analog current signals.
- FIG. 1 illustrates a
data driver 1 of the prior art. As it shows, thedata driver 1 includes afirst shift register 101, adata register 103, avoltage latch 105, aconverter 107, acurrent latch 109, acurrent source 111, and asecond shift register 113. Theconverter 107 is configured to receive thedigital voltage signals 110, which will later drive pixels to emit light, from thevoltage latch 105, and to convert thedigital voltage signals 110 into analogcurrent signals 112 based on the reference currents provided by thecurrent source 111. Thesecond shift register 113 is configured to switch on or off each cell in thecurrent latch 109 in order to store the analogcurrent signals 112 sent by theconverter 107. After a proper period of time, anenabling signal 108 enables thecurrent latch 109 so that all the analogcurrent signals 114, identical to the analogcurrent signals 112, are able to reach all pixels of the AMOLED to present a transient frame. - The framework of the
converter 107 is basically a current mirror. FIG. 2 illustrates one kind of current mirror of the prior art. With reference to FIG. 2, a reference current Is, generated by thecurrent source 111 shown in FIG. 1, mirrors Ip1, Ip2, Ip3, etc. through a transistor MP1. It is noted that the values of the mirrored currents, e.g. Ip1, Ip2, Ip3, etc., are associated with the characteristics, i.e. aspect ratio, threshold voltage, and mobility, of MP2, MP3, MP4, etc. Once any deviation from the theoretical characteristics of the transistors is induced during fabricating, the practical values of the mirrored current Ip1, Ip2, Ip3 etc. will bring error as well. The error, even if it is tiny, might still influence the gray level that an analog current signal actually sets in due to the narrow band of each gray level and, therefore, pixels might emit unexpected illumination. - The present invention discloses a data driver for an active matrix organic light emitting display (AMOLED), which converts digital voltage signals into analog current signals in order to drive all pixels in the display to emit light.
- The data driver includes a first shift register, a data register, a data latch, a second shift register, and N converters. The first shift register is configured to provide an N-bit first control signal. The data register is configured to store N M-bit digital voltage signals by switching on the cells in it in turn in response to the first control signal, and to send the N digital voltage signals to the data latch. The data latch is configured to receive the N digital voltage signals and respectively transmit them to the N converters in response to an enabling signal. The second shift register is configured to provide an (M+1)-bit second control signal to control the procedure of converting the digital voltage signals into analog current signals.
- Each converter of the data driver of the present invention is a digital-voltage-to-analog-current converter with M units regarded as current sources. Each current source (or each unit) includes two control signals to enable or disable the transistors within so as to control the generation timing of mirrored currents. The current source can overcome the drawbacks of the prior art and, therefore, the mirrored current does not deviate even if the characteristics of the transistors within have been changed during fabricating.
- FIG. 1 illustrates a data driver of the prior art.
- FIG. 2 is the exemplary circuitry of a current mirror of the prior art.
- FIG. 3 illustrates the data driver of the present invention.
- FIG. 4 illustrates the converter of the present invention.
- FIG. 5 is the circuitry of a current mirror of the present invention.
- With reference to FIG. 3, the
data driver 2 disclosed by the present invention includes afirst shift register 201, adata register 203, adata latch 205, asecond shift register 207, andN converters 209. Thefirst shift register 201 is configured to receive adata shift signal 202 and provide an N-bitfirst control signal 204. Thefirst control signal 204 is transmitted to thedata register 203 to switch on the cells in thedata register 203 so that N M-bitdigital voltage signals 206 are stored in turn. Thedigital voltage signals 206 are the signals that need to be converted into analogcurrent signals 218, which are then respectively transmitted through data lines to drive pixels and make pixels emit light. After receiving and storing all of thedigital voltage signals 206, thedata register 203 will send thesesignals 206 to thedata latch 205. Thedata latch 205 is switched on by an enablingsignal 210 at a particular timing so that thedigital voltage signals 208, identical to thedigital voltage signals 206, are able to be transmitted toN converters 209 respectively. Thesecond shift register 207 is configured to provide an (M+1)-bitsecond control signal 216 in response to asignal 214 to activate the procedure of convertingdigital voltage signals 212, identical to thedigital voltage signals 208, to analogcurrent signals 218 inN converters 209. Theconverters 209 are digital-voltage-to-analog-current converters with the same function that thecurrent latch 109 shown in FIG. 1 has. Each of theconverters 209 is capable of seizing the converted analogcurrent signals 218 and does not release them to pixels until all of thedigital voltage signals 212 have been converted. - To specify one preferred embodiment of the
converters 209 of the present invention, each digital voltage signal is assumed to be a 6-bit signal. As shown in FIG. 4, each of theN converters 209, responsive to a 6-bit input, is required to have 6first devices 301 and 6second devices 303. Eachfirst device 301, responsive to one of the preceding 6 bits SW0˜SW5 of thesecond control signal 216, is configured to generate one of the 6 first mirrored currents Im0˜Im5 respectively, and to transmit it to the correspondingsecond device 303. Eachsecond device 303, responsive to both a last bit SW6 of thesecond control signal 216 and one of the 6 first mirrored currents Im0˜Im5, is configured to generate one of the 6 second mirrored currents I10˜I15. Finally, the specificdigital voltage signal 212 is converted into an analogcurrent signal 218 when all of the 6 second mirrored currents I10˜I15 are added together. - Take the
unit 3 shown in FIG. 4 as an example, thefirst device 301 converts the reference current Iref1 provided by thecurrent source 211 into a first mirrored current Im1 after receiving the second bit SW1 of thesecond control signal 216. Thesecond device 303 then converts the first mirrored current Im1 into a second mirrored current I11, according to the value of the second bit D1 of the specificdigital voltage signal 206 while receiving the last bit SW6 of thesecond control signal 216. - The
current source 211 of the embodiment has at least 6 outputs so that it provides 6 different reference currents Iref0˜Iref5 for the 6first devices 301 to respectively generate the 6 first mirrored currents Im0˜Im5. The value of each 6 referent currents Iref0˜Iref5 is 2 times larger than that of each preceding one. If Iref0=2 μA, for example, then Iref1=4 μA, Iref2=8 μA, Iref3=16 μA, Iref4=32 μA, and Iref5=64 μA. Assuming that one of the digital voltage signals is (D5D4D3D2D1D0)=(101001), the corresponding analog current signal ITOTAL generated by theconverter 209, as shown in FIG. 4, will equal IM0+Im3+Im5=Iref0+Iref3+Iref5=82 μA. - FIG. 5 illustrates the circuitry of the
unit 3 shown in FIG. 4. Theconverter 209 can provide a high level voltage source VDD and a low level voltage source VSS externally or internally. Thefirst device 301 includes a first transistor M1, a second transistor M2, a third transistor M3, and a first capacitor C1. The first transistor M1 and the second transistor M2 are n-channel TFTs, and the third transistor M3 is a p-channel TFT. All of the transistors M1, M2, and M3 include a source, a drain, and a gate respectively. Since there is no difference between the source and the drain of a TFT, both are renamed as a first terminal and a second terminal in the following description to avoid misunderstanding. The first capacitor C1 includes afirst end 1 st and a second end 2nd. The interconnections within thefirst device 301 include: the gate G of the first transistor M1 is configured to input the second bit SW1 of thesecond control signal 216, the second terminal 2nd of the first transistor M1 is connected to the second output Iref1 of thecurrent source 211, thefirst terminal 1 st of the first transistor M1 is respectively connected to thefirst terminal 1 st of the second transistor M2 and the second terminal 2nd of the third transistor M3, the gate G of the second transistor M2 is connected to the gate G of the first transistor M1, the second terminal 2nd of the second transistor M2 is respectively connected to the gate G of the third transistor M3 and the second end 2nd of the first capacitor C1, and thefirst end 1 st of the first capacitor C1 is respectively connected to thefirst terminal 1 st of the third transistor M3 and the high level voltage source VDD. - The
second device 303 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a second capacitor C2. The transistors M4˜M7 are all n-channel TFTs having afirst terminal 1 st, a second terminal 2nd, and a gate G. The second capacitor C2 includes afirst end 1 st and a second end 2nd. The interconnections within thesecond device 303 include: the gate G of the fourth transistor M4 is configured to input the last bit SW6 of thesecond control signal 216, the second terminal 2nd of the fourth transistor M4 is connected to the second terminal 2nd of the third transistor M3 of thefirst device 301, thefirst terminal 1 st of the fourth transistor M4 is respectively connected to thefirst terminal 1 st of the fifth transistor M5 and the second terminal 2nd of the sixth transistor M6, the gate G of the fifth transistor M5 is connected to the gate G of the fourth transistor M4, the second terminal 2nd of the fifth transistor M5 is respectively connected to the gate G of the sixth transistor M6 and the second end 2nd of the second capacitor C2, thefirst end 1 st of the second capacitor C2 is respectively connected to thefirst terminal 1 st of the sixth transistor M6 and the low level voltage source VSS, thefirst terminal 1 st of the seventh transistor M7 is connected to the second terminal 2nd of the sixth transistor M6, and the gate G of the seventh transistor M7 is configured to input the second bit D1 of the 6-bitdigital voltage signal 212. - The second bit SW1 of the
second control signal 216 is used to enable or disable the first transistor M1 and the second transistor M2. When SW1 is high, the first transistor M1 and the second transistor M2 are enabled so that the second reference current Iref1 provided by thecurrent source 211 is able to flow through the first transistor M1 and the third transistor M3 and hence charge the first capacitor C1. In other words, the second reference current Iref1 is converted into a corresponding first voltage stored in the first capacitor C1. After the first capacitor C1 is fully charged, SW1 will switch to a low level so that the first transistor M1 and the second transistor M2 are disabled and, therefore, the first voltage is saved in the first capacitor C1. - The last bit SW6 of the
second control signal 216 is used herein to enable or disable the fourth transistor M4 and the fifth transistor M5. When SW6 is high, the fourth transistor M4 and the fifth transistor M5 are enabled so that the first voltage stored in the first capacitor C1 is able to convert into a second voltage stored in the second capacitor C2. After the second capacitor C2 is fully charged, SW6 switches to a low level to disable the fourth transistor M4 and the fifth transistor M5 and, therefore, the second voltage is saved in the second capacitor C2. If the second bit D1 of thedigital voltage signal 212 transmitted to theconverter 209 shown in FIG. 4 is high, the second voltage will be converted into the second mirrored current I11 flowing through the sixth transistor M6 and the seventh transistor M7. Otherwise, the transistor M7 will be off and the second mirrored current I11 will not appear. -
- According to this equation, when the first capacitor C1 is in charging mode, the second reference current Iref1 can be converted into a corresponding VGS stored in the first capacitor C1 regardless of the practical aspect ratio, threshold voltage, or mobility of the third transistor M3. When SW6 is high, the VGS stored in the first capacitor C1 is converted into the first mirrored current Im1 to charge the second capacitor C2 through the transistors M3, M4, and M6. Because the VGS still biases on the third transistor M3, the value of the second mirrored current I11 is substantially equal to that of the first mirrored current Im1, i.e. equal to the reference current Iref1.
- Based on the aforementioned function of the
unit 3, one can appreciate that theunit 3 is a current mirror. In this current mirror, SW1 is regarded as a first control signal for enabling or disabling the first transistor M1 and the second transistor M2; SW1 also assures that the reference current Iref1 be converted into the first voltage stored in the first capacitor C1. Moreover, SW6 is regarded as a second control signal for enabling or disabling the fourth transistor M4 and the fifth transistor M5; SW6 assures that the first voltage be converted into the corresponding second voltage stored in the second capacitor C2. The second mirrored current I11 is then generated in reference to the second voltage, i.e. in reference to the reference current Iref1. The framework of the current mirror of the present invention has an advantage of generating a steady mirrored current without respect to the characteristics of the transistors within. - The frameworks and functions of other units shown in FIG. 4 are identical to those of the
unit 3. As FIG. 4 shows, the second terminals of all the seventh transistors M7 of thesecond device 303 are respectively connected to a common node n1. A sum ITOTAL of all the currents flowing through the common node n1 is one of the analogcurrent signals 218, which drives one pixel in an AMOLED to emit light. There areN converters 209 provided by the present invention to drive N pixels in an AMOLED to emit light simultaneously. - As set forth above, the data driver of the present invention is capable of converting digital voltage control signals for controlling pixels to emit light into analog current signals that can drive OLEDs directly. Moreover, the data driver of the present invention is capable of generating steady analog current signals even if the characteristics of the transistors within deviate from theoretical values during fabricating.
Claims (15)
Applications Claiming Priority (3)
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TW092103685A TW594634B (en) | 2003-02-21 | 2003-02-21 | Data driver |
TW092103685 | 2003-02-21 | ||
TW92103685A | 2003-02-21 |
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US20040164886A1 true US20040164886A1 (en) | 2004-08-26 |
US6788231B1 US6788231B1 (en) | 2004-09-07 |
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US10/459,479 Expired - Lifetime US6788231B1 (en) | 2003-02-21 | 2003-06-12 | Data driver |
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Also Published As
Publication number | Publication date |
---|---|
TW200416653A (en) | 2004-09-01 |
TW594634B (en) | 2004-06-21 |
JP2004252404A (en) | 2004-09-09 |
JP3949617B2 (en) | 2007-07-25 |
US6788231B1 (en) | 2004-09-07 |
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