US20040180524A1 - Shielded multi-conductor interconnect bus for MEMS - Google Patents
Shielded multi-conductor interconnect bus for MEMS Download PDFInfo
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- US20040180524A1 US20040180524A1 US10/815,137 US81513704A US2004180524A1 US 20040180524 A1 US20040180524 A1 US 20040180524A1 US 81513704 A US81513704 A US 81513704A US 2004180524 A1 US2004180524 A1 US 2004180524A1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0006—Interconnects
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B26/00—Optical devices or arrangements for the control of light using movable or deformable optical elements
- G02B26/08—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
- G02B26/0816—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements
- G02B26/0833—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD
- G02B26/0841—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light by means of one or more reflecting elements the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD the reflecting element being moved or deformed by electrostatic means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49872—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing semiconductor material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates generally to microelectromechanical systems (MEMS), and more particularly to the design and fabrication of interconnect architectures for MEMS.
- MEMS microelectromechanical systems
- MEMS can include numerous electromechanical devices fabricated on a single substrate, many of which are to be separately actuated in order to achieve a desired operation.
- a MEMS optical switch may include numerous mirrors that are each positionable in a desired orientation for reflecting optical signals between originating and target locations upon actuation of one or more microactuators associated with each mirror. In order for each mirror to be separately positioned, separate control signals need to be supplied to the microactuators associated with each mirror.
- each microactuator to a control signal source with a separate electrical conductor (i.e., an interconnect line) fabricated on the surface of the substrate that extends between its associated microactuator and a bond pad at the periphery of the substrate where it can be easily connected to an off-chip control signal source.
- the separate interconnect lines together comprise an interconnect bus and are typically arranged to run parallel with each other for substantial portions of their length.
- the amount of footprint required on the surface of the substrate for an interconnect bus is an important factor in designing MEMS since increasing the footprint of the interconnect bus decreases the amount of footprint available for desired devices (e.g., mirrors and actuators).
- Another consideration is possible cross-talk between the separate interconnect lines. Cross-talk is a problem because a control signal intended for one actuator can be coupled from its interconnect line into adjacent interconnect lines causing undesired actuation of other actuators.
- a further consideration is the possibility of shorting between adjacent interconnect lines. Where the interconnect bus lines are exposed on the surface of the substrate, particles and the like can settle across adjacent interconnect lines thereby causing short circuits effecting operation of the MEMS.
- the present invention provides a shielded multi-conductor interconnect bus for MEMS and a method for fabricating such an interconnect bus.
- the shielded multi-conductor interconnect bus of the present invention substantially reduces the possibility of cross-talk between adjacent interconnect lines, alleviates the possibility of short circuits due to particles and the like settling across adjacent interconnect lines, and optimizes the amount of footprint required for such an interconnect bus.
- a shielded multi-conductor interconnect bus includes a substrate.
- the substrate may, for example, be comprised of silicon.
- a first dielectric layer overlies and is supported by at least a portion of the substrate.
- the first dielectric layer may, for example, be the lowest layer of material on the substrate (i.e., it may be formed directly on the upper surface of the substrate without any intervening layers).
- the substrate is comprised of silicon and the first dielectric layer comprises a dielectric stack deposited directly on the upper surface of the substrate that includes a lower thermal oxide layer and an upper silicon nitride layer.
- a plurality of substantially parallel electrically conductive lines are formed on the first dielectric layer.
- the electrically conductive lines may be formed from a first layer of doped polysilicon.
- the interconnect bus also includes a plurality of substantially parallel electrically conductive walls formed on the first dielectric layer.
- electrically conductive walls described herein do not have to be continuous along their lengthwise extent and may, in fact, have one or more breaks formed therein as desired.
- Each electrically conductive wall includes an upper section that extends vertically above the level of the electrically conductive lines.
- the lower sections of the electrically conductive walls may be formed from the first layer of doped polysilicon and the upper sections of the electrically conductive walls may be formed from a second layer of doped polysilicon.
- the second layer of doped polysilicon may be comprised of a thinner lower layer of doped polysilicon and a thicker upper layer of doped polysilicon.
- each channel preferably extends vertically downward through the entire thickness of the first dielectric layer to expose the upper surface of the substrate along at least a portion of each channel, and, more preferably, along the entire length of each channel.
- each set of electrically conductive lines includes at least one of the electrically conductive lines, and may include two or more electrically conductive lines.
- the electrically conductive walls also contact the underside of an electrically conductive shield positioned in a spaced relation above the electrically conductive lines.
- the electrically conductive shield may be formed from the second layer of doped polysilicon.
- the second dielectric layer may be comprised of a sacrificial material (e.g., silicon dioxide or silicate glass).
- the second dielectric layer includes a plurality of channels formed therein permitting the upper sections of the electrically conductive walls to extend vertically upward therethrough to contact the underside of the electrically conductive shield.
- each electrically conductive line is surrounded by dielectric material, and each set of electrically conductive lines is electrically isolated from the other sets of electrically conductive lines within, what is in effect, an equipotential tube comprising the substrate on the bottom, the electrically conductive walls on either side and the electrically conductive shield on the top.
- a shielded multi-conductor interconnect bus in accordance with the present invention may be fabricated on a substrate that has one or more intervening layers of electrically conductive material and/or dielectric material between the upper surface of the substrate and the first layer of dielectric material.
- the channels in the first dielectric layer extend vertically down into the first dielectric layer to expose the upper surface of an intervening layer of electrically conductive material, and the intervening layer of electrically conductive material, rather than the substrate, serves as the bottom of the equipotential tube.
- a method for making a shielded multi-conductor interconnect bus begins with the step of removing portions of a first layer of dielectric material (e.g., a dielectric stack comprising a lower thermal oxide layer and an upper silicon nitride layer) overlying and supported by at least a portion of a substrate (e.g., a silicon substrate) to provide a plurality of substantially parallel channels in the first layer of dielectric material.
- a first layer of dielectric material e.g., a dielectric stack comprising a lower thermal oxide layer and an upper silicon nitride layer
- a substrate e.g., a silicon substrate
- the first dielectric layer may be the lowest layer of material deposited on the substrate and sufficient material may be removed so that the channels in the first layer of dielectric material extend vertically downward through the first layer of dielectric material to preferably expose the upper surface of the substrate along at least a portion of each channel, and, more preferably, along the entire length of each channel.
- a first layer of electrically conductive material e.g., doped polysilicon
- strips of the first layer of electrically conductive material are then removed to expose an upper surface of the first layer of dielectric material at the bottom of each strip.
- Removal of the strips provides a plurality of electrically conductive lines on the first layer of dielectric material that typically extend substantially parallel with the channels formed in the first layer of dielectric material.
- the material may be removed from the first dielectric layer and the first electrically conductive layer, respectively, in a pattern wherein one of the channels defined thereby is located between sets of the electrically conductive lines defined thereby, with each set of electrically conductive lines including at least one electrically conductive line.
- a second layer of dielectric material is then deposited over the first layer of electrically conductive material (e.g., a sacrificial material such as silicon dioxide or silicate glass), with the second layer of dielectric material filling in the strips removed from the first layer of electrically conductive material. Portions of the second layer of dielectric material are removed therefrom to provide a plurality of substantially parallel channels in the second layer of dielectric material. The channels in the second layer of dielectric material are located to overlie the filled channels in the first layer of dielectric material, and the channels extend downward through the second layer of dielectric material to expose the first layer of electrically conductive material filling the channels in the first layer of dielectric material.
- a sacrificial material such as silicon dioxide or silicate glass
- a second layer of electrically conductive material (e.g. doped polysilicon) is then deposited in the channels formed in the second layer of dielectric material and over the remaining portions of the second dielectric layer.
- the second layer of electrically conductive material may actually be comprised of two layers of doped polysilicon deposited in several in steps. For example, a thin lower layer of doped polysilicon may be deposited, a layer of sacrificial material may be deposited, the sacrificial material may be removed, and a thicker upper layer of doped polysilicon may then be deposited.
- a shielded multi-conductor interconnect bus includes a substrate.
- a plurality of electrically conductive lines are formed on the substrate, with each electrically conductive line being surrounded by dielectric material along a lengthwise extent of each electrically conductive line.
- An electrically conductive shield overlies and is positioned in a spaced relation above the electrically conductive lines.
- a plurality of electrically conductive walls are also formed on the substrate, with each electrically conductive wall being in contact along a lower section thereof with the substrate and along an upper section thereof with the electrically conductive shield.
- the electrically conductive lines and electrically conductive walls are arranged in pattern wherein one of the electrically conductive walls is located between sets of the electrically conductive lines, with each set of electrically conductive lines including at least one electrically conductive line.
- the substrate is a silicon substrate covered with a dielectric stack (e.g., a lower thermal oxide layer and an upper silicon nitride layer), the electrically conductive lines, walls and shield are comprised of doped polysilicon, and the electrically conductive lines are covered with a sacrificial material (e.g., silicon dioxide or silicate glass).
- a shielded electrically conductive line includes a substrate and a first dielectric layer overlying and supported by at least a portion of the substrate.
- the first dielectric layer may, for example, be the lowest layer of material on the substrate.
- the first dielectric layer is comprised of silicon and the first dielectric layer comprises a dielectric stack deposited directly on an upper surface of the substrate.
- There is one electrically conductive line formed on the first dielectric layer which may be formed from a first layer of doped polysilicon.
- a pair of parallel electrically conductive walls are also formed on the first dielectric layer with each electrically conductive wall being located on an opposing side of the electrically conductive line.
- Each electrically conductive wall includes an upper section extending above the level of the electrically conductive line.
- the lower sections of the electrically conductive walls may also be formed from the first layer of doped polysilicon
- the upper sections of the electrically conductive walls may be formed from a second layer of doped polysilicon, which may itself be comprised of a thinner lower layer of doped polysilicon and a thicker upper layer of doped polysilicon.
- An electrically conductive shield formed, for example, from the second electrically conductive layer is positioned in a spaced relation above the electrically conductive line in contact with the upper sections of the electrically conductive walls.
- the shielded electrically conductive line may be an individual line extending, for example, between a bond pad and a MEM device, or the shielded electrically conductive line may also comprise a transversely oriented electrically conductive line extending from a shielded interconnect bus to connect a line of the shielded interconnect bus with, for example, a desired MEM device.
- FIGS. 1 A-E are cross-sectional views illustrating the microfabrication process of a portion of one embodiment of a shielded multi-conductor interconnect bus in accordance with the present invention
- FIGS. 2 A-B are top views illustrating the microfabrication process of a portion of the shielded multi-conductor interconnect bus shown in FIGS. 1 A-E;
- FIGS. 3 A-B are perspective cross-sectional views of portions of two embodiments of a shielded multi-conductor interconnect bus in accordance with the present invention having enhanced conductive line density;
- FIG. 3C is a perspective cross-sectional view of a portion of an embodiment of a shielded multi-conductor interconnect bus in accordance with the present invention having a single shielded electrically conductive line breaking out from the bus;
- FIG. 3D is a top cross-sectional view of the portion of the shielded multiconductor interconnect bus having a single shielded electrically conductive line breaking out from the bus;
- FIG. 3E is a cross-sectional view of the single shielded electrically conductive line
- FIGS. 4 A-B are perspective cross-sectional and cross-sectional views of a portion of one embodiment of a multi-level shielded multi-conductor interconnect bus in accordance with the present invention.
- FIGS. 4 C-D are perspective cross-sectional and cross-sectional views of a portion of another embodiment of a multi-level shielded multi-conductor interconnect bus in accordance with the present invention.
- FIG. 5A is a perspective cross-sectional view of a portion of an embodiment of a multi-level shielded multi-conductor interconnect bus in accordance with the present invention having staggered conductive lines supported by anchor posts;
- FIGS. 5 B-C are top cross-sectional views of portions of two embodiments of a multi-level shielded multi-conductor interconnect bus in accordance with the present invention having non-staggered conductive lines supported by anchor posts;
- FIG. 6 is a cross-sectional view of an embodiment of a multi-level shielded multi-conductor interconnect bus in accordance with the present invention having three levels of conductive lines;
- FIG. 7 is a top view of an embodiment of a multi-level shielded multi-conductor interconnect bus in accordance with the present invention where upper level conductive lines shift to the lower level.
- FIGS. 1 A-E and FIGS. 2 A-B there are shown cross-sectional and top views, respectively, illustrating the microfabrication process of a portion of one embodiment of a shielded multi-conductor interconnect bus 10 .
- the microfabrication process begins with a substrate 20 having a first dielectric layer 30 formed thereon.
- the substrate 20 may be comprised of silicon
- the first dielectric layer 30 may be comprised of a lower layer 30 A of thermal oxide (e.g., typically about 630 nanometers thick) formed by a wet oxidation process at an elevated temperature (e.g., 1050° C.
- an upper layer 30 B of silicon nitride e.g., typically about 800 nanometers thick
- LPCVD low-pressure chemical vapor deposition
- a plurality of substantially parallel channels 32 are formed in the first dielectric layer 30 .
- the channels 32 may be formed, for example, by a mask and etch removal process employing appropriate masking agents and etchants depending upon the material that is to be removed.
- Each channel 32 preferably extends vertically down through the first dielectric layer 30 to expose the upper surface of the substrate 20 in one or more locations along the length of the channel 32 , and more preferably, along the entire length of the channel 32 .
- FIG. 1A shows a cross-sectional view and FIG. 2A shows a top view after the channels 32 have been formed in the first dielectric layer 30 .
- a first layer of an electrically conductive material (the first electrically conductive layer 40 ) is deposited over the remaining portions of the first dielectric layer 30 and in the channels 32 .
- the first electrically conductive layer 40 is comprised of an electrically conductive material such as, for example, polycrystalline silicon (also termed polysilicon).
- the first electrically conductive layer 40 is also referred to herein as the Poly 0 layer 40 .
- the Poly 0 layer is typically about 300 nanometers thick with subsequent polysilicon layers being thicker (e.g., typically between about 1.0 and 2.5 microns thick).
- the Poly 0 layer 40 (and other polysilicon layers described hereafter) may be deposited using a LPCVD process at a temperature of about 580° C.
- various dopant materials e.g., phosphorous
- a plurality of parallel Poly 0 conductive lines 42 are formed between the filled channels 32 in the first dielectric layer 30 by removing strips 44 from the Poly 0 layer 40 on both sides of each channel 32 in the first dielectric layer 30 .
- the Poly 0 conductive lines 42 are electrically isolated from the substrate 20 along their entire length by the first dielectric layer 30 underneath the Poly 0 conductive lines 42 .
- the Poly 0 material remaining in and above the filled channels 32 forms Poly 0 shield walls 46 between each of the Poly 0 conductive lines 42 .
- the strips 44 removed from the Poly 0 layer 40 extend down to the first dielectric layer 30 along their entire length in order to electrically isolate the Poly 0 conductive lines 42 from the Poly 0 shield walls 46 .
- the strips 44 may be located at a small distance from the sides of each channel 32 in the first dielectric layer 30 so that the Poly 0 shield walls 46 overlap the first dielectric layer 30 by a small amount on either side of each channel 32 . This small overlap allows for alignment tolerance during the fabrication process and ensures that the Poly 0 shield wall 46 completely seals and protects the lower oxide layer 30 A.
- FIG. 1B shows a cross-sectional view and FIG. 2B shows a top view after the strips 44 have been removed from the Poly 0 layer 40 in order to form the Poly 0 conductive lines 42 and Poly 0 shield walls 46 .
- a second dielectric layer 50 is deposited over the Poly 0 layer 40 .
- the second dielectric layer 50 is comprised of an electrically insulating material such as, for example, a sacrificial material (e.g., silicon dioxide or silicate glass).
- the second dielectric layer 50 is also referred to herein as the Sacox 1 layer 50 .
- the Sacox 1 layer 50 (and other sacrificial layers described herein) may be deposited using a LPCVD process at a temperature of about 580° C.
- the Sacox 1 layer 50 (and subsequent sacrificial layers) is typically about 2.0 microns thick.
- the Sacox 1 layer 50 fills in the strips 44 removed from the Poly 0 layer 40 .
- a plurality of channels 52 are then formed in the Sacox 1 layer 50 .
- Each of the channels 52 in the Sacox 1 layer 50 is located and oriented to coincide with a corresponding one of the channels 32 in the first dielectric layer 30 and extends down through the Sacox 1 layer 50 to expose the upper surface of the Poly 0 shield 46 formed in its corresponding channel 32 in the first dielectric layer 30 .
- the upper surface of each Poly 0 shield wall 46 is exposed by the channel 52 in the Sacox 1 layer 50 in one or more locations along its length, and preferably is exposed along the entire length of the Poly 0 shield wall 46 .
- FIG. 1D shows a cross-sectional view after the channels 52 have been formed in the Sacox 1 layer 50 to expose the upper surfaces of the Poly 0 shield walls 46 .
- a second layer of electrically conductive material (the second electrically conductive layer 60 ) is deposited.
- the second electrically conductive layer 60 is comprised of an electrically conductive material such as, for example, doped polysilicon.
- the second electrically conductive layer 60 is also referred to herein as the Poly 1 layer 60 .
- the Poly 1 layer 60 fills the bottom and sidewalls of the channels 52 in the Sacox 1 layer 50 and covers the remaining portions of the Sacox 1 layer 50 .
- a third layer of electrically conductive material (the third electrically conductive layer 70 ) is then deposited over the Poly 1 layer 60 .
- the third electrically conductive layer 70 is comprised of an electrically conductive material such as, for example, doped polysilicon.
- the third electrically conductive layer 70 is also referred to herein as the Poly 2 layer 70 .
- a third dielectric layer (not shown) of sacrificial material may have been deposited over the Poly 1 layer 60 and removed from the regions of the Poly 1 layer 60 of interest to the structures described herein.
- the third dielectric layer may be utilized in maintaining desired separation between the Poly 1 and Poly 2 layers 60 , 70 in other microelectromechanical structures, but such separation is not desired herein.
- the Poly 1 and Poly 2 layers 60 , 70 may be considered to be a single layer of polysilicon material.
- the Poly 2 layer 70 fills in the remainder of the channels 52 made in the Sacox 1 layer 50 to form, together with the Poly 1 layer 60 , Poly 1 /Poly 2 shield walls 66 on top of the Poly 0 shield walls 46 and a horizontal Poly 1 /Poly 2 shield 78 over the Poly 0 conductive lines 42 .
- the Poly 1 /Poly 2 shield 78 is electrically connected to the substrate 20 by the Poly 0 and Poly 1 /Poly 2 shield walls 46 , 66 formed in the channels 32 , 52 in first dielectric layer 30 and the Sacox 1 layer 50 on either side of each Poly 0 conductive line 42 .
- each Poly 0 conductive line 42 is, in effect, surrounded along its lengthwise extent by dielectric material that is in turn encased in an equipotential, electrically conductive tube thereby keeping the various Poly 0 conductive lines 42 electrically isolated from one another.
- Poly 1 /Poly 2 shield 78 also prevents shorting between Poly 0 conductive lines 42 by preventing particles or the like from contacting adjacent Poly 0 conductive lines 42 , as might happen in interconnect buses where the conductive lines are exposed along their lengthwise extent.
- the various polysilicon and sacrificial layers and structures shown are idealized representations of the actual layers and structures that are formed in the various processing steps.
- the corners of various structures e.g., the channels 32 , 52 and strips 44
- layers of material overlying the channels 32 , 52 and strips 44 may, for example, have depressions coinciding with the locations of the channels 32 , 52 and strips 44 instead of being perfectly level across the channels 32 .
- the size of the depressions and other defects, if any, may be reduced through the use of intermediate chemical mechanical polishing steps to planarize the various layers of polysilicon and sacrificial material after they are deposited.
- Enhanced Poly 0 conductive line 42 density is desirable in order to reduce the amount of footprint required for the interconnect bus and thus increase the amount of footprint available for the fabrication of MEM devices on substrate 20 .
- enhanced density may be achieved by grouping sets of Poly 0 conductive lines 42 together between Poly 0 and Poly 1 /Poly 2 shield walls 46 , 66 .
- FIG. 3A shows a cross-sectional view of a portion of a second embodiment of a shielded multi-conductor interconnect bus 310 A wherein the Poly 0 conductive lines 42 are grouped into sets having two conductive lines 42 in each set.
- the Poly 0 and Poly 1 /Poly 2 shield walls 46 , 66 are located between the sets of Poly 0 conductive lines 42 to reduce or eliminate possible cross-talk between the sets of conductive lines 42 .
- Such a shielded multi-conductor interconnect bus 310 A is particularly suited for feeding control signals to MEM mirror positioning systems having two MEM actuators for each positionable mirror because cross-talk between the pair of Poly 0 conductive lines 42 interconnecting the pair of actuators associated with each mirror may be of limited concern.
- each set of Poly 0 conductive lines 42 need not have the same number of Poly 0 conductive lines 42 .
- some sets of Poly 0 conductive lines 42 may have only one Poly 0 conductive line 42 , other sets may have two Poly 0 conductive lines 42 , and other sets may have three or more Poly 0 conductive lines 42 .
- the Sacox 1 layer 50 remains over the Poly 0 conductive lines 42 .
- the Sacox 1 layer 50 may be removed in part or in its entirety (e.g., during subsequent etching of additional layers).
- the possibility that the Poly 1 /Poly 2 shield 78 might come into contact with the Poly 0 conductive lines 42 due to electrostatic attractive forces or capillary forces resulting from wet chemical processing pulling the Poly 1 /Poly 2 shield 78 downward thereby causing a short circuit situation needs to be considered.
- One manner of alleviating this possibility is to limit the lateral spacing between the Poly 0 and Poly 1 /Poly 2 shield walls 46 , 66 that support the Poly 1 /Poly 2 shield 78 above the Poly 0 conductive lines 42 .
- the required lateral spacing depends upon a number of factors, including the flexibility of the Poly 1 /Poly 2 shield 78 and the anticipated voltage difference(s) between the Poly 1 /Poly 2 shield 78 and the Poly 0 conductive lines 42 .
- the Poly 0 and Poly 1 /Poly 2 shield walls 46 , 66 are preferably laterally spaced no more than 10 to 20 microns apart, although several times this distance (e.g., 50 microns) is possible under the right conditions. This assumes that the Poly 1 /Poly 2 shield is approximately 2.5 microns thick and the anticipated voltage difference between the Poly 0 conductive lines and the Poly 1 /Poly 2 shield is less than 300V.
- FIGS. 3 C-D there is shown a portion of an embodiment of a shielded multi-conductor interconnect bus 310 C having multiple Poly 0 conductive lines 42 grouped into sets between the Poly 0 and Poly 1 /Poly 2 shield walls 46 , 66 , with one of the Poly 0 conductive lines 42 breaking away from the bus 310 C.
- outer Poly 0 conductive line 42 A may, for example, be broken away from the bus 310 C to connect it to a bond pad, MEM actuator, or other MEM structure to which Poly 0 conductive line 42 A feeds electrical signals.
- FIG. 3E shows a cross-sectional view of the single shielded Poly 0 conductive line 42 A that is broken out of the bus 310 C.
- conductive lines may break away from any of the shielded interconnect buses described herein in a similar manner. Further, it will be appreciated that multiple conductive lines may break away from a shielded interconnect bus, either individually or as a group between one pair of conductive shield walls.
- FIGS. 4 A-D in addition to grouping conductive lines into sets, the density of conductive lines can also be increased by adding additional layers of conductive lines.
- FIGS. 4 A-B show perspective cross-sectional and cross-sectional views of a portion of one embodiment of a multi-level shielded multi-conductor interconnect bus 410 A that has two levels of conductive lines.
- the multi-level shielded multi-conductor interconnect bus 410 A includes a fourth dielectric layer 80 overlying the Poly 2 layer 70 .
- the fourth dielectric layer 80 is comprised of an electrically insulating material such as, for example, a sacrificial material (e.g. silicon dioxide or silicate glass).
- the fourth dielectric layer 80 is also referred to herein as the Sacox 3 layer 80 .
- Parallel channels 82 are formed in the Sacox 3 layer 80 .
- the channels 82 in the Sacox 3 layer 80 extend vertically down through the Sacox 3 layer to expose the upper surface of the Poly 2 layer 70 in one or more locations along the length of the channels 82 , and preferably expose the upper surface of the Poly 2 layer 70 along the entire length of each channel 82 .
- a fourth layer of an electrically conductive material (the fourth electrically conductive layer 90 ) is formed over the Sacox 3 layer 80 .
- the electrically conductive material comprising the fourth electrically conductive layer 90 is, for example, doped polysilicon.
- the fourth electrically conductive layer 90 is also referred to herein as the Poly 3 layer 90 .
- the Poly 3 layer 90 fills in the channels 82 in the Sacox 3 layer 80 .
- Poly 3 conductive lines 92 and shield walls 96 are provided by removing strips 94 from the Poly 3 layer 90 on each side of the channels 82 in the Sacox 3 layer 80 .
- a fifth dielectric layer 100 comprised of for example, a sacrificial material (e.g.
- the fifth dielectric layer 100 is also referred to herein as the Sacox 4 layer 100 .
- Channels 102 aligned over the Poly 3 shield walls 96 are formed in the Sacox 4 layer 100 to expose the upper surfaces of the Poly 3 shield walls 96 along at least portions of, and preferably their entire, length.
- a fifth electrically conductive layer 110 (also referred to herein as the Poly 4 layer 110 ), comprised of, for example, doped polysilicon is deposited over the Sacox 4 layer 100 and into the channels 102 in the Sacox 4 layer 100 to provide a horizontal Poly 4 shield 118 over the Poly 3 conductive lines.
- the upper level Poly 3 conductive lines 92 and shield walls 96 are oriented in the same direction as the lower level Poly 0 conductive lines 42 and shield walls 46 . However, it is also possible to orient the upper level Poly 3 conductive lines 92 and shield walls 96 transverse to the lower level Poly 0 conductive lines 42 and shield walls 46 .
- FIGS. 1-10 illustrate the multi-level shielded multi-conductor interconnect bus 410 A of FIGS. 4 A-B.
- FIGS. 4 C-D show perspective cross-sectional and cross-sectional views of a portion of a second embodiment of a multi-level shielded multi-conductor interconnect bus 410 B that has two levels of conductive lines 42 , 92 , with the upper level conductive lines 92 being oriented transverse to the lower level conductive lines 42 .
- the Sacox 3 and Sacox 4 layers 80 , 100 remain around the Poly 3 conductive lines 92 to support the second level Poly 3 conductive lines 92 above the Poly 2 layer 70 and prevent electrostatic or capillary attractive forces from pulling the Poly 3 conductive lines 92 downward into contact with the Poly 2 layer 70 , upward into contact with the Poly 4 layer 110 , or sideways into contact with the Poly 3 shield walls 96 on either side thereof.
- etch release holes may be formed in the various polysilicon layers 40 , 70 , 90 , 110 in order to allow for the removal of isolated or encapsulated sacrificial material where desired.
- the possibility of undesirable contact between the Poly 3 conductive lines 92 and either the Poly 2 layer 70 , the Poly 3 shield walls 96 , or the Poly 4 layer 110 can be alleviated by periodically anchoring the Poly 3 conductive lines 92 along their length.
- FIG. 5A shows an embodiment of a multi-level shielded multi-conductor interconnect bus 510 A wherein anchor posts 120 are periodically spaced along the length of the Poly 3 conductive lines 92 .
- the anchor posts 120 extend downward through appropriately sized holes formed in the Poly 2 layer 70 (and the Sacox 1 layer 50 if it has not also been removed) and rest on top of the first dielectric layer 30 without contacting the lower level Poly 0 conductive lines 42 .
- the lower level Poly 0 conductive lines 42 and upper level Poly 3 conductive lines 92 are staggered so that there is adequate space between adjacent Poly 0 conductive lines 42 to accommodate the anchor posts 120 therebetween that support each upper level Poly 3 conductive line 42 .
- isolated pads of Poly 0 layer 40 material that are slightly larger than the cross-sectional area of the anchor posts 120 will typically be fabricated beneath the anchor posts 120 .
- the Poly 0 conductive lines 42 can also be configured to have appropriately sized holes formed therethrough that accommodate the anchor posts 120 .
- FIG. 5B shows a top cross-sectional view of a multi-level shielded multi-conductor interconnect bus 510 B taken at the interface between the Poly 0 layer 40 and the Sacox 1 layer 50 wherein the Poly 0 conductive lines 42 are configured to have donut-like sections in order to provide holes therethrough for the anchor posts 120 .
- FIG. 5C shows a top cross-sectional view of a multi-level shielded multi-conductor interconnect bus 510 C taken at the interface between the Poly 0 layer 40 and the Sacox 1 layer 50 wherein the Poly 0 conductive lines 42 are configured to have lateral jogs at various locations along their lengthwise extent in order to accommodate the anchor posts 120 .
- FIG. 6 shows a multi-level shielded multi-conductor interconnect bus 610 having three levels of conductive lines.
- the multi-level shielded multi-conductor interconnect bus 610 includes Poly 0 conductive lines 42 , Poly 2 conductive lines 72 , and Poly 3 conductive lines 92 and a Poly 4 shield 118 over the three level Poly 0 , Poly 2 , and Poly 3 conductive lines 42 , 72 , 92 .
- the Sacox 1 , Sacox 3 and Sacox 4 layers 50 , 80 , 100 remain around the conductive lines 42 , 72 , 92 in order to support the conductive lines 42 , 72 , 92 and prevent undesired movement of the conductive lines 42 , 72 , 92 due to electrostatic attractive forces.
- the conductive lines 42 , 72 , 92 may also be grouped at each level into sets between the Poly 0 , Poly 1 , Poly 2 and Poly 3 shield walls 46 , 66 , 76 , 96 (e.g., sets of two conductive lines 42 , 72 , 92 each as in shown in FIG. 6).
- the number of conductive lines 42 , 72 , 92 in each set need not be the same across the same level or at different levels.
- Shifting the upper level conductive lines 72 , 92 down to the Poly 0 level may be necessary because where the conductive lines 72 , 92 exit their shielding, the Sacox 1 , Sacox 3 and Sacox 4 layers 50 , 80 , 100 supporting the conductive lines 72 , 92 may be etched away, and thus unless the upper level conductive lines 72 , 92 are supported at their endpoints, the upper level conductive lines 72 , 92 will be cantilevered over the substrate 20 near their endpoints and thus inherently weak.
- FIG. 7 One manner of getting the upper level conductive lines 72 , 92 down to the Poly 0 level is shown in FIG. 7.
- FIG. 7 there is shown a top view of a two-level shielded multi-conductor interconnect bus 710 (with the Poly 4 shield 118 represented by the dotted line box) having Poly 0 conductive lines 42 and Poly 3 conductive lines 72 , with the Poly 0 and Poly 3 conductive lines 42 , 72 being staggered.
- the technique illustrated in FIG. 7 can also be applied to shift down Poly 4 conductive lines 92 where the conductive lines 42 , 72 , 92 are appropriately staggered. As is shown in FIG.
- an anchor 120 is formed that extends between the Poly 3 conductive line 72 and the level of the Poly 0 layer 40 where the conductive line 72 is continued at the Poly 0 level to a corresponding bond pad 130 or MEM device.
- the anchor posts 120 that shift the Poly 3 conductive lines 72 down to the Poly 0 layer 40 are preferably formed at a sufficient distance back from where the Poly 3 conductive lines 72 exit from under the Poly 4 shield 118 in order to ensure that enough sacrificial material remains around the Poly 3 conductive lines 72 beyond the anchor post 120 to provide adequate support of the Poly 3 conductive lines 72 .
Abstract
A shielded multi-conductor interconnect bus for use in interconnecting MEM devices with control signal sources or the like and a method of fabricating a shielded multi-conductor interconnect bus are disclosed. In one embodiment, a shielded interconnect bus formed on a substrate (20) includes a plurality of electrically conductive lines (42) arranged in sets of one, two or more conductive lines between electrically conductive shield walls (46, 66). The electrically conductive lines (42) are surrounded by layers of dielectric material (30, 50). An electrically conductive shield (78) overlies the electrically conductive lines (42) and electrically conductive shield walls (46, 66).
Description
- This application is a divisional of and claims priority from U.S. patent application Ser. No. 10/099,724, filed on Mar. 15, 2002, and entitled “SHIELDED MULTI-CONDUCTOR INTERCONNECT BUS FOR MEMS”, the entire disclosure of which is incorporated by reference in its entirety herein.
- The present invention relates generally to microelectromechanical systems (MEMS), and more particularly to the design and fabrication of interconnect architectures for MEMS.
- MEMS can include numerous electromechanical devices fabricated on a single substrate, many of which are to be separately actuated in order to achieve a desired operation. For example, a MEMS optical switch may include numerous mirrors that are each positionable in a desired orientation for reflecting optical signals between originating and target locations upon actuation of one or more microactuators associated with each mirror. In order for each mirror to be separately positioned, separate control signals need to be supplied to the microactuators associated with each mirror. One manner of accomplishing this is to connect each microactuator to a control signal source with a separate electrical conductor (i.e., an interconnect line) fabricated on the surface of the substrate that extends between its associated microactuator and a bond pad at the periphery of the substrate where it can be easily connected to an off-chip control signal source. In this regard, the separate interconnect lines together comprise an interconnect bus and are typically arranged to run parallel with each other for substantial portions of their length.
- As may be appreciated, the amount of footprint required on the surface of the substrate for an interconnect bus is an important factor in designing MEMS since increasing the footprint of the interconnect bus decreases the amount of footprint available for desired devices (e.g., mirrors and actuators). Another consideration is possible cross-talk between the separate interconnect lines. Cross-talk is a problem because a control signal intended for one actuator can be coupled from its interconnect line into adjacent interconnect lines causing undesired actuation of other actuators. A further consideration is the possibility of shorting between adjacent interconnect lines. Where the interconnect bus lines are exposed on the surface of the substrate, particles and the like can settle across adjacent interconnect lines thereby causing short circuits effecting operation of the MEMS.
- Accordingly, the present invention provides a shielded multi-conductor interconnect bus for MEMS and a method for fabricating such an interconnect bus. The shielded multi-conductor interconnect bus of the present invention substantially reduces the possibility of cross-talk between adjacent interconnect lines, alleviates the possibility of short circuits due to particles and the like settling across adjacent interconnect lines, and optimizes the amount of footprint required for such an interconnect bus.
- According to one aspect of the present invention, a shielded multi-conductor interconnect bus includes a substrate. The substrate may, for example, be comprised of silicon. A first dielectric layer overlies and is supported by at least a portion of the substrate. In this regard, the first dielectric layer may, for example, be the lowest layer of material on the substrate (i.e., it may be formed directly on the upper surface of the substrate without any intervening layers). In one embodiment, the substrate is comprised of silicon and the first dielectric layer comprises a dielectric stack deposited directly on the upper surface of the substrate that includes a lower thermal oxide layer and an upper silicon nitride layer. A plurality of substantially parallel electrically conductive lines are formed on the first dielectric layer. In this regard, the electrically conductive lines may be formed from a first layer of doped polysilicon.
- The interconnect bus also includes a plurality of substantially parallel electrically conductive walls formed on the first dielectric layer. Although desirable, it should be understood that electrically conductive walls described herein do not have to be continuous along their lengthwise extent and may, in fact, have one or more breaks formed therein as desired. Each electrically conductive wall includes an upper section that extends vertically above the level of the electrically conductive lines. There may also be a plurality of substantially parallel channels formed in the first dielectric layer with lower sections of the electrically conductive walls being formed in the channels. In this regard, the lower sections of the electrically conductive walls may be formed from the first layer of doped polysilicon and the upper sections of the electrically conductive walls may be formed from a second layer of doped polysilicon. The second layer of doped polysilicon may be comprised of a thinner lower layer of doped polysilicon and a thicker upper layer of doped polysilicon. Where the first dielectric layer is the lowest layer of material on the substrate, each channel preferably extends vertically downward through the entire thickness of the first dielectric layer to expose the upper surface of the substrate along at least a portion of each channel, and, more preferably, along the entire length of each channel.
- The electrically conductive lines and electrically conductive walls are arranged in pattern such that an electrically conductive wall is located between adjacent sets of the electrically conductive lines. In this regard, each set of electrically conductive lines includes at least one of the electrically conductive lines, and may include two or more electrically conductive lines.
- In addition to separating adjacent sets of electrically conductive lines, the electrically conductive walls also contact the underside of an electrically conductive shield positioned in a spaced relation above the electrically conductive lines. The electrically conductive shield may be formed from the second layer of doped polysilicon. In one embodiment, there is a second dielectric layer beneath the electrically conductive shield overlying the electrically conductive lines and the first dielectric layer. The second dielectric layer may be comprised of a sacrificial material (e.g., silicon dioxide or silicate glass). The second dielectric layer includes a plurality of channels formed therein permitting the upper sections of the electrically conductive walls to extend vertically upward therethrough to contact the underside of the electrically conductive shield. Thus, each electrically conductive line is surrounded by dielectric material, and each set of electrically conductive lines is electrically isolated from the other sets of electrically conductive lines within, what is in effect, an equipotential tube comprising the substrate on the bottom, the electrically conductive walls on either side and the electrically conductive shield on the top.
- It should be noted that a shielded multi-conductor interconnect bus in accordance with the present invention may be fabricated on a substrate that has one or more intervening layers of electrically conductive material and/or dielectric material between the upper surface of the substrate and the first layer of dielectric material. In this regard, the channels in the first dielectric layer extend vertically down into the first dielectric layer to expose the upper surface of an intervening layer of electrically conductive material, and the intervening layer of electrically conductive material, rather than the substrate, serves as the bottom of the equipotential tube.
- According to another aspect of the present invention, a method for making a shielded multi-conductor interconnect bus begins with the step of removing portions of a first layer of dielectric material (e.g., a dielectric stack comprising a lower thermal oxide layer and an upper silicon nitride layer) overlying and supported by at least a portion of a substrate (e.g., a silicon substrate) to provide a plurality of substantially parallel channels in the first layer of dielectric material. In this regard, the first dielectric layer may be the lowest layer of material deposited on the substrate and sufficient material may be removed so that the channels in the first layer of dielectric material extend vertically downward through the first layer of dielectric material to preferably expose the upper surface of the substrate along at least a portion of each channel, and, more preferably, along the entire length of each channel. A first layer of electrically conductive material (e.g., doped polysilicon) is then deposited over the first layer of dielectric material, with the first layer of electrically conductive material filling the channels formed in the first layer of dielectric material. Strips of the first layer of electrically conductive material are then removed to expose an upper surface of the first layer of dielectric material at the bottom of each strip. Removal of the strips provides a plurality of electrically conductive lines on the first layer of dielectric material that typically extend substantially parallel with the channels formed in the first layer of dielectric material. In this regard, the material may be removed from the first dielectric layer and the first electrically conductive layer, respectively, in a pattern wherein one of the channels defined thereby is located between sets of the electrically conductive lines defined thereby, with each set of electrically conductive lines including at least one electrically conductive line.
- After the electrically conductive lines are formed, a second layer of dielectric material is then deposited over the first layer of electrically conductive material (e.g., a sacrificial material such as silicon dioxide or silicate glass), with the second layer of dielectric material filling in the strips removed from the first layer of electrically conductive material. Portions of the second layer of dielectric material are removed therefrom to provide a plurality of substantially parallel channels in the second layer of dielectric material. The channels in the second layer of dielectric material are located to overlie the filled channels in the first layer of dielectric material, and the channels extend downward through the second layer of dielectric material to expose the first layer of electrically conductive material filling the channels in the first layer of dielectric material. A second layer of electrically conductive material (e.g. doped polysilicon) is then deposited in the channels formed in the second layer of dielectric material and over the remaining portions of the second dielectric layer. In some fabrication processes, the second layer of electrically conductive material may actually be comprised of two layers of doped polysilicon deposited in several in steps. For example, a thin lower layer of doped polysilicon may be deposited, a layer of sacrificial material may be deposited, the sacrificial material may be removed, and a thicker upper layer of doped polysilicon may then be deposited.
- According to a further aspect of the present invention, a shielded multi-conductor interconnect bus includes a substrate. A plurality of electrically conductive lines are formed on the substrate, with each electrically conductive line being surrounded by dielectric material along a lengthwise extent of each electrically conductive line. An electrically conductive shield overlies and is positioned in a spaced relation above the electrically conductive lines. A plurality of electrically conductive walls are also formed on the substrate, with each electrically conductive wall being in contact along a lower section thereof with the substrate and along an upper section thereof with the electrically conductive shield. The electrically conductive lines and electrically conductive walls are arranged in pattern wherein one of the electrically conductive walls is located between sets of the electrically conductive lines, with each set of electrically conductive lines including at least one electrically conductive line. In one embodiment, the substrate is a silicon substrate covered with a dielectric stack (e.g., a lower thermal oxide layer and an upper silicon nitride layer), the electrically conductive lines, walls and shield are comprised of doped polysilicon, and the electrically conductive lines are covered with a sacrificial material (e.g., silicon dioxide or silicate glass).
- According to one more aspect of the present invention, a shielded electrically conductive line includes a substrate and a first dielectric layer overlying and supported by at least a portion of the substrate. In this regard, the first dielectric layer may, for example, be the lowest layer of material on the substrate. In one embodiment, the first dielectric layer is comprised of silicon and the first dielectric layer comprises a dielectric stack deposited directly on an upper surface of the substrate. There is one electrically conductive line formed on the first dielectric layer, which may be formed from a first layer of doped polysilicon. A pair of parallel electrically conductive walls are also formed on the first dielectric layer with each electrically conductive wall being located on an opposing side of the electrically conductive line. Each electrically conductive wall includes an upper section extending above the level of the electrically conductive line. There may also be a pair of channels formed in the first dielectric layer, with lower sections of the electrically conductive walls formed in the channels. In this regard, the lower sections of the electrically conductive walls may also be formed from the first layer of doped polysilicon, and the upper sections of the electrically conductive walls may be formed from a second layer of doped polysilicon, which may itself be comprised of a thinner lower layer of doped polysilicon and a thicker upper layer of doped polysilicon. An electrically conductive shield formed, for example, from the second electrically conductive layer is positioned in a spaced relation above the electrically conductive line in contact with the upper sections of the electrically conductive walls. The shielded electrically conductive line may be an individual line extending, for example, between a bond pad and a MEM device, or the shielded electrically conductive line may also comprise a transversely oriented electrically conductive line extending from a shielded interconnect bus to connect a line of the shielded interconnect bus with, for example, a desired MEM device.
- These and other aspects and advantages of the present invention will be apparent upon review of the following Detailed Description when taken in conjunction with the accompanying figures.
- For a more complete understanding of the present invention and further advantages thereof, reference is now made to the following Detailed Description, taken in conjunction with the drawings, in which:
- FIGS.1A-E are cross-sectional views illustrating the microfabrication process of a portion of one embodiment of a shielded multi-conductor interconnect bus in accordance with the present invention;
- FIGS.2A-B are top views illustrating the microfabrication process of a portion of the shielded multi-conductor interconnect bus shown in FIGS. 1A-E;
- FIGS.3A-B are perspective cross-sectional views of portions of two embodiments of a shielded multi-conductor interconnect bus in accordance with the present invention having enhanced conductive line density;
- FIG. 3C is a perspective cross-sectional view of a portion of an embodiment of a shielded multi-conductor interconnect bus in accordance with the present invention having a single shielded electrically conductive line breaking out from the bus;
- FIG. 3D is a top cross-sectional view of the portion of the shielded multiconductor interconnect bus having a single shielded electrically conductive line breaking out from the bus;
- FIG. 3E is a cross-sectional view of the single shielded electrically conductive line;
- FIGS.4A-B are perspective cross-sectional and cross-sectional views of a portion of one embodiment of a multi-level shielded multi-conductor interconnect bus in accordance with the present invention;
- FIGS.4C-D are perspective cross-sectional and cross-sectional views of a portion of another embodiment of a multi-level shielded multi-conductor interconnect bus in accordance with the present invention;
- FIG. 5A is a perspective cross-sectional view of a portion of an embodiment of a multi-level shielded multi-conductor interconnect bus in accordance with the present invention having staggered conductive lines supported by anchor posts;
- FIGS.5B-C are top cross-sectional views of portions of two embodiments of a multi-level shielded multi-conductor interconnect bus in accordance with the present invention having non-staggered conductive lines supported by anchor posts;
- FIG. 6 is a cross-sectional view of an embodiment of a multi-level shielded multi-conductor interconnect bus in accordance with the present invention having three levels of conductive lines; and
- FIG. 7 is a top view of an embodiment of a multi-level shielded multi-conductor interconnect bus in accordance with the present invention where upper level conductive lines shift to the lower level.
- Referring to FIGS.1A-E and FIGS. 2A-B, there are shown cross-sectional and top views, respectively, illustrating the microfabrication process of a portion of one embodiment of a shielded
multi-conductor interconnect bus 10. The microfabrication process begins with asubstrate 20 having afirst dielectric layer 30 formed thereon. In this regard, thesubstrate 20 may be comprised of silicon, and thefirst dielectric layer 30 may be comprised of alower layer 30A of thermal oxide (e.g., typically about 630 nanometers thick) formed by a wet oxidation process at an elevated temperature (e.g., 1050° C. for about 1.5 hours) and anupper layer 30B of silicon nitride (e.g., typically about 800 nanometers thick) deposited over the thermal oxide layer using a low-pressure chemical vapor deposition (LPCVD) process at a temperature of about 850° C. - A plurality of substantially
parallel channels 32 are formed in thefirst dielectric layer 30. Thechannels 32, as with other features of the shieldedmulti-conductor interconnect bus 10 wherein material is removed from one or more layers of material, may be formed, for example, by a mask and etch removal process employing appropriate masking agents and etchants depending upon the material that is to be removed. Eachchannel 32 preferably extends vertically down through thefirst dielectric layer 30 to expose the upper surface of thesubstrate 20 in one or more locations along the length of thechannel 32, and more preferably, along the entire length of thechannel 32. FIG. 1A shows a cross-sectional view and FIG. 2A shows a top view after thechannels 32 have been formed in thefirst dielectric layer 30. - After the
channels 32 in thefirst dielectric layer 30 are formed, a first layer of an electrically conductive material (the first electrically conductive layer 40) is deposited over the remaining portions of thefirst dielectric layer 30 and in thechannels 32. The first electricallyconductive layer 40 is comprised of an electrically conductive material such as, for example, polycrystalline silicon (also termed polysilicon). In this regard, the first electricallyconductive layer 40 is also referred to herein as thePoly0 layer 40. The Poly0 layer is typically about 300 nanometers thick with subsequent polysilicon layers being thicker (e.g., typically between about 1.0 and 2.5 microns thick). The Poly0 layer 40 (and other polysilicon layers described hereafter) may be deposited using a LPCVD process at a temperature of about 580° C. In depositing the Poly0 layer (and other polysilicon layers described hereafter), various dopant materials (e.g., phosphorous) can be employed to make the polysilicon electrically conductive. - After the
Poly0 layer 40 is deposited, a plurality of parallel Poly0conductive lines 42 are formed between the filledchannels 32 in thefirst dielectric layer 30 by removingstrips 44 from thePoly0 layer 40 on both sides of eachchannel 32 in thefirst dielectric layer 30. The Poly0conductive lines 42 are electrically isolated from thesubstrate 20 along their entire length by thefirst dielectric layer 30 underneath the Poly0conductive lines 42. The Poly0 material remaining in and above the filledchannels 32 formsPoly0 shield walls 46 between each of the Poly0conductive lines 42. Thestrips 44 removed from thePoly0 layer 40 extend down to thefirst dielectric layer 30 along their entire length in order to electrically isolate the Poly0conductive lines 42 from thePoly0 shield walls 46. Thestrips 44 may be located at a small distance from the sides of eachchannel 32 in thefirst dielectric layer 30 so that thePoly0 shield walls 46 overlap thefirst dielectric layer 30 by a small amount on either side of eachchannel 32. This small overlap allows for alignment tolerance during the fabrication process and ensures that thePoly0 shield wall 46 completely seals and protects thelower oxide layer 30A. FIG. 1B shows a cross-sectional view and FIG. 2B shows a top view after thestrips 44 have been removed from thePoly0 layer 40 in order to form the Poly0conductive lines 42 andPoly0 shield walls 46. - After the Poly0
conductive lines 42 andPoly0 shield walls 46 are formed in thePoly0 layer 40, asecond dielectric layer 50 is deposited over thePoly0 layer 40. Thesecond dielectric layer 50 is comprised of an electrically insulating material such as, for example, a sacrificial material (e.g., silicon dioxide or silicate glass). In this regard, thesecond dielectric layer 50 is also referred to herein as theSacox1 layer 50. The Sacox1 layer 50 (and other sacrificial layers described herein) may be deposited using a LPCVD process at a temperature of about 580° C. The Sacox1 layer 50 (and subsequent sacrificial layers) is typically about 2.0 microns thick. TheSacox1 layer 50 fills in thestrips 44 removed from thePoly0 layer 40. A plurality ofchannels 52 are then formed in theSacox1 layer 50. Each of thechannels 52 in theSacox1 layer 50 is located and oriented to coincide with a corresponding one of thechannels 32 in thefirst dielectric layer 30 and extends down through theSacox1 layer 50 to expose the upper surface of thePoly0 shield 46 formed in its correspondingchannel 32 in thefirst dielectric layer 30. The upper surface of eachPoly0 shield wall 46 is exposed by thechannel 52 in theSacox1 layer 50 in one or more locations along its length, and preferably is exposed along the entire length of thePoly0 shield wall 46. FIG. 1D shows a cross-sectional view after thechannels 52 have been formed in theSacox1 layer 50 to expose the upper surfaces of thePoly0 shield walls 46. - After the
channels 52 are formed in theSacox1 layer 50, a second layer of electrically conductive material (the second electrically conductive layer 60) is deposited. The second electricallyconductive layer 60 is comprised of an electrically conductive material such as, for example, doped polysilicon. In this regard, the second electricallyconductive layer 60 is also referred to herein as thePoly1 layer 60. ThePoly1 layer 60 fills the bottom and sidewalls of thechannels 52 in theSacox1 layer 50 and covers the remaining portions of theSacox1 layer 50. - A third layer of electrically conductive material (the third electrically conductive layer70) is then deposited over the
Poly1 layer 60. The third electricallyconductive layer 70 is comprised of an electrically conductive material such as, for example, doped polysilicon. In this regard, the third electricallyconductive layer 70 is also referred to herein as thePoly2 layer 70. Prior to depositing thePoly2 layer 70 over thePoly1 layer 60, a third dielectric layer (not shown) of sacrificial material may have been deposited over thePoly1 layer 60 and removed from the regions of thePoly1 layer 60 of interest to the structures described herein. The third dielectric layer (the Sacox2 layer) may be utilized in maintaining desired separation between the Poly1 and Poly2 layers 60, 70 in other microelectromechanical structures, but such separation is not desired herein. In this regard, the Poly1 and Poly2 layers 60, 70 may be considered to be a single layer of polysilicon material. ThePoly2 layer 70 fills in the remainder of thechannels 52 made in theSacox1 layer 50 to form, together with thePoly1 layer 60, Poly1/Poly2 shield walls 66 on top of thePoly0 shield walls 46 and a horizontal Poly1/Poly2 shield 78 over the Poly0conductive lines 42. - The Poly1/
Poly2 shield 78 is electrically connected to thesubstrate 20 by the Poly0 and Poly1/Poly2 shield walls channels first dielectric layer 30 and theSacox1 layer 50 on either side of each Poly0conductive line 42. Thus, each Poly0conductive line 42 is, in effect, surrounded along its lengthwise extent by dielectric material that is in turn encased in an equipotential, electrically conductive tube thereby keeping the various Poly0conductive lines 42 electrically isolated from one another. Additionally, the Poly1/Poly2 shield 78 also prevents shorting between Poly0conductive lines 42 by preventing particles or the like from contacting adjacent Poly0conductive lines 42, as might happen in interconnect buses where the conductive lines are exposed along their lengthwise extent. - It should be noted that in the figures described herein, the various polysilicon and sacrificial layers and structures shown are idealized representations of the actual layers and structures that are formed in the various processing steps. In this regard, the corners of various structures (e.g., the
channels channels channels channels 32. The size of the depressions and other defects, if any, may be reduced through the use of intermediate chemical mechanical polishing steps to planarize the various layers of polysilicon and sacrificial material after they are deposited. - Referring now to FIGS.3A-B, it is possible to increase the density of the shielded
multi-conductor interconnect bus 10 while maintaining the same width Poly0conductive lines 42 and Poly0 and Poly1/Poly2 shield walls conductive line 42 density is desirable in order to reduce the amount of footprint required for the interconnect bus and thus increase the amount of footprint available for the fabrication of MEM devices onsubstrate 20. When the possibility of cross-talk between some of the Poly0conductive lines 42 is not a significant concern, enhanced density may be achieved by grouping sets of Poly0conductive lines 42 together between Poly0 and Poly1/Poly2 shield walls multi-conductor interconnect bus 310A wherein the Poly0conductive lines 42 are grouped into sets having twoconductive lines 42 in each set. The Poly0 and Poly1/Poly2 shield walls conductive lines 42 to reduce or eliminate possible cross-talk between the sets ofconductive lines 42. Such a shieldedmulti-conductor interconnect bus 310A is particularly suited for feeding control signals to MEM mirror positioning systems having two MEM actuators for each positionable mirror because cross-talk between the pair of Poly0conductive lines 42 interconnecting the pair of actuators associated with each mirror may be of limited concern. It should be noted that in other embodiments, each set of Poly0conductive lines 42 need not have the same number of Poly0conductive lines 42. For example, as is illustrated in the cross-sectional view of FIG. 3B, some sets of Poly0conductive lines 42 may have only one Poly0conductive line 42, other sets may have two Poly0conductive lines 42, and other sets may have three or more Poly0conductive lines 42. - In the previously described embodiments of the shielded
multi-conductor interconnect bus Sacox1 layer 50 remains over the Poly0conductive lines 42. In some cases, theSacox1 layer 50 may be removed in part or in its entirety (e.g., during subsequent etching of additional layers). In such situations, the possibility that the Poly1/Poly2 shield 78 might come into contact with the Poly0conductive lines 42 due to electrostatic attractive forces or capillary forces resulting from wet chemical processing pulling the Poly1/Poly2 shield 78 downward thereby causing a short circuit situation needs to be considered. One manner of alleviating this possibility is to limit the lateral spacing between the Poly0 and Poly1/Poly2 shield walls Poly2 shield 78 above the Poly0conductive lines 42. The required lateral spacing depends upon a number of factors, including the flexibility of the Poly1/Poly2 shield 78 and the anticipated voltage difference(s) between the Poly1/Poly2 shield 78 and the Poly0conductive lines 42. In this regard, the Poly0 and Poly1/Poly2 shield walls - Referring now to FIGS.3C-D, there is shown a portion of an embodiment of a shielded
multi-conductor interconnect bus 310C having multiple Poly0conductive lines 42 grouped into sets between the Poly0 and Poly1/Poly2 shield walls conductive lines 42 breaking away from thebus 310C. In this regard, outer Poly0conductive line 42A may, for example, be broken away from thebus 310C to connect it to a bond pad, MEM actuator, or other MEM structure to which Poly0conductive line 42A feeds electrical signals. FIG. 3E shows a cross-sectional view of the single shielded Poly0conductive line 42A that is broken out of thebus 310C. - In order to allow Poly0
conductive line 42A to break transversely away from thebus 310C, there is a break formed in the outer Poly0 and Poly1/Poly2 shield walls conductive line 42A, the outer Poly0 and Poly1/Poly2 shield walls conductive line 42A. The Poly1/Poly2 shield 78 is likewise continued over the Poly0conductive line 42A, supported in a spaced relation above the Poly0conductive line 42A by the Poly0 and Poly1/Poly2 shield walls - Referring now to FIGS.4A-D, in addition to grouping conductive lines into sets, the density of conductive lines can also be increased by adding additional layers of conductive lines. FIGS. 4A-B show perspective cross-sectional and cross-sectional views of a portion of one embodiment of a multi-level shielded
multi-conductor interconnect bus 410A that has two levels of conductive lines. The multi-level shieldedmulti-conductor interconnect bus 410A includes afourth dielectric layer 80 overlying thePoly2 layer 70. Thefourth dielectric layer 80 is comprised of an electrically insulating material such as, for example, a sacrificial material (e.g. silicon dioxide or silicate glass). In this regard, thefourth dielectric layer 80 is also referred to herein as theSacox3 layer 80.Parallel channels 82 are formed in theSacox3 layer 80. Thechannels 82 in theSacox3 layer 80 extend vertically down through the Sacox3 layer to expose the upper surface of thePoly2 layer 70 in one or more locations along the length of thechannels 82, and preferably expose the upper surface of thePoly2 layer 70 along the entire length of eachchannel 82. - A fourth layer of an electrically conductive material (the fourth electrically conductive layer90) is formed over the
Sacox3 layer 80. The electrically conductive material comprising the fourth electricallyconductive layer 90 is, for example, doped polysilicon. In this regard, the fourth electricallyconductive layer 90 is also referred to herein as thePoly3 layer 90. ThePoly3 layer 90 fills in thechannels 82 in theSacox3 layer 80. Poly3conductive lines 92 andshield walls 96 are provided by removingstrips 94 from thePoly3 layer 90 on each side of thechannels 82 in theSacox3 layer 80. Afifth dielectric layer 100 comprised of for example, a sacrificial material (e.g. silicon dioxide or silicate glass), is formed over the Poly3conductive lines 92 andshield walls 96. Thefifth dielectric layer 100 is also referred to herein as theSacox4 layer 100.Channels 102 aligned over thePoly3 shield walls 96 are formed in theSacox4 layer 100 to expose the upper surfaces of thePoly3 shield walls 96 along at least portions of, and preferably their entire, length. A fifth electrically conductive layer 110 (also referred to herein as the Poly4 layer 110), comprised of, for example, doped polysilicon is deposited over theSacox4 layer 100 and into thechannels 102 in theSacox4 layer 100 to provide ahorizontal Poly4 shield 118 over the Poly3 conductive lines. - In the multi-level shielded
multi-conductor interconnect bus 410A of FIGS. 4A-B, the upper level Poly3conductive lines 92 andshield walls 96 are oriented in the same direction as the lower level Poly0conductive lines 42 andshield walls 46. However, it is also possible to orient the upper level Poly3conductive lines 92 andshield walls 96 transverse to the lower level Poly0conductive lines 42 andshield walls 46. FIGS. 4C-D show perspective cross-sectional and cross-sectional views of a portion of a second embodiment of a multi-level shieldedmulti-conductor interconnect bus 410B that has two levels ofconductive lines conductive lines 92 being oriented transverse to the lower levelconductive lines 42. - Although other microfabrication processes may be employed in fabricating multi-level shielded
multi-conductor interconnect buses 410A-D as described above, the SUMMiT V™ surface micromachining process developed at Sandia National Laboratories and described, for example, in U.S. Pat. No. 6,082,208, issued Jul. 4, 2000 entitled “Method For Fabricating Five-Level Microelectromechanical Structures And Microelectromechanical Transmission Formed”, incorporated by reference herein, is particularly useful for fabricating the multi-level shieldedmulti-conductor interconnect buses 410A-D. Employing the SUMMiT V™ surface micromachining process to fabricate the multi-level shieldedmulti-conductor interconnect buses 410A-D permits easy incorporation of theinterconnect buses 410A-D into MEM systems fabricated from five polysilicon levels such as some MEM mirror positioning systems useful in optical cross connects and the like. - Referring now to FIGS.5A-C, in the previously described multi-level shielded
multi-conductor interconnect buses 410A-D, the Sacox3 and Sacox4 layers 80, 100 remain around the Poly3conductive lines 92 to support the second level Poly3conductive lines 92 above thePoly2 layer 70 and prevent electrostatic or capillary attractive forces from pulling the Poly3conductive lines 92 downward into contact with thePoly2 layer 70, upward into contact with thePoly4 layer 110, or sideways into contact with thePoly3 shield walls 96 on either side thereof. However, it is possible to fabricate multi-level shielded multi-conductor interconnect buses where the Sacox3 and Sacox4 layers 80, 100 are removed (e.g. during subsequent etching steps) from around the Poly3conductive lines 92, either partially or in their entirety. In this regard, etch release holes (not shown) or the like may be formed in thevarious polysilicon layers conductive lines 92 and either thePoly2 layer 70, thePoly3 shield walls 96, or thePoly4 layer 110 can be alleviated by periodically anchoring the Poly3conductive lines 92 along their length. - FIG. 5A shows an embodiment of a multi-level shielded
multi-conductor interconnect bus 510A wherein anchor posts 120 are periodically spaced along the length of the Poly3conductive lines 92. The anchor posts 120 extend downward through appropriately sized holes formed in the Poly2 layer 70 (and theSacox1 layer 50 if it has not also been removed) and rest on top of thefirst dielectric layer 30 without contacting the lower level Poly0conductive lines 42. In this regard, the lower level Poly0conductive lines 42 and upper level Poly3conductive lines 92 are staggered so that there is adequate space between adjacent Poly0conductive lines 42 to accommodate theanchor posts 120 therebetween that support each upper level Poly3conductive line 42. In some fabrication processes (e.g., the SUMMiT V™ process), isolated pads ofPoly0 layer 40 material that are slightly larger than the cross-sectional area of the anchor posts 120 will typically be fabricated beneath the anchor posts 120. - As an alternative to staggering the lower level Poly0
conductive lines 42 and upper level Poly3conductive lines 92, the Poly0conductive lines 42 can also be configured to have appropriately sized holes formed therethrough that accommodate the anchor posts 120. By way of example, FIG. 5B shows a top cross-sectional view of a multi-level shieldedmulti-conductor interconnect bus 510B taken at the interface between thePoly0 layer 40 and theSacox1 layer 50 wherein the Poly0conductive lines 42 are configured to have donut-like sections in order to provide holes therethrough for the anchor posts 120. The donut-like sections of adjacent Poly0conductive lines 42 are staggered along the lengthwise extent of the Poly0conductive lines 42 in order to reduce the lateral width required for theinterconnect bus 510B. As may be appreciated, the Poly0conductive lines 42 may be configured in many other manners as well in order to accommodate the anchor posts 120. For example, FIG. 5C shows a top cross-sectional view of a multi-level shieldedmulti-conductor interconnect bus 510C taken at the interface between thePoly0 layer 40 and theSacox1 layer 50 wherein the Poly0conductive lines 42 are configured to have lateral jogs at various locations along their lengthwise extent in order to accommodate the anchor posts 120. - Referring now to FIG. 6, there may be more than two levels of conductive lines. For example, FIG. 6 shows a multi-level shielded
multi-conductor interconnect bus 610 having three levels of conductive lines. The multi-level shieldedmulti-conductor interconnect bus 610 includes Poly0conductive lines 42, Poly2conductive lines 72, and Poly3conductive lines 92 and aPoly4 shield 118 over the three level Poly0, Poly2, and Poly3conductive lines conductive lines conductive lines conductive lines conductive lines conductive lines Poly3 shield walls conductive lines conductive lines - In the previously described embodiments of a multi-level shielded
multi-conductor interconnect bus 410A-D, 510A-C, 610, it is desirable to shift theconductive lines Poly0 level 40 prior to where they reach their endpoints (e.g., where they contact a bond pad at one end and an actuated structure at the other). Shifting the upper levelconductive lines conductive lines conductive lines conductive lines conductive lines substrate 20 near their endpoints and thus inherently weak. - One manner of getting the upper level
conductive lines Poly4 shield 118 represented by the dotted line box) having Poly0conductive lines 42 and Poly3conductive lines 72, with the Poly0 and Poly3conductive lines conductive lines 92 where theconductive lines conductive lines 72 reach their endpoints, ananchor 120 is formed that extends between the Poly3conductive line 72 and the level of thePoly0 layer 40 where theconductive line 72 is continued at the Poly0 level to acorresponding bond pad 130 or MEM device. The anchor posts 120 that shift the Poly3conductive lines 72 down to thePoly0 layer 40 are preferably formed at a sufficient distance back from where the Poly3conductive lines 72 exit from under thePoly4 shield 118 in order to ensure that enough sacrificial material remains around the Poly3conductive lines 72 beyond theanchor post 120 to provide adequate support of the Poly3conductive lines 72. In this regard, it is also possible to have a small cavity between where the anchor posts 120 shift the Poly3conductive lines 72 down to thePoly0 layer 40 and the end of the sacrificial material. It should be noted that, in addition to solving the problem of having unsupported upper levelconductive lines 72 adjacent to their endpoints, shifting the upper levelconductive lines 72 down to the Poly0 level has the added advantage of making it simpler to attach the lower and upper levelconductive lines interconnect bus 710 to an array of devices since the endpoints of all of theconductive lines - While various embodiments of the present invention have been described in detail, further modifications and adaptations of the invention may occur to those skilled in the art. However, it is to be expressly understood that such modifications and adaptations are within the spirit and scope of the present invention.
Claims (8)
1. A method for making a shielded multi-conductor interconnect bus comprising the steps of:
removing portions of a first layer of dielectric material overlying and supported by at least a portion of a substrate to provide a plurality of parallel channels in the first layer of dielectric material;
depositing a first layer of electrically conductive material over the first layer of dielectric material, the first layer of electrically conductive material filling the channels formed in the first layer of dielectric material;
removing strips of the first layer of electrically conductive material to provide a plurality of electrically conductive lines on the first layer of dielectric material extending parallel with the channels formed in the first layer of dielectric material, wherein an upper surface of the first layer of dielectric material is exposed at the bottom of each strip;
depositing a second layer of dielectric material over the first layer of electrically conductive material, wherein the second layer of dielectric material fills the strips removed from the first layer of electrically conductive material;
removing portions of the second layer of dielectric material to provide a plurality of parallel channels in the second layer of dielectric material, the channels in the second layer of dielectric material being located to overlie the filled channels in the first layer of dielectric material and extending downward through the second layer of dielectric material to expose the first layer of electrically conductive material filling the channels in the first layer of dielectric material; and
depositing a second layer of electrically conductive material over the second layer of dielectric material, wherein the second layer of electrically conductive material fills the channels formed in the second layer of dielectric material.
2. The method of claim 1 wherein in said step of removing portions of a first layer of dielectric material, the substrate is comprised of silicon and the first dielectric layer comprises a dielectric stack layer covering an upper surface of the substrate comprising a lower layer of thermal oxide and an upper layer of silicon nitride.
3. The method of claim 2 wherein in said step of removing portions of a first layer of dielectric material, sufficient material is removed to provide channels in the first layer of dielectric material that extend vertically downward through the first layer of dielectric material to expose the upper surface of the substrate along at least a portion of each channel.
4. The method of claim 1 wherein in said steps of removing portions of a first layer of dielectric material and removing strips of the first layer of electrically conductive material, the portions are removed in a manner providing channels and strips arranged in a pattern wherein one of the channels is located between sets of the electrically conductive lines, each set of electrically conductive lines including at least one electrically conductive line.
5. The method of claim 1 wherein in said step of depositing a second layer of dielectric material, the dielectric material comprises one of silicon dioxide and silicate glass.
6. The method of claim 1 wherein in said step of depositing a first layer of electrically conductive material, the electrically conductive material comprises doped polysilicon.
7. The method of claim I wherein in said step of depositing a second layer of electrically conductive material, the electrically conductive material comprises doped polysilicon.
8. The method of claim 1 wherein said step of depositing a second layer of electrically conductive material comprises the steps of:
depositing a lower layer of doped polysilicon;
depositing an intervening layer of sacrificial material;
removing the intervening layer of sacrificial material; and
depositing an upper layer of doped polysilicon.
Priority Applications (1)
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US10/815,137 US20040180524A1 (en) | 2002-03-15 | 2004-03-31 | Shielded multi-conductor interconnect bus for MEMS |
Applications Claiming Priority (2)
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US10/099,724 US6731513B2 (en) | 2002-03-15 | 2002-03-15 | Shielded multi-conductor interconnect bus for MEMS |
US10/815,137 US20040180524A1 (en) | 2002-03-15 | 2004-03-31 | Shielded multi-conductor interconnect bus for MEMS |
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US10/099,724 Division US6731513B2 (en) | 2002-03-15 | 2002-03-15 | Shielded multi-conductor interconnect bus for MEMS |
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US10/099,724 Expired - Lifetime US6731513B2 (en) | 2002-03-15 | 2002-03-15 | Shielded multi-conductor interconnect bus for MEMS |
US10/815,137 Abandoned US20040180524A1 (en) | 2002-03-15 | 2004-03-31 | Shielded multi-conductor interconnect bus for MEMS |
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US20110084394A1 (en) * | 2009-10-13 | 2011-04-14 | Hui-Min Wu | Semiconductor Structure |
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US7566974B2 (en) * | 2004-09-29 | 2009-07-28 | Sandisk 3D, Llc | Doped polysilicon via connecting polysilicon layers |
US8149489B2 (en) | 2005-01-05 | 2012-04-03 | Nippon Telegraph And Telephone Corporation | Mirror device, mirror array, optical switch, mirror device manufacturing method, and mirror substrate manufacturing method |
US7535320B2 (en) * | 2005-07-12 | 2009-05-19 | U.S. Monolithics, L.L.C. | Phase shifter with flexible control voltage |
TWI294681B (en) * | 2006-01-25 | 2008-03-11 | Ind Tech Res Inst | Image ground shielding structure |
US7928008B2 (en) * | 2007-01-18 | 2011-04-19 | Terasemicon Corporation | Method for fabricating semiconductor device |
US8704714B2 (en) * | 2011-06-02 | 2014-04-22 | Digi International Inc. | Surface mount module embedded antenna |
US9128289B2 (en) | 2012-12-28 | 2015-09-08 | Pixtronix, Inc. | Display apparatus incorporating high-aspect ratio electrical interconnects |
JP6741933B2 (en) | 2015-10-02 | 2020-08-19 | ミツミ電機株式会社 | Optical scanning module, optical scanning control device |
US10939541B2 (en) * | 2017-03-31 | 2021-03-02 | Huawei Technologies Co., Ltd. | Shield structure for a low crosstalk single ended clock distribution circuit |
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Also Published As
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US20030173654A1 (en) | 2003-09-18 |
US6731513B2 (en) | 2004-05-04 |
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