US20040183103A1

US20040183103A1 - Semiconductor integrated circuit having an oblique global signal wiring and semiconductor integrated circuit wiring method

Info

Publication number: US20040183103A1
Application number: US10/762,156
Authority: US
Inventors: Naohito Kojima; Fumihiro Minami; Kimiyoshi Usami
Original assignee: Individual
Current assignee: Toshiba Corp
Priority date: 2003-01-20
Filing date: 2004-01-20
Publication date: 2004-09-23
Also published as: US20070235766A1; US8026537B2; JP2004228164A

Abstract

A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. P2003-011631, filed on Jan. 20, 2003; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuit and the fabrication method, particularly to the semiconductor integrated circuit that comprises a function block and a global signal wiring, and the fabrication method.

2. Description of the Related Art

The following design techniques are generalized for high-speed, large scale integrated circuit (LSI) design. To begin with, a circuit employed in a semiconductor integrated circuit is converted into hard macro blocks (function blocks) each corresponding to a function. The function blocks are then automatically arranged upon the semiconductor integrated circuit substrate, and the terminals of each function block are electrically connected to other circuits through wiring. This type of design is executed using a computer aided design (CAD) system.

Here, the semiconductor integrated circuit includes at least an integrated circuit that employs standard cell method and an application specific integrated circuit (ASIC) or the like. A wire herein means a signal wiring having a relatively long length passing across the entire substrate, such as a data bus through which transmission/reception of a data signal is performed between function blocks or with another circuit, or an address bus through which transmission/reception of an address signal is performed. Such a signal wiring is typically called a global signal wiring. Furthermore, the substrate during the design phase means a virtual substrate constructed in a memory space of the CAD system, and corresponds to a real semiconductor substrate or a real semiconductor chip of an actual product (a semiconductor integrated circuit).

Since the number of wiring layers is limited in semiconductor integrated circuit design, when the areas above the function blocks are set as prohibition areas for the global signal wirings, the global signal wirings must bypass the function block perimeter. When the size of the function blocks is extremely large relative to the substrate size, the necessary length of the global signal wirings for bypassing is extremely long. The increased global signal wiring length may cause an operation timing error (a timing violation), requiring redesigning.

In order to avoid an increase in wiring lengths, a design method of limiting the wiring layers utilized for connecting within the function block to only a few layers from the bottom layer upward, and allocating global signal wirings to the upper wiring layers could be employed. According to this design method, the global signal wirings may pass over the function block.

However, the following problems are not taken into account in such a semiconductor integrated circuit design method.

The global signal wirings may pass over the function block with the above design method; however additional buffering cells may not be arranged inside the function block in accordance with the global signal wiring passing route. In this case, the buffering cell is a circuit (intermediate cell) that amplifies a signal (increases driving capability) to be propagated through a global signal wiring.

Furthermore, since arrangement of buffering cells within the function block is impossible, arrangement of a buffering cell outside of the function block in the vicinity of each facing side of the function block, and connecting these buffering cells by means of the global signal wiring that passes over the function block is needed. Nevertheless, in the case of a function block of a huge size, the length of the global signal wiring that passes over the function block is extremely long, and the wiring capacitance thereof increases. Even if a buffering cell of high drive ability is arranged, the signal rising/falling time falls outside of design rule limitations, and timing error occurs. That is to say, the wiring length that a buffering cell can drive has a limit. So, in the case of a function block of a huge size, since a global signal wiring that passes over the function block cannot be arranged, a global signal wiring that bypasses the function block must be arranged.

Therefore, as shown in FIG. 1, basic structure of a semiconductor integrated circuit according to a related art includes a

function block

2 upon a substrate 1, a first buffering cell 3 a, which is arranged in the vicinity of a first side 2 a of the function block 2, a second buffering cell 3 b 1 and a third buffering cell 3 b 2, which is arranged in the vicinity of a second side 2 b adjacent to the first side 2 a, and a fourth buffering cell 3 c, which is arranged in the vicinity of a third side 2 c adjacent to the second side 2 b. The first buffering cell 3 a and the second buffering cell 3 b 1 are connected by signal wiring 4 a that bypasses the function block 2. The second buffering cell 3 b 1 and the third buffering cell 3 b 2 are connected by signal wiring 4 b. The third buffering cell 3 b 2 and the fourth buffering cell 3 c are connected by signal wiring 4 c that bypasses the function block 2. When global signal wiring to bypass the function block 2 is long, by reason of a limit to the wiring length that buffering cell 3 a to 3 c can drive, it is necessary to arrange a plurality of buffering cells between the first buffering cell 3 a and the fourth buffering cell 3 c.

It should be noted that this type of semiconductor integrated circuit design method is disclosed in U.S. Pat. No. 6,436,804 B2.

SUMMARY OF THE INVENTION

An aspect of the present invention inheres in a semiconductor integrated circuit including a function block arranged on a substrate; a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block; and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.

Another aspect of the present invention inheres in a semiconductor integrated circuit including a function block arranged on a substrate; a plurality of signal wirings having a length shorter than a length of a side of the function block on the substrate; a plurality of buffering cells electrically connected in series between each of the signal wirings; and a signal wiring passing obliquely across the corner between a first side and a second side of the function block, which connects the buffering cells arranged adjacent to the first side and adjacent to the second side adjacent to the first side of the function block.

Still another aspect of the present invention inheres in a semiconductor integrated circuit including a function block arranged on a substrate; a plurality of buffering cells arranged regularly in the function block at an appointed interval; and a signal wiring extending obliquely relative to a side of the function block, which is connected between adjacent buffering cells.

Yet still another aspect of the present invention inheres in a method of manufacturing a semiconductor integrated circuit, including arranging a function block on a substrate; arranging a signal wiring which passes over the function block obliquely relative to a first side and a second side adjacent to the first side of the function block; and arranging a first buffering cell connected to one end of the signal wiring, adjacent to the first side of the function block and a second buffering cell connected to another end of the signal wiring, adjacent to the second side of the function block.

Further aspect of the present invention inheres in a method of manufacturing a semiconductor integrated circuit, including arranging a plurality of function blocks on a substrate; extracting a first function block with minimum signal loss in the function blocks in a signal wiring route; extracting a second function block arranged near the first function block; arranging a signal wiring which passes obliquely relative to a first side and a second side adjacent to the first side of the second function block; determining whether a length of the signal wiring exceeds the signal wiring length limitation; determining whether a signal timing satisfies at least a design rule when the length of the signal wiring exceeds the signal wiring length limitation; determining whether a buffering cell can be arranged when the signal timing fails to satisfy the design rule; and arranging a first buffering cell connected to one end of the signal wiring, adjacent to the first side of the second function block and a second buffering cell connected to another end of the signal wiring, adjacent to the second side of the second function block.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view showing a basic structure of a semiconductor integrated circuit in the prior art; [0019]
FIG. 2 is a schematic view showing a first basic structure of a semiconductor integrated circuit according to a first embodiment of the present invention; [0020]
FIG. 3 is a schematic view showing a second basic structure of the semiconductor integrated circuit according to the first embodiment of the present invention; [0021]
FIG. 4 is a schematic view showing a third basic structure of the semiconductor integrated circuit according to the first embodiment of the present invention; [0022]
FIG. 5 is a schematic view showing a fourth basic structure of the semiconductor integrated circuit according to the first embodiment of the present invention; [0023]
FIG. 6 is a plane view showing an example of a layout of a structure of the semiconductor integrated circuit according to the first embodiment of the present invention; [0024]
FIG. 7A is a circuit diagram of a first basic structure of a buffering cell of the semiconductor integrated circuit according to the first embodiment of the present invention; [0025]
FIG. 7B is a plane view showing the first basic structure of the buffering cell of the semiconductor integrated circuit according to the first embodiment of the present invention; [0026]
FIG. 8A is a circuit diagram of a second basic structure of a buffering cell of the semiconductor integrated circuit according to the first embodiment of the present invention; [0027]
FIG. 8B is a plane view showing the second basic structure of the buffering cell of the semiconductor integrated circuit according to the first embodiment of the present invention; [0028]
FIG. 9A is a circuit diagram of a third basic structure of a buffering cell of the semiconductor integrated circuit according to the first embodiment of the present invention; [0029]
FIG. 9B is a plane view showing the third basic structure of the buffering cell of the semiconductor integrated circuit according to the first embodiment of the present invention; [0030]
FIG. 10 is a circuit diagram of a fourth basic structure of a buffering cell of the semiconductor integrated circuit according to the first embodiment of the present invention; [0031]
FIG. 11 is a plane view showing a first exemplary layout of a signal wiring of the semiconductor integrated circuit according to the first embodiment of the present invention; [0032]
FIG. 12 is a plane view showing a second exemplary layout of the signal wiring of the semiconductor integrated circuit according to the first embodiment of the present invention; [0033]
FIG. 13 is a plane view showing a third exemplary layout of the signal wiring of the semiconductor integrated circuit according to the first embodiment of the present invention; [0034]
FIG. 14 is a flowchart for explaining a fabrication method of the semiconductor integrated circuit according to the first embodiment of the present invention; [0035]
FIG. 15 is a flowchart for explaining a substantial part of the fabrication method of the semiconductor integrated circuit according to the first embodiment of the present invention; [0036]
FIG. 16 is a view showing schematic circuit configuration of a CAD system executing the fabrication method of the semiconductor integrated circuit according to the first embodiment of the present invention; and [0037]
FIG. 17 is a schematic view showing a configuration of a function block of a semiconductor integrated circuit according to a second embodiment of the present invention; [0038]
FIG. 18 is a schematic view showing a basic structure of a semiconductor integrated circuit according to a third embodiment of the present invention.[0039]

DETAILED DESCRIPTION OF THE INVENTION

Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified. [0040]
Generally and as it is conventional in the representation of semiconductor devices, it will be appreciated that the various drawings are not drawn to scale from one figure to another nor inside a given figure. [0041]
In the following descriptions, numerous specific details are set fourth such as specific signal values, etc. to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known circuits have been shown in block diagram form in order not to obscure the present invention in unnecessary detail. [0042]
First Embodiment [0043]
(First Basic Structure of a Semiconductor Integrated Circuit) [0044]
As shown in FIG. 2, a first basic structure of a semiconductor integrated circuit according to a first embodiment of the present invention includes a [0045] function block 2 arranged on a substrate 1, a first buffering cell 3 a, which is arranged in the vicinity of or adjacent to a first side 2 a of the function block 2, a second buffering cell 3 b, which is arranged in the vicinity of or adjacent to a second side 2 b adjacent to the first side 2 a, and a signal wiring 4 a, which passes over the function block 2 obliquely relative to the first side 2 a and the second side 2 b, connecting the first buffering cell 3 a and the second buffering cell 3 b.
Similarly, the semiconductor integrated circuit includes the [0046] function block 2 upon the substrate 1, the second buffering cell 3 b, which is arranged in the vicinity of or adjacent to the second side 2 b of the function block 2, a third buffering cell 3 c, which is arranged in the vicinity of or adjacent to a third side 2 c adjacent to the second side 2 b, and a signal wiring 4 b, which passes over the function block 2 obliquely relative to the second side 2 b and the third side 2 c, connecting the second buffering cell 3 b and the third buffering cell 3 c.
In other words, the semiconductor integrated circuit includes the [0047] function block 2 upon the substrate 1, a plurality of the signal wirings 4 a and 4 b, which have a shorter length than the length of sides 2 a through 2 d of the function block 2, and a plurality of the buffering cells 3 a to 3 c, which are electrically connected in series between each of a plurality of the signal wirings 4 a and 4 b, and also includes at least a signal wiring 4 a, which connects the buffering cells 3 a and 3 b arranged in the vicinity of or adjacent to the first side 2 a and the second side 2 b adjacent to this first side 2 a of the function block 2, and passes obliquely across the corner between the first side 2 a and the second side 2 b of the function block 2. The arrangement structure for each of the function block 2, the buffering cells 3 b and 3 c, and the signal wiring 4 b is also the same.
The semiconductor integrated circuit according to the first embodiment herein is a semiconductor integrated circuit that employs standard cell method and ASIC or the like, which are designed using a CAD system. [0048]
The photo masks are made based on this design data, and a semiconductor integrated circuit is fabricated as an actual product by a semiconductor fabrication process using these photo masks. [0049]
The [0050] substrate 1 is a semiconductor substrate (semiconductor chip) of, for example, a silicon single crystal or a compound semiconductor with an actual product. The substrate 1 is a virtual substrate that is constructed in a memory space of the CAD system during the design phase.
The [0051] function block 2 is a circuit block having one or a plurality of specific functions, a logic function, a calculation function, a memory function or the like, and is a mega cell, a macro cell, a mega block, a macro block or the like. The function block 2, in the CAD system design, is stored in a database as a piece of parts data, and can be freely arranged and rearranged on the substrate. More concretely, a central processing unit (CPU), read only memory (ROM) or random access memory (RAM) or the like corresponds to the function block 2.
With this semiconductor integrated circuit, [0052] intra-block wirings 4× and 4 y are typically arranged inside the function block 2 and other circuit blocks, but are not limited to being arranged only in this region. The intra-block wirings 4 x and 4 y are used to connect semiconductor devices such as transistors, resistors, capacitors and diodes that configure the function block 2, and may also connect circuits configured with semiconductor devices, and may further be used as power supply wiring, which supply power to the semiconductor devices and circuits. In the multi-level wiring structure employed by the semiconductor integrated circuit, the intra-block wirings 4 x and 4 y are allocated to several layers from the bottom layer upward on the substrate 1 side. For example, the intra-block wiring 4 x is allocated to the first wiring layer (and/or the third wiring layer) extending in an X direction substantially parallel to the second side 2 b and the fourth side 2 d of the function block 2. The intra-block wiring 4 y is allocated to the second wiring layer (and/or the fourth wiring layer) extending in a Y direction substantially parallel to the first side 2 a and the third side 2 c of the function block 2. The intra-block wirings 4 x and 4 y are electrically connected by connecting-hole interconnects such as through-hole interconnects or via interconnects not shown in the drawings.
The [0053] intra-block wirings 4 x and 4 y are made of, for example, a low resistant wiring material such as aluminum (Al), an aluminum alloy (Al—Si, Al—Cu, Al—Cu—Si or the like), copper (Cu), or a copper alloy. It should be noted that the intra-block wiring 4 x is exemplary ‘first signal wiring’ according to the present embodiment, and the intra-block wiring 4 y is exemplary ‘second signal wirings’ according to the present embodiment.
The signal wirings [0054] 4 a and 4 b are arranged across the entire substrate, and are part of the signal wiring that passes over the function block 2 as the long global signal wiring. Signals to be propagated through the signal wirings 4 a and 4 b are important for providing circuit operation timing for data signals and address signals in the entire semiconductor integrated circuit. The signal wirings 4 a and 4 b being arranged in, for example, the third wiring layer (or the fifth wiring layer), which is a layer higher than the intra-block wirings 4 x and 4 y, is practical for passing obliquely over the function block 2. Furthermore, with the first basic structure, the signal wiring 4 a may be arranged in the third wiring layer (or the fifth wiring layer), and the signal wiring 4 b may be arranged in the fourth wiring layer (or the sixth wiring layer). Moreover, the signal wiring 4 a may be arranged in the fourth wiring layer (or the sixth wiring layer), and the signal wiring 4 b may be arranged in the third wiring layer (or the fifth wiring layer). The wiring material for the signal wirings 4 a and 4 b is the same as that for the intra-block wirings 4 x and 4 y, for example. It should be noted that the signal wirings 4 a and 4 b are exemplary ‘signal wiring’ according to the present embodiment.
With the semiconductor integrated circuit according to the first embodiment, an angle θ1 of the [0055] signal wiring 4 a relative to the second side 2 b of the function block 2 or the intra-block wiring 4 x extending direction (wiring length direction) is set to 45 degrees. Obliquely arranging the signal wiring 4 a as a signal wiring as such allows the signal wiring 4 a length to be shortened to approximately 1/{square root}{square root over (2)} rather than when bypassing along the first side 2 a and the second side 2 b as indicated by a dotted wiring in FIG. 2. Similarly, an angle θ2 of the signal wiring 4 b relative to the second side 2 b of the function block 2 or the intra-block wirings 4 x extending direction is set to 45 degrees. The signal wiring 4 b may also have its length shortened to approximately 1/{square root}{square root over (2)}.
As described above, the wiring length that the [0056] buffering cells 3 a to 3 c can drive has a limit. Therefore, it is necessary to arrange at least two buffering cells in between the buffering cell 3 a and the buffering cell 3 c, when the wiring length that the buffering cells 3 a to 3 c can drive is larger than 2 times of the sum of length in the case of the signal wirings 4 a and 4 b bypassing the circuit block 2. However, if the signal wirings 4 a and 4 b are oblique wiring, the sum of wiring length of the signal wirings 4 a and 4 b is shortened, and as a result, the number of buffering cell can be reduced.
Moreover, an insertion pitch for the [0057] buffering cells 3 a to 3 c to be electrically inserted in series for every constant wiring length may also be shortened to approximately 1/{square root}{fraction (2)} along with the shortening of the lengths of the signal wirings 4 a and 4 b. In other words, the lengths of the respective signal wirings 4 a and 4 b become equivalent to the insertion pitch for the buffering cells 3 a to 3 c. For example, in the case of the size of the substrate 1 being a 10 mm square, the lengths of the respective signal wirings 4 a and 4 b may be set to 2 mm, and the insertion pitch for the buffering cells 3 a to 3 c may be set to 2 mm.
It should be noted that with the semiconductor integrated circuit according to the first embodiment, the [0058] buffering cells 3 a to 3 c are arranged outside of the function block 2. Basic cells not shown in the drawing that can configure a specific basic circuit such as an inverter circuit or a NAND circuit are arranged outside of this function block 2 in the design phase of the CAD system, and the buffering cells 3 a to 3 c are configured with those basic cells. The detailed structure of the buffering cells 3 a to 3 c is described later.
With the first basic structure of the semiconductor integrated circuit according to the first embodiment structured in this manner, the [0059] buffering cells 3 a and 3 b are arranged in the vicinity of or adjacent to the adjacent first side 2 a and the second side 2 b of the function block 2, respectively, and the signal wiring 4 a, which is connected to these buffering cells 3 a and 3 b so as to pass obliquely over the function block 2, is arranged; thus, the wiring length of the signal wiring 4 a may be shortened, and the wiring capacitance may be reduced. Moreover, the driving capability of the buffering cell 3 a may be relatively increased as the wiring capacitance reduces. Similarly, the buffering cells 3 b and 3 c are arranged in the vicinity of or adjacent to the adjacent second side 2 b and the third side 2 c of the function block 2, respectively, and the signal wiring 4 b, which is connected to these buffering cells 3 b and 3 c so as to pass obliquely over the function block 2, is arranged; thus, the wiring length of the signal wiring 4 b may be shortened, and the wiring capacitance may be reduced. Moreover, the driving capability of the buffering cell 3 b may be relatively increased as the wiring capacitance reduces. Accordingly, since the global signal wiring that bypasses the function block 2 may be reduced, and signal delay may be prevented, a semiconductor integrated circuit with excellent operating capability that is optimum for high integration can be obtained.
It should be noted that with the semiconductor integrated circuit according to the first embodiment, both the angle θ1 of the [0060] signal wiring 4 a and the angle θ2 of the signal wiring 4 b are set to 45 degrees and those signal wirings pass over the function block 2, however, the present embodiment is not limited to this angle. The present embodiment may set the angles θ1 and θ2 to 30 degrees or 60 degrees, for example. In any case, the angles θ1 and θ2 may be appropriately selected considering that they are manageable angles in the CAD system, the sufficient fabrication process yield of the semiconductor integrated circuit can be ensured, and such above-mentioned sufficient results can be obtained.
(Second Basic Structure of a Semiconductor Integrated Circuit) [0061]
A second basic structure of the semiconductor integrated circuit according to the first embodiment will be described using an example including a [0062] function block 2 with a form different than that of the function block 2 with the first basic structure. As shown in FIG. 3, the semiconductor integrated circuit includes the function block 2 upon the substrate 1, the first buffering cell 3 a, which is arranged in the vicinity of or adjacent to the first side 2 a of the function block 2, the second buffering cell 3 b, which is arranged in the vicinity of or adjacent to the second side 2 b adjacent to the first side 2 a, and the signal wiring 4 a, which passes obliquely over the function block 2 relative to the first side 2 a and the second side 2 b, connecting the first buffering cell 3 a and the second buffering cell 3 b.
Similarly, the semiconductor integrated circuit includes the [0063] function block 2 upon the substrate 1, the third buffering cell 3 c, which is arranged in the vicinity of or adjacent to the second side 2 b of the function block 2, a fourth buffering cell 3 d, which is arranged in the vicinity of or adjacent to the third side 2 c adjacent to the second side 2 b, and a signal wiring 4 c, which passes obliquely over the function block 2 relative to the second side 2 b and the third side 2 c, connecting the third buffering cell 3 c and the fourth buffering cell 3 d.
The [0064] function block 2 with the second basic structure has either a larger planar size than that of the function block 2 with the first basic structure, or an oblong planar form with the second side 2 b longer than the first side 2 a. In other words, the function block 2 having at least the second side 2 b sufficiently longer than the length of each of the signal wirings 4 a to 4 c, which are global signal wirings, is arranged in the semiconductor integrated circuit.
With the semiconductor integrated circuit including this [0065] function block 2, the signal wiring 4 a, which is the same as signal wiring 4 a with the first basic structure, and the signal wiring 4 c, which is the same as signal wiring 4 b with the first basic structure, pass obliquely over the function block 2, and the signal wiring 4 b is arranged outside of the function block 2 substantially parallel to the second side 2 b. On the outside of the function block 2, the signal wiring 4 b connects the buffering cells 3 b and 3 c, which are arranged along the second side 2 b apart from each other.
It is practical to arrange the [0066] signal wirings 4 a, 4 b and 4 c in the same wiring layer (for example, the third or the fifth wiring layer) as in the first basic structure. Furthermore, each of the signal wirings 4 a, 4 b and 4 c may be arranged in a separate wiring layer. Moreover, arranging the signal wirings 4 a and 4 c in the same wiring layer, and the signal wiring 4 b in a separate wiring layer from the signal wirings 4 a and 4 c is also possible.
The same results as obtained with the first basic structure can be obtained with the second basic structure of the semiconductor integrated circuit according to the first embodiment configured in this manner. [0067]
(Third Basic Structure of a Semiconductor Integrated Circuit) [0068]
A third basic structure of the semiconductor integrated circuit according to the first embodiment is for describing an example where the [0069] signal wirings 4 a and 4 b with the first basic structure are bus signal wiring. As shown in FIG. 4, the semiconductor integrated circuit includes the function block 2 upon the substrate 1, first buffering cells 30 a to 32 a, which are arranged in the vicinity of the first side 2 a of the function block 2, second buffering cells 30 b to 32 b, which are arranged in the vicinity of the second side 2 b adjacent to the first side 2 a, and signal wirings 40 a to 42 a, which pass obliquely over the function block 2 relative to the first side 2 a and the second side 2 b, connecting the first buffering cells 30 a to 32 a and the second buffering cells 30 b to 32 b, respectively.
Similarly, the semiconductor integrated circuit includes the [0070] function block 2 upon the substrate 1, the second buffering cells 30 b to 32 b, which are arranged in the vicinity of the second side 2 b of the function block 2, third buffering cells 30 c to 32 c, which are arranged in the vicinity of the third side 2 c adjacent to the second side 2 b, and signal wirings 40 b to 42 b, which pass obliquely over the function block 2 relative to the second side 2 b and the third side 2 c, connecting the second buffering cells 30 b to 32 b and the third buffering cells 30 c to 32 c, respectively.
The planar shape of the [0071] function block 2 with the third basic structure is the same shape as that of the function block 2 with the first basic structure. Part of the signal wirings 40 a to 42 a and 40 b to 42 b of the global signal wirings such as data buses and address buses pass over the function block 2.
With the third basic structure shown in FIG. 4, since the [0072] buffering cells 30 b to 32 b are aligned in the X direction along the second side 2 b, crossing wirings are necessary, and thus it is practical to arrange the signal wirings 40 to 42 a and the signal wirings 40 b to 42 b in different wiring layers. It should be noted that when the buffering cells 30 b to 32 b are aligned in the Y direction, crossing wiring is not necessary, and thus the signal wirings 40 a to 42 a and the signal wirings 40 b to 42 b may be arranged in the same wiring layer.
The same results as obtained with the first basic structure can be obtained with the third basic structure of the semiconductor integrated circuit according to the first embodiment configured in this manner. [0073]
It should be noted that three [0074] signal wirings 40 a to 42 a and signal wirings 40 b to 42 b have been described with the third basic structure in order to simplify the description, however, there may be two, four or more signal wirings. This is the same for a fourth basic structure described later.
(Fourth Basic Structure of a Semiconductor Integrated Circuit) [0075]
The fourth basic structure of the semiconductor integrated circuit according to the first embodiment is for describing an example where the second and third basic structures are combined. As shown in FIG. 5, the semiconductor integrated circuit includes the [0076] function block 2 upon the substrate 1, the first buffering cells 30 a to 32 a, which are arranged in the vicinity of the first side 2 a of the function block 2, the second buffering cells 30 b to 32 b, which are arranged in the vicinity of the second side 2 b adjacent to the first side 2 a, and the signal wirings 40 a to 42 a, which pass obliquely over the function block 2 relative to the first side 2 a and the second side 2 b, connecting the first buffering cells 30 a to 32 a and the second buffering cells 30 b to 32 b, respectively.
Similarly, the semiconductor integrated circuit includes the [0077] function block 2 upon the substrate 1, the third buffering cells 30 c to 32 c, which are arranged in the vicinity of the second side 2 b of the function block 2, fourth buffering cells 30 d to 32 d, which are arranged in the vicinity of the third side 2 c adjacent to the second side 2 b, and signal wirings 40 c to 42 c, which pass obliquely over the function block 2 relative to the second side 2 b and the third side 2 c, connecting the third buffering cells 30 c to 32 c and the fourth buffering cells 30 d to 32 d, respectively.
The signal wirings [0078] 40 a to 42 a and 40 c to 42 c are bus signal wirings and are global signal wirings like the signal wirings 40 a to 42 a and 40 b to 42 b with the third basic structure.
The [0079] function block 2 with the fourth basic structure has either a large planar size or an oblong planar shape in the same way as the function block 2 with the aforementioned second basic structure.
In the semiconductor integrated circuit including this [0080] function block 2, as with the signal wiring 4 b with the aforementioned second basic structure, the signal wirings 40 b to 42 b are arranged outside of the function block 2 substantially parallel along the second side 2 b thereof. Furthermore, on the outside of the function block 2, the signal wirings 40 b to 42 b connect the buffering cells 30 b to 32 b and 30 c to 32 c arranged along the second side 2 b apart from each other, respectively.
The same results as obtained with the first basic structure can be obtained with the fourth basic structure of the semiconductor integrated circuit according to the first embodiment configured in this manner. [0081]
(A concrete Layout of a Semiconductor Integrated Circuit) [0082]
Next, a concrete layout structure of the semiconductor integrated circuit according to the first embodiment is described. In this case, the semiconductor integrated circuit is one that employs standard cell method. [0083]
As shown in FIG. 6, a semiconductor integrated [0084] circuit 10 includes a substrate 1, a plurality of input/output buffering cells 5, which are aligned along each side of the surrounding areas upon the substrate 1, and function blocks 20 to 22 and random logic rows 6, which are arranged in the central area upon the substrate 1.
The input/[0085] output buffering cells 5 are interface circuits between the semiconductor integrated circuit 10 interior and the exterior thereof. The input/output buffering cells 5 comprise a plurality of semiconductor devices that can configure input interface circuits, output interface circuits, input/output interface circuits and the like (a layout structure thereof is not shown in the drawing.) Moreover, the input/output buffering cells 5 comprise semiconductor devices including at least transistors, resistors, and capacitors and the like that can configure input protection circuits and output protection circuits and the like. Furthermore, the input/output buffering cells 5 comprise external terminals (bonding pads) not shown in the drawing.
The function blocks [0086] 20 to 22 have a function equivalent to that of the function block 2 of the above-mentioned semiconductor integrated circuit described in the first basic structure, and correspond to mega cells or the like.
The [0087] random logic rows 6 are configured with a plurality of basic cells evenly aligned in the X direction. Each of these basic cells is arranged between wiring areas in the Y direction. Each basic cell includes a plurality of semiconductor devices that can configure logic circuits such as an inverter circuit or a NAND circuit by reconfiguring the intra-block wirings 4 x and 4 y.
(First Basic Structure of a Buffering Cell) [0088]
Next, with the first basic structure of the semiconductor integrated circuit, a concrete structure of the first through [0089] third buffering cells 3 a to 3 c inserted between the signal wirings 4 a to 4 c, which are global signal wirings, is described. It should be noted that since the structure of the buffering cells 30 a, 31 a, 32 a and 3 a in the second through fourth basic structures of the semiconductor integrated circuit are the same, descriptions thereof are omitted. Furthermore, in the description of the first through fourth basic structures of the buffering cell 3 a, a generic reference numeral ‘3’ is attached to the buffering cells to avoid complicated reference numerals and simplify description.
<Circuit Structure>[0090]
The [0091] buffering cell 3 with the first basic structure, as shown in FIG. 7A, is configured by two-step structure inverter circuits 301 and 302, which are electrically connected in series between a signal input terminal S1 and a signal output terminal S2.
The [0092] inverter circuit 301 is a front circuit connected directly to the signal input terminal S1. This inverter circuit 301 is configured with an n-channel insulated gate field-effect transistor (hereafter, simply referred to as IGFET) Q11 and a p-channel IGFET Q21, which form a complementary IGFET structure. Here, the IGFET denotes at least a metal oxide semiconductor field-effect transistor (MOSFET) and a metal insulator semiconductor field-effect transistor (MISFET). The n-channel IGFET Q11 has a gate electrode connected to the signal input terminal S1, the source electrode connected to a reference power supply V_ss, and the drain electrode connected to the drain electrode of the p-channel IGFET Q21. The reference power supply V_ssis a ground potential, for example 0V, for the circuit. The p-channel IGFET Q21 has a gate electrode connected to the signal input terminal S1, and the source electrode connected to an operating power supply V_dd. The operating power supply V_ddis an operating voltage, for example 1.7V to 3.3 V, for the circuit.
The [0093] inverter circuit 302 is a subsequent circuit (a following circuit) connected directly to the signal input terminal S2. This inverter circuit 302 is a complementary IGFET including an n-channel IGFET Q12 and a p-channel IGFET Q22 as with the inverter circuit 301. The n-channel IGFET Q12 has a gate electrode connected to the drain electrode of the n-channel IGFET Q11 and the p-channel IGFET Q21, the source electrode connected to a reference power supply V_ss, and the drain electrode connected to the drain electrode of the p-channel IGFET Q22. The p-channel IGFET Q22 has a gate electrode connected to the drain electrode of the n-channel IGFET Q11 and the p-channel IGFET Q21, and the source electrode connected to an operating power supply V_dd. The drain electrodes of the n-channel IGFET Q12 and the p-channel IGFET Q22 are connected to the signal output terminal S2.
<Device Structure>[0094]
The [0095] aforementioned buffering cells 3 are configured with, for example, the basic cells of the random logic rows 6 shown in FIG. 6. Herein, only the inverter circuit 301 to configure the buffering cell 3 is described, and since the device structure of the inverter circuit 302 is the same as that of the inverter circuit 301, description thereof is omitted.
As shown in FIG. 7B, the n-channel IGFET Q[0096] 11 of the inverter circuit 301 is arranged in a p-well region 101 formed in the substrate 1 surface, which is enclosed by an isolation insulating film 111. In other words, the n-channel IGFET Q11 includes the p-well region 101, which is used as an active region, a gate insulator (not shown in the drawing) arranged on this p-well region 101, a gate electrode 112 arranged on the gate insulator, and a pair of n-type semiconductor regions 113, which are used as the source and drain regions arranged on both sides along the length of the gate electrode 112.
A single layer film made from either a silicon oxide layer, a silicon nitride film or an oxynitride film, or a compound film thereof may be practically used as the gate insulator. A single layer film made from either a silicon polycrystalwiring film, a refractory metal film, or a refractory metal silicide film, or a compound film layered with a refractory metal film, or a refractory metal silicide film upon a silicon polycrystalwiring film may be practically used as the [0097] gate electrode 112. A lightly doped drain (LDD) structure may be practically used for the n-type semiconductor region 113.
The p-channel IGFET Q[0098] 21 is arranged in an n-well region 102 formed in the substrate 1 surface, which is enclosed by the isolation insulating film 111. In other words, the n-channel IGFET Q21 includes the n-well region 102, which is used as an active region, a gate insulator not shown in the drawing arranged on this n-well region 102, a gate electrode 112 arranged on the gate insulator, and a pair of p-type semiconductor regions 114, which are used as the source and drain regions arranged on both sides along the length of the gate electrode 112. The practical materials for the gate insulator and the gate electrode and the practical structure of the p-type semiconductor region 114 are the same as with the n-channel IGGET Q11.
In the [0099] random logic rows 6, an intra-cell power supply wiring (V_ss) 401 and an intra-cell operating power supply wiring (V_dd) 402 are arranged extending in the X direction. The intra-cell power supply wiring (V_ss) 401 is connected to the n-type semiconductor region (source region) 113 of the n-channel IGFET Q11 through an intra-cell wiring 403. The intra-cell operating power supply wiring 402 is connected to the p-type semiconductor region (source region) 114 of the p-channel IGFET Q21 through an intra-cell wiring 403. Furthermore, the gate electrodes 112 of the n-channel IGFET Q11 and the p-channel IGFET Q21 are connected, respectively, to the signal input terminal S1 through an intra-cell wiring 403, and the drain region is connected to the subsequent circuit 302. The intra-cell power supply wiring 401, the intra-cell operating power supply wiring 402 and the intra-cell wirings 403 are arranged in the first wiring layer and are made of, for example, an aluminum alloy (Al—Si, Al—Cu, Al—Cu—Si or the like).
(Second Basic Structure of a Buffering Cell) [0100]
A [0101] buffering cell 3 with a second basic structure is one with double the driving capability of the buffering cell 3 with the first basic structure.
<Circuit Structure>[0102]
The [0103] buffering cell 3 with the second basic structure, as shown in FIG. 8A, is configured by two-step structure inverter circuits 301 and 302, which are electrically connected in series between the signal input terminal S1 and the signal output terminal S2.
The [0104] inverter circuit 301 is a front circuit connected directly to the signal input terminal S1. This inverter circuit 301 has a two-step structure where the drain electrodes of the n-channel IGFET Q11 and the p-channel IGFET Q21 and the drain electrodes of the n-channel IGFET Q12 and the p-channel IGFET Q22 are electrically connected, respectively. Each of the n-channel IGFET Q11 and Q12 has a gate electrode connected to the signal input terminal S1, the source electrode connected to a reference power supply V_ss, and the drain electrode connected to the drain electrode of the p-channel IGFET Q21 and Q22. Each of the p-channel IGFET Q21 and Q22 has a gate electrode connected to the signal input terminal S1, and the source electrode connected to an operating power supply V_dd.
The [0105] inverter circuit 302 is a subsequent circuit connected directly to the signal output terminal S2. This inverter circuit 302, similar to the inverter circuit 301, has a two-step structure where the drain electrodes of an n-channel IGFET Q13 and a p-channel IGFET Q23 and the drain electrodes of an n-channel IGFET Q14 and a p-channel IGFET Q24 are electrically connected, respectively. Each of the n-channel IGFET Q13 and Q14 has a gate electrode connected to the inverter circuit 301 (the drain electrodes of IGFET Q11, Q12, Q21, and Q22), a source electrode connected to a reference power supply V_ss, and a drain electrode connected to the drain electrodes of the p-channel IGFET Q23 and Q24. Each of the p-channel IGFET Q23 and Q24 has a gate electrode connected to the signal input terminal S1, and a source electrode connected to an operating power supply V_dd. The drain electrodes of the n-channel IGFET Q13 and Q14 and the p-channel IGFET Q23 and Q24 are connected to the signal output terminal S2.
<Device Structure>[0106]
Herein, as with the buffering [0107] cell 3 having the first basic structure, only the inverter circuit 301 of the buffering cell 3 is described, and description of the inverter circuit 302 is omitted.
The n-channel IGFET Q[0108] 11 and Q12 of the inverter circuit 301, as shown in FIG. 8B, are arranged with their gate width directions in accordance, facing the Y direction adjacent to each other. The n-channel IGFET Q11 and Q12 are both arranged in the p-well region 101 formed in the substrate 1 surface, which is enclosed by the isolation insulating film 111. In other words, each of the n-channel IGFET Q11 and Q12 includes the p-well region 101, which is used as an active region, a gate insulator (not shown in the drawing) arranged on this p-well region 101, a gate electrode 112 arranged on the gate insulator, and a pair of n-type semiconductor regions 113, which are used as the source and drain regions arranged on both sides along the length of the gate electrode 112.
The p-channel IGFET Q[0109] 21 and Q22 are arranged with their gate width directions in accordance, facing the Y direction adjacent to each other. The p-channel IGFET Q21 and Q22 are both arranged in the n-well region 102 formed in the substrate 1 surface, which is enclosed by the isolation insulating film 111. In other words, each of the p-channel IGFET Q21 and Q22 includes the n-well region 102, which is used as an active region, a gate insulator (not shown in the drawing) arranged on this n-well region 102, a gate electrode 112 arranged on the gate insulator, and a pair of n-type semiconductor regions 114, which are used as the source and drain regions arranged on both sides along the length of the gate electrode 112.
It should be noted that the practical materials for the gate insulator and gate electrodes of the n-channel IGFET Q[0110] 11 and Q12 and the p-channel IGFET Q21 and Q22, as well as the practical structure of the n-type semiconductor region 113 and the p-type semiconductor region 114 are the same as for the n-channel IGFET Q11 and the p-channel IGFET Q21 with the first basic structure. Furthermore, the intra-cell power supply wiring 401, the intra-cell operating power supply wiring 402 and the intra-cell wirings 403 are similar to the intra-cell reference power supply wiring 401 with the first basic structure, only differing in their wire connection patterns.
(Third Basic Structure of a Buffering Cell) [0111]
A [0112] buffering cell 3 with a third basic structure is one with triple the driving capability of the buffering cell 3 with the first basic structure.
<Circuit Structure>[0113]
The [0114] buffering cell 3 with the third basic structure, as shown in FIG. 9A, is configured by the two-step structure inverter circuits 301 and 302, which are electrically connected in series between the signal input terminal S1 and the signal output terminal S2.
The [0115] inverter circuit 301 is a front circuit connected directly to the signal input terminal S1, and basically has the same structure as the inverter circuit 301 of the buffering cell 3 with the second basic structure. Namely, the inverter circuit 301 has a two-step structure where the drain electrodes of the n-channel IGFET Q11 and the p-channel IGFET Q21 and the drain electrodes of the n-channel IGFET Q12 and the p-channel IGFET Q22 are electrically connected, respectively. Each of the n-channel IGFET Q11 and Q12 has a gate electrode connected to the signal input terminal S1, a source electrode connected to a reference power supply V_ss, and a drain electrode connected to the drain electrode of the p-channel IGFET Q21 and Q22. Each of the p-channel IGFET Q21 and Q22 has a gate electrode connected to the signal input terminal S1, and a source electrode connected to an operating power supply V_dd.
The [0116] inverter circuit 302 is a subsequent circuit connected directly to the signal output terminal S2. This inverter circuit 302 has a three-step structure where the drain electrodes of the n-channel IGFET Q113 and the p-channel IGFET Q23, the drain electrodes of the n-channel IGFET Q14 and the p-channel IGFET Q24, and the drain electrodes of an n-channel IGFET Q15 and a p-channel IGFET Q25 are electrically connected, respectively. Each of the n-channel IGFET Q13, Q14 and Q15 has a gate electrode connected to the inverter circuit 301 (the drain electrode of IGFET Q11, Q12, Q21, and Q22), a source electrode connected to a reference power supply V_ss, and a drain electrode connected to the drain electrode of the p-channel IGFET Q23 and Q24. Each of the p-channel IGFET Q23, Q24 and Q25 has a gate electrode connected to the signal input terminal S1, and a source electrode connected to an operating power supply V_dd. The drain electrodes of the n-channel IGFET Q13 to Q15 and the p-channel IGFET Q23 to Q25 are connected to the signal output terminal S2.
<Device Structure>[0117]
The basic structure of [0118] inverter circuit 301 of the buffering cell 3 is the same as that of the inverter circuits 301 and 302 of the buffering cell 3 with the second basic structure, and thus only the inverter circuit 302 of the buffering cell 3 is described here, and description of the inverter circuit 301 is omitted.
The n-channel IGFET Q[0119] 13, Q14 and Q15 of the inverter circuit 302, as shown in FIG. 9B, are arranged with their gate width directions in accordance, facing the Y direction adjacent to each other. The n-channel IGFET Q13, Q14 and Q15 are all arranged in the p-well region 101 formed in the substrate 1 surface, which is enclosed by the isolation insulating film 111. In other words, the n-channel IGFET Q13, Q14 and Q15 include the p-well region 101, which is used as an active region, a gate insulator not shown in the drawing arranged on this p-well region 1, a gate electrode 112 arranged on the gate insulator, and a pair of n-type semiconductor regions 113, which are used as the source and drain regions arranged on both sides along the length of the gate electrode 112.
The p-channel IGFET Q[0120] 23, Q24 and Q25 are arranged with their gate width directions in accordance, and the n-channel IGFET Q13, Q14 and Q15 are arranged with their gate width directions in accordance, facing the Y direction adjacent to each other, respectively. The p-channel IGFET Q23, Q24 and Q25 are all arranged in the n-well region 102 formed in the substrate 1 surface, which is enclosed by the isolation insulating film 111. In other words, the p-channel IGFET Q23, Q24 and Q25 include the n-well region 102, which is used as an active region, a gate insulator not shown in the drawing arranged on this p-well region 1, a gate electrode 112 arranged on the gate insulator, and a pair of p-type semiconductor regions 113, which are used as the source and drain regions arranged on both sides along the length of the gate electrode 112.
It should be noted that the practical materials for the gate insulator and gate electrodes of the n-channel IGFET Q[0121] 13, Q14 and Q15 and the p-channel IGFET Q23, Q24 and Q25, as well as the practical structure of the n-type semiconductor region 113 and the p-type semiconductor region 114 are the same as with the n-channel IGFET Q11 and the p-channel IGFET Q21 having the first basic structure. Furthermore, the intra-cell power supply wiring (V_ss) 401, the intra-cell operating power supply wiring (V_dd) 402 and the intra-cell wirings 403 are similar to intra-cell reference power supply wiring 401 with the first basic structure only differing in their wire connection patterns.
(Fourth Basic Structure of a Buffering Cell) [0122]
A [0123] buffering cell 3 with a fourth basic structure has triple the driving capabilities of both the inverter circuits 301 and 302 in the buffering cell 3 with the first basic structure.
<Circuit Structure>[0124]
The [0125] buffering cell 3 with the fourth basic structure, as shown in FIG. 10, is configured by the two-step structure inverter circuits 301 and 302, which are electrically connected in series between the signal input terminal S1 and the signal output terminal S2.
The [0126] inverter circuit 301 is a front circuit connected directly to the signal input terminal S1, and basically has the same structure as the inverter circuit 302 of the buffering cell 3 with the third basic structure. Namely, the inverter circuit 301 has a three-step structure where the drain electrodes of the n-channel IGFET Q11 and the p-channel IGFET Q21, the drain electrodes of the n-channel IGFET Q12 and the p-channel IGFET Q22, and the drain electrodes of an n-channel IGFET Q13 and a p-channel IGFET Q23 are electrically connected, respectively. Each of the n-channel IGFET Q11, Q12 and Q13 has a gate electrode connected to the signal input terminal S1, a source electrode connected to a reference power supply V_ss, and a drain electrode connected to the drain electrodes of the p-channel IGFET Q21, Q22 and Q23. Each of the p-channel IGFET Q21, Q22 and Q23 has a gate electrode connected to the signal input terminal S1, and a source electrode connected to an operating power supply V_dd.
The [0127] inverter circuit 302 is a subsequent circuit connected directly to the signal input terminal S2, and basically has the same structure as the inverter circuit 302 of the buffering cell 3 with the third basic structure. The inverter circuit 302 has a three-step structure where the drain electrodes of the n-channel IGFET Q14 and the p-channel IGFET Q24, the drain electrodes of the n-channel IGFET Q15 and the p-channel IGFET Q25, and the drain electrodes of an n-channel IGFET Q16 and a p-channel IGFET Q26 are electrically connected, respectively. Each of the n-channel IGFET Q14, Q15 and Q16 has a gate electrode connected to the inverter circuit 301 (the drain electrode of IGFET Q11, Q12, Q13, Q21, Q22 and Q23), a source electrode connected to a reference power supply V_ss, and a drain electrode connected to the drain electrodes of the p-channel IGFET Q24, Q25 and Q26. Each of the p-channel IGFET Q24, Q25 and Q26 has a gate electrode connected to the signal input terminal S1, and a source electrode connected to an operating power supply V_dd. The drain electrodes of the n-channel IGFET Q14 to Q16 and the p-channel IGFET Q24 to Q26 are connected to the signal output terminal S2.
<Device Structure>[0128]
The basic structure of [0129] inverter circuits 301 and 302 of the buffering cell 3 is the same as that of the inverter circuit 302 of the buffering cell 3 with the third basic structure, and thus description of the device structure thereof is omitted.
(Another Basic Structure of a Buffering Cell) [0130]
As mentioned before, the structure of the [0131] buffering cell 3 can be appropriately modified. For example, when the global signal wiring is relatively long and the wiring load is large, at least the inverter circuit 302 of the buffering cell 3 can be configured by a four- or more step structure. Furthermore, in the case of enhancing the driving capability, at least the IGFET Q gate width of the final output phase of the inverter circuit 302 may be longer than the other IGFET Q gate width.
(First Exemplary Layout of Signal Lines) [0132]
Next, a first exemplary layout of global signal wirings in a semiconductor integrated [0133] circuit 10 is shown in FIG. 11. Here, for simplification of description, an example of two global signal wirings 4A and 4B being conveniently arranged is described.
The function blocks [0134] 23 and 24 are arranged upon the substrate 1 of the semiconductor integrated circuit 10. In FIG. 11, the global signal wiring 4A, which extends from an input/output buffering cell 5A arranged on the left side of the substrate 1, passes obliquely over the function block 23, and extends across an extensive range until reaching close to the right side of the substrate 1. A part of a signal wiring 4 a of the global signal wiring 4A passing over the function block 23 is arranged obliquely relative to the first side 2 a and the second side 2 b of the function block 23. A buffering cell 3 a is arranged in the vicinity of or adjacent to the first side 2 a of the function block 23, and a buffering cell 3 b is arranged in the vicinity of or adjacent to the second side 2 b. One end of the signal wiring 4 a is electrically connected to the buffering cell 3 a, and the other end is electrically connected to the buffering cell 3 b.
Similarly, the [0135] global signal wiring 4B, which extends from an input/output buffering cell 5B arranged on the left side of the substrate 1, passes over the function block 24 at an angle, and extends across an extensive range until reaching close to the right side of the substrate 1. A part of the signal wiring 4 a of the global signal wiring 4B passing over the function block 24 is arranged obliquely relative to the first side 2 a and the second side 2 b of the function block 24. A buffering cell 3 a is arranged in the vicinity of or adjacent to the first side 2 a of the function block 24, and a buffering cell 3 b is arranged in the vicinity of or adjacent to the second side 2 b. One end of the signal wiring 4 a is electrically connected to the buffering cell 3 a, and the other end is electrically connected to the buffering cell 3 b.
With the semiconductor integrated [0136] circuit 10, which includes such a first layout of global signal wiring, the wiring length of the global signal wirings 4A and 4B can be shortened, and the wiring capacitance can be reduced due to the signal wiring 4 a passing over the function blocks 23 and 24. The number of necessary buffering cells can be reduced in the global signal wiring 4A by shortening the wiring length of global signal wiring 4A. Similarly, the number of necessary buffering cells can be reduced in the global signal wiring 4 B by shortening the wiring length of global signal wiring 4B. In addition, structure of buffering cell 3 can be optimized depending on wiring capacitance, and electricity composed and an area of a buffering cell can be reduced. Moreover, the driving capability of the buffering cell 3 a may be relatively increased as the wiring capacitance reduces. Accordingly, since the frequency of the global signal wiring 4A bypassing the function block 23 may be reduced, the frequency of the global signal wiring 4B bypassing the function block 24 may be reduced, and signal delay may be prevented, the semiconductor integrated circuit 10 with excellent operating capability that is optimum for high integration can be provided.
(Second Exemplary Layout of Signal wirings) [0137]
Next, a second exemplary layout of global signal wiring in the semiconductor integrated [0138] circuit 10 is shown in FIG. 12. The second layout is one for describing an example that moderates or disperses signal wiring hotspots between function blocks. In the following description, a ‘hotspot’ is an area where signal wiring is crowded. It should be noted that the second layout is not limited to only global signal wiring, and may be applied to the layout for signal wiring and power supply wiring arranged between function blocks.
In the semiconductor integrated [0139] circuit 10, a function block 25 is arranged at the lower left of the substrate 1, a function block 26 is arranged at the upper left, a function block 27 is arranged at the upper right, and a function block 28 is arranged at the lower right. It should be noted that the case of four function blocks 25 to 28 being conveniently arranged is described; however, the number of function blocks to be arranged is not limited thereto. The function block 25 outputs a predetermined signal to the function block 27, which is arranged at the upper right as viewed from the function block 25, through signal wirings 4C and 4D. The signal wiring 4C extends from the function block 25 to the right side (X direction), passes obliquely over the function block 28, which is arranged on the right side as viewed from the function block 25, and then extends to the upper side (Y direction), connecting to the function block 27. A buffering cell 30 a is arranged in the vicinity of or adjacent to the first side 2 a of the function block 28, and a buffering cell 30 b is arranged in the vicinity of or adjacent to the second side 2 b. One end of the signal wiring 40 a, which is a part of the signal wiring 4C and passes over the function block 28, is connected to the buffering cell 30 a, and the other end is connected to the buffering cell 30 b. Similarly, the signal wiring 4D extends from the function block 25 to the right side, passes obliquely over the function block 28, and extends to the upper side, connecting to the function block 27. A buffering cell 31 a is arranged in the vicinity of or adjacent to the first side 2 a of the function block 28, and a buffering cell 31 b is arranged in the vicinity of or adjacent to the second side 2 b. One end of the signal wiring 41 a, which is a part of the signal wiring 4D and passes over the function block 28, is connected to the buffering cell 31 a, and the other end is connected to the buffering cell 31 b.
Furthermore, the [0140] function block 27 outputs a predetermined signal to the function block 25 through signal wirings 4E, 4F, 4G and 4H. The signal wirings 4E and 4F pass between the four function blocks 25 to 28, namely hotspots that easily become congested with signal wiring.
The [0141] signal wiring 4G extends from the function block 27 to the left side (X direction), passes obliquely over the function block 26, which is arranged on the left side as viewed from the function block 27, and then extends to the lower side (Y direction), connecting to the function block 25. A buffering cell 30 a is arranged in the vicinity of the third side 2 c of the function block 26, and a buffering cell 30 b is arranged in the vicinity of the fourth side 2 d. One end of the signal wiring 40 a, which is a part of the signal wiring 4G and which passes over the function block 26, is connected to the buffering cell 30 a, and the other end is connected to the buffering cell 30 b. Similarly, the signal wiring 4H extends from the function block 27 to the left side, passes obliquely over the function block 26, and then extends to the lower side, connecting to the function block 25. A buffering cell 31 a is arranged in the vicinity of the third side 2 c of the function block 28, and a buffering cell 31 b is arranged in the vicinity of the fourth side 2 d. The signal wiring 41 a, which is a part of the signal wiring 4H and passes over the function block 26, is connected to one end of the buffering cell 31 a, and the other end is connected to the buffering cell 31 b.
The [0142] function block 25 and the function block 26, which is arranged on the upper side as viewed from the function block 25, are directly connected through signal wirings 41 and 4J. Here, when the wiring lengths of the signal wirings 41 and 4J are shorter than those of the signal wirings 4E and 4F, and the driving capability of the final output phase circuit of the function blocks 25 and 26 is sufficient, a buffering cell 3 need not be arranged in between the signal wirings 41 and 4J.
Moreover, the [0143] function block 26 outputs a predetermined signal to the function block 28, which is arranged at the lower right as viewed from the function block 26, through signal wirings 4K, 4L and 4M. The signal wiring 4K extends from the function block 26 to the right side (X direction), passes obliquely over the function block 27, which is arranged on the right side as viewed from the function block 26, and then extends to the lower side (Y direction), connecting to the function block 28. A buffering cell 30 a is arranged in the vicinity of the first side 2 a of the function block 27, and a buffering cell 30 b is arranged in the vicinity of the fourth side 2 d. One end of the signal wiring 40 a, which is a part of the signal wiring 4K and passes over the function block 27, is connected to the buffering cell 30 a, and the other end is connected to the buffering cell 30 b. Similarly, the signal wiring 4L extends from the function block 26 to the right side, passes obliquely over the function block 27, and then extends to the lower side, connecting to the function block 28. A buffering cell 31 a is arranged in the vicinity of the first side 2 a of the function block 27, and a buffering cell 31 b is arranged in the vicinity of the fourth side 2 d. One end of the signal wiring 41 a, which is a part of the signal wiring 4L and passes over the function block 27, is connected to the buffering cell 31 a, and the other end is connected to the buffering cell 31 b. The signal wiring 4M extends from the function block 26 to the right side, passes obliquely over the function block 27, and then extends to the lower side, connecting to the function block 28. A buffering cell 32 a is arranged in the vicinity of the first side 2 a of the function block 27, and a buffering cell 32 b is arranged in the vicinity of the fourth side 2 d. One end of the signal wiring 42 a, which is a part of the signal wiring 4M and passes over the function block 27, is connected to the buffering cell 32 a, and the other end is connected to the buffering cell 32 b.
With the semiconductor integrated [0144] circuit 10 according to the first embodiment configured in this manner, the signal wirings 40 a and 41 a, which are part of the signal wirings 4C and 4D, respectively, pass obliquely over the function block 28, the signal wirings 40 a and 41 a, which are part of the signal wirings 4G and 4H, respectively, pass obliquely over the function block 26, and the signal wirings 40 a, 41 a and 42 a, which are part of the signal wirings 4K, 4L and 4M, respectively, pass obliquely over the function block 27, allowing reduction or dispersion of signal wiring hotspots between function blocks.
Moreover, with the semiconductor integrated [0145] circuit 10, reducing bypassing signal wirings, which are routed around the perimeter of the function blocks 25 to 28, while dispersing hotspots is possible, thereby allowing control of signal transmission delay and implementation of high-speed circuit operation. In addition, buffering cell numerical reduction is possible by reducing the length of the bypassing signal wiring. Electricity consumption and an area of a buffering cell can be reduced because a structure of a buffering cell can be optimized according to the decrease in wiring capacitance.
Furthermore, with the semiconductor integrated [0146] circuit 10, arrangement regions for the signal wirings may be utilized effectively due to the dispersion of the hotspots, thereby improving integration.
(Third Exemplary Layout of Signal Lines) [0147]
Next, a third exemplary layout of global signal wirings in the semiconductor integrated [0148] circuit 10 is shown in FIG. 13. The third layout is one for describing an example that has various global signal wirings pass obliquely over a single function block as long as the wiring length limitation allows. It should be noted that the third layout, as with the second layout, is not limited to only global signal wiring, and may be applied to a layout for signal wiring and power supply wiring arranged between function blocks.
With the semiconductor integrated [0149] circuit 10 shown in FIG. 13, a function block 2 is arranged in the upper left corner upon the substrate 1, and input/output buffering cells 5 are arranged along the first side (left side) 2 a and the second side (upper side) 2 b of the function block 2.
Signal wirings [0150] 4O and 4P, which extend to the lower side, pass obliquely over the function block 2 from upper left to lower right, and then extend to the right side, are connected to an input/output buffering cell 5C arranged on the upper side. Since the driving capability of the output circuit of the input/output buffering cell 5C is typically higher than that of the output of a logic circuit in the function block 2 not shown in the drawing, a buffering cell 3 is not particularly necessary near the second side 2 b of the function block 2 when passing over the function block 2 directly from the input/output buffering cell 5C. The signal wiring 40 a of the signal wiring 40 that passes over the function block 2 is arranged obliquely from the second side 2 b towards the third side 2 c, connecting to the buffering cell 30 a. The signal wiring 41 a of the signal wiring 4P that passes over the function block 2 is arranged obliquely from the second side 2 b towards the third side 2 c, connecting to the buffering cell 31 a.
Meanwhile, [0151] signal wirings 4Q, 4R and 4S, which extend to the right side, pass obliquely over the same function block 2 from upper left to lower right, and then extend to the lower side, are connected to an input/output buffering cell 5D arranged on the left side. A buffering cell 3 is not particularly necessary near the first side 2 a of the function block 2. The signal wiring 40 a of the signal wiring 4Q that passes over the function block 2 is arranged obliquely from the first side 2 a towards the fourth side 2 d, connecting to the buffering cell 30 a. Similarly, the signal wiring 41 a of the signal wiring 4R that passes over the function block 2 is arranged obliquely from the first side 2 a towards the fourth side 2 d, connecting to the buffering cell 31 a. The signal wiring 42 a of the signal wiring 4S that passes over the function block 2 is arranged obliquely from the first side 2 a towards the fourth side 2 d, connecting to the buffering cell 32 a.
It should be noted that in FIG. 13, a signal wiring (or global signal wiring) [0152] 4T extends towards the right side from an input/output buffering cell 5F arranged on the upper side, and a signal wiring (or global signal wiring) 4U extends toward the lower side from an input/output buffering cell 5E arranged on the left side. These signal wirings 4T and 4U are orthogonal wirings, but however do not pass obliquely over the function block 2 so as to satisfy the constraint for the wiring length.
With the semiconductor integrated [0153] circuit 10 according to the first embodiment configured in this manner, the same results as with the second layout may be obtained, as well as arranging multiple types of global signal wirings including the signal wirings 40 and 4P, which pass obliquely over the upper right corner of the function block 2, and the signal wirings 4Q, 4R, and 4S, which pass obliquely over the lower left corner.
(Semiconductor Integrated Circuit Fabrication Method) [0154]
An example of a fabrication method of the semiconductor integrated [0155] circuit 10, particularly a fabrication method of the semiconductor integrated circuit 10, which includes a global signal wiring fabrication method using a CAD system, is described referencing the flowcharts shown in FIG. 14 and FIG. 15, and a configuration of the CAD system shown in FIG. 16.
The CAD system shown in FIG. 16 includes a [0156] CPU 500, a database unit 600, a main memory unit 700, an input unit 810, and an output unit 820. Moreover, the CPU 500 includes an input data module 501, a circuit arrangement module 502, a clock signal wiring module 503, a power supply wiring module 504, a global wiring module 505, a block extraction module 506, an evaluation module 507, a buffering cell module 508, and an inspection module 509. The input data module 501 creates input files by reading out necessary data from the database unit 600 and the main memory unit 700 in order for the CAD system to make a photo mask (reticle). The circuit arrangement module 502 arranges function blocks and the like based on the input file information. The clock signal wiring module 503 arranges clock signal wiring. The power supply wiring module 504 arranges power supply wiring. The global wiring module 505 arranges global signal wiring. The block extraction module 506 extracts circuit blocks existing along a global signal wiring route. The evaluation module 507 evaluates the global signal wiring based on a predetermined design rule. The buffering cell module 508 determines whether or not to arrange a buffering cell along a global signal wiring route. The inspection module 509 inspects electrical characteristics of global signal wiring. The database unit 600 includes a parts data memory domain 601 and a design rule memory domain 602. The parts data memory domain 601 stores parts data information for circuit blocks and the like. The design rule memory domain 602 stores predetermined design rules for circuit arrangement and wiring. The main memory unit 700 includes a circuit data memory domain 701, an arrangement data memory domain 702, and a mask data memory domain 703. The circuit data memory domain 701 stores information for designing semiconductor integrated circuits. The arrangement data memory domain 702 stores arrangement information for semiconductor integrated circuit being designed. The mask data memory domain 703 stores information for circuit arrangements and wiring and the like generated by the CAD system.
With the CAD system shown in FIG. 16, information necessary for designing the semiconductor integrated circuit, which is input through the [0157] input unit 810, is stored in the database unit 600 and the main memory unit 700. The CPU 500 can perform circuit arrangement and wiring that satisfies design rules, store information necessary for making the photo masks (reticles) in the main memory unit 700, and retrieve it through the output unit 820.
(1) To begin with, various information stored in the [0158] database unit 600 and the main memory unit 700 through the input unit 810 necessary for designing the semiconductor integrated circuit is read by the input data module 501, creating an input file (S10). The created input file is stored in the arrangement data memory domain 702.
(2) The [0159] circuit arrangement module 502 reads circuit information stored in the arrangement data memory domain 702, arranging a function block 2 upon the substrate 1 (see the layout for the semiconductor integrated circuit 10 shown in FIG. 6). In this case, a function block includes at least a mega cell, as mentioned earlier.
(3) Next, the [0160] circuit arrangement module 502 uses as the random logic rows 6 a region in which the function block 2 is not arranged upon the substrate 1, arranging a logic circuit in these random logic rows 6 (S12).
(4) The clock [0161] signal wiring module 503 reads out the circuit information stored in the arrangement data memory domain 702, arranging a clock signal wiring upon the substrate 1 (S13). The clock signal wiring is arranged prior to power supply wiring and signal wiring in order to allow the system to operate at a high speed. It is practical to arrange the clock signal wiring using the top wiring layer, which cannot be easily restricted by the layout.
(5) The power [0162] supply wiring module 504 reads the circuit information stored in the arrangement data memory domain 702, arranging a power supply wiring upon the substrate 1 (S14). The power supply wiring is typically arranged with one set of a reference power supply wiring V_ss, which supplies a circuit reference power supply of 0V, for example, and an operating power supply wiring V_dd, which supplies a circuit operating power supply of 3.3V to 5V, for example. The power supply wiring is arranged, for example, in the second wiring layer as a fixed pattern extending along the outer edge of the substrate 1 on the input/output buffering cells 5. Furthermore, the power supply wiring is arranged, for example, in the second wiring layer on the random logic rows 6 in the basic cell arranging direction. Moreover, the power supply wiring is arranged in a large area, which includes the areas on the function block 2 and the random logic rows 6 in the substrate 1, and which is arranged in a relatively higher wiring layer which is a lower than the clock signal wiring layer.
(6) Next, the [0163] global wiring module 505 reads the circuit information stored in the arrangement data memory domain 702, arranging a global signal wiring (S15). Global signal wiring arrangement begins with the design of a global signal wiring route including at least the arrangement of orthogonal signal wiring typically arranged in either the X direction or the Y direction, arrangement of oblique signal wiring 4, and arrangement of buffering cells 3 (S16). As shown in FIG. 15, to begin with, in the route of the global signal wirings, a function block 2 with minimum signal loss is extracted by the block extraction module 506 (S160). It is then determined whether or not a function block 2 with minimum signal loss exists (S161). If a function block 2 with minimum signal loss does not exist, this global signal wiring routing design concludes (S162). If a function block 2 with minimum signal loss exists, an arbitrary function block 2 existing near the function block 2 with minimum signal loss is extracted by the block extraction module 506 (S163). The signal loss due to this function block 2 is greater than the minimum signal loss. If a function block 2 does not exist, a function block 2 with minimum signal loss is once again extracted (S1160). If a function block 2 exists, the increased amount of signal loss due to arranging orthogonal signal wirings around this function block 2, or arranging oblique signal wirings passing over the function block 2 is calculated by the evaluation module 507, and then added to the arrangement data memory domain 702 (S165). The evaluation module 507 then reads from the design rule memory domain 602 the design rule for global signal wiring length, and when a buffering cell 3 is not arranged, determines whether or not the orthogonal signal wirings or the oblique signal wirings exceed the signal wiring length limitation (S166). If the signal wiring length exceeds the limitation, a function block 2 with minimum signal loss is once again extracted (S160). If the signal wiring length does not exceed the limitation, the evaluation module 507 reads the design rule for signal rising/falling times from the design rule memory domain 602, and determines whether or not the signal rising/falling times on the orthogonal signal wirings or the oblique signal wirings satisfy the design rule, namely whether or not a timing error occurs (S167). If the design rule is satisfied and a timing error does not occur, the signal wiring route is decided, and this global signal wiring routing design is concluded (S168). If the design rule is not satisfied and a timing error occurs, the buffering cell module 508 determines whether or not a buffering cell 3 can be arranged (S169). If the buffering cell 3 can be arranged, the arrangement position of the buffering cell 3 for the signal wiring route being designed is stored as a final point in the arrangement data memory domain 702, and this global signal wiring routing design is reset at the same time (S170). A single function block 2 is then extracted again (S163), and the same processing is repeatedly executed until a single function block 2 can no longer be extracted. Meanwhile, if the buffering cell 3 cannot be arranged, orthogonal signal wirings or oblique signal wirings are added to the current signal wiring route being designed and stored in the arrangement data memory domain 702 (S171). A single function block 2 is then extracted again (S163), and the same processing is repeatedly executed. Based on the layout information for the buffering cell 3 stored in the arrangement data memory domain 702, as shown in FIG. 14, the buffering cell 3 is additionally arranged along the global signal wiring route by the global wiring module 505 (S17). The global wiring module 505 designates a route for the global signal wiring including oblique signal wiring created based on the global signal wiring design (S18). The final route for this global signal wiring is decided (S19), and the global signal wiring is arranged.
(7) Electrical characteristics such as a timing error of the arranged global signal wiring are inspected by the inspection module [0164] 509 (S20).
(8) If there are no defects as a result of the inspection, arrangement information for [0165] function blocks 2, random logic rows 6, clock signal wiring, power supply wiring, or global signal wiring are stored in the mask data memory domain 703 (S21).
(9) Based on the information created by the CAD system described above and stored in the mask [0166] data memory domain 703, semiconductor integrated circuit 10 photo masks (reticles) are made.
(10) Using the photo masks, the semiconductor integrated [0167] circuit 10 according to the first embodiment can be completed upon an actual substrate 1 by executing various fabrication processes such as photolithography, etching and film deposition.
With the fabrication method of the semiconductor integrated [0168] circuit 10 according to the first embodiment described above, since the global signal wiring that pass obliquely over the function block 2, and the buffering cells 3 may be easily configured utilizing the CAD system, the time necessary for development of the semiconductor integrated circuit 10 to product completion may be shortened.
Second Embodiment [0169]
A second embodiment of the present invention is one for describing an example that comprises a [0170] buffering cell 3 in a function block 2 and a global signal wiring 4 to pass obliquely over the function block 2 inside of the semiconductor integrated circuit 10 according to the first embodiment.
As shown in FIG. 17, the semiconductor integrated [0171] circuit 10 according to the second embodiment comprises a function block 2 upon a substrate 1, a plurality of buffering cells 3(3 ₁₁-3 ₃₅) arranged in the function block 2 regularly inside at an appointed interval, and the global signal wiring 4 at least one part of which extends in the direction oblique to the side of the function block 2 and is connected between adjacent buffering cells 3.
The [0172] buffering cell 3 is arranged in the function block 2 beforehand, and it is used appropriately when it is necessary for the global signal wiring 4 to pass. In FIG. 17, a broken line is added for convenience to explain intelligibly an arrangement layout of the buffering cell 3, but there is not a broken line on the function block 2 of the semiconductor integrated circuit 10 of the real product. On a monitor screen of a CAD system, the broken line as grid can be displayed in order to do a design easily. In the second embodiment, the buffering cell 3 is arranged at an interval by an X direction and a Y direction. In other words, the buffering cell 3 is arranged at a crossing (coordinates) of the broken line arranged at intervals of each in an X direction and a Y direction, or in each corner part of a square sectioned in the broken line.
Furthermore, the buffering [0173] cell 3 according to the second embodiment comprises the first buffering cell 3A and the second buffering cell 3B whose drive ability differs from each other, as one set. Here, the first buffering cell 3A comprises the buffering cell 3 having the output inverter circuit 302 of one-step structure shown in FIG. 7A, for example. The second buffering cell 3B comprises the buffering cell 3 having output the inverter circuit 302 of two-step structure shown in FIG. 8A, for example. In other words, the second drive ability of the buffering cell 3B is stronger than the first buffering cell 3A.
In addition, the [0174] first buffering cell 3A may comprise the buffering cell 3 shown in FIG. 8A or FIG. 9A, the second buffering cell 3B may comprise the buffering cell 3 shown in FIG. 9A or FIG. 10. Furthermore, in the first buffering cell 3A and the second buffering cell 3B, the number of steps of output inverter circuit 302 are made the same, and by means of changing a gate width of IGFET Q of the inverter circuit 302, a drive ability may be adjusted.
As shown in FIG. 17, the [0175] global signal wiring 4 passes the buffering cell 3 ₁₁, 3 ₂₂, 3 ₃₃, and 3₃₅respectively, and connects a input terminal S3 arranged by the second side (appearances) 2 b of the function block 2 and the output terminal S4 arranged on the fourth side (a lower side) 2 d of the function block 2. In other words, the global signal wiring 4 extends from the input terminal S3 to the lower side (Y direction), connecting to the buffering cell 3 ₁₁at first. The first buffering cell 3A is used for this buffering cell 3 ₁₁because it does not need a strong drive ability so that a distance from the next buffering cell 3 ₂₂can be comparatively short. And, the global signal wiring 4 extends from the buffering cell 3 ₁₁to the lower right side as a signal wiring which is inclined by an angle of 45 degrees relative to the second side 2 b, connecting to the buffering cell 3 ₂₂. The first buffering cell 3A is used for this buffering cell 3 ₂₂because it does not need a strong drive ability so that a distance from the next buffering cell 3 ₃₃can be comparatively short. Similarly, the global signal wiring 4 extends from buffering cell 3 ₂₂to the lower right side as a signal wiring which is inclined by an angle of 45 degrees relative to the second side 2 b, connecting to the buffering cell 3 ₃₃. The second buffering cell 3B is used for this buffering cell 3 ₃₃because it needs a strong drive ability so that a distance from the next buffering cell 3 ₃₅is comparatively long. Furthermore, the global signal wiring 4 extends from the buffering cell 3 ₃₃to the lower side (Y direction), connecting to the buffering cell 3 ₃₅. The second buffering cell 3B is used for this buffering cell 3 ₃₅because it needs a strong drive ability to drive an outside circuit of function block 2 through the output side S4. And, the global signal wiring 4 extends from the buffering cell 335 to the lower side (Y direction), connecting to the output terminal S4.
With the semiconductor integrated [0176] circuit 10 according to the second embodiment configured in this manner, the global signal wiring 4 can pass over the function block 2 of a huge size more than a limit of wiring length, by using a plurality of buffering cells 3 arranged in the function block 2 regularly as intermediate cells.
Furthermore, a route of the [0177] global signal wiring 4 to pass over the function block 2 can be predicted easily by having cells 3 arranged regularly. Therefore, by arranging the electric shield layer on a route of the global signal wiring 4 to pass the function block 2 beforehand, an electric interference between the function block 2 and the global signal wiring 4 to pass over the function block 2 can be minimized.
Furthermore, by using an oblique signal wiring with more than one in connection of the [0178] buffering cells 3 in the function block 2, bypassing signal wiring in the function block 2 is reduced, and route length of the global signal wiring 4 can be shortened.
With the semiconductor integrated [0179] circuit 10 according to the second embodiment, the buffering cells 3 in the function block 2 may be arranged at positions corresponding to each corner part such as in a triangle, hexagon, not only a square sectioned by the broken line which is added in convenience. In addition, the buffering cells 3 may comprise more than three buffering cells, and are not limited to being the first buffering cell 3A and the second buffering cell 3B.
Third Embodiment [0180]
A third embodiment of the present invention is described using an example that prevents cross talk between global signal wirings passing over the [0181] function block 2 in the semiconductor integrated circuit 10 according to the first embodiment.
As shown in FIG. 18, the semiconductor integrated [0182] circuit 10 according to the third embodiment comprises a wave guide 410 and 411 that are arranged adjacent to a signal wiring 40 a and 40 b passing over the function block 2 obliquely, extending substantially parallel to a signal wiring 40 a and 40 b. A fixed power supply is supplied in the wave guide 410 and 411. Furthermore, the semiconductor integrated circuit 10 according to the third embodiment comprises the wave guide 411 and 412 that are arranged adjacent to the signal wiring 41 a and 41 b passing over the function block 2 obliquely, extending substantially parallel to the signal wiring 41 a and 41 b. A fixed power supply is supplied in the wave guide 411 and 412.
The [0183] signal wiring 40 a and 40 b and the signal wiring 41 a and 41 b are global signal wirings and used as a bus, for example. By arranging the wave guide 410 along one side of signal wiring 40 a and 40 b (bottom in a figure), and arranging wave guide 411 along another side (the upper part in a figure), there can be a layout which arranges signal wiring 40 a and 40 b between wave guide 410 and 411. Similarly, by arranging the wave guide 411 along one side of signal wiring 41 a and 41 b (bottom in a figure), and arranging the wave guide 412 along another side (the upper part in a figure), there can be a layout which arranges signal wiring 41 a and 41 b between wave guide 411 and 412.
The [0184] signal wiring 40 a and 41 a and the wave guide 410 to 412 which is arranged in parallel to the signal wiring 40 a and 41 a, are set in the same wiring layer to reduce electric interference between the signal wiring 40 a and 41 a. And it is desirable for width of the wave guide 410 to 412 not to exceed a thickness of the wave guide 410 to 412 in order to keep down an occupation area to a minimum. Similarly, the signal wiring 40 b and 41 b and the wave guide 410 to 412, arranged in parallel to the signal wiring 40 a and 41 a, are set in the same wiring layer. The wiring layer in which the signal wiring 40 a and 41 a is arranged is basically different from the wiring layer in which the signal wiring 40 b and 41 b is arranged.
In addition, on a database of a CAD system, the [0185] wave guide 410 to 412 are built in beforehand by data of the global signal wiring. In other words, the wave guide 410 to 412 can be designed at the same time as designing the global signal wiring. It is not necessary to design the wave guide 410 to 412 after designing the global signal wiring. It is practical to supply 0V that has a reference power supply V_ssin the wave guide 410 to 412, for example.
With the semiconductor integrated [0186] circuit 10 according to the third embodiment configured in this manner, since the wave guide 411 is arranged between the signal wiring 40 a and 40 b and between the signal wiring 41 a and 41 b at least, occurrence of electric interference, namely cross talk, can be reduced.
Other Embodiments [0187]
As described above, the semiconductor integrated [0188] circuit 10 according to the first through third embodiments comprises the function block 2 arranged on substrate 1 (semiconductor wafer, a semiconductor chip, etc) comprising of a silicon single crystal, and the global signal wiring passing over the function block 2. These embodiment can be applied to the semiconductor integrated circuit (a system board, a mother board, a logic board, a memory board, etc) which comprises a wiring substrate in which a semiconductor integrated circuit 10 considered to be the function block 2 is included and the global signal wiring passes over the wiring substrate. A printed circuit board (PCB), a ceramics substrate, a carbonization silicon substrate, a glass substrate or the like can be used practically for the wiring substrate.
Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof. [0189]

Claims

What is claimed is:

1. A semiconductor integrated circuit comprising:

a function block arranged on a substrate;

a first buffering cell arranged adjacent to a first side of the function block;

a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block; and

signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.

2. The semiconductor integrated circuit of claim 1, further comprising:

a first signal wiring extending in an X direction, which extends obliquely relative to the signal wiring; and

a second signal wiring extending in a Y direction, which is perpendicular to the first signal wiring and extends obliquely relative to the signal wiring.

3. The semiconductor integrated circuit of claim 2, wherein the signal wiring is arranged in a layer higher than the layer in which the first signal wiring and the second signal wiring are arranged.

4. The semiconductor integrated circuit of claim 2, wherein the signal wiring has an intersecting angle either 45 degrees and 135 degree relative to either of the first signal wiring and the second signal wiring.

5. The semiconductor integrated circuit of claim 1, wherein the signal wiring is a global signal wiring including one of a data bus and an address bus, arranged substantially in the entire area on the substrate.

6. The semiconductor integrated circuit of claim 1, wherein the first buffering cell and the second buffering cell are arranged outside of the function block.

7. The semiconductor integrated circuit of claim 1, further comprising a wave guide arranged adjacent to the signal wiring and extending substantially parallel to the signal.

8. A semiconductor integrated circuit comprising:

a function block arranged on a substrate;

a plurality of signal wirings having a length shorter than a length of a side of the function block on the substrate;

a plurality of buffering cells electrically connected in series between each of the signal wirings; and

a signal wiring passing obliquely across the corner between a first side and a second side of the function block, which connects the buffering cells arranged adjacent to the first side and adjacent to the second side adjacent to the first side of the function block.

9. A semiconductor integrated circuit comprising:

a function block arranged on a substrate;

a plurality of buffering cells arranged regularly in the function block at an appointed interval; and

a signal wiring extending obliquely relative to a side of the function block, which is connected between adjacent buffering cells.

10. The semiconductor integrated circuit of claim 9, wherein each of the buffering cells comprises a first buffering cell and a second buffering cell having different drive abilities respectively.

11. The semiconductor integrated circuit of claim 9, wherein the signal wiring is a global signal wiring including one of a data bus and an address bus, arranged substantially in the entire area on the substrate and passes over the function block.

12. A method for manufacturing a semiconductor integrated circuit comprising:

arranging a function block on a substrate;

arranging a signal wiring which passes over the function block obliquely relative to a first side and a second side adjacent to the first side of the function block; and

arranging a first buffering cell connected to one end of the signal wiring, adjacent to the first side of the function block and a second buffering cell connected to another end of the signal wiring, adjacent to the second side of the function block.

13. A method for manufacturing a semiconductor integrated circuit comprising:

arranging a plurality of function blocks on a substrate;

extracting a first function block with minimum signal loss in the function blocks in a signal wiring route;

extracting a second function block arranged near the first function block;

arranging a signal wiring which passes obliquely relative to a first side and a second side adjacent to the first side of the second function block;

determining whether a length of the signal wiring exceeds the signal wiring length limitation;

determining whether signal timing satisfies a design rule at least when the length of the signal wiring exceeds the signal wiring length limitation;

determining whether a buffering cell can be arranged when the signal timing fails to satisfy the design rule; and

arranging a first buffering cell connected to one end of the signal wiring, adjacent to the first side of the second function block and a second buffering cell connected to another end of the signal wiring, adjacent to the second side of the second function block.