US20040188765A1 - Cmos device integration for low external resistance - Google Patents
Cmos device integration for low external resistance Download PDFInfo
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- US20040188765A1 US20040188765A1 US10/249,295 US24929503A US2004188765A1 US 20040188765 A1 US20040188765 A1 US 20040188765A1 US 24929503 A US24929503 A US 24929503A US 2004188765 A1 US2004188765 A1 US 2004188765A1
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- 230000010354 integration Effects 0.000 title description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 187
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 138
- 238000000034 method Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 125000006850 spacer group Chemical group 0.000 claims description 65
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 239000002019 doping agent Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 12
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 230000007423 decrease Effects 0.000 abstract description 7
- 230000000295 complement effect Effects 0.000 abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 3
- 150000004706 metal oxides Chemical class 0.000 abstract description 3
- 238000010348 incorporation Methods 0.000 abstract 2
- 239000007943 implant Substances 0.000 description 35
- 239000004020 conductor Substances 0.000 description 17
- 239000000463 material Substances 0.000 description 11
- 230000008569 process Effects 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 229910052785 arsenic Inorganic materials 0.000 description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000004913 activation Effects 0.000 description 5
- 230000003247 decreasing effect Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910021478 group 5 element Inorganic materials 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000224 chemical solution deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910004481 Ta2O3 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Definitions
- the present invention relates to semiconductor devices and methods of fabricating semiconductor devices, and more particularly to an improved Complementary Metal Oxide Semiconductor (CMOS) device with a lower external resistance and a method for fabricating the improved CMOS device.
- CMOS Complementary Metal Oxide Semiconductor
- FETs field effect transistors
- MOSFETs metal-oxide-semiconductor field effect transistors
- CMOS complementary metal oxide semiconductors
- Rext also known as source/drain resistance.
- External resistance is the sum of all of the resistance values in a MOSFET device except for channel resistance. The external resistance is attributed to doping and diffusion of the wafer as well as the silicidation process.
- a gate region 5 is formed atop a Si-containing substrate 10 .
- the gate region 5 includes a gate silicide 4 atop a gate conductor 3 , which is positioned atop a gate dielectric 2 .
- the Si-containing substrate 10 includes deep source/drain regions 6 , source/drain extensions 7 , thick silicide contacts 8 , and a channel region 9 .
- the source/drain extensions 7 partially extend under the gate region 5 .
- the electron path W 1 through which the current of electron flow to reach the silicide region 8 begins at the end of the source/drain extensions 7 abutting the channel region 9 and extends to the thick silicide region 8 . Decreasing the dimensions of the electron path W 1 increases the performance of the device. Therefore, it would be desirable to decrease the electron path W 1 by decreasing the distance between the silicide region and the end of the source/drain extension regions 7 abutting the channel region 9 .
- the electron path W 1 i.e., path of current through the source/drain extension region 7 prior to reaching the low-resistance thick silicide 8 , is on the order of 60 nm.
- the thick silicide 8 cannot be brought closer to the channel for the following reasons:
- the final spacer width must be reduced, decreasing the distance between the deep source/drain regions 6 and the channel region 9 . Decreasing the proximity between the deep source/drain regions 6 and the channel region 9 increases the interaction between the deep source/drain regions 6 and the channel region 9 resulting in increased short channel effects. Short channel effects are well known to those skilled in the art as a decrease in threshold voltage, Vt, due to electrical charge sharing between the gate and the source drain regions, resulting in degradation of the devices ability to control whether the device is on or off.
- the present invention provides a MOSFET device that has a low external resistance and a method for producing such a low external resistance MOSFET device.
- Conventional device designs have an external resistance on the order of 200-300 ohm-micron for NFET devices.
- the inventive MOSFET has a low external resistance that is about 10% to 50% less than conventional designs.
- the inventive MOSFET device also incorporates low sheet resistance interconnects. In high performance chip designs, it is desirable to produce low external resistance devices incorporating low resistance contacts for interconnects between the devices incorporated within the chip.
- the inventive MOSFET device achieves a low external resistance through the application of a first and second silicide region where the first silicide region is of a lesser thickness than the second silicide region and is in close proximity to the channel region of the device.
- First silicide regions are thinner than conventional silicide regions and therefore avoid the disadvantages inherent in spacing conventional silicides in close proximity to the channel region.
- Second silicide regions have a greater thickness than first silicide regions and provide low sheet resistance interconnects for the devices incorporated within the chip.
- the first silicide region can be brought to within about 2 nm to about 15 nm of the source/drain extension tip at the channel end. This is much closer than the distance used in conventional MOSFET designs, which is on the order of approximately 60 nm.
- the first silicide region is of a lower resistance than the source/drain extension regions.
- the method of the present invention comprises the steps of:
- first silicide regions having a first silicide thickness in the substrate as well as atop an exposed surface of the gate region
- One embodiment of the present invention is directed to a method for producing a low resistance N-type doped Field Effect Transistor (NFET) device.
- NFET Field Effect Transistor
- Doping a Si-containing substrate with a group V element of the Periodic Table of Elements typically produces an NFET device.
- predoping of the gate can be implemented.
- a second implant forms source/drain extension regions.
- deep source/drain regions are formed using a further implant.
- a second embodiment of the present invention is directed to a method for producing a low resistance P-type doped field effect transistor (PFET) device.
- PFET devices are typically produced within Si-containing substrates by doping the substrate with a group III-A element of the Periodic Table of Elements.
- PFET devices incorporating first silicide regions using one implant for the source/drain extensions and a second implant for the deep/source drain regions, it is possible to produce both the source/drain extensions and the deep source/drain regions using a single implant.
- the inventive low resistance MOSFET comprises:
- a substrate comprising a first silicide region with a first silicide thickness and abutting a second silicide region with a second silicide thickness, wherein the second silicide thickness is greater than the first silicide thickness;
- second spacers abutting sidewalls of the first spacers, said second spacers having a second spacer width greater than the first spacer width, wherein the second spacers are positioned atop and are self-aligned to said first silicide region.
- FIG. 1 is a pictorial representation (through a cross-sectional view) showing a conventional MOSFET device incorporating thick silicide regions spaced approximately 60 nm from the channel region.
- FIG. 2 is a pictorial representation (through a cross-sectional view) of the inventive MOSFET device incorporating a thin silicide region in close proximity to the channel region.
- FIG. 3( a )-( h ) are pictorial representations (through a cross-sectional views) showing the basic processing steps that are employed in one embodiment of the present invention.
- a NFET device incorporating a thin silicide region in close proximity to the channel region is produced.
- FIGS. 4 ( a )-( g ) are pictorial representations (through cross-sectional views) showing the basic processing steps that are employed in another embodiment of the present invention.
- a PFET device incorporating a thin silicide region in close proximity to the channel region is produced.
- FIG. 2 depicts the MOSFET device of the present invention.
- the inventive MOSFET device includes a first silicide region 11 having a first silicide thickness T 1 , and a second silicide region 12 having a second silicide thickness T 2 , where the second silicide thickness T 2 is greater than the first silicide thickness T 1 .
- the inventive MOSFET device also includes a gate region 5 positioned atop a substrate 10 .
- the gate region 5 includes a gate dielectric 2 ; a gate conductor 3 having sidewalls protected by an oxide layer (not specifically labeled) positioned atop the gate dielectric 2 ; and a gate silicide 4 positioned atop the gate conductor 3 .
- the substrate 10 includes deep source/drain regions 6 , source/drain extensions 7 , first silicide regions 11 and second silicide regions 12 .
- First spacers 14 having a first spacer width W 2 , abut the gate region 5 .
- Second spacers 15 having a second spacer width W 3 greater than first spacer width W 2 , are formed atop and self-aligned to the first silicide regions 11 as well as abutting first spacers 14 .
- Second silicide regions 12 function as low resistivity contacts incorporated into chip designs requiring low sheet resistance interconnects.
- the first silicide regions 11 allow for low resistivity silicide to be positioned closer to the channel region 9 of the device.
- the electron path W 4 through which current flows before reaching low resistivity silicide can be reduced to less than about 20 nm, more preferably less than about 5 nm.
- Another aspect of the present invention includes the method for producing the inventive MOSFET device incorporating first and second silicide regions. Reference is made to the embodiment shown in FIGS. 3 ( a )- 3 ( h ).
- a low external resistance NFET is produced by incorporating a first silicide region 11 , having a thickness of the order of about 2 nm to about 15 nm, in close proximity to the channel region 9 of the device.
- a patterned gate region 5 is formed atop a substrate 10 utilizing conventional methods including deposition and lithography.
- the pattern gate region 5 includes a gate conductor 3 positioned atop a gate dielectric 2 .
- the substrate 10 includes, but is not limited to: any semiconducting material such conventional Si-containing materials, GaAs, InAs and other like semiconductors.
- Si-containing materials include, but are not limited to: Si, bulk Si, single crystal Si, polycrystalline Si, SiGe, amorphous Si, silicon-on-insulator substrates (SOI), SiGe-on-insulator (SGOI), annealed poly Si, and poly Si line structures.
- Layered semiconductors such as Si/Ge are also contemplated herein.
- the gate dielectric 2 formed atop the substrate 10 , is typically an oxide material and is generally greater than 0.8 nm thick, and preferably about 1.0 nm to about 1.2 nm thick.
- the gate dielectric 2 may also be composed of a nitride, oxynitride, or combination thereof, with and without the oxide material.
- the gate dielectric 2 is formed using conventional techniques such as chemical vapor deposition (CVD), atomic layer CVD (ALCVD), pulsed CVD, plasma assisted CVD, sputtering, and chemical solution deposition, or alternatively, the gate dielectric 2 is formed by a thermal growing process, which may include oxidation, oxynitridation, nitridation, and/or plasma or radical treatment.
- Suitable examples of oxides that can be employed as the gate dielectric 2 include, but are not limited to: SiO2, Al 2 O3, ZrO2, HfO2, Ta 2 O3, TiO2, perovskite-type oxides and combinations and multi-layers thereof.
- the gate dielectric 2 can be in either amorphous, polycrystalline, or epitaxial form.
- the gate conductor 3 can be comprised of polysilicon or an appropriate metal.
- the gate conductor 3 is formed atop the gate dielectric 2 utilizing a conventional deposition process such as CVD and sputtering.
- the patterned gate region 5 is formed utilizing conventional photolithography and etching. Specifically, a pattern is produced by applying a photoresist to the surface to be patterned; exposing the photoresist to a pattern of radiation; and then developing the pattern into the photoresist utilizing a conventional resist developer. Once the patterning of the photoresist is completed, the sections covered by the photoresist are protected, while the exposed regions are removed using a selective etching process that removes the unprotected regions. Following the formation of the patterned gate region 5 , a protection oxide layer is formed about and protecting the patterned gate region 5 . The protection oxide layer is produced by thermal oxidation of the gate region 5 .
- a pre-doping of the gate conductor 3 may be performed at this point of the present invention. Predoping of the gate conductor allows for the utilization of elements with high diffusion rates, while avoiding diffusion of the implanted elements from the source/drain regions 6 into the channel region 9 of the device that increase the incidence of short channel effects.
- phosphorus predoping of the gate conductor 3 is preferred, for its high diffusion rate, but must be implemented in a pre-dope of only the gate region 5 in order to avoid channel effects within the substrate 10 .
- Pre-doping is utilized to avoid applying the heavy dose/fast diffusing species required in the gate region 9 from being applied to the source/drain region 6 where it will encroach into the channel region 9 and produce a short channel effect.
- the pre-dope may be conducted during deposition of the gate conductor material prior to patterning and etch; after etching of the gate conductor 3 ; or in-situ.
- a typical gate implant dose range is from about 5 ⁇ 10 15 atoms/cm 2 to about 2 ⁇ 10 16 atoms/cm 2 , with an optimal dose of about 8 ⁇ 10 15 atoms/cm 2 .
- the implant energy is kept substantially low to prevent penetration of implanted species into the substrate 10 .
- the implant energy should be substantially large to allow for ion penetration into the gate conductor 3 .
- a typical implant energy range is from about 1 to about 20 keV, with an optimal energy of approximately 12 keV.
- Implant dopants may be type III-A elements or a type V elements. Implant energies depend on the species being implanted, the above described implant energies are most suitable for phosphorous.
- An optional block-mask can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.
- the block-mask application and implantation procedure can be repeated to dope selected gate conductors with different dopant types.
- source/drain extension regions 7 are formed in substrate 10 and partially extend under the gate region 5 .
- Source/drain extension regions 7 are formed via ion implantation and comprise a combination of normally incident and angled implants to form the desired grading in the extensions.
- arsenic as opposed to phosphorus, is preferred in order to avoid short channel-effect degradation caused by source/drain encroachment into the channel region that occurs when utilizing implant elements with a high rate of diffusion.
- arsenic implants are preferred, other group V elements utilized to form NFET devices may be incorporated into the inventive method, also including phosphorus and antimony.
- Implant energies for forming source/drain extension regions 7 are typically: from about 1 keV to about 5 keV, preferably about 3 keV, for arsenic; from about 1 keV to about 7 keV, preferably about 4 keV, for BF 2 ; and from about 1 keV to about 2 keV, preferably about 1 keV, for boron. These implants are typically carried out using a low concentration of dopant dose on the order of 5 ⁇ 10 14 atoms/cm 2 ⁇ 2 ⁇ 10 15 atoms/cm 2 , preferably about 1 ⁇ 10 15 atoms/cm 2
- first spacers 14 are formed abutting the gate region 5 as depicted in FIG. 3( c ).
- First spacers 14 are formed using conventional deposition and etch processes that are well known in the art.
- First spacers 14 have a first spacer width W 2 of preferably from about 3 nm to about 40 nm; more preferably about 5.0 nm to about 20.0 nm; even more preferably from about 7.0 nm to about 15.0 nm; and most preferably about 10 nm.
- First spacer width W 2 is less than second spacer width W 3 .
- First spacer 14 may be comprised of a dielectric material such as a nitride. The first spacer 14 materials most preferably comprise SiN.
- a higher energy ion implant is conducted to form deep source/drain regions 6 .
- These implants are typically carried out using a high concentration of dopant dose on the order of about 1 ⁇ 10 15 atoms/cm 2 to about 5 ⁇ 10 15 atoms/cm 2 , preferably about 3 ⁇ 10 15 atoms/cm 2 .
- Implant energy is dependent on implant species and substrate; i.e., arsenic implant of a SOI CMOS substrate typically requires an implant from about 10 keV to about 20 keV.
- Deep source/drain regions 6 are preferably formed using a group V dopant implant, preferably arsenic because it diffuses into the substrate slowly.
- Group IIIA elements may also be utilized as the implant for deep source/drain 6 formation.
- the source/drain and gate regions are activated by activation annealing using conventional processes such as, but not limited to: rapid thermal annealing, furnace annealing or flashlamp annealing.
- Activation anneal is conducted at a temperature above 850° C. with an optimal temperature of about 1000° C.
- This step of the present invention activates the dopant atoms, which changes the conductivity of the Si-containing material to which the dopants were implanted.
- the resultant structure produced during activation anneal is depicted in FIG. 3( e ).
- the inventive first silicide region 11 is formed as depicted in FIG. 3( f ).
- Silicide formation typically requires depositing a metal layer onto the surface of a Si-containing material or wafer.
- the metal layer may be formed using a conventional process including, but not limited to: chemical vapor deposition (CVD), plasma-assisted CVD, high-density chemical vapor deposition (HDCVD), plating, sputtering, evaporation and chemical solution deposition.
- Metals deposited for silicide formation include Ta, Ti, W, Pt, Co, Ni, and combinations thereof, most preferably Co.
- the structure is then subjected to an annealing step using conventional processes such as, but not limited to: rapid thermal annealing.
- the deposited metal reacts with Si forming a metal silicide.
- Metal is deposited onto exposed portions of source/drain extension regions 7 to form a metal layer with a thickness from about 2 nm to about 7 nm, preferably about 2 nm.
- Depositing a 2 nm thick layer of Co atop a Si-containing material forms a thin silicide layer 11 having a thickness of about 7 nm.
- Metal is also deposited atop the gate conductor 3 and forms a gate silicide region 4 .
- First silicide region 11 has a first silicide thickness T 1 of about 1 nm to about 20 nm, preferably from about 2.0 nm to about 15 nm, even more preferably from about 5.0 nm to about 12.0 nm, and most preferably from about 7.0 nm to about 10.0 nm.
- Second silicide thickness T 2 is greater than first silicide thickness T 1 .
- the end of the first silicide region 11 closest to the channel region 9 of the device is spaced, W 4 , about 2 nm to about 15 nm, preferably about 3 nm to about 10 nm, most preferably about 7 nm, from the end of the source/drain extension regions 7 abutting the channel region 9 .
- the introduction of the low resistance first silicide region 11 into the source/drain extension region 7 in closer proximity to the channel region 9 than previously possible decreases the external resistance of the device.
- second spacers 15 are formed atop thin silicide region and abutting first spacers 14 .
- Second spacers 15 are formed using conventional deposition and etching processes that are well known in the art and have a second spacer width W 3 from about 20 nm to about 90 nm, preferably from about 30 nm to about 70 nm, even more preferably from about 40 nm to about 60 nm, and most preferably 50 nm.
- Second spacer width W 3 is greater than first spacer width W 2 .
- Second spacer 15 may be comprised of a dielectric material such as a nitride, oxide, oxynitride, or a combination thereof. Second spacer 15 materials most preferably comprise SiN.
- second silicide regions having second silicide thickness T 2 are formed as depicted in FIG. 3( h ).
- Second silicide regions 12 are thicker, having a greater depth dimension from the surface of the substrate T 2 , than first silicide region 11 .
- Second silicide 12 formation requires that further metal be deposited atop exposed silicide regions not protected by first and second spacers 14 , 15 .
- First silicide region 11 is self-aligned to and protected from further metal deposition by second spacers 15 .
- Metals deposited for second silicide 12 formation include Ta, Ti, W, Pt, Co, Ni, and combinations thereof, most preferably Co.
- the metal layer formed after second deposition has a thickness ranging from about 6 nm to about 10 nm.
- the structure is then subjected to an annealing step, at a temperature of about 400° C. to about 850° C. using conventional processes such as, but not limited to: rapid thermal annealing.
- the anneal process for silicide formation is dependent on the metal utilized; i.e., for Co the first temperature for monosilicide formation is about 500° C., while the second temperature for disilicide formation is about 750° C.
- the resulting thickness T 2 of the second silicide region 12 is from about 10 nm to about 40 nm thick, preferably from about 15 nm to about 35 nm thick, more preferably from about 20 nm to about 35 nm thick, even more preferably from about 20 nm to about 30 nm thick; and most preferably about 20 nm thick.
- the resultant NFET comprises a second silicide region 72 and a first silicide region 11 ; where the first silicide region 11 decreases the external resistance of the device and the second silicide region 12 serves as a low resistance interconnect.
- a second anneal may be conducted in order to produce a lower resistivity phase of the first and second silicide regions 11 , 12 .
- the C49 phase of TiSi 2 forms at an anneal temperature of approximately 600° C. to 625° C. and has a resistivity of approximately 60 to 65 micro-ohms-cm, while the C54 phase, produced after a second anneal of about 800° C. or greater, has a much lower resistivity of about 10 to about 15 micro-ohms-cm.
- a second embodiment of the present invention is a method for producing a low resistance PFET as depicted in FIGS. 4 ( a )- 4 ( g ). It is possible to integrate PFET production in a manner analogous to the NFET, with the exception of changing the doping materials from group V elements to group IIIA elements. Alternatively, a second embodiment of the inventive method produces low resistance PFET devices utilizing a single implant to form both source/drain extensions and deep source/drain regions. Utilizing a single implant to produce both the source/drain extension and the deep source/drain regions substantially reduces encroachment of the implant elements upon the channel and the likelihood of short channel effects.
- a single low energy implant (please enter the energy of the implant) is introduced via ion implantation to form a shallow source/drain extension 20 .
- Implant energies for forming source/drain regions 7 are typically: from about 1 keV to about 5 keV, preferably about 3 keV, for arsenic; from about 1 keV to about 7 keV, preferably about 4 keV, for BF 2 ; and from about 1 keV to about 2 keV, preferably about 1 keV, for boron.
- an activation anneal is conducted at approximately 850° C., more preferably at about 1000° C. as depicted in FIG. 3( d ).
- boron is preferred, other type III elements may be utilized for producing PFET devices.
- First silicide regions 11 are formed, as described in the above method for producing NFET devices.
- First silicide regions 11 have a thickness T 1 of about 5 nm to about 15 nm and allow for the silicide region to be brought within 2 nm to about 15 nm, preferably about 7 nm, of the end of the shallow source/drain extension 20 abutting the channel region 9 of the device.
- second spacers 15 are formed atop first silicide 11 regions and second silicide 12 region formed following the same or similar process steps as described above for producing NFET devices.
- the resultant PFET comprises a second silicide region 12 and a first silicide region 11 ; where the first silicide region 11 decreases the external resistance of the device and the second silicide region 12 serves as a low resistance interconnect.
Abstract
Description
- The present invention relates to semiconductor devices and methods of fabricating semiconductor devices, and more particularly to an improved Complementary Metal Oxide Semiconductor (CMOS) device with a lower external resistance and a method for fabricating the improved CMOS device.
- An important property of high performance semiconductor devices is the ability to conduct electricity. Current is inversely related to resistance. Traditionally, increasing the cross section of the semiconducting material; shortening the length for the electron path; increasing the voltage; or decreasing the resistivity of the semiconducting material can all decrease resistivity and increase electron flow through electrical devices.
- In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device while maintaining the device's electrical properties.
- Additionally, all dimensions of the device must be scaled simultaneously in order to optimize electrical performance of a device.
- One of the primary challenges to MOSFET scaling is lowering the device's external resistance (Rext), also known as source/drain resistance. External resistance is the sum of all of the resistance values in a MOSFET device except for channel resistance. The external resistance is attributed to doping and diffusion of the wafer as well as the silicidation process. When scaling MOSFET devices, and if the device gate-length and the gate oxide thickness are reduced and the external resistance is held constant, then the performance benefits achieved through scaling will be limited.
- In conventional MOSFET designs, as depicted in FIG. 1, a
gate region 5 is formed atop a Si-containingsubstrate 10. Thegate region 5 includes agate silicide 4 atop agate conductor 3, which is positioned atop a gate dielectric 2. The Si-containingsubstrate 10 includes deep source/drain regions 6, source/drain extensions 7,thick silicide contacts 8, and achannel region 9. The source/drain extensions 7 partially extend under thegate region 5. The electron path W1, through which the current of electron flow to reach thesilicide region 8 begins at the end of the source/drain extensions 7 abutting thechannel region 9 and extends to thethick silicide region 8. Decreasing the dimensions of the electron path W1 increases the performance of the device. Therefore, it would be desirable to decrease the electron path W1 by decreasing the distance between the silicide region and the end of the source/drain extension regions 7 abutting thechannel region 9. - Utilizing current MOSFET designs, the electron path W1, i.e., path of current through the source/
drain extension region 7 prior to reaching the low-resistancethick silicide 8, is on the order of 60 nm. In conventional MOSFET designs, thethick silicide 8 cannot be brought closer to the channel for the following reasons: - First, conventional MOSFET designs utilize thick silicide layers for reducing the sheet resistance between the devices incorporated in the chip's design. The thicker the silicide, the greater the cross-section of the interconnect, resulting in a low resistance/high current interconnect. Thick silicides form into the substrate in both horizontal and vertical directions during anneal processing steps and therefore must have appropriate spacing away from the extension edge at the channel-end tip and the extension edge at the bottom of the junction.
- For example, when utilizing cobalt for silicidation, a 5-10 nm deposited Co layer will diffuse to a depth of approximately 20-40 nm and will also diffuse laterally. Thick silicide regions can give rise to a substantial degree of interface roughness, which can lead to punch-through of the thin extension junctions. Punch-through can lead to excessive level of junction leakage. The above limit on how close a silicide may be brought to the channel without statistical failure or penalty in yield is a fundamental integration constraint for the conventional MOSFET.
- Second, in order to bring the silicide closer to the
channel region 9, the final spacer width must be reduced, decreasing the distance between the deep source/drain regions 6and thechannel region 9. Decreasing the proximity between the deep source/drain regions 6and thechannel region 9 increases the interaction between the deep source/drain regions 6 and thechannel region 9 resulting in increased short channel effects. Short channel effects are well known to those skilled in the art as a decrease in threshold voltage, Vt, due to electrical charge sharing between the gate and the source drain regions, resulting in degradation of the devices ability to control whether the device is on or off. - It would be desirable to provide a MOSFET device that has a minimized external resistance.
- The present invention provides a MOSFET device that has a low external resistance and a method for producing such a low external resistance MOSFET device. Conventional device designs have an external resistance on the order of 200-300 ohm-micron for NFET devices. The inventive MOSFET has a low external resistance that is about 10% to 50% less than conventional designs. The inventive MOSFET device also incorporates low sheet resistance interconnects. In high performance chip designs, it is desirable to produce low external resistance devices incorporating low resistance contacts for interconnects between the devices incorporated within the chip. The inventive MOSFET device achieves a low external resistance through the application of a first and second silicide region where the first silicide region is of a lesser thickness than the second silicide region and is in close proximity to the channel region of the device. First silicide regions are thinner than conventional silicide regions and therefore avoid the disadvantages inherent in spacing conventional silicides in close proximity to the channel region. Second silicide regions have a greater thickness than first silicide regions and provide low sheet resistance interconnects for the devices incorporated within the chip.
- The first silicide region, can be brought to within about 2 nm to about 15 nm of the source/drain extension tip at the channel end. This is much closer than the distance used in conventional MOSFET designs, which is on the order of approximately 60 nm. The first silicide region is of a lower resistance than the source/drain extension regions. By incorporating the first silicide into the source/drain extension region, the external resistance of the device of the present invention is reduced by the difference between the resistance of the source/drain extension region and the first silicide region.
- In broad terms, the method of the present invention comprises the steps of:
- forming a gate region atop a surface of a substrate;
- forming first spacers with a first spacer width on sidewalls of the gate region;
- forming first silicide regions having a first silicide thickness in the substrate as well as atop an exposed surface of the gate region;
- forming second spacers with a second width greater than the first spacer width on the substrate, wherein second spacers protect the first silicide region in the substrate; and
- forming second silicide regions in said substrate and atop said surface of the gate region, where the second silicide has a thickness that is greater than the first silicide thickness.
- One embodiment of the present invention is directed to a method for producing a low resistance N-type doped Field Effect Transistor (NFET) device. Doping a Si-containing substrate with a group V element of the Periodic Table of Elements typically produces an NFET device. When producing a low resistance NFET device incorporating first silicide regions, predoping of the gate can be implemented. Following gate pre-doping, a second implant forms source/drain extension regions. Finally, deep source/drain regions are formed using a further implant.
- A second embodiment of the present invention is directed to a method for producing a low resistance P-type doped field effect transistor (PFET) device. PFET devices are typically produced within Si-containing substrates by doping the substrate with a group III-A element of the Periodic Table of Elements. In addition to producing low resistance PFET devices incorporating first silicide regions using one implant for the source/drain extensions and a second implant for the deep/source drain regions, it is possible to produce both the source/drain extensions and the deep source/drain regions using a single implant.
- Another aspect of the present invention relates to a low resistance MOSFET produced using the method of the present invention. In broad terms, the inventive low resistance MOSFET comprises:
- a substrate comprising a first silicide region with a first silicide thickness and abutting a second silicide region with a second silicide thickness, wherein the second silicide thickness is greater than the first silicide thickness;
- a patterned gate region atop the substrate;
- first spacers abutting sidewalls of said pattern gate region having a first spacer width; and
- second spacers abutting sidewalls of the first spacers, said second spacers having a second spacer width greater than the first spacer width, wherein the second spacers are positioned atop and are self-aligned to said first silicide region.
- FIG. 1 is a pictorial representation (through a cross-sectional view) showing a conventional MOSFET device incorporating thick silicide regions spaced approximately 60 nm from the channel region.
- FIG. 2 is a pictorial representation (through a cross-sectional view) of the inventive MOSFET device incorporating a thin silicide region in close proximity to the channel region.
- FIG. 3(a)-(h) are pictorial representations (through a cross-sectional views) showing the basic processing steps that are employed in one embodiment of the present invention. In the illustrated embodiment, a NFET device incorporating a thin silicide region in close proximity to the channel region is produced.
- FIGS.4(a)-(g) are pictorial representations (through cross-sectional views) showing the basic processing steps that are employed in another embodiment of the present invention. In the illustrated embodiment, a PFET device incorporating a thin silicide region in close proximity to the channel region is produced.
- The present invention, which provides a method of fabricating a low external resistance MOSFET device as well as the MOSFET structure formed by the inventive method, will now be described in more detail by referring to the drawings that accompany the present application. It is noted that in the accompanying drawings, like reference numerals are used for describing like and corresponding elements.
- Reference is first made to FIG. 2, which depicts the MOSFET device of the present invention. The inventive MOSFET device, includes a
first silicide region 11 having a first silicide thickness T1, and asecond silicide region 12 having a second silicide thickness T2, where the second silicide thickness T2 is greater than the first silicide thickness T1. The inventive MOSFET device also includes agate region 5 positioned atop asubstrate 10. Thegate region 5 includes agate dielectric 2; agate conductor 3 having sidewalls protected by an oxide layer (not specifically labeled) positioned atop thegate dielectric 2; and agate silicide 4 positioned atop thegate conductor 3. Thesubstrate 10 includes deep source/drain regions 6, source/drain extensions 7,first silicide regions 11 andsecond silicide regions 12.First spacers 14, having a first spacer width W2, abut thegate region 5.Second spacers 15, having a second spacer width W3 greater than first spacer width W2, are formed atop and self-aligned to thefirst silicide regions 11 as well as abuttingfirst spacers 14. -
Second silicide regions 12 function as low resistivity contacts incorporated into chip designs requiring low sheet resistance interconnects. Thefirst silicide regions 11 allow for low resistivity silicide to be positioned closer to thechannel region 9 of the device. By incorporatingfirst silicide regions 11, the electron path W4 through which current flows before reaching low resistivity silicide can be reduced to less than about 20 nm, more preferably less than about 5 nm. - Another aspect of the present invention includes the method for producing the inventive MOSFET device incorporating first and second silicide regions. Reference is made to the embodiment shown in FIGS.3(a)-3(h). In the present invention, a low external resistance NFET is produced by incorporating a
first silicide region 11, having a thickness of the order of about 2 nm to about 15 nm, in close proximity to thechannel region 9 of the device. - Referring to FIG. 3(a), a
patterned gate region 5 is formed atop asubstrate 10 utilizing conventional methods including deposition and lithography. Thepattern gate region 5 includes agate conductor 3 positioned atop agate dielectric 2. Thesubstrate 10 includes, but is not limited to: any semiconducting material such conventional Si-containing materials, GaAs, InAs and other like semiconductors. Si-containing materials include, but are not limited to: Si, bulk Si, single crystal Si, polycrystalline Si, SiGe, amorphous Si, silicon-on-insulator substrates (SOI), SiGe-on-insulator (SGOI), annealed poly Si, and poly Si line structures. Layered semiconductors such as Si/Ge are also contemplated herein. - The
gate dielectric 2, formed atop thesubstrate 10, is typically an oxide material and is generally greater than 0.8 nm thick, and preferably about 1.0 nm to about 1.2 nm thick. Thegate dielectric 2 may also be composed of a nitride, oxynitride, or combination thereof, with and without the oxide material. Thegate dielectric 2 is formed using conventional techniques such as chemical vapor deposition (CVD), atomic layer CVD (ALCVD), pulsed CVD, plasma assisted CVD, sputtering, and chemical solution deposition, or alternatively, thegate dielectric 2 is formed by a thermal growing process, which may include oxidation, oxynitridation, nitridation, and/or plasma or radical treatment. Suitable examples of oxides that can be employed as thegate dielectric 2 include, but are not limited to: SiO2, Al2O3, ZrO2, HfO2, Ta2O3, TiO2, perovskite-type oxides and combinations and multi-layers thereof. Thegate dielectric 2 can be in either amorphous, polycrystalline, or epitaxial form. - The
gate conductor 3 can be comprised of polysilicon or an appropriate metal. Thegate conductor 3 is formed atop thegate dielectric 2 utilizing a conventional deposition process such as CVD and sputtering. - After forming
gate dielectric 2 andgate conductor 3, the patternedgate region 5 is formed utilizing conventional photolithography and etching. Specifically, a pattern is produced by applying a photoresist to the surface to be patterned; exposing the photoresist to a pattern of radiation; and then developing the pattern into the photoresist utilizing a conventional resist developer. Once the patterning of the photoresist is completed, the sections covered by the photoresist are protected, while the exposed regions are removed using a selective etching process that removes the unprotected regions. Following the formation of the patternedgate region 5, a protection oxide layer is formed about and protecting the patternedgate region 5. The protection oxide layer is produced by thermal oxidation of thegate region 5. - A pre-doping of the
gate conductor 3 may be performed at this point of the present invention. Predoping of the gate conductor allows for the utilization of elements with high diffusion rates, while avoiding diffusion of the implanted elements from the source/drain regions 6 into thechannel region 9 of the device that increase the incidence of short channel effects. When producing a NFET device, phosphorus predoping of thegate conductor 3 is preferred, for its high diffusion rate, but must be implemented in a pre-dope of only thegate region 5 in order to avoid channel effects within thesubstrate 10. Pre-doping is utilized to avoid applying the heavy dose/fast diffusing species required in thegate region 9 from being applied to the source/drain region 6 where it will encroach into thechannel region 9 and produce a short channel effect. The pre-dope may be conducted during deposition of the gate conductor material prior to patterning and etch; after etching of thegate conductor 3; or in-situ. A typical gate implant dose range is from about 5×1015 atoms/cm2 to about 2×1016 atoms/cm2, with an optimal dose of about 8×1015 atoms/cm2. The implant energy is kept substantially low to prevent penetration of implanted species into thesubstrate 10. If the protection oxide layer is present, the implant energy should be substantially large to allow for ion penetration into thegate conductor 3. A typical implant energy range is from about 1 to about 20 keV, with an optimal energy of approximately 12 keV. Implant dopants may be type III-A elements or a type V elements. Implant energies depend on the species being implanted, the above described implant energies are most suitable for phosphorous. - An optional block-mask can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type. The block-mask application and implantation procedure can be repeated to dope selected gate conductors with different dopant types.
- Referring to FIG. 3(b), source/
drain extension regions 7 are formed insubstrate 10 and partially extend under thegate region 5. Source/drain extension regions 7 are formed via ion implantation and comprise a combination of normally incident and angled implants to form the desired grading in the extensions. For producing NFET devices arsenic, as opposed to phosphorus, is preferred in order to avoid short channel-effect degradation caused by source/drain encroachment into the channel region that occurs when utilizing implant elements with a high rate of diffusion. Although arsenic implants are preferred, other group V elements utilized to form NFET devices may be incorporated into the inventive method, also including phosphorus and antimony. Implant energies for forming source/drain extension regions 7 are typically: from about 1 keV to about 5 keV, preferably about 3 keV, for arsenic; from about 1 keV to about 7 keV, preferably about 4 keV, for BF2; and from about 1 keV to about 2 keV, preferably about 1 keV, for boron. These implants are typically carried out using a low concentration of dopant dose on the order of 5×1014 atoms/cm2−2×1015 atoms/cm2, preferably about 1×1015 atoms/cm2 - Following source/
drain extension region 7 implants,first spacers 14 are formed abutting thegate region 5 as depicted in FIG. 3(c).First spacers 14 are formed using conventional deposition and etch processes that are well known in the art.First spacers 14 have a first spacer width W2 of preferably from about 3 nm to about 40 nm; more preferably about 5.0 nm to about 20.0 nm; even more preferably from about 7.0 nm to about 15.0 nm; and most preferably about 10 nm. First spacer width W2 is less than second spacer width W3.First spacer 14 may be comprised of a dielectric material such as a nitride. Thefirst spacer 14 materials most preferably comprise SiN. - Referring to FIG. 3(d), following
first spacer 14 formation, a higher energy ion implant is conducted to form deep source/drain regions 6. These implants are typically carried out using a high concentration of dopant dose on the order of about 1×1015 atoms/cm2 to about 5×1015 atoms/cm2, preferably about 3×1015 atoms/cm2. Implant energy is dependent on implant species and substrate; i.e., arsenic implant of a SOI CMOS substrate typically requires an implant from about 10 keV to about 20 keV. Deep source/drain regions 6 are preferably formed using a group V dopant implant, preferably arsenic because it diffuses into the substrate slowly. Group IIIA elements may also be utilized as the implant for deep source/drain 6 formation. - Following deep source/drain region6formation, the source/drain and gate regions are activated by activation annealing using conventional processes such as, but not limited to: rapid thermal annealing, furnace annealing or flashlamp annealing. Activation anneal is conducted at a temperature above 850° C. with an optimal temperature of about 1000° C. This step of the present invention activates the dopant atoms, which changes the conductivity of the Si-containing material to which the dopants were implanted. The resultant structure produced during activation anneal is depicted in FIG. 3(e).
- Following activation anneal, the inventive
first silicide region 11 is formed as depicted in FIG. 3(f). Silicide formation typically requires depositing a metal layer onto the surface of a Si-containing material or wafer. The metal layer may be formed using a conventional process including, but not limited to: chemical vapor deposition (CVD), plasma-assisted CVD, high-density chemical vapor deposition (HDCVD), plating, sputtering, evaporation and chemical solution deposition. Metals deposited for silicide formation include Ta, Ti, W, Pt, Co, Ni, and combinations thereof, most preferably Co. Following deposition, the structure is then subjected to an annealing step using conventional processes such as, but not limited to: rapid thermal annealing. During thermal annealing, the deposited metal reacts with Si forming a metal silicide. Metal is deposited onto exposed portions of source/drain extension regions 7 to form a metal layer with a thickness from about 2 nm to about 7 nm, preferably about 2 nm. Depositing a 2 nm thick layer of Co atop a Si-containing material forms athin silicide layer 11 having a thickness of about 7 nm. Metal is also deposited atop thegate conductor 3 and forms agate silicide region 4. -
First silicide region 11 has a first silicide thickness T1 of about 1 nm to about 20 nm, preferably from about 2.0 nm to about 15 nm, even more preferably from about 5.0 nm to about 12.0 nm, and most preferably from about 7.0 nm to about 10.0 nm. Second silicide thickness T2 is greater than first silicide thickness T1. The end of thefirst silicide region 11 closest to thechannel region 9 of the device is spaced, W4, about 2 nm to about 15 nm, preferably about 3 nm to about 10 nm, most preferably about 7 nm, from the end of the source/drain extension regions 7 abutting thechannel region 9. The introduction of the low resistancefirst silicide region 11 into the source/drain extension region 7 in closer proximity to thechannel region 9 than previously possible decreases the external resistance of the device. - Referring to FIG. 3(g),
second spacers 15 are formed atop thin silicide region and abuttingfirst spacers 14.Second spacers 15 are formed using conventional deposition and etching processes that are well known in the art and have a second spacer width W3 from about 20 nm to about 90 nm, preferably from about 30 nm to about 70 nm, even more preferably from about 40 nm to about 60 nm, and most preferably 50 nm. Second spacer width W3 is greater than first spacer width W2.Second spacer 15 may be comprised of a dielectric material such as a nitride, oxide, oxynitride, or a combination thereof.Second spacer 15 materials most preferably comprise SiN. - Following
second spacer 15 formation, second silicide regions having second silicide thickness T2 are formed as depicted in FIG. 3(h).Second silicide regions 12 are thicker, having a greater depth dimension from the surface of the substrate T2, thanfirst silicide region 11.Second silicide 12 formation requires that further metal be deposited atop exposed silicide regions not protected by first andsecond spacers First silicide region 11 is self-aligned to and protected from further metal deposition bysecond spacers 15. Metals deposited forsecond silicide 12 formation include Ta, Ti, W, Pt, Co, Ni, and combinations thereof, most preferably Co. The metal layer formed after second deposition has a thickness ranging from about 6 nm to about 10 nm. - Following deposition, the structure is then subjected to an annealing step, at a temperature of about 400° C. to about 850° C. using conventional processes such as, but not limited to: rapid thermal annealing. The anneal process for silicide formation is dependent on the metal utilized; i.e., for Co the first temperature for monosilicide formation is about 500° C., while the second temperature for disilicide formation is about 750° C. Following anneal, the resulting thickness T2 of the
second silicide region 12 is from about 10 nm to about 40 nm thick, preferably from about 15 nm to about 35 nm thick, more preferably from about 20 nm to about 35 nm thick, even more preferably from about 20 nm to about 30 nm thick; and most preferably about 20 nm thick. The resultant NFET comprises a second silicide region 72 and afirst silicide region 11; where thefirst silicide region 11 decreases the external resistance of the device and thesecond silicide region 12 serves as a low resistance interconnect. - Optionally, a second anneal may be conducted in order to produce a lower resistivity phase of the first and
second silicide regions - A second embodiment of the present invention is a method for producing a low resistance PFET as depicted in FIGS.4(a)-4(g). It is possible to integrate PFET production in a manner analogous to the NFET, with the exception of changing the doping materials from group V elements to group IIIA elements. Alternatively, a second embodiment of the inventive method produces low resistance PFET devices utilizing a single implant to form both source/drain extensions and deep source/drain regions. Utilizing a single implant to produce both the source/drain extension and the deep source/drain regions substantially reduces encroachment of the implant elements upon the channel and the likelihood of short channel effects.
- Referring to FIGS.4(a)-(b), to produce PFET devices incorporating the inventive
first silicide 11, an implant to pre-dope thegate conductor 3 and only a single implant to form source/drain regions is performed. All other process steps relating togate region 5 formation andspacer first silicide 11, as discussed above. - Referring to FIGS.4(c)-(d), a single low energy implant (please enter the energy of the implant) is introduced via ion implantation to form a shallow source/
drain extension 20. Implant energies for forming source/drain regions 7 are typically: from about 1 keV to about 5 keV, preferably about 3 keV, for arsenic; from about 1 keV to about 7 keV, preferably about 4 keV, for BF2; and from about 1 keV to about 2 keV, preferably about 1 keV, for boron. Following the single low energy implant, an activation anneal is conducted at approximately 850° C., more preferably at about 1000° C. as depicted in FIG. 3(d). Although boron is preferred, other type III elements may be utilized for producing PFET devices. - Referring to FIG. 4(e), the inventive
first silicide 11 regions are formed, as described in the above method for producing NFET devices.First silicide regions 11 have a thickness T1 of about 5 nm to about 15 nm and allow for the silicide region to be brought within 2 nm to about 15 nm, preferably about 7 nm, of the end of the shallow source/drain extension 20 abutting thechannel region 9 of the device. - Referring to FIGS.4(f)-(g), following
first silicide formation 11,second spacers 15 are formed atopfirst silicide 11 regions andsecond silicide 12 region formed following the same or similar process steps as described above for producing NFET devices. The resultant PFET comprises asecond silicide region 12 and afirst silicide region 11; where thefirst silicide region 11 decreases the external resistance of the device and thesecond silicide region 12 serves as a low resistance interconnect. - While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
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US10/249,295 US20040188765A1 (en) | 2003-03-28 | 2003-03-28 | Cmos device integration for low external resistance |
US10/763,308 US7189644B2 (en) | 2003-03-28 | 2004-01-23 | CMOS device integration for low external resistance |
TW093104490A TWI331375B (en) | 2003-03-28 | 2004-02-23 | Cmos device integration for low external resistance |
PCT/GB2004/000928 WO2004086491A1 (en) | 2003-03-28 | 2004-03-05 | Cmos integration for multi-thickness silicide devices |
KR1020057015899A KR100951205B1 (en) | 2003-03-28 | 2004-03-05 | Cmos integration for multi-thickness silicide devices |
EP04717685A EP1611605A1 (en) | 2003-03-28 | 2004-03-05 | Cmos integration for multi-thickness silicide devices |
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US20040188765A1 true US20040188765A1 (en) | 2004-09-30 |
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US10/763,308 Expired - Fee Related US7189644B2 (en) | 2003-03-28 | 2004-01-23 | CMOS device integration for low external resistance |
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EP (1) | EP1611605A1 (en) |
KR (1) | KR100951205B1 (en) |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050145956A1 (en) * | 2004-01-05 | 2005-07-07 | Taiwan Semiconductor Manufacturing Co. | Devices with high-k gate dielectric |
KR100642648B1 (en) * | 2005-09-13 | 2006-11-10 | 삼성전자주식회사 | Contact structure having silicide layers, semiconductor device employing the same, and methods of fabricating the same |
US20120217589A1 (en) * | 2010-12-03 | 2012-08-30 | Haizhou Yin | Semiconductor structure and method for manufacturing the same |
US10217819B2 (en) | 2015-05-20 | 2019-02-26 | Samsung Electronics Co., Ltd. | Semiconductor device including metal-2 dimensional material-semiconductor contact |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20050066872A (en) * | 2003-12-27 | 2005-06-30 | 동부아남반도체 주식회사 | Method for fabricating high voltage semiconductor device having high breakdown voltage |
US20080150024A1 (en) * | 2004-02-19 | 2008-06-26 | Koninklijke Philips Electronic, N.V. | Semiconductor Device and Method of Manufacturing a Semiconductor Device |
US7064396B2 (en) * | 2004-03-01 | 2006-06-20 | Freescale Semiconductor, Inc. | Integrated circuit with multiple spacer insulating region widths |
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US7129548B2 (en) * | 2004-08-11 | 2006-10-31 | International Business Machines Corporation | MOSFET structure with multiple self-aligned silicide contacts |
FR2888985A1 (en) * | 2005-07-20 | 2007-01-26 | St Microelectronics Crolles 2 | Integrated circuit, has pair of metal silicide layers located on source/drain extension regions and source/drain regions, respectively, where thickness of metal silicide layer located on extension regions is less than other silicide layer |
US20070072358A1 (en) * | 2005-09-29 | 2007-03-29 | Chih-Ning Wu | Method of manufacturing metal-oxide-semiconductor transistor devices |
CN103928329B (en) * | 2013-01-10 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Mos transistor and forming method thereof |
CN108470686B (en) | 2017-06-30 | 2019-10-18 | 长鑫存储技术有限公司 | A kind of semiconductor device structure and preparation method thereof |
Citations (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4876213A (en) * | 1988-10-31 | 1989-10-24 | Motorola, Inc. | Salicided source/drain structure |
US5605865A (en) * | 1995-04-03 | 1997-02-25 | Motorola Inc. | Method for forming self-aligned silicide in a semiconductor device using vapor phase reaction |
US5710450A (en) * | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
US5841173A (en) * | 1995-06-16 | 1998-11-24 | Matsushita Electric Industrial Co., Ltd. | MOS semiconductor device with excellent drain current |
US5851866A (en) * | 1996-11-27 | 1998-12-22 | Lg Semicon Co., Ltd. | Fabrication method for CMOS with sidewalls |
US5933741A (en) * | 1997-08-18 | 1999-08-03 | Vanguard International Semiconductor Corporation | Method of making titanium silicide source/drains and tungsten silicide gate electrodes for field effect transistors |
US6063681A (en) * | 1998-01-13 | 2000-05-16 | Lg Semicon Co., Ltd. | Silicide formation using two metalizations |
US6093628A (en) * | 1998-10-01 | 2000-07-25 | Chartered Semiconductor Manufacturing, Ltd | Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application |
US6187619B1 (en) * | 1998-02-17 | 2001-02-13 | Shye-Lin Wu | Method to fabricate short-channel MOSFETs with an improvement in ESD resistance |
US6198142B1 (en) * | 1998-07-31 | 2001-03-06 | Intel Corporation | Transistor with minimal junction capacitance and method of fabrication |
US6207563B1 (en) * | 1999-02-05 | 2001-03-27 | Advanced Micro Devices, Inc. | Low-leakage CoSi2-processing by high temperature thermal processing |
US6211027B1 (en) * | 1999-11-19 | 2001-04-03 | United Microelectronics Corp. | Method for manufacturing PMOS transistor |
US6242776B1 (en) * | 1999-06-02 | 2001-06-05 | Advanced Micro Devices, Inc. | Device improvement by lowering LDD resistance with new silicide process |
US6319807B1 (en) * | 2000-02-07 | 2001-11-20 | United Microelectronics Corp. | Method for forming a semiconductor device by using reverse-offset spacer process |
US6376351B1 (en) * | 2001-06-28 | 2002-04-23 | Taiwan Semiconductor Manufacturing Company | High Fmax RF MOSFET with embedded stack gate |
US20020048919A1 (en) * | 1994-01-28 | 2002-04-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having metal silicide film and manufacturing method thereof |
US6380057B1 (en) * | 2001-02-13 | 2002-04-30 | Advanced Micro Devices, Inc. | Enhancement of nickel silicide formation by use of nickel pre-amorphizing implant |
US6413829B1 (en) * | 2001-06-01 | 2002-07-02 | Advanced Micro Devices, Inc. | Field effect transistor in SOI technology with schottky-contact extensions |
US6432763B1 (en) * | 2001-03-15 | 2002-08-13 | Advanced Micro Devices, Inc. | Field effect transistor having doped gate with prevention of contamination from the gate during implantation |
US6451701B1 (en) * | 2001-11-14 | 2002-09-17 | Taiwan Semiconductor Manufacturing Company | Method for making low-resistance silicide contacts between closely spaced electrically conducting lines for field effect transistors |
US6451679B1 (en) * | 2000-04-03 | 2002-09-17 | Taiwan Semiconductor Manufacturing Company | Ion mixing between two-step titanium deposition process for titanium salicide CMOS technology |
US6459106B2 (en) * | 1999-11-22 | 2002-10-01 | International Business Machines Corporation | Dynamic threshold voltage devices with low gate to substrate resistance |
US6465294B1 (en) * | 2001-03-16 | 2002-10-15 | Taiwan Semiconductor Manufacturing Company | Self-aligned process for a stacked gate RF MOSFET device |
US6465847B1 (en) * | 2001-06-11 | 2002-10-15 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions |
US6518631B1 (en) * | 2001-04-02 | 2003-02-11 | Advanced Micro Devices, Inc. | Multi-Thickness silicide device formed by succesive spacers |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4764477A (en) * | 1987-04-06 | 1988-08-16 | Motorola, Inc. | CMOS process flow with small gate geometry LDO N-channel transistors |
US6187643B1 (en) * | 1999-06-29 | 2001-02-13 | Varian Semiconductor Equipment Associates, Inc. | Simplified semiconductor device manufacturing using low energy high tilt angle and high energy post-gate ion implantation (PoGI) |
KR100305681B1 (en) * | 1999-10-04 | 2001-11-02 | 윤종용 | semiconductor device and method for manufacturing the same |
US6399452B1 (en) * | 2000-07-08 | 2002-06-04 | Advanced Micro Devices, Inc. | Method of fabricating transistors with low thermal budget |
US20020102802A1 (en) * | 2001-02-01 | 2002-08-01 | Tan Cheng Cheh | Novel technique to achieve thick silicide film for ultra-shallow junctions |
US20020137268A1 (en) | 2001-03-20 | 2002-09-26 | Pellerin John G. | Method of forming silicide contacts and device incorporation same |
WO2002082503A2 (en) | 2001-04-02 | 2002-10-17 | Advanced Micro Devices, Inc. | Multi-thickness silicide device |
-
2003
- 2003-03-28 US US10/249,295 patent/US20040188765A1/en not_active Abandoned
-
2004
- 2004-01-23 US US10/763,308 patent/US7189644B2/en not_active Expired - Fee Related
- 2004-02-23 TW TW093104490A patent/TWI331375B/en not_active IP Right Cessation
- 2004-03-05 KR KR1020057015899A patent/KR100951205B1/en not_active IP Right Cessation
- 2004-03-05 EP EP04717685A patent/EP1611605A1/en not_active Withdrawn
- 2004-03-05 CN CNB2004800022293A patent/CN100442462C/en not_active Expired - Fee Related
- 2004-03-05 WO PCT/GB2004/000928 patent/WO2004086491A1/en active Application Filing
Patent Citations (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4876213A (en) * | 1988-10-31 | 1989-10-24 | Motorola, Inc. | Salicided source/drain structure |
US20020048919A1 (en) * | 1994-01-28 | 2002-04-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having metal silicide film and manufacturing method thereof |
US5710450A (en) * | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
US5605865A (en) * | 1995-04-03 | 1997-02-25 | Motorola Inc. | Method for forming self-aligned silicide in a semiconductor device using vapor phase reaction |
US5841173A (en) * | 1995-06-16 | 1998-11-24 | Matsushita Electric Industrial Co., Ltd. | MOS semiconductor device with excellent drain current |
US5851866A (en) * | 1996-11-27 | 1998-12-22 | Lg Semicon Co., Ltd. | Fabrication method for CMOS with sidewalls |
US5933741A (en) * | 1997-08-18 | 1999-08-03 | Vanguard International Semiconductor Corporation | Method of making titanium silicide source/drains and tungsten silicide gate electrodes for field effect transistors |
US6063681A (en) * | 1998-01-13 | 2000-05-16 | Lg Semicon Co., Ltd. | Silicide formation using two metalizations |
US6187619B1 (en) * | 1998-02-17 | 2001-02-13 | Shye-Lin Wu | Method to fabricate short-channel MOSFETs with an improvement in ESD resistance |
US6198142B1 (en) * | 1998-07-31 | 2001-03-06 | Intel Corporation | Transistor with minimal junction capacitance and method of fabrication |
US6093628A (en) * | 1998-10-01 | 2000-07-25 | Chartered Semiconductor Manufacturing, Ltd | Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application |
US6207563B1 (en) * | 1999-02-05 | 2001-03-27 | Advanced Micro Devices, Inc. | Low-leakage CoSi2-processing by high temperature thermal processing |
US6242776B1 (en) * | 1999-06-02 | 2001-06-05 | Advanced Micro Devices, Inc. | Device improvement by lowering LDD resistance with new silicide process |
US6211027B1 (en) * | 1999-11-19 | 2001-04-03 | United Microelectronics Corp. | Method for manufacturing PMOS transistor |
US6459106B2 (en) * | 1999-11-22 | 2002-10-01 | International Business Machines Corporation | Dynamic threshold voltage devices with low gate to substrate resistance |
US6319807B1 (en) * | 2000-02-07 | 2001-11-20 | United Microelectronics Corp. | Method for forming a semiconductor device by using reverse-offset spacer process |
US6451679B1 (en) * | 2000-04-03 | 2002-09-17 | Taiwan Semiconductor Manufacturing Company | Ion mixing between two-step titanium deposition process for titanium salicide CMOS technology |
US6380057B1 (en) * | 2001-02-13 | 2002-04-30 | Advanced Micro Devices, Inc. | Enhancement of nickel silicide formation by use of nickel pre-amorphizing implant |
US6432763B1 (en) * | 2001-03-15 | 2002-08-13 | Advanced Micro Devices, Inc. | Field effect transistor having doped gate with prevention of contamination from the gate during implantation |
US6465294B1 (en) * | 2001-03-16 | 2002-10-15 | Taiwan Semiconductor Manufacturing Company | Self-aligned process for a stacked gate RF MOSFET device |
US6518631B1 (en) * | 2001-04-02 | 2003-02-11 | Advanced Micro Devices, Inc. | Multi-Thickness silicide device formed by succesive spacers |
US6413829B1 (en) * | 2001-06-01 | 2002-07-02 | Advanced Micro Devices, Inc. | Field effect transistor in SOI technology with schottky-contact extensions |
US6465847B1 (en) * | 2001-06-11 | 2002-10-15 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions |
US6376351B1 (en) * | 2001-06-28 | 2002-04-23 | Taiwan Semiconductor Manufacturing Company | High Fmax RF MOSFET with embedded stack gate |
US6451701B1 (en) * | 2001-11-14 | 2002-09-17 | Taiwan Semiconductor Manufacturing Company | Method for making low-resistance silicide contacts between closely spaced electrically conducting lines for field effect transistors |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050145956A1 (en) * | 2004-01-05 | 2005-07-07 | Taiwan Semiconductor Manufacturing Co. | Devices with high-k gate dielectric |
KR100642648B1 (en) * | 2005-09-13 | 2006-11-10 | 삼성전자주식회사 | Contact structure having silicide layers, semiconductor device employing the same, and methods of fabricating the same |
US20120217589A1 (en) * | 2010-12-03 | 2012-08-30 | Haizhou Yin | Semiconductor structure and method for manufacturing the same |
US8822334B2 (en) * | 2010-12-03 | 2014-09-02 | The Institute of Microelectronics, Chinese Academy of Science | Semiconductor structure and method for manufacturing the same |
US10217819B2 (en) | 2015-05-20 | 2019-02-26 | Samsung Electronics Co., Ltd. | Semiconductor device including metal-2 dimensional material-semiconductor contact |
US10559660B2 (en) | 2015-05-20 | 2020-02-11 | Samsung Electronics Co., Ltd. | Semiconductor device including metal-2 dimensional material-semiconductor contact |
US10790356B2 (en) | 2015-05-20 | 2020-09-29 | Samsung Electronics Co., Ltd. | Semiconductor device including metal-2 dimensional material-semiconductor contact |
US11342414B2 (en) * | 2015-05-20 | 2022-05-24 | Samsung Electronics Co., Ltd. | Semiconductor device including metal-2 dimensional material-semiconductor contact |
US20220262903A1 (en) * | 2015-05-20 | 2022-08-18 | Samsung Electronics Co., Ltd. | Semiconductor device including metal-2 dimensional material-semiconductor contact |
Also Published As
Publication number | Publication date |
---|---|
CN100442462C (en) | 2008-12-10 |
CN1784774A (en) | 2006-06-07 |
WO2004086491A1 (en) | 2004-10-07 |
TW200425412A (en) | 2004-11-16 |
EP1611605A1 (en) | 2006-01-04 |
KR20050107591A (en) | 2005-11-14 |
US20040188766A1 (en) | 2004-09-30 |
KR100951205B1 (en) | 2010-04-05 |
TWI331375B (en) | 2010-10-01 |
US7189644B2 (en) | 2007-03-13 |
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