US20040223390A1 - Resistance variable memory element having chalcogenide glass for improved switching characteristics - Google Patents

Resistance variable memory element having chalcogenide glass for improved switching characteristics Download PDF

Info

Publication number
US20040223390A1
US20040223390A1 US10/865,903 US86590304A US2004223390A1 US 20040223390 A1 US20040223390 A1 US 20040223390A1 US 86590304 A US86590304 A US 86590304A US 2004223390 A1 US2004223390 A1 US 2004223390A1
Authority
US
United States
Prior art keywords
resistance variable
glass
germanium
silver
annealed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/865,903
Inventor
Kristy Campbell
John Moore
Terry Gilton
Joseph Brooks
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Round Rock Research LLC
Original Assignee
Campbell Kristy A.
John Moore
Gilton Terry L.
Brooks Joseph F.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Campbell Kristy A., John Moore, Gilton Terry L., Brooks Joseph F. filed Critical Campbell Kristy A.
Priority to US10/865,903 priority Critical patent/US20040223390A1/en
Publication of US20040223390A1 publication Critical patent/US20040223390A1/en
Assigned to ROUND ROCK RESEARCH, LLC reassignment ROUND ROCK RESEARCH, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of the switching material, e.g. post-treatment, doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of the switching material, e.g. post-treatment, doping
    • H10N70/046—Modification of the switching material, e.g. post-treatment, doping by diffusion, e.g. photo-dissolution
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825—Selenides, e.g. GeSe

Definitions

  • the present invention relates to the field of random access memory (RAM) devices formed using a resistance variable material, and in particular to a resistance variable memory element having improved switching characteristics.
  • RAM random access memory
  • a well known semiconductor component is semiconductor memory, such as a random access memory (RAM).
  • RAM permits repeated read and write operations on memory elements.
  • RAM devices are volatile, in that stored data is lost once the power source is disconnected or removed.
  • RAM devices include dynamic random access memory (DRAM), synchronized dynamic random access memory (SDRAM) and static random access memory (SRAM).
  • DRAM dynamic random access memory
  • SDRAM synchronized dynamic random access memory
  • SRAM static random access memory
  • DRAMS and SDRAMS also typically store data in capacitors which require periodic refreshing to maintain the stored data.
  • a write operation to a low resistance state is performed by applying a voltage potential across the two electrodes.
  • the mechanism by which the resistance of the element is changed is not fully understood.
  • the conductively-doped dielectric material undergoes a structural change at a certain applied voltage with the growth of a conductive dendrite or filament between the electrodes effectively interconnecting the two electrodes and setting the memory element in a low resistance state.
  • the dendrite is thought to grow through the resistance variable material in a path of least resistance.
  • the low resistance state will remain intact for days or weeks after the voltage potentials are removed.
  • Such material can be returned to its high resistance state by applying a reverse voltage potential between the electrodes of at least the same order of magnitude as used to write the element to the low resistance state. Again, the highly resistive state is maintained once the voltage potential is removed.
  • a device can function, for example, as a resistance variable memory element having two resistance states, which can define two logic states.
  • One preferred resistance variable material comprises a chalcogenide glass.
  • a specific example is germanium-selenide (Ge x Se 100 ⁇ x ) comprising silver (Ag).
  • One method of providing silver to the germanium-selenide composition is to initially form a germanium-selenide glass and then deposit a thin layer of silver upon the glass, for example by sputtering, physical vapor deposition, or other known technique in the art.
  • the layer of silver is irradiated, preferably with electromagnetic energy at a wavelength less than 600 nanometers, so that the energy passes through the silver and to the silver/glass interface, to break a chalcogenide bond of the chalcogenide material such that the glass is doped with silver.
  • Silver may also be provided to the glass by processing the glass with silver, as in the case of a silver-germanium-selenide glass.
  • Another method for providing metal to the glass is to provide a layer of silver-selenide on a germanium-selenide glass.
  • the mean coordination number of the glass defines the tightness of the glass matrix. If the chalcogenide glass matrix is tight, then a larger resistance change is inhibited when a memory element switches from an on to an off state. On the other hand, if the chalcogenide glass matrix is looser (more open), then a larger resistance change is more easily facilitated. Accordingly, glasses having an open matrix, e.g., a larger resistance change, require a longer time to write when reprogrammed to the low resistance state. Conversely, glasses having a tight matrix, e.g. inhibiting large resistance changes, will write to the low resistance state faster.
  • glasses having an open matrix may comprise silver
  • a disadvantage of using a tight matrix glass is that it is difficult to provide silver to the glass and achieve good switching.
  • Silver can be directly incorporated into a resistance variable material having an open matrix, such as Ge 20 Se 80 or Ge 23 Se 77 to form silver-selenide within the Ge x Se 100 ⁇ x backbone.
  • the Ge x Se 100 ⁇ x backbone is lacking the Se that went into forming the silver-selenide.
  • the remaining glass backbone does not have a mean coordinator number corresponding to a tight matrix, like Ge 40 Se 60 . As a consequence, there is greater Ag mobility causing a larger resistance change when a memory element is programmed back to its high resistance state.
  • chalcogenide glass memory element comprising silver and which also has a tight glass matrix to inhibit metal migration thus allowing the memory element to retain memory longer and inhibiting a large resistance change when the memory element is programmed back to its high resistance state.
  • the invention provides a metal containing resistance variable material having a tighter more rigid glass matrix, which exhibits improved switching characteristics and data retention.
  • the invention also provides a Ge x Se 100 ⁇ x glass memory element incorporating silver therein and which has a tighter more rigid glass matrix.
  • the invention provides a method in which a metal is incorporated into a resistance variable material and then the metal containing resistance variable material is annealed to provide a tighter more rigid glass matrix.
  • the invention provides a method in which a silver-germanium-selenide glass is annealed to provide a tighter more rigid glass matrix.
  • FIG. 1 illustrates a process according to an embodiment of the present invention
  • FIG. 2 is a cross-sectional view of a resistance variable memory element constructed in accordance with the process of FIG. 1;
  • FIG. 3 illustrates a computer system having one or more memory devices that contains resistance variable memory elements according to the present invention.
  • substrate used in the following description may include any supporting structure including but not limited to a semiconductor substrate that has an exposed substrate surface. Structure should be understood to include silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. When reference is made to a substrate or wafer in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor or foundation.
  • SOI silicon-on-insulator
  • SOS silicon-on-sapphire
  • silver is intended to include not only elemental silver, but silver with other trace metals or in various alloyed combinations with other metals as known in the semiconductor industry, as long as such silver alloy is conductive, and as long as the physical and electrical properties of the silver remain unchanged.
  • silver-selenide is intended to include various species of silver-selenide, including some species which have a slight excess or deficit of silver, for instance, Ag 2 Se, Ag 2+x Se, and Ag 2 ⁇ x Se.
  • semi-volatile memory device is intended to include any memory device which is capable of maintaining its memory state after power is removed from the device for a prolonged period of time. Thus, semi-volatile memory devices are capable of retaining stored data after the power source is disconnected or removed.
  • semi-volatile memory device as used herein includes not only semi-volatile memory devices, but also non-volatile memory devices.
  • resistance variable material is intended to include chalcogenide glasses, and chalcogenide glasses comprising a metal, such as silver.
  • resistance variable material includes silver doped chalcogenide glasses, silver-germanium-selenide glasses, and chalcogenide glasses comprising a silver selenide layer.
  • resistance variable memory element is intended to include any memory element, including programmable conductor memory elements, semi-volatile memory elements, and non-volatile memory elements which exhibit a resistance change in response to an applied voltage.
  • the present invention relates to a method of forming a resistance variable memory element having improved switching characteristics and to the resulting memory element.
  • the tightness and hence rigidity of the glass matrix of a chalcogenide glass used in a resistance variable memory element determines the speed at which a memory elements switches. For instance, if the memory element erases to a larger or higher resistance, the memory element will write more slowly than if the memory element erases to a smaller or lower resistance.
  • the tightness of the glass matrix is generally characterized by the mean coordination of the glass. Boolchand et al. in Onset of Rigidity in Steps in Chalcogenide Glass, Properties and Applications of Amorphous Materials, pp.
  • glasses having a rigid network structure inhibit larger resistance changes, resulting in memory elements which can be reprogrammed to a low resistance state relatively faster, thusly having shorter write cycles and better switching characteristics.
  • silver is incorporated into a lower rigidity glass, such as for example Ge 20 Se 80 to Ge 23 Se 77 .
  • the silver containing glass is annealed, preferably by heating, to produce a more rigid glass.
  • the silver containing glass is also preferably annealed in the presence of oxygen. Annealing drives off a portion of the selenium in the glass and raises the germanium to selenium ratio. It is known that the higher the germanium to selenium ratio, the more tightly packed the glass matrix and the more rigid the structure. Accordingly, a memory element formed of the annealed glass switches faster than conventionally formed glasses.
  • Typical temperatures for packaging of memory elements are of about 170° C. to about 190° C. (e.g., for encapsulation) and can be as high as 230° C. (e.g., for wire bonding).
  • Typical processing steps during the fabrication of resistance variable memory elements for example photoresist and/or nitride deposition processes, can also take place at temperatures of about 200° C.
  • Generally acceptable chalcogenide glass compositions for resistance variable memory elements have a glass transition temperature, which is about or higher than the highest packaging and/or processing temperatures used during the formation of the memory device or of the packaging of the memory device itself. For instance, Ge 40 Se 60 glass has a bulk material glass transition temperature of about 347° C.
  • transition temperature of the backbone may be slightly higher than the transition temperature of the bulk resistance variable material. Accordingly, to prevent glass transition, the resistance variable material thin-film is annealed at temperatures close to or slightly below the thin-film glass transition temperature of the resistance variable material.
  • FIG. 1 illustrates a process 100 according to an exemplary embodiment of the method of the invention. While FIG. 2 depicts one exemplary structure formed in accordance with the process of FIG. 1.
  • a first electrode is formed over a substrate assembly.
  • the material used to form the electrode can be selected from a variety of conductive materials, for example, tungsten, nickel, tantalum, titanium, titanium nitride, aluminum, platinum, or silver, among many others.
  • an insulating layer is formed in contact with the first electrode.
  • This and any other subsequently formed insulating layers may be formed of a conventional insulating nitride or oxide, among others.
  • the present invention is not limited, however, to the above-listed materials and other insulating and/or dielectric materials known in the industry may be used.
  • the insulating layer may be formed by any known deposition methods, for example, by sputtering, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD) or physical vapor deposition (PVD), among others.
  • the insulating layer is etched to form an opening, which exposes the first electrode.
  • a resistance variable material is deposited into the opening.
  • the resistance variable material is deposited in such a manner so as to contact the first electrode.
  • the resistance variable material is a germanium-selenide glass.
  • the germanium-selenide glass composition is of a relatively low rigidity, such as one having a Ge x Se 100 ⁇ x stoichiometry of from about Ge 20 Se 80 to about Ge 23 Se 77 .
  • the resistance variable material may be deposited by any known deposition methods, for example, by sputtering, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD) or physical vapor deposition (PVD).
  • the resistance variable material may be formed over the first electrode to dimensions (i.e., length, thickness, and width) suitable to produce desired electrical characteristics of the memory element.
  • a metal such as silver
  • silver is incorporated into the resistance variable material.
  • silver (Ag) is preferably incorporated into the resistance variable material.
  • One technique for incorporating silver into a germanium-selenide glass is by processing the glass with silver to form silver-germanium-selenide.
  • Another technique for incorporating silver into a resistance variable material is doping.
  • the resistance variable material may be doped by first coating the material with a layer of silver, for example, by sputtering, and then driving the silver into the material with UV radiation.
  • the silver can be co-sputtered with the resistance variable material composition to produce a doped resistance variable material.
  • Silver may also be incorporated into the resistance variable material by providing silver as a separate layer, for instance, a silver-selenide (silver-selenide) layer provided on a germanium-selenide glass.
  • the resistance variable material backbone is annealed.
  • the backbone may be annealed at this point in processing, preferably by heating the substrate assembly.
  • the backbone may be annealed at any suitable time during fabrication of the resistance variable memory element.
  • a suitable annealing temperature is an elevated temperature close to or slightly below the thin-film glass transition temperature of the resistance variable material.
  • a preferred range of elevated annealing temperatures for a germanium-selenide glass backbone is from about 200° C. to about 330° C.
  • the substrate is preferably annealed for about 5 to about 15 minutes, and more preferably about 10 minutes.
  • the substrate is also preferably annealed in an atmosphere comprising oxygen. Annealing the substrate drives off some selenium from the germanium-selenide glass. The loss of selenium in the glass backbone changes the stoichiometry of the glass increasing the relative amount of germanium and providing a more rigid glass.
  • a second metal electrode is formed in contact with the silver-germanium-selenide glass.
  • the annealing step can be performed at any time during the fabrication and/or packaging of the memory element, provided suitable annealing temperatures as noted above are present.
  • FIG. 2 The structure produced by one implementation of the exemplary process described with reference to FIG. 1 is shown in FIG. 2 in the context of a random access memory device.
  • the invention may be used in other types of memory devices.
  • other embodiments may be used and structural or logical changes may be made to the described and illustrated embodiment without departing from the spirit or the scope of the present invention.
  • FIG. 2 illustrates an exemplary construction of a resistance variable memory element.
  • a resistance variable memory element 10 in accordance with the present invention is generally fabricated over a semiconductor substrate 62 and comprises a first insulating layer 60 formed over a substrate 62 in and on which may be fabricated access circuitry for operating a resistance variable memory element as part of a memory array of such elements.
  • the insulating layer 60 contains a conductive plug 61 .
  • a first metal electrode 52 is formed within a second insulating layer 53 provided over the insulating layer 60 and plug 61 .
  • a third insulating layer 68 is formed over the first electrode 52 and second insulating layer 53 .
  • an etched opening is provided for depositing a chalcogenide glass 58 in the opening of the third insulating layer 68 .
  • the chalcogenide glass 58 is deposited in the opening and in contact with the first electrode 52 .
  • a metal preferably silver
  • the glass may be a silver-germanium-selenide glass, or the metal may be provided in numerous different ways, including incorporation into the glass by doping the glass with a metal dopant.
  • the metal dopant preferably comprises silver.
  • the glass backbone 66 is subsequently annealed to drive off selenium from the silver-germanium-selenide glass and form a more rigid glass structure.
  • a second metal electrode 54 is formed in contact with the silver-germanium-selenide glass 58 .
  • the third insulating layer 68 may be formed, for example, between the first electrode 52 and the second electrode 54 of any suitable insulator, for example a nitride, an oxide, or other insulator.
  • the third insulating layer 68 may be formed by any known deposition method, for example, by sputtering, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD) or physical vapor deposition (PVD), among others.
  • the third insulating layer 68 may comprise an insulating material that provides a diffusion barrier for metals, such as silver.
  • a preferred insulating material is silicon nitride, but those skilled in the art will appreciate that there are other numerous suitable insulating materials for this purpose.
  • the thickness T of the third insulating layer 68 and chalcogenide glass 58 is in the range of from about 100 Angstroms to about 10,000 Angstroms and is preferably about 500 Angstroms.
  • the chalcogenide glass 58 is preferably a germanium-selenide composition comprising silver and having a Ge/Se stoichiometry of from about Ge 20 Se 80 to about Ge 23 Se 77 .
  • the invention may also be carried out with other chalcogenide glasses having other metals incorporated therein, as long as the glass is annealed to increase its rigidity.
  • the first electrode 52 may also be electrically connected to a source/drain region 81 of an access transistor 83 , which is fabricated within and on substrate 62 .
  • Another source/drain region 85 may be connected by a bit line plug 87 to a bit line of a memory array.
  • the gate of the transistor 83 may be part of a word line which is connected to a plurality of resistance variable memory elements just as the bit line 93 may be coupled to a plurality of resistance variable memory elements through respective access transistors.
  • the bit line 93 may be formed over a fourth insulating layer 91 and may be formed of any conductive material, for example, a metal. As shown, the bit line 93 connects to the bit line plug 87 , which in turn connects with access transistor 83 .
  • FIG. 2 illustrates the formation of only one resistance variable memory element 10 , it should be understood that the present invention contemplates the formation of any number of such resistance variable memory elements, which can be formed within one or more memory element arrays.

Abstract

The present invention is related to methods of fabricating a resistance variable memory element and a device formed therefrom having improved switching characteristics. According to an embodiment of the present invention a resistance variable material memory element is annealed to remove stoichiometric amounts of a component of the resistance variable material. According to another embodiment of the present invention a silver-germanium-selenide glass is annealed for a duration of about 10 minutes in the presence of oxygen to drive off selenium and increase the rigidity of the glass.

Description

    FIELD OF THE INVENTION
  • The present invention relates to the field of random access memory (RAM) devices formed using a resistance variable material, and in particular to a resistance variable memory element having improved switching characteristics. [0001]
    • BACKGROUND OF THE INVENTION
  • A well known semiconductor component is semiconductor memory, such as a random access memory (RAM). RAM permits repeated read and write operations on memory elements. Typically, RAM devices are volatile, in that stored data is lost once the power source is disconnected or removed. Non-limiting examples of RAM devices include dynamic random access memory (DRAM), synchronized dynamic random access memory (SDRAM) and static random access memory (SRAM). In addition, DRAMS and SDRAMS also typically store data in capacitors which require periodic refreshing to maintain the stored data. [0002]
  • In recent years, the number and density of memory elements in memory devices have been increasing. Accordingly, the size of each element has been shrinking, which in the case of DRAMs also shortens the element's data holding time. Typically, a DRAM memory device relies on element capacity for data storage and receives a refresh command in a conventional standardized cycle, about every 100 milliseconds. However, with increasing element number and density, it is becoming more and more difficult to refresh all memory elements at least once within a refresh period. In addition, refresh operations consume power. [0003]
  • Recently resistance variable memory elements, which includes programmable conductor memory elements, have been investigated for suitability as semi-volatile and non-volatile random access memory elements. Kozicki et al. in U.S. Pat. Nos. 5,761,115; 5,896,312; 5,914,893; and 6,084,796, discloses a programmable conductor memory element including an insulating dielectric material formed of a chalcogenide glass disposed between two electrodes. A conductive material, such as silver, is incorporated into the dielectric material. The resistance of the dielectric material can be changed between high resistance and low resistance states. The programmable conductor memory is normally in a high resistance state when at rest. A write operation to a low resistance state is performed by applying a voltage potential across the two electrodes. The mechanism by which the resistance of the element is changed is not fully understood. In one theory suggested by Kozicki et al., the conductively-doped dielectric material undergoes a structural change at a certain applied voltage with the growth of a conductive dendrite or filament between the electrodes effectively interconnecting the two electrodes and setting the memory element in a low resistance state. The dendrite is thought to grow through the resistance variable material in a path of least resistance. [0004]
  • The low resistance state will remain intact for days or weeks after the voltage potentials are removed. Such material can be returned to its high resistance state by applying a reverse voltage potential between the electrodes of at least the same order of magnitude as used to write the element to the low resistance state. Again, the highly resistive state is maintained once the voltage potential is removed. This way, such a device can function, for example, as a resistance variable memory element having two resistance states, which can define two logic states. [0005]
  • One preferred resistance variable material comprises a chalcogenide glass. A specific example is germanium-selenide (Ge[0006] xSe100−x) comprising silver (Ag). One method of providing silver to the germanium-selenide composition is to initially form a germanium-selenide glass and then deposit a thin layer of silver upon the glass, for example by sputtering, physical vapor deposition, or other known technique in the art. The layer of silver is irradiated, preferably with electromagnetic energy at a wavelength less than 600 nanometers, so that the energy passes through the silver and to the silver/glass interface, to break a chalcogenide bond of the chalcogenide material such that the glass is doped with silver. Silver may also be provided to the glass by processing the glass with silver, as in the case of a silver-germanium-selenide glass. Another method for providing metal to the glass is to provide a layer of silver-selenide on a germanium-selenide glass.
  • The mean coordination number of the glass defines the tightness of the glass matrix. If the chalcogenide glass matrix is tight, then a larger resistance change is inhibited when a memory element switches from an on to an off state. On the other hand, if the chalcogenide glass matrix is looser (more open), then a larger resistance change is more easily facilitated. Accordingly, glasses having an open matrix, e.g., a larger resistance change, require a longer time to write when reprogrammed to the low resistance state. Conversely, glasses having a tight matrix, e.g. inhibiting large resistance changes, will write to the low resistance state faster. [0007]
  • Although glasses having an open matrix may comprise silver, it would be advantageous to use a silver containing glass having a tight matrix. However, a disadvantage of using a tight matrix glass is that it is difficult to provide silver to the glass and achieve good switching. [0008]
  • Silver can be directly incorporated into a resistance variable material having an open matrix, such as Ge[0009] 20Se80 or Ge23Se77 to form silver-selenide within the GexSe100−x backbone. The GexSe100−x backbone, however, is lacking the Se that went into forming the silver-selenide. The remaining glass backbone does not have a mean coordinator number corresponding to a tight matrix, like Ge40Se60. As a consequence, there is greater Ag mobility causing a larger resistance change when a memory element is programmed back to its high resistance state.
  • It would be desirable to have a chalcogenide glass memory element comprising silver and which also has a tight glass matrix to inhibit metal migration thus allowing the memory element to retain memory longer and inhibiting a large resistance change when the memory element is programmed back to its high resistance state. [0010]
    • BRIEF SUMMARY OF THE INVENTION
  • In its structure aspect, the invention provides a metal containing resistance variable material having a tighter more rigid glass matrix, which exhibits improved switching characteristics and data retention. [0011]
  • The invention also provides a Ge[0012] xSe100−x glass memory element incorporating silver therein and which has a tighter more rigid glass matrix.
  • In its method aspect, the invention provides a method in which a metal is incorporated into a resistance variable material and then the metal containing resistance variable material is annealed to provide a tighter more rigid glass matrix. [0013]
  • In a more specific aspect, the invention provides a method in which a silver-germanium-selenide glass is annealed to provide a tighter more rigid glass matrix.[0014]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • These and other features and advantages of the invention will be better understood from the following detailed description, which is provided in connection with the accompanying drawings. [0015]
  • FIG. 1 illustrates a process according to an embodiment of the present invention; [0016]
  • FIG. 2 is a cross-sectional view of a resistance variable memory element constructed in accordance with the process of FIG. 1; and [0017]
  • FIG. 3 illustrates a computer system having one or more memory devices that contains resistance variable memory elements according to the present invention. [0018]
    • DETAILED DESCRIPTION OF THE INVENTION
  • In the following detailed description, reference is made to various specific structural and process embodiments of the invention. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that other embodiments may be employed, and that various structural, logical and electrical changes may be made without departing from the spirit or scope of the invention. [0019]
  • The term “substrate” used in the following description may include any supporting structure including but not limited to a semiconductor substrate that has an exposed substrate surface. Structure should be understood to include silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. When reference is made to a substrate or wafer in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor or foundation. [0020]
  • The term “silver” is intended to include not only elemental silver, but silver with other trace metals or in various alloyed combinations with other metals as known in the semiconductor industry, as long as such silver alloy is conductive, and as long as the physical and electrical properties of the silver remain unchanged. [0021]
  • The term “silver-selenide” is intended to include various species of silver-selenide, including some species which have a slight excess or deficit of silver, for instance, Ag[0022] 2Se, Ag2+xSe, and Ag2−xSe.
  • The term “semi-volatile memory device” is intended to include any memory device which is capable of maintaining its memory state after power is removed from the device for a prolonged period of time. Thus, semi-volatile memory devices are capable of retaining stored data after the power source is disconnected or removed. The term “semi-volatile memory device” as used herein includes not only semi-volatile memory devices, but also non-volatile memory devices. [0023]
  • The term “resistance variable material” is intended to include chalcogenide glasses, and chalcogenide glasses comprising a metal, such as silver. For instance the term “resistance variable material” includes silver doped chalcogenide glasses, silver-germanium-selenide glasses, and chalcogenide glasses comprising a silver selenide layer. [0024]
  • The term “resistance variable memory element” is intended to include any memory element, including programmable conductor memory elements, semi-volatile memory elements, and non-volatile memory elements which exhibit a resistance change in response to an applied voltage. [0025]
  • The present invention relates to a method of forming a resistance variable memory element having improved switching characteristics and to the resulting memory element. [0026]
  • Applicants have discovered that the tightness and hence rigidity of the glass matrix of a chalcogenide glass used in a resistance variable memory element determines the speed at which a memory elements switches. For instance, if the memory element erases to a larger or higher resistance, the memory element will write more slowly than if the memory element erases to a smaller or lower resistance. The tightness of the glass matrix is generally characterized by the mean coordination of the glass. Boolchand et al. in [0027] Onset of Rigidity in Steps in Chalcogenide Glass, Properties and Applications of Amorphous Materials, pp. 97-132, (2001), the disclosure of which is incorporated by reference herein, observes a floppy to rigid transition in GexSe100−x glasses that occurs when x=0.23 (x being the germanium molar concentration). Raman scattering and Temperature Modulated Differential Scanning Calorimetric (MDSC) measurements have shown that a stiffness threshold occurs at a mean coordination number of r=2.46. Thus a glass having a stoichiometry greater than about Ge23S77 or a mean coordination number of about 2.46 or greater is rigid. Glasses characterized as rigid are stiff and have a rigid network or closed matrix type structure. Lower rigidity glasses, i.e., glasses having an open matrix, include glasses having a stoichiometric range of about Ge20Se80 to about Ge23Se77.
  • Applicants have further discovered that glasses having a rigid network structure inhibit larger resistance changes, resulting in memory elements which can be reprogrammed to a low resistance state relatively faster, thusly having shorter write cycles and better switching characteristics. [0028]
  • In accordance with the invention, silver is incorporated into a lower rigidity glass, such as for example Ge[0029] 20Se80 to Ge23Se77. Then the silver containing glass is annealed, preferably by heating, to produce a more rigid glass. The silver containing glass is also preferably annealed in the presence of oxygen. Annealing drives off a portion of the selenium in the glass and raises the germanium to selenium ratio. It is known that the higher the germanium to selenium ratio, the more tightly packed the glass matrix and the more rigid the structure. Accordingly, a memory element formed of the annealed glass switches faster than conventionally formed glasses.
  • Typical temperatures for packaging of memory elements are of about 170° C. to about 190° C. (e.g., for encapsulation) and can be as high as 230° C. (e.g., for wire bonding). Typical processing steps during the fabrication of resistance variable memory elements, for example photoresist and/or nitride deposition processes, can also take place at temperatures of about 200° C. Generally acceptable chalcogenide glass compositions for resistance variable memory elements have a glass transition temperature, which is about or higher than the highest packaging and/or processing temperatures used during the formation of the memory device or of the packaging of the memory device itself. For instance, Ge[0030] 40Se60 glass has a bulk material glass transition temperature of about 347° C. It is believed that the thin-film, as opposed to the bulk material, transition temperature of the backbone may be slightly higher than the transition temperature of the bulk resistance variable material. Accordingly, to prevent glass transition, the resistance variable material thin-film is annealed at temperatures close to or slightly below the thin-film glass transition temperature of the resistance variable material.
  • FIG. 1 illustrates a [0031] process 100 according to an exemplary embodiment of the method of the invention. While FIG. 2 depicts one exemplary structure formed in accordance with the process of FIG. 1.
  • Refer now to FIG. 1 at process segment [0032] 110 a first electrode is formed over a substrate assembly. The material used to form the electrode can be selected from a variety of conductive materials, for example, tungsten, nickel, tantalum, titanium, titanium nitride, aluminum, platinum, or silver, among many others.
  • Next, at [0033] process segment 120, an insulating layer is formed in contact with the first electrode. This and any other subsequently formed insulating layers may be formed of a conventional insulating nitride or oxide, among others. The present invention is not limited, however, to the above-listed materials and other insulating and/or dielectric materials known in the industry may be used. The insulating layer may be formed by any known deposition methods, for example, by sputtering, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD) or physical vapor deposition (PVD), among others.
  • In the [0034] next process segment 130, the insulating layer is etched to form an opening, which exposes the first electrode. Subsequently, in process segment 140, a resistance variable material is deposited into the opening. The resistance variable material is deposited in such a manner so as to contact the first electrode. In an exemplary embodiment, the resistance variable material is a germanium-selenide glass. The germanium-selenide glass composition is of a relatively low rigidity, such as one having a GexSe100−x stoichiometry of from about Ge20Se80 to about Ge23Se77. The resistance variable material may be deposited by any known deposition methods, for example, by sputtering, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD) or physical vapor deposition (PVD). The resistance variable material may be formed over the first electrode to dimensions (i.e., length, thickness, and width) suitable to produce desired electrical characteristics of the memory element.
  • In [0035] process segment 150, a metal, such as silver, is incorporated into the resistance variable material. For a GexSe100−x glass where x=20 to 23, silver (Ag) is preferably incorporated into the resistance variable material. One technique for incorporating silver into a germanium-selenide glass is by processing the glass with silver to form silver-germanium-selenide. Another technique for incorporating silver into a resistance variable material is doping. The resistance variable material may be doped by first coating the material with a layer of silver, for example, by sputtering, and then driving the silver into the material with UV radiation. Alternatively, the silver can be co-sputtered with the resistance variable material composition to produce a doped resistance variable material. Silver may also be incorporated into the resistance variable material by providing silver as a separate layer, for instance, a silver-selenide (silver-selenide) layer provided on a germanium-selenide glass.
  • In [0036] process segment 160, the resistance variable material backbone is annealed. The backbone may be annealed at this point in processing, preferably by heating the substrate assembly. However, the backbone may be annealed at any suitable time during fabrication of the resistance variable memory element. A suitable annealing temperature is an elevated temperature close to or slightly below the thin-film glass transition temperature of the resistance variable material. A preferred range of elevated annealing temperatures for a germanium-selenide glass backbone, is from about 200° C. to about 330° C. The substrate is preferably annealed for about 5 to about 15 minutes, and more preferably about 10 minutes. The substrate is also preferably annealed in an atmosphere comprising oxygen. Annealing the substrate drives off some selenium from the germanium-selenide glass. The loss of selenium in the glass backbone changes the stoichiometry of the glass increasing the relative amount of germanium and providing a more rigid glass.
  • After annealing, in [0037] process segment 170, a second metal electrode is formed in contact with the silver-germanium-selenide glass. As noted, the annealing step can be performed at any time during the fabrication and/or packaging of the memory element, provided suitable annealing temperatures as noted above are present.
  • The structure produced by one implementation of the exemplary process described with reference to FIG. 1 is shown in FIG. 2 in the context of a random access memory device. However, it should be understood that the invention may be used in other types of memory devices. Also, other embodiments may be used and structural or logical changes may be made to the described and illustrated embodiment without departing from the spirit or the scope of the present invention. [0038]
  • FIG. 2 illustrates an exemplary construction of a resistance variable memory element. A resistance [0039] variable memory element 10 in accordance with the present invention is generally fabricated over a semiconductor substrate 62 and comprises a first insulating layer 60 formed over a substrate 62 in and on which may be fabricated access circuitry for operating a resistance variable memory element as part of a memory array of such elements. The insulating layer 60 contains a conductive plug 61. In accordance with process segment 110, a first metal electrode 52 is formed within a second insulating layer 53 provided over the insulating layer 60 and plug 61. In accordance with process segment 120, a third insulating layer 68 is formed over the first electrode 52 and second insulating layer 53. In accordance with process segment 130, an etched opening is provided for depositing a chalcogenide glass 58 in the opening of the third insulating layer 68.
  • Following through to process [0040] segment 140, the chalcogenide glass 58 is deposited in the opening and in contact with the first electrode 52. In accordance with process segment 150, a metal, preferably silver, is incorporated into the chalcogenide glass. As described, the glass may be a silver-germanium-selenide glass, or the metal may be provided in numerous different ways, including incorporation into the glass by doping the glass with a metal dopant. The metal dopant preferably comprises silver.
  • In accordance with [0041] process segment 160, the glass backbone 66 is subsequently annealed to drive off selenium from the silver-germanium-selenide glass and form a more rigid glass structure. Next, according to process segment 170, a second metal electrode 54 is formed in contact with the silver-germanium-selenide glass 58.
  • The third insulating [0042] layer 68 may be formed, for example, between the first electrode 52 and the second electrode 54 of any suitable insulator, for example a nitride, an oxide, or other insulator. The third insulating layer 68 may be formed by any known deposition method, for example, by sputtering, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD) or physical vapor deposition (PVD), among others. The third insulating layer 68 may comprise an insulating material that provides a diffusion barrier for metals, such as silver. A preferred insulating material is silicon nitride, but those skilled in the art will appreciate that there are other numerous suitable insulating materials for this purpose. The thickness T of the third insulating layer 68 and chalcogenide glass 58 is in the range of from about 100 Angstroms to about 10,000 Angstroms and is preferably about 500 Angstroms.
  • As noted, the [0043] chalcogenide glass 58 is preferably a germanium-selenide composition comprising silver and having a Ge/Se stoichiometry of from about Ge20Se80 to about Ge23Se77. However, the invention may also be carried out with other chalcogenide glasses having other metals incorporated therein, as long as the glass is annealed to increase its rigidity.
  • The [0044] first electrode 52 may also be electrically connected to a source/drain region 81 of an access transistor 83, which is fabricated within and on substrate 62. Another source/drain region 85 may be connected by a bit line plug 87 to a bit line of a memory array. The gate of the transistor 83 may be part of a word line which is connected to a plurality of resistance variable memory elements just as the bit line 93 may be coupled to a plurality of resistance variable memory elements through respective access transistors. The bit line 93 may be formed over a fourth insulating layer 91 and may be formed of any conductive material, for example, a metal. As shown, the bit line 93 connects to the bit line plug 87, which in turn connects with access transistor 83.
  • Although FIG. 2 illustrates the formation of only one resistance [0045] variable memory element 10, it should be understood that the present invention contemplates the formation of any number of such resistance variable memory elements, which can be formed within one or more memory element arrays.
  • The above description and drawings are only to be considered illustrative of exemplary embodiments, which achieve the features and advantages of the present invention. Modification and substitutions to specific process conditions and structures can be made without departing from the spirit and scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims. [0046]

Claims (27)

1-33. (Canceled).
34. A resistance variable memory element comprising;
a first electrode;
an annealed silver-germanium-selenide glass in electrical communication with said first electrode; and
a second electrode in electrical communication with said annealed silver-germanium-selenide glass.
35. The element of claim 34 wherein said glass has a germanium molar concentration number greater than about 0.23.
36. The element of claim 34 wherein said glass has a mean coordination number of at least about 2.46.
37. A chalcogenide element comprising:
an annealed silver doped germanium-selenide glass, wherein said glass has a germanium molar concentration number of greater than about 0.23.
38. A chalcogenide element comprising:
an annealed silver doped germanium-selenide glass, wherein said glass has a mean coordination number of at least about 2.46.
39. A resistance variable element comprising:
an annealed metal containing resistance variable material having an increased rigidity.
40. The element of claim 39 wherein said metal is silver.
41. The element of claim 39 wherein said annealed metal containing resistance variable material comprises a germanium-selenide glass.
42. The element of claim 41 wherein said germanium-selenide glass has a germanium molar concentration number of greater than about 0.23.
43. The element of claim 39 wherein said annealed metal containing resistance variable material has a mean coordination number of at least about 2.46.
44. The element of claim 39 wherein said annealed metal containing resistance variable material comprises a silver doped germanium-selenide.
45. A resistance variable element comprising:
an annealed metal containing resistance variable materials having an increased rigidity;
at least one access transistor and at least one capacitor for storing a data value which is associated with said access transistor, and
at least one metal plug electrically connected to an active area of said transistor.
46. The element of claim 45 wherein said metal comprises silver.
47. The element of claim 45 wherein said annealed metal containing resistance variable material comprises a germanium-selenide glass.
48. The element of claim 47 wherein said germanium-selenide glass has a germanium molar concentration number of greater than about 0.23.
49. The element of claim 45 wherein said annealed metal containing resistance variable material has a mean coordination number of at least about 2.46.
50. The device element of claim 45 wherein said annealed metal containing resistance variable material comprises a silver doped germanium-selenide.
51. A computer device having a memory, said memory comprising:
an annealed metal containing resistance variable material having increased rigidity.
52. The device of claim 51 wherein said metal comprises silver.
53. The device of claim 51 wherein said annealed metal containing resistance variable material comprises a germanium-selenide glass.
54. The device of claim 53 wherein said germanium-selenide glass has a germanium molar concentration number of greater than about 0.23.
55. The device of claim 51 wherein said annealed metal containing resistance variable material has a mean coordination number of at least about 2.46.
56. The device of claim 51 wherein said annealed metal containing resistance variable material comprises a silver doped germanium-selenide.
57. A resistance variable element comprising:
an annealed resistance variable material having an increased rigidity.
58. The element of claim 57 wherein said annealed resistance variable material comprises silver.
59. The device element of claim 57 wherein said annealed resistance variable material comprises a germanium-selenide glass.
US10/865,903 2002-02-15 2004-06-14 Resistance variable memory element having chalcogenide glass for improved switching characteristics Abandoned US20040223390A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/865,903 US20040223390A1 (en) 2002-02-15 2004-06-14 Resistance variable memory element having chalcogenide glass for improved switching characteristics

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/075,390 US6867064B2 (en) 2002-02-15 2002-02-15 Method to alter chalcogenide glass for improved switching characteristics
US10/865,903 US20040223390A1 (en) 2002-02-15 2004-06-14 Resistance variable memory element having chalcogenide glass for improved switching characteristics

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/075,390 Division US6867064B2 (en) 2002-02-15 2002-02-15 Method to alter chalcogenide glass for improved switching characteristics

Publications (1)

Publication Number Publication Date
US20040223390A1 true US20040223390A1 (en) 2004-11-11

Family

ID=27732421

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/075,390 Expired - Fee Related US6867064B2 (en) 2002-02-15 2002-02-15 Method to alter chalcogenide glass for improved switching characteristics
US10/865,903 Abandoned US20040223390A1 (en) 2002-02-15 2004-06-14 Resistance variable memory element having chalcogenide glass for improved switching characteristics

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/075,390 Expired - Fee Related US6867064B2 (en) 2002-02-15 2002-02-15 Method to alter chalcogenide glass for improved switching characteristics

Country Status (1)

Country Link
US (2) US6867064B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080121859A1 (en) * 2006-10-19 2008-05-29 Boise State University Forced ion migration for chalcogenide phase change memory device
US7479650B2 (en) * 2002-04-10 2009-01-20 Micron Technology, Inc. Method of manufacture of programmable conductor memory
US20100027324A1 (en) * 2008-08-01 2010-02-04 Boise State University Variable integrated analog resistor
US20110079709A1 (en) * 2009-10-07 2011-04-07 Campbell Kristy A Wide band sensor
US20120132881A1 (en) * 2010-11-29 2012-05-31 Jun Liu Cross-point memory with self-defined memory elements
US8284590B2 (en) 2010-05-06 2012-10-09 Boise State University Integratable programmable capacitive device
US8467236B2 (en) 2008-08-01 2013-06-18 Boise State University Continuously variable resistor

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7102150B2 (en) * 2001-05-11 2006-09-05 Harshfield Steven T PCRAM memory cell and method of making same
US6951805B2 (en) * 2001-08-01 2005-10-04 Micron Technology, Inc. Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry
US6955940B2 (en) 2001-08-29 2005-10-18 Micron Technology, Inc. Method of forming chalcogenide comprising devices
US6881623B2 (en) * 2001-08-29 2005-04-19 Micron Technology, Inc. Method of forming chalcogenide comprising devices, method of forming a programmable memory cell of memory circuitry, and a chalcogenide comprising device
US6646902B2 (en) 2001-08-30 2003-11-11 Micron Technology, Inc. Method of retaining memory state in a programmable conductor RAM
US6791859B2 (en) 2001-11-20 2004-09-14 Micron Technology, Inc. Complementary bit PCRAM sense amplifier and method of operation
US6909656B2 (en) * 2002-01-04 2005-06-21 Micron Technology, Inc. PCRAM rewrite prevention
US6867064B2 (en) * 2002-02-15 2005-03-15 Micron Technology, Inc. Method to alter chalcogenide glass for improved switching characteristics
US7151273B2 (en) 2002-02-20 2006-12-19 Micron Technology, Inc. Silver-selenide/chalcogenide glass stack for resistance variable memory
US6864500B2 (en) * 2002-04-10 2005-03-08 Micron Technology, Inc. Programmable conductor memory cell structure
US6825135B2 (en) 2002-06-06 2004-11-30 Micron Technology, Inc. Elimination of dendrite formation during metal/chalcogenide glass deposition
US6890790B2 (en) * 2002-06-06 2005-05-10 Micron Technology, Inc. Co-sputter deposition of metal-doped chalcogenides
US6867996B2 (en) * 2002-08-29 2005-03-15 Micron Technology, Inc. Single-polarity programmable resistance-variable memory element
US6864521B2 (en) * 2002-08-29 2005-03-08 Micron Technology, Inc. Method to control silver concentration in a resistance variable memory element
US7364644B2 (en) 2002-08-29 2008-04-29 Micron Technology, Inc. Silver selenide film stoichiometry and morphology control in sputter deposition
US6867114B2 (en) * 2002-08-29 2005-03-15 Micron Technology Inc. Methods to form a memory cell with metal-rich metal chalcogenide
US7022579B2 (en) * 2003-03-14 2006-04-04 Micron Technology, Inc. Method for filling via with metal
US6903361B2 (en) * 2003-09-17 2005-06-07 Micron Technology, Inc. Non-volatile memory structure
KR100533958B1 (en) 2004-01-05 2005-12-06 삼성전자주식회사 Phase-change memory device and method of manufacturing the same
US7583551B2 (en) 2004-03-10 2009-09-01 Micron Technology, Inc. Power management control and controlling memory refresh operations
US7326950B2 (en) 2004-07-19 2008-02-05 Micron Technology, Inc. Memory device with switching glass layer
US7354793B2 (en) 2004-08-12 2008-04-08 Micron Technology, Inc. Method of forming a PCRAM device incorporating a resistance-variable chalocogenide element
US7365411B2 (en) 2004-08-12 2008-04-29 Micron Technology, Inc. Resistance variable memory with temperature tolerant materials
DE102004046804B4 (en) * 2004-09-27 2006-10-05 Infineon Technologies Ag Resistively switching semiconductor memory
US20060131555A1 (en) * 2004-12-22 2006-06-22 Micron Technology, Inc. Resistance variable devices with controllable channels
US7374174B2 (en) 2004-12-22 2008-05-20 Micron Technology, Inc. Small electrode for resistance variable devices
US7317200B2 (en) 2005-02-23 2008-01-08 Micron Technology, Inc. SnSe-based limited reprogrammable cell
US20060228853A1 (en) * 2005-03-28 2006-10-12 Won-Cheol Jeong Memory devices including spacers on sidewalls of memory storage elements and related methods
US7427770B2 (en) 2005-04-22 2008-09-23 Micron Technology, Inc. Memory array for increased bit density
US7709289B2 (en) 2005-04-22 2010-05-04 Micron Technology, Inc. Memory elements having patterned electrodes and method of forming the same
US7274034B2 (en) 2005-08-01 2007-09-25 Micron Technology, Inc. Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
US7332735B2 (en) 2005-08-02 2008-02-19 Micron Technology, Inc. Phase change memory cell and method of formation
US7579615B2 (en) 2005-08-09 2009-08-25 Micron Technology, Inc. Access transistor for memory device
US7251154B2 (en) 2005-08-15 2007-07-31 Micron Technology, Inc. Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
US20070045606A1 (en) * 2005-08-30 2007-03-01 Michele Magistretti Shaping a phase change layer in a phase change memory cell
US7560723B2 (en) 2006-08-29 2009-07-14 Micron Technology, Inc. Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication
US7940552B2 (en) * 2007-04-30 2011-05-10 Samsung Electronics Co., Ltd. Multiple level cell phase-change memory device having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices
KR100914267B1 (en) * 2007-06-20 2009-08-27 삼성전자주식회사 Resistance changeable memory device and forming thereof
US7825479B2 (en) 2008-08-06 2010-11-02 International Business Machines Corporation Electrical antifuse having a multi-thickness dielectric layer
KR101445333B1 (en) * 2008-08-29 2014-10-01 삼성전자주식회사 Methods for forming resistance changeable memory devices
FR2965569B1 (en) * 2010-10-04 2019-06-14 X-Fab France USE OF A PROCESS FOR DEPOSITION BY CATHODIC SPRAYING OF A CHALCOGENURE LAYER
FR2977709B1 (en) 2011-07-05 2015-01-02 Altis Semiconductor Snc METHOD FOR MANUFACTURING A PROGRAMMABLE MEMORY MICROELECTRONIC DEVICE
US9130162B2 (en) 2012-12-20 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Resistance variable memory structure and method of forming the same
KR102053926B1 (en) * 2013-03-15 2019-12-09 에스케이하이닉스 주식회사 Semiconductor device and method for manufacturing the same, and micro processor, processor, system, data storage system and memory system including the semiconductor device
RU2540486C1 (en) * 2013-09-27 2015-02-10 федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский национальный исследовательский университет информационных технологий, механики и оптики" (Университет ИТМО) Method of obtainment of resistance storage element

Citations (89)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4809044A (en) * 1986-08-22 1989-02-28 Energy Conversion Devices, Inc. Thin film overvoltage protection devices
US4818717A (en) * 1986-06-27 1989-04-04 Energy Conversion Devices, Inc. Method for making electronic matrix arrays
US4843443A (en) * 1984-05-14 1989-06-27 Energy Conversion Devices, Inc. Thin film field effect transistor and method of making same
US4845533A (en) * 1986-08-22 1989-07-04 Energy Conversion Devices, Inc. Thin film electrical devices with amorphous carbon electrodes and method of making same
US4853785A (en) * 1986-10-15 1989-08-01 Energy Conversion Devices, Inc. Electronic camera including electronic signal storage cartridge
US4891330A (en) * 1987-07-27 1990-01-02 Energy Conversion Devices, Inc. Method of fabricating n-type and p-type microcrystalline semiconductor alloy material including band gap widening elements
US5128099A (en) * 1991-02-15 1992-07-07 Energy Conversion Devices, Inc. Congruent state changeable optical memory material and device
US5177567A (en) * 1991-07-19 1993-01-05 Energy Conversion Devices, Inc. Thin-film structure for chalcogenide electrical switching devices and process therefor
US5296716A (en) * 1991-01-18 1994-03-22 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
US5335219A (en) * 1991-01-18 1994-08-02 Ovshinsky Stanford R Homogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements
US5341328A (en) * 1991-01-18 1994-08-23 Energy Conversion Devices, Inc. Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life
US5406506A (en) * 1993-11-09 1995-04-11 United Microelectronics Corp. Domino adder circuit having MOS transistors in the carry evaluating paths
US5414271A (en) * 1991-01-18 1995-05-09 Energy Conversion Devices, Inc. Electrically erasable memory elements having improved set resistance stability
US5534711A (en) * 1991-01-18 1996-07-09 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
US5534712A (en) * 1991-01-18 1996-07-09 Energy Conversion Devices, Inc. Electrically erasable memory elements characterized by reduced current and improved thermal stability
US5536947A (en) * 1991-01-18 1996-07-16 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory element and arrays fabricated therefrom
US5543737A (en) * 1995-02-10 1996-08-06 Energy Conversion Devices, Inc. Logical operation circuit employing two-terminal chalcogenide switches
US5591501A (en) * 1995-12-20 1997-01-07 Energy Conversion Devices, Inc. Optical recording medium having a plurality of discrete phase change data recording points
US5596522A (en) * 1991-01-18 1997-01-21 Energy Conversion Devices, Inc. Homogeneous compositions of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements
US5714768A (en) * 1995-10-24 1998-02-03 Energy Conversion Devices, Inc. Second-layer phase change memory array on top of a logic device
US5814527A (en) * 1996-07-22 1998-09-29 Micron Technology, Inc. Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories
US5893732A (en) * 1996-10-25 1999-04-13 Micron Technology, Inc. Method of fabricating intermediate SRAM array product and conditioning memory elements thereof
US5896843A (en) * 1997-11-24 1999-04-27 Siemens Automotive Corporation Fuel rail damper
US5912839A (en) * 1998-06-23 1999-06-15 Energy Conversion Devices, Inc. Universal memory element and method of programming same
US5933365A (en) * 1997-06-19 1999-08-03 Energy Conversion Devices, Inc. Memory element with energy control mechanism
US6011757A (en) * 1998-01-27 2000-01-04 Ovshinsky; Stanford R. Optical recording media having increased erasability
US6031287A (en) * 1997-06-18 2000-02-29 Micron Technology, Inc. Contact structure and memory element incorporating the same
US6087674A (en) * 1996-10-28 2000-07-11 Energy Conversion Devices, Inc. Memory element with memory material comprising phase-change material and dielectric material
US20020000666A1 (en) * 1998-08-31 2002-01-03 Michael N. Kozicki Self-repairing interconnections for electrical circuits
US6339544B1 (en) * 2000-09-29 2002-01-15 Intel Corporation Method to enhance performance of thermal resistor device
US6404665B1 (en) * 2000-09-29 2002-06-11 Intel Corporation Compositionally modified resistive electrode
US6429064B1 (en) * 2000-09-29 2002-08-06 Intel Corporation Reduced contact area of sidewall conductor
US20020106849A1 (en) * 2001-02-08 2002-08-08 Moore John T. Method of forming non-volatile resistance variable devices, method of precluding diffusion of a metal into adjacent chalcogenide material, and non-volatile resistance variable devices
US6437383B1 (en) * 2000-12-21 2002-08-20 Intel Corporation Dual trench isolation for a phase-change memory cell and method of making same
US6440837B1 (en) * 2000-07-14 2002-08-27 Micron Technology, Inc. Method of forming a contact structure in a semiconductor device
US20020123170A1 (en) * 2001-03-02 2002-09-05 Moore John T. PCRAM cell manufacturing
US20020123169A1 (en) * 2001-03-01 2002-09-05 Moore John T. Methods of forming non-volatile resistance variable devices, and non-volatile resistance variable devices
US20020127886A1 (en) * 2001-03-07 2002-09-12 Moore John T. Method to manufacture a buried electrode PCRAM cell
US20020132417A1 (en) * 2001-03-15 2002-09-19 Jiutao Li Agglomeration elimination for metal sputter deposition of chalcogenides
US6507061B1 (en) * 2001-08-31 2003-01-14 Intel Corporation Multiple layer phase-change memory
US6511862B2 (en) * 2001-06-30 2003-01-28 Ovonyx, Inc. Modified contact for programmable devices
US6512241B1 (en) * 2001-12-31 2003-01-28 Intel Corporation Phase change material memory device
US6511867B2 (en) * 2001-06-30 2003-01-28 Ovonyx, Inc. Utilizing atomic layer deposition for programmable device
US6514805B2 (en) * 2001-06-30 2003-02-04 Intel Corporation Trench sidewall profile for device isolation
US20030027416A1 (en) * 2001-08-01 2003-02-06 Moore John T. Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry
US20030032254A1 (en) * 2000-12-08 2003-02-13 Gilton Terry L. Resistance variable device, analog memory device, and programmable memory cell
US20030035314A1 (en) * 1998-12-04 2003-02-20 Kozicki Michael N. Programmable microelectronic devices and methods of forming and programming same
US20030035315A1 (en) * 2001-04-06 2003-02-20 Kozicki Michael N. Microelectronic device, structure, and system, including a memory structure having a variable programmable property and method of forming the same
US20030038301A1 (en) * 2001-08-27 2003-02-27 John Moore Apparatus and method for dual cell common electrode PCRAM memory device
US20030045049A1 (en) * 2001-08-29 2003-03-06 Campbell Kristy A. Method of forming chalcogenide comprising devices
US20030045054A1 (en) * 2001-08-29 2003-03-06 Campbell Kristy A. Method of forming non-volatile resistance variable devices, method of forming a programmable memory cell of memory circuitry, and a non-volatile resistance variable device
US20030043631A1 (en) * 2001-08-30 2003-03-06 Gilton Terry L. Method of retaining memory state in a programmable conductor RAM
US6531373B2 (en) * 2000-12-27 2003-03-11 Ovonyx, Inc. Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements
US20030048744A1 (en) * 2001-09-01 2003-03-13 Ovshinsky Stanford R. Increased data storage in optical data storage and retrieval systems using blue lasers and/or plasmon lenses
US20030048519A1 (en) * 2000-02-11 2003-03-13 Kozicki Michael N. Microelectronic photonic structure and device and method of forming the same
US20030049912A1 (en) * 2001-08-29 2003-03-13 Campbell Kristy A. Method of forming chalcogenide comprsing devices and method of forming a programmable memory cell of memory circuitry
US20030047765A1 (en) * 2001-08-30 2003-03-13 Campbell Kristy A. Stoichiometry for chalcogenide glasses useful for memory devices and method of formation
US6534781B2 (en) * 2000-12-26 2003-03-18 Ovonyx, Inc. Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact
US6545907B1 (en) * 2001-10-30 2003-04-08 Ovonyx, Inc. Technique and apparatus for performing write operations to a phase change material memory device
US6545287B2 (en) * 2001-09-07 2003-04-08 Intel Corporation Using selective deposition to form phase-change memory cells
US20030068862A1 (en) * 2001-08-30 2003-04-10 Jiutao Li Integrated circuit device and fabrication using metal-doped chalcogenide materials
US6555860B2 (en) * 2000-09-29 2003-04-29 Intel Corporation Compositionally modified resistive electrode
US6563164B2 (en) * 2000-09-29 2003-05-13 Ovonyx, Inc. Compositionally modified resistive electrode
US6566700B2 (en) * 2001-10-11 2003-05-20 Ovonyx, Inc. Carbon-containing interfacial layer for phase-change memory
US6567293B1 (en) * 2000-09-29 2003-05-20 Ovonyx, Inc. Single level metal memory cell using chalcogenide cladding
US20030096497A1 (en) * 2001-11-19 2003-05-22 Micron Technology, Inc. Electrode structure for use in an integrated circuit
US20030095426A1 (en) * 2001-11-20 2003-05-22 Glen Hush Complementary bit PCRAM sense amplifier and method of operation
US6569705B2 (en) * 2000-12-21 2003-05-27 Intel Corporation Metal structure for a phase-change memory device
US6570784B2 (en) * 2001-06-29 2003-05-27 Ovonyx, Inc. Programming a phase-change material memory
US6576921B2 (en) * 2001-11-08 2003-06-10 Intel Corporation Isolating phase change material memory cells
US20030107105A1 (en) * 1999-08-31 2003-06-12 Kozicki Michael N. Programmable chip-to-substrate interconnect structure and device and method of forming same
US20030117831A1 (en) * 2001-12-20 2003-06-26 Glen Hush Programmable conductor random access memory and a method for writing thereto
US6586761B2 (en) * 2001-09-07 2003-07-01 Intel Corporation Phase change material memory device
US6589714B2 (en) * 2001-06-26 2003-07-08 Ovonyx, Inc. Method for making programmable resistance memory element using silylated photoresist
US6590807B2 (en) * 2001-08-02 2003-07-08 Intel Corporation Method for reading a structural phase-change memory
US20030128612A1 (en) * 2002-01-04 2003-07-10 John Moore PCRAM rewrite prevention
US20030137869A1 (en) * 1998-12-04 2003-07-24 Kozicki Michael N. Programmable microelectronic device, structure, and system and method of forming the same
US20030143782A1 (en) * 2002-01-31 2003-07-31 Gilton Terry L. Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures
US6605527B2 (en) * 2001-06-30 2003-08-12 Intel Corporation Reduced area intersection between electrode and programming element
US20030156447A1 (en) * 2000-02-11 2003-08-21 Kozicki Michael N. Programming circuit for a programmable microelectronic device, system including the circuit, and method of forming the same
US20030156463A1 (en) * 2002-02-19 2003-08-21 Casper Stephen L. Programmable conductor random access memory and method for sensing same
US20030155589A1 (en) * 2002-02-20 2003-08-21 Campbell Kristy A. Silver-selenide/chalcogenide glass stack for resistance variable memory
US20030155606A1 (en) * 2002-02-15 2003-08-21 Campbell Kristy A. Method to alter chalcogenide glass for improved switching characteristics
US6673700B2 (en) * 2001-06-30 2004-01-06 Ovonyx, Inc. Reduced area intersection between electrode and programming element
US6687427B2 (en) * 2000-12-29 2004-02-03 Intel Corporation Optic switch
US6690026B2 (en) * 2001-09-28 2004-02-10 Intel Corporation Method of fabricating a three-dimensional array of active media
US6696355B2 (en) * 2000-12-14 2004-02-24 Ovonyx, Inc. Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory
US20040035401A1 (en) * 2002-08-26 2004-02-26 Subramanian Ramachandran Hydrogen powered scooter
US6714954B2 (en) * 2002-05-10 2004-03-30 Energy Conversion Devices, Inc. Methods of factoring and modular arithmetic

Family Cites Families (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US163828A (en) * 1875-05-25 Improvement in apparatus for variegating soap
US137869A (en) * 1873-04-15 Improvement in stilts
US38301A (en) * 1863-04-28 Improved alloys of aluminum
US47772A (en) * 1865-05-16 Improvement in grain-separators
US190289A (en) * 1877-05-01 Improvement in sewing-machine shuttles
US47765A (en) * 1865-05-16 Improved metallic thill-holder
US32254A (en) * 1861-05-07 Improvement in methods of distillation
US47773A (en) * 1865-05-16 Chakles k
US43631A (en) * 1864-07-26 Adjusting patterns foe boots
US3271591A (en) 1963-09-20 1966-09-06 Energy Conversion Devices Inc Symmetrical current controlling device
US3622319A (en) 1966-10-20 1971-11-23 Western Electric Co Nonreflecting photomasks and methods of making same
US3868651A (en) 1970-08-13 1975-02-25 Energy Conversion Devices Inc Method and apparatus for storing and reading data in a memory having catalytic material to initiate amorphous to crystalline change in memory structure
US3743847A (en) 1971-06-01 1973-07-03 Motorola Inc Amorphous silicon film as a uv filter
US4267261A (en) 1971-07-15 1981-05-12 Energy Conversion Devices, Inc. Method for full format imaging
US3961314A (en) 1974-03-05 1976-06-01 Energy Conversion Devices, Inc. Structure and method for producing an image
US3966317A (en) 1974-04-08 1976-06-29 Energy Conversion Devices, Inc. Dry process production of archival microform records from hard copy
US4177474A (en) 1977-05-18 1979-12-04 Energy Conversion Devices, Inc. High temperature amorphous semiconductor member and method of making the same
JPS5565365A (en) 1978-11-07 1980-05-16 Nippon Telegr & Teleph Corp <Ntt> Pattern forming method
DE2901303C2 (en) 1979-01-15 1984-04-19 Max Planck Gesellschaft Zur Foerderung Der Wissenschaften E.V., 3400 Goettingen Solid ionic conductor material, its use and process for its manufacture
US4312938A (en) 1979-07-06 1982-01-26 Drexler Technology Corporation Method for making a broadband reflective laser recording and data storage medium with absorptive underlayer
US4269935A (en) 1979-07-13 1981-05-26 Ionomet Company, Inc. Process of doping silver image in chalcogenide layer
US4316946A (en) 1979-12-03 1982-02-23 Ionomet Company, Inc. Surface sensitized chalcogenide product and process for making and using the same
US4499557A (en) 1980-10-28 1985-02-12 Energy Conversion Devices, Inc. Programmable cell for use in programmable electronic arrays
US4405710A (en) 1981-06-22 1983-09-20 Cornell Research Foundation, Inc. Ion beam exposure of (g-Gex -Se1-x) inorganic resists
US4737379A (en) 1982-09-24 1988-04-12 Energy Conversion Devices, Inc. Plasma deposited coatings, and low temperature plasma method of making same
US4545111A (en) 1983-01-18 1985-10-08 Energy Conversion Devices, Inc. Method for making, parallel preprogramming or field programming of electronic matrix arrays
US4608296A (en) 1983-12-06 1986-08-26 Energy Conversion Devices, Inc. Superconducting films and devices exhibiting AC to DC conversion
US4795657A (en) 1984-04-13 1989-01-03 Energy Conversion Devices, Inc. Method of fabricating a programmable array
US4769338A (en) 1984-05-14 1988-09-06 Energy Conversion Devices, Inc. Thin film field effect transistor and method of making same
US4673957A (en) 1984-05-14 1987-06-16 Energy Conversion Devices, Inc. Integrated circuit compatible thin film field effect transistor and method of making same
US4670763A (en) 1984-05-14 1987-06-02 Energy Conversion Devices, Inc. Thin film field effect transistor
US4668968A (en) 1984-05-14 1987-05-26 Energy Conversion Devices, Inc. Integrated circuit compatible thin film field effect transistor and method of making same
US4678679A (en) 1984-06-25 1987-07-07 Energy Conversion Devices, Inc. Continuous deposition of activated process gases
US4646266A (en) 1984-09-28 1987-02-24 Energy Conversion Devices, Inc. Programmable semiconductor structures and methods for using the same
US4637895A (en) 1985-04-01 1987-01-20 Energy Conversion Devices, Inc. Gas mixtures for the vapor deposition of semiconductor material
US4664939A (en) 1985-04-01 1987-05-12 Energy Conversion Devices, Inc. Vertical semiconductor processor
US4710899A (en) 1985-06-10 1987-12-01 Energy Conversion Devices, Inc. Data storage medium incorporating a transition metal for increased switching speed
US4671618A (en) 1986-05-22 1987-06-09 Wu Bao Gang Liquid crystalline-plastic material having submillisecond switch times and extended memory
US4766471A (en) 1986-01-23 1988-08-23 Energy Conversion Devices, Inc. Thin film electro-optical devices
US4728406A (en) 1986-08-18 1988-03-01 Energy Conversion Devices, Inc. Method for plasma - coating a semiconductor body
US4788594A (en) 1986-10-15 1988-11-29 Energy Conversion Devices, Inc. Solid state electronic camera including thin film matrix of photosensors
US4847674A (en) 1987-03-10 1989-07-11 Advanced Micro Devices, Inc. High speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism
US4800526A (en) 1987-05-08 1989-01-24 Gaf Corporation Memory element for information storage and retrieval system and associated process
US4775425A (en) 1987-07-27 1988-10-04 Energy Conversion Devices, Inc. P and n-type microcrystalline semiconductor alloy material including band gap widening elements, devices utilizing same
US4804490A (en) * 1987-10-13 1989-02-14 Energy Conversion Devices, Inc. Method of fabricating stabilized threshold switching material
US5272359A (en) 1988-04-07 1993-12-21 California Institute Of Technology Reversible non-volatile switch based on a TCNQ charge transfer complex
GB8910854D0 (en) 1989-05-11 1989-06-28 British Petroleum Co Plc Semiconductor device
US4920078A (en) * 1989-06-02 1990-04-24 Bell Communications Research, Inc. Arsenic sulfide surface passivation of III-V semiconductors
US5159661A (en) 1990-10-05 1992-10-27 Energy Conversion Devices, Inc. Vertically interconnected parallel distributed processor
US5314772A (en) 1990-10-09 1994-05-24 Arizona Board Of Regents High resolution, multi-layer resist for microlithography and method therefor
JPH0770731B2 (en) 1990-11-22 1995-07-31 松下電器産業株式会社 Electroplastic element
US5330630A (en) * 1991-01-02 1994-07-19 Energy Conversion Devices, Inc. Switch with improved threshold voltage
US5166758A (en) 1991-01-18 1992-11-24 Energy Conversion Devices, Inc. Electrically erasable phase change memory
US5406509A (en) 1991-01-18 1995-04-11 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
US5219788A (en) 1991-02-25 1993-06-15 Ibm Corporation Bilayer metallization cap for photolithography
FR2679633B1 (en) 1991-07-26 1997-12-12 Faiveley Sa INSTALLATION FOR PRODUCING COLD BY SOLID / GAS REACTION, THE REACTOR INCLUDING MEANS OF COOLING.
US5359205A (en) 1991-11-07 1994-10-25 Energy Conversion Devices, Inc. Electrically erasable memory elements characterized by reduced current and improved thermal stability
US5238862A (en) 1992-03-18 1993-08-24 Micron Technology, Inc. Method of forming a stacked capacitor with striated electrode
KR940004732A (en) 1992-08-07 1994-03-15 가나이 쯔또무 Pattern formation method and thin film formation method used for pattern formation
US5350484A (en) 1992-09-08 1994-09-27 Intel Corporation Method for the anisotropic etching of metal films in the fabrication of interconnects
US5818749A (en) 1993-08-20 1998-10-06 Micron Technology, Inc. Integrated circuit memory device
BE1007902A3 (en) 1993-12-23 1995-11-14 Philips Electronics Nv Switching element with memory with schottky barrier tunnel.
US5500532A (en) 1994-08-18 1996-03-19 Arizona Board Of Regents Personal electronic dosimeter
JP2643870B2 (en) 1994-11-29 1997-08-20 日本電気株式会社 Method for manufacturing semiconductor memory device
US6420725B1 (en) 1995-06-07 2002-07-16 Micron Technology, Inc. Method and apparatus for forming an integrated circuit electrode having a reduced contact area
US5869843A (en) 1995-06-07 1999-02-09 Micron Technology, Inc. Memory array having a multi-state element and method for forming such array or cells thereof
US5751012A (en) 1995-06-07 1998-05-12 Micron Technology, Inc. Polysilicon pillar diode for use in a non-volatile memory cell
JP3363154B2 (en) 1995-06-07 2003-01-08 ミクロン テクノロジー、インコーポレイテッド Stack / trench diode for use with multi-state material in a non-volatile memory cell
US5879955A (en) * 1995-06-07 1999-03-09 Micron Technology, Inc. Method for fabricating an array of ultra-small pores for chalcogenide memory cells
US5789758A (en) 1995-06-07 1998-08-04 Micron Technology, Inc. Chalcogenide memory cell with a plurality of chalcogenide electrodes
US5837564A (en) 1995-11-01 1998-11-17 Micron Technology, Inc. Method for optimal crystallization to obtain high electrical performance from chalcogenides
US5694054A (en) 1995-11-28 1997-12-02 Energy Conversion Devices, Inc. Integrated drivers for flat panel displays employing chalcogenide logic elements
US6653733B1 (en) * 1996-02-23 2003-11-25 Micron Technology, Inc. Conductors in semiconductor devices
US5687112A (en) 1996-04-19 1997-11-11 Energy Conversion Devices, Inc. Multibit single cell memory element having tapered contact
US5851882A (en) 1996-05-06 1998-12-22 Micron Technology, Inc. ZPROM manufacture and design and methods for forming thin structures using spacers as an etching mask
US5761115A (en) 1996-05-30 1998-06-02 Axon Technologies Corporation Programmable metallization cell structure and method of making same
US5789277A (en) 1996-07-22 1998-08-04 Micron Technology, Inc. Method of making chalogenide memory device
US5998244A (en) * 1996-08-22 1999-12-07 Micron Technology, Inc. Memory cell incorporating a chalcogenide element and method of making same
US5825046A (en) 1996-10-28 1998-10-20 Energy Conversion Devices, Inc. Composite memory material comprising a mixture of phase-change memory material and dielectric material
US5846889A (en) 1997-03-14 1998-12-08 The United States Of America As Represented By The Secretary Of The Navy Infrared transparent selenide glasses
US5998066A (en) 1997-05-16 1999-12-07 Aerial Imaging Corporation Gray scale mask and depth pattern transfer technique using inorganic chalcogenide glass
US6141241A (en) 1998-06-23 2000-10-31 Energy Conversion Devices, Inc. Universal memory element with systems employing same and apparatus and method for reading, writing and programming same
US6177338B1 (en) * 1999-02-08 2001-01-23 Taiwan Semiconductor Manufacturing Company Two step barrier process
US6072716A (en) 1999-04-14 2000-06-06 Massachusetts Institute Of Technology Memory structures and methods of making same
US6143604A (en) 1999-06-04 2000-11-07 Taiwan Semiconductor Manufacturing Company Method for fabricating small-size two-step contacts for word-line strapping on dynamic random access memory (DRAM)

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4843443A (en) * 1984-05-14 1989-06-27 Energy Conversion Devices, Inc. Thin film field effect transistor and method of making same
US4818717A (en) * 1986-06-27 1989-04-04 Energy Conversion Devices, Inc. Method for making electronic matrix arrays
US4809044A (en) * 1986-08-22 1989-02-28 Energy Conversion Devices, Inc. Thin film overvoltage protection devices
US4845533A (en) * 1986-08-22 1989-07-04 Energy Conversion Devices, Inc. Thin film electrical devices with amorphous carbon electrodes and method of making same
US4853785A (en) * 1986-10-15 1989-08-01 Energy Conversion Devices, Inc. Electronic camera including electronic signal storage cartridge
US4891330A (en) * 1987-07-27 1990-01-02 Energy Conversion Devices, Inc. Method of fabricating n-type and p-type microcrystalline semiconductor alloy material including band gap widening elements
US5341328A (en) * 1991-01-18 1994-08-23 Energy Conversion Devices, Inc. Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life
US5534712A (en) * 1991-01-18 1996-07-09 Energy Conversion Devices, Inc. Electrically erasable memory elements characterized by reduced current and improved thermal stability
US5296716A (en) * 1991-01-18 1994-03-22 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
US5335219A (en) * 1991-01-18 1994-08-02 Ovshinsky Stanford R Homogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements
US5596522A (en) * 1991-01-18 1997-01-21 Energy Conversion Devices, Inc. Homogeneous compositions of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements
US5536947A (en) * 1991-01-18 1996-07-16 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory element and arrays fabricated therefrom
US5414271A (en) * 1991-01-18 1995-05-09 Energy Conversion Devices, Inc. Electrically erasable memory elements having improved set resistance stability
US5534711A (en) * 1991-01-18 1996-07-09 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
US5128099A (en) * 1991-02-15 1992-07-07 Energy Conversion Devices, Inc. Congruent state changeable optical memory material and device
US5177567A (en) * 1991-07-19 1993-01-05 Energy Conversion Devices, Inc. Thin-film structure for chalcogenide electrical switching devices and process therefor
US5406506A (en) * 1993-11-09 1995-04-11 United Microelectronics Corp. Domino adder circuit having MOS transistors in the carry evaluating paths
US5543737A (en) * 1995-02-10 1996-08-06 Energy Conversion Devices, Inc. Logical operation circuit employing two-terminal chalcogenide switches
US5714768A (en) * 1995-10-24 1998-02-03 Energy Conversion Devices, Inc. Second-layer phase change memory array on top of a logic device
US5591501A (en) * 1995-12-20 1997-01-07 Energy Conversion Devices, Inc. Optical recording medium having a plurality of discrete phase change data recording points
US5814527A (en) * 1996-07-22 1998-09-29 Micron Technology, Inc. Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories
US5893732A (en) * 1996-10-25 1999-04-13 Micron Technology, Inc. Method of fabricating intermediate SRAM array product and conditioning memory elements thereof
US6087674A (en) * 1996-10-28 2000-07-11 Energy Conversion Devices, Inc. Memory element with memory material comprising phase-change material and dielectric material
US6031287A (en) * 1997-06-18 2000-02-29 Micron Technology, Inc. Contact structure and memory element incorporating the same
US5933365A (en) * 1997-06-19 1999-08-03 Energy Conversion Devices, Inc. Memory element with energy control mechanism
US5896843A (en) * 1997-11-24 1999-04-27 Siemens Automotive Corporation Fuel rail damper
US6011757A (en) * 1998-01-27 2000-01-04 Ovshinsky; Stanford R. Optical recording media having increased erasability
US5912839A (en) * 1998-06-23 1999-06-15 Energy Conversion Devices, Inc. Universal memory element and method of programming same
US20020000666A1 (en) * 1998-08-31 2002-01-03 Michael N. Kozicki Self-repairing interconnections for electrical circuits
US20030137869A1 (en) * 1998-12-04 2003-07-24 Kozicki Michael N. Programmable microelectronic device, structure, and system and method of forming the same
US20030035314A1 (en) * 1998-12-04 2003-02-20 Kozicki Michael N. Programmable microelectronic devices and methods of forming and programming same
US20030107105A1 (en) * 1999-08-31 2003-06-12 Kozicki Michael N. Programmable chip-to-substrate interconnect structure and device and method of forming same
US20030156447A1 (en) * 2000-02-11 2003-08-21 Kozicki Michael N. Programming circuit for a programmable microelectronic device, system including the circuit, and method of forming the same
US20030048519A1 (en) * 2000-02-11 2003-03-13 Kozicki Michael N. Microelectronic photonic structure and device and method of forming the same
US6440837B1 (en) * 2000-07-14 2002-08-27 Micron Technology, Inc. Method of forming a contact structure in a semiconductor device
US6429064B1 (en) * 2000-09-29 2002-08-06 Intel Corporation Reduced contact area of sidewall conductor
US6597009B2 (en) * 2000-09-29 2003-07-22 Intel Corporation Reduced contact area of sidewall conductor
US6404665B1 (en) * 2000-09-29 2002-06-11 Intel Corporation Compositionally modified resistive electrode
US6567293B1 (en) * 2000-09-29 2003-05-20 Ovonyx, Inc. Single level metal memory cell using chalcogenide cladding
US6563164B2 (en) * 2000-09-29 2003-05-13 Ovonyx, Inc. Compositionally modified resistive electrode
US6555860B2 (en) * 2000-09-29 2003-04-29 Intel Corporation Compositionally modified resistive electrode
US6339544B1 (en) * 2000-09-29 2002-01-15 Intel Corporation Method to enhance performance of thermal resistor device
US20030032254A1 (en) * 2000-12-08 2003-02-13 Gilton Terry L. Resistance variable device, analog memory device, and programmable memory cell
US6696355B2 (en) * 2000-12-14 2004-02-24 Ovonyx, Inc. Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory
US6569705B2 (en) * 2000-12-21 2003-05-27 Intel Corporation Metal structure for a phase-change memory device
US6437383B1 (en) * 2000-12-21 2002-08-20 Intel Corporation Dual trench isolation for a phase-change memory cell and method of making same
US6534781B2 (en) * 2000-12-26 2003-03-18 Ovonyx, Inc. Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact
US6593176B2 (en) * 2000-12-26 2003-07-15 Ovonyx, Inc. Method for forming phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact
US6531373B2 (en) * 2000-12-27 2003-03-11 Ovonyx, Inc. Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements
US6687427B2 (en) * 2000-12-29 2004-02-03 Intel Corporation Optic switch
US20020106849A1 (en) * 2001-02-08 2002-08-08 Moore John T. Method of forming non-volatile resistance variable devices, method of precluding diffusion of a metal into adjacent chalcogenide material, and non-volatile resistance variable devices
US20020123169A1 (en) * 2001-03-01 2002-09-05 Moore John T. Methods of forming non-volatile resistance variable devices, and non-volatile resistance variable devices
US20020123248A1 (en) * 2001-03-01 2002-09-05 Moore John T. Methods of metal doping a chalcogenide material
US20030001229A1 (en) * 2001-03-01 2003-01-02 Moore John T. Chalcogenide comprising device
US20020123170A1 (en) * 2001-03-02 2002-09-05 Moore John T. PCRAM cell manufacturing
US20020127886A1 (en) * 2001-03-07 2002-09-12 Moore John T. Method to manufacture a buried electrode PCRAM cell
US20030047772A1 (en) * 2001-03-15 2003-03-13 Jiutao Li Agglomeration elimination for metal sputter deposition of chalcogenides
US20020132417A1 (en) * 2001-03-15 2002-09-19 Jiutao Li Agglomeration elimination for metal sputter deposition of chalcogenides
US20030047773A1 (en) * 2001-03-15 2003-03-13 Jiutao Li Agglomeration elimination for metal sputter deposition of chalcogenides
US20030035315A1 (en) * 2001-04-06 2003-02-20 Kozicki Michael N. Microelectronic device, structure, and system, including a memory structure having a variable programmable property and method of forming the same
US6589714B2 (en) * 2001-06-26 2003-07-08 Ovonyx, Inc. Method for making programmable resistance memory element using silylated photoresist
US6570784B2 (en) * 2001-06-29 2003-05-27 Ovonyx, Inc. Programming a phase-change material memory
US6687153B2 (en) * 2001-06-29 2004-02-03 Ovonyx, Inc. Programming a phase-change material memory
US6605527B2 (en) * 2001-06-30 2003-08-12 Intel Corporation Reduced area intersection between electrode and programming element
US6514805B2 (en) * 2001-06-30 2003-02-04 Intel Corporation Trench sidewall profile for device isolation
US6511867B2 (en) * 2001-06-30 2003-01-28 Ovonyx, Inc. Utilizing atomic layer deposition for programmable device
US6511862B2 (en) * 2001-06-30 2003-01-28 Ovonyx, Inc. Modified contact for programmable devices
US6673700B2 (en) * 2001-06-30 2004-01-06 Ovonyx, Inc. Reduced area intersection between electrode and programming element
US20030027416A1 (en) * 2001-08-01 2003-02-06 Moore John T. Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry
US6707712B2 (en) * 2001-08-02 2004-03-16 Intel Corporation Method for reading a structural phase-change memory
US6590807B2 (en) * 2001-08-02 2003-07-08 Intel Corporation Method for reading a structural phase-change memory
US20030038301A1 (en) * 2001-08-27 2003-02-27 John Moore Apparatus and method for dual cell common electrode PCRAM memory device
US20030049912A1 (en) * 2001-08-29 2003-03-13 Campbell Kristy A. Method of forming chalcogenide comprsing devices and method of forming a programmable memory cell of memory circuitry
US20030045049A1 (en) * 2001-08-29 2003-03-06 Campbell Kristy A. Method of forming chalcogenide comprising devices
US20030045054A1 (en) * 2001-08-29 2003-03-06 Campbell Kristy A. Method of forming non-volatile resistance variable devices, method of forming a programmable memory cell of memory circuitry, and a non-volatile resistance variable device
US20030047765A1 (en) * 2001-08-30 2003-03-13 Campbell Kristy A. Stoichiometry for chalcogenide glasses useful for memory devices and method of formation
US20030043631A1 (en) * 2001-08-30 2003-03-06 Gilton Terry L. Method of retaining memory state in a programmable conductor RAM
US20030068861A1 (en) * 2001-08-30 2003-04-10 Jiutao Li Integrated circuit device and fabrication using metal-doped chalcogenide materials
US20030068862A1 (en) * 2001-08-30 2003-04-10 Jiutao Li Integrated circuit device and fabrication using metal-doped chalcogenide materials
US6674115B2 (en) * 2001-08-31 2004-01-06 Intel Corporation Multiple layer phrase-change memory
US6507061B1 (en) * 2001-08-31 2003-01-14 Intel Corporation Multiple layer phase-change memory
US20030048744A1 (en) * 2001-09-01 2003-03-13 Ovshinsky Stanford R. Increased data storage in optical data storage and retrieval systems using blue lasers and/or plasmon lenses
US6586761B2 (en) * 2001-09-07 2003-07-01 Intel Corporation Phase change material memory device
US6545287B2 (en) * 2001-09-07 2003-04-08 Intel Corporation Using selective deposition to form phase-change memory cells
US6690026B2 (en) * 2001-09-28 2004-02-10 Intel Corporation Method of fabricating a three-dimensional array of active media
US6566700B2 (en) * 2001-10-11 2003-05-20 Ovonyx, Inc. Carbon-containing interfacial layer for phase-change memory
US6545907B1 (en) * 2001-10-30 2003-04-08 Ovonyx, Inc. Technique and apparatus for performing write operations to a phase change material memory device
US6576921B2 (en) * 2001-11-08 2003-06-10 Intel Corporation Isolating phase change material memory cells
US20030096497A1 (en) * 2001-11-19 2003-05-22 Micron Technology, Inc. Electrode structure for use in an integrated circuit
US20030095426A1 (en) * 2001-11-20 2003-05-22 Glen Hush Complementary bit PCRAM sense amplifier and method of operation
US20030117831A1 (en) * 2001-12-20 2003-06-26 Glen Hush Programmable conductor random access memory and a method for writing thereto
US6512241B1 (en) * 2001-12-31 2003-01-28 Intel Corporation Phase change material memory device
US20030128612A1 (en) * 2002-01-04 2003-07-10 John Moore PCRAM rewrite prevention
US20030143782A1 (en) * 2002-01-31 2003-07-31 Gilton Terry L. Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures
US20030155606A1 (en) * 2002-02-15 2003-08-21 Campbell Kristy A. Method to alter chalcogenide glass for improved switching characteristics
US20030156463A1 (en) * 2002-02-19 2003-08-21 Casper Stephen L. Programmable conductor random access memory and method for sensing same
US20030155589A1 (en) * 2002-02-20 2003-08-21 Campbell Kristy A. Silver-selenide/chalcogenide glass stack for resistance variable memory
US6714954B2 (en) * 2002-05-10 2004-03-30 Energy Conversion Devices, Inc. Methods of factoring and modular arithmetic
US20040035401A1 (en) * 2002-08-26 2004-02-26 Subramanian Ramachandran Hydrogen powered scooter

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7479650B2 (en) * 2002-04-10 2009-01-20 Micron Technology, Inc. Method of manufacture of programmable conductor memory
US20080121859A1 (en) * 2006-10-19 2008-05-29 Boise State University Forced ion migration for chalcogenide phase change memory device
US7924608B2 (en) 2006-10-19 2011-04-12 Boise State University Forced ion migration for chalcogenide phase change memory device
US8295081B2 (en) 2006-10-19 2012-10-23 Boise State University Forced ion migration for chalcogenide phase change memory device
US8611146B2 (en) 2006-10-19 2013-12-17 Boise State University Forced ion migration for chalcogenide phase change memory device
US20100027324A1 (en) * 2008-08-01 2010-02-04 Boise State University Variable integrated analog resistor
US8238146B2 (en) 2008-08-01 2012-08-07 Boise State University Variable integrated analog resistor
US8467236B2 (en) 2008-08-01 2013-06-18 Boise State University Continuously variable resistor
US20110079709A1 (en) * 2009-10-07 2011-04-07 Campbell Kristy A Wide band sensor
US8284590B2 (en) 2010-05-06 2012-10-09 Boise State University Integratable programmable capacitive device
US20120132881A1 (en) * 2010-11-29 2012-05-31 Jun Liu Cross-point memory with self-defined memory elements
US10297640B2 (en) * 2010-11-29 2019-05-21 Micron Technology, Inc. Cross-point memory with self-defined memory elements

Also Published As

Publication number Publication date
US20030155606A1 (en) 2003-08-21
US6867064B2 (en) 2005-03-15

Similar Documents

Publication Publication Date Title
US6867064B2 (en) Method to alter chalcogenide glass for improved switching characteristics
US20200227423A1 (en) Ferroelectric Devices and Methods of Forming Ferroelectric Devices
US8466445B2 (en) Silver-selenide/chalcogenide glass stack for resistance variable memory and manufacturing method thereof
US6891749B2 (en) Resistance variable ‘on ’ memory
US6646902B2 (en) Method of retaining memory state in a programmable conductor RAM
CN101677081B (en) Phase change memory cell array with self-converged bottom electrode and method for manufacturing
US7030405B2 (en) Method and apparatus for resistance variable material cells
US7087454B2 (en) Fabrication of single polarity programmable resistance structure
US7933139B2 (en) One-transistor, one-resistor, one-capacitor phase change memory
US7692177B2 (en) Resistance variable memory element and its method of formation
US7294527B2 (en) Method of forming a memory cell
US20050266635A1 (en) Graded GexSe100-x concentration in PCRAM
US7163837B2 (en) Method of forming a resistance variable memory element
US20040238918A1 (en) Method of manufacture of a PCRAM memory cell
US7061004B2 (en) Resistance variable memory elements and methods of formation

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: ROUND ROCK RESEARCH, LLC,NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223