US20040235398A1

US20040235398A1 - Chemical mechanical planarization method and apparatus for improved process uniformity, reduced topography and reduced defects

Info

Publication number: US20040235398A1
Application number: US10/843,265
Authority: US
Inventors: Brian Thornton; Anil Pant
Original assignee: Planar Labs Corp
Current assignee: Planar Labs Corp
Priority date: 2003-05-08
Filing date: 2004-05-10
Publication date: 2004-11-25

Abstract

A method and apparatus for utilizing an optimized polishing pad to increase planarity and reduce defects in CMP processing. The optimized polishing pad includes a polishing surface to remove material from and maintain a uniform polish rate with respect to a wafer surface. The polishing pad has a hardness between 62 and 98 shore A and a tensile modulus between 3,500 and 35,000 psi. A three-stage CMP process utilizes a hard pad, a first optimized pad and a second optimized pad to increase planarity while reducing surface defects.

Description

RELATED APPLICATION

This application is related to and hereby claims the priority benefit of U.S. Provisional Patent Application No. 60/469,164, entitled “Chemical Mechanical Planarization Method for Improved Process Uniformity, Reduced Topography and Reduced Defects,” filed May 8, 2003, incorporated herein by reference.[0001]

FIELD OF THE INVENTION

The present invention relates to the field of chemical mechanical polishing/planarization (CMP) and relates specifically to material properties of a polishing pad utilized in CMP processing.

BACKGROUND OF THE INVENTION

In modem integrated circuit (IC) fabrication technology, it is necessary to form various embedded structures over previously constructed layers of integrated circuits formed on semiconductor wafers. During the manufacturing process, certain portions of these layers need complete or partial removal to achieve the desired device structure. Chemical mechanical polishing/planarization (CMP) is a popular method to achieve this material removal. CMP is also used to prepare the surface of the bare semiconductor wafer for device construction.

In CMP a wafer is typically pressed against a moving polishing pad. Chemically active slurry containing abrasive particles is applied to the pad. The relative motion between the pad and wafer in combination with the chemical activity and abrasion from the slurry result in very precise material removal.

The polishing pad surface characteristics, microscale, and macroscale material properties are known to impact the polishing performance. Harder, less complaint pads are known to create contact pressure peaks on the high portions of the deposited films. In a similar fashion, there are large-scale pressure gradients across the wafer surface corresponding to the overall flatness (or lack thereof) of the wafer surface.

The polish rate at locations on the wafer surface exposed to high contact pressure is higher than those areas experiencing low contact pressure. Thus harder, less compliant pads exhibit more anisotropic material removal than softer pads, which exhibit more uniform material removal across the wafer surface.

The purpose of CMP processing in IC fabrication is to remove steps in the wafer surface corresponding to a pattern of features underlying the top-most deposition layer. More anisotropic polishing behavior reduces the required film thickness (overburden) and polish time required to achieve desired results. As a result the industry has migrated toward hard pads for many of the CMP process applications. Some exemplary applications are inter-layer dielectric and shallow trench isolation.

Soft pads are typically used for final surface finish and in some polishing processes, such as tungsten via formation, where the planarization requirements are less demanding. For the traditional aluminum interconnect construction, process engineers had the choice between a hard pad or a soft pad and nothing in between.

IC (integrated circuit) performance requirements constantly drive fabrication process technology. As feature sizes have decreased and clock speeds have increased, IC construction has favored the higher conductivity of copper over aluminum for interconnects. This has brought about a growing market for copper CMP and a drift from tungsten and inter-level dielectric (ILD) polishing steps to copper polish steps in the fabrication process flow.

A typical copper film stack consists of a diffusion barrier layer, such as Tantalum, Tantalum Nitride, or Tantalum plus Tantalum Nitride bi-layers to prevent the rapid diffusion of copper into the underlying dielectric material. During the next process step a copper seed layer is deposited followed by electroplating the bulk copper material.

These metal films are highly susceptible to scratching and pitting. Hard pads have a tendency to induce more of these surface defects than soft pads, but soft pads do not planarize as well as hard pads and result in an uneven or non-planar surface.

SUMMARY OF THE INVENTION

The present invention provides for a method and apparatus for using at least one optimized pad to increase planarity and decrease surface defects during CMP processing. The polishing pad includes a polishing surface to remove material from and maintain a uniform polish rate with respect to a wafer surface. The polishing pad may have a hardness ranging between 62 to 98 shore A and a tensile modulus between 3500 to 35,000 psi (pounds per square inch).

In one embodiment, the polishing pad is a poromeric polyurethane coating on a polyurethane impregnated polyester felt substrate. In various embodiments, the polishing pad is comprised of one of a cast polyurethane material, polyurethane impregnated felt material or a coated polyurethane material on a substrate, such as a Mylar film.

The polishing surface of the polishing pad may further comprise an embossed or textured surface to distribute slurry as well as to allow for improved transport of polishing by-products when the polishing pad is used to polish a wafer surface. The polishing pad may further include pores with sizes ranging from 0.5 to 100 micro-meters.

In one embodiment, the optimized polishing pad is a composite polishing pad comprising at least two coupled polishing pads wherein one of the polishing pads has a polishing surface to make contact with a wafer surface to remove material from and maintain a uniform polish rate with respect to the wafer surface. Each polishing pad may be configured to have particular physical properties of hardness and tensile modulus when coupled, wherein the composite hardness may range between 62 to 98 shore A and the composite tensile modulus between 3,500 to 35,000 psi. The coupled polishing pads may be a poromeric polyurethane coating on a polyurethane impregnated polyester felt substrate or they may be comprised of one of a cast polyurethane material, polyurethane impregnated felt material or a coated polyurethane material on a substrate. In one embodiment, the polishing surface may also include an embossed or textured surface to distribute slurry as well as to allow for improved transport of polishing by-products when the composite polishing pad is used to polish the wafer surface.

In one embodiment a method for increasing planarity and decreasing surface defects during CMP processing comprises three stages. First, reducing a step height of deposition material corresponding to a pattern of features underlying a top-most deposition layer of a wafer by applying a hard pad to the wafer surface, wherein the hard pad has a hardness from 55 to 70 shore D and a tensile modulus from 45,000 to 90,000 psi. Second, removing bulk material corresponding to the remaining top-most deposition layer to expose an underlying surface of the wafer by applying a first optimized pad to the wafer surface, wherein the first optimized pad has a hardness from 78 to 98 shore A and a tensile modulus from 10,000 to 35,000 psi. Third, polishing the exposed underlying surface of wafer to reduce surface defects and maintain planarity by applying a second optimized pad, wherein the second optimized pad has a hardness from 62 to 78 shore A and a tensile modulus from 3,500 to 10,000 psi.

The first optimized and the second optimized pad may be comprised of a poromeric polyurethane coating on a polyurethane impregnated polyester felt substrate. In another embodiment, at least one of the hard pad, the first optimized pad, and the second optimized pad is comprised of one of a cast polyurethane material, polyurethane impregnated felt material or a coated polyurethane material on a substrate.

In another embodiment, a polishing surface of at least one of the hard pad, the first optimized pad, and the second optimized pad may further comprise an embossed or textured surface to distribute slurry and carry away removed material when the polishing pad is used to grind and/or polish the wafer surface.

In other embodiments, the first and second optimized pads are composite polishing pads further comprising at least two coupled polishing pads, wherein one of the polishing pads has a polishing surface to make contact with a wafer surface and each of the polishing pads configured to have particular physical properties of a hardness and a tensile modulus when coupled, wherein the hardness for the first optimized polishing pad is from 78 to 98 shore A and the tensile modulus is from 10,000 to 35,000 psi and the hardness for the second optimized polishing pad is from 62 to 78 shore A and the tensile modulus is from 3,500 to 10,000 psi, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which: [0020]
FIG. 1A is a cross section of an electroplated wafer illustrating a step height corresponding to a pattern of features underlying a top-most deposition layer; [0021]
FIG. 1B is a cross section of an electroplated wafer illustrating a reduction of step height during CMP processing; [0022]
FIG. 2A is a cross section of an electroplated wafer illustrating dishing defects caused by a soft polishing pad; [0023]
FIG. 2B is a cross section of an electroplated wafer illustrating surface defects caused by a hard polishing pad; [0024]
FIG. 2C is a cross section of an electroplated wafer illustrating high planarity and reduced defects the use of an optimized polishing pad, according to one embodiment of the present invention; [0025]
FIG. 3 illustrates an exemplary polishing pad optimized to increase planarity and reduce surface defects during CMP processing, according to one embodiment of the present invention; and [0026]
FIG. 4 illustrates an exemplary composite polishing pad optimized to increase planarity and reduce surface defects during CMP processing, according to one embodiment of the present invention. [0027]

DETAILED DESCRIPTION

The present invention recognizes the trade-off between soft and hard pads is gradual. The traditional choice of a hard or soft pad does not address all of the demands of newer fabrication techniques and CMP processes. Although exemplified here with copper interconnect fabrication, it will be appreciated that various embodiments of the present invention for an optimized polishing pad and methods for use as described herein can be equally applied to other types of fabrication and deposition removal techniques. [0028]
In copper interconnect fabrication, feature outlines and depths may be defined in an insulating layer by etching. Then, a barrier layer of metal is deposited on all exposed surfaces including the sides and bottom of the defined features and copper is deposited directly onto the barrier. [0029]
In one embodiment of the present invention, the copper polish process is divided into three distinct stages. Each stage may use a polishing pad optimized for particular demands of that stage. [0030]
A hard pad is used in the first stage for step height reduction. A first optimized pad of the present invention is used in the second or intermediate polish stage for bulk material (e.g., bulk copper) removal and a second optimized pad is used in the third or polishing stage to remove and polish remaining material (e.g., copper barrier) to reduce surface defects created from the second stage and expose underlying features, such as interconnects. [0031]
FIGS. 1A to B illustrate the first two stages of the three-stage process discussed above. FIG. 1A is a cross section of [0032] wafer 100 illustrating a step height corresponding to a pattern of features underlying a top-most deposition layer. Because of feature size variation and varying pattern densities the electroplating process induces topographic variation. For example, the topography of the trenches of the insulation layer 106 may be replicated whole or in part by the electroplated copper 102 deposited on top of barrier layer 104. This is further illustrated by step height 108 when compared to interconnect lines 110. It is this excess material that is eliminated in subsequent CMP processing according to various embodiments of the present invention.
During the first stage of copper CMP, the step height may be rapidly reduced with a hard pad having exemplary physical properties ranging from 55 to 70 shore D and tensile modulus from 45,000 to 90,000 psi. After some time, only very small step heights remain, if any, as shown by reduced [0033] step height 112 illustrated in FIG. 1B.
In stage two, the remaining [0034] copper layer 102 including the reduced step height 112 is removed until the barrier layer 104 is exposed above the insulation layer 106, as illustrated in FIGS. 2A-2C. In one embodiment of the present invention, a first optimized pad is used to remove the bulk of the remaining copper layer 102. Once the copper clears, the polishing is stopped to avoid dishing into the interconnect features and the wafer is ready for removal of barrier layer 104 and final polishing in stage three. The first and second optimized pads may have physical properties as illustrated below in Table 1. In another embodiment, the first optimized pad is used as the initial pad in place of using the hard pad described above.
The first optimized pad may be softer than the initial hard pad and may be harder than the second optimized pad used during the third stage. For example, a hard pad may have a hardness range of 55 to 70 shore D and a tensile modulus of 65,000 psi, while a second optimized pad has a hardness between 62 to 78 shore A and a tensile modulus between 3,500 and 10,000 psi. Falling between the two, the first optimized pad may have a hardness between 78 to 98 shore A and a tensile modulus between 10,000 and 35,000 psi. [0035]
Slurries are typically used in all three stages and are chemically selective to enhance bulk copper and barrier removal, and polish rate. For example, to control material removal, a slurry used in stage three may be selected to enhance the relative polish rate of the [0036] barrier metal 104. With the copper cleared from the barrier layer 104, there is still the potential to remove copper from the interconnect lines 110 while using soft pads and a potential to create surface defects (e.g., scratching and pitting) while using hard pads.
FIGS. 2A and 2B are cross sections of reduced [0037] wafer 200 illustrating defects caused by a soft polishing pad and a hard polishing pad, respectively. FIG. 2A specifically illustrates dishing defects caused by a soft pad. Although soft pads do not produce many surface defects, they do not planarize well enough to eliminate the remaining copper layer 102 before clearing copper material from interconnect lines 110 relative to the planar surface of the barrier layer 104, as illustrated by interconnect surfaces 202. This copper loss is an undesirable effect known in the industry as dishing.
FIG. 2B illustrates the use of a hard pad during stage three of CMP processing. Although hard pads planarize well resulting in reduced dishing, they have a tendency to induce more surface defects such as scratching and pitting than do soft pads, particularly in metal films (e.g., copper layer [0038] 102), as illustrated on surface 204 that includes the insulation layer 104 and the surface of interconnect lines 110.

FIG. 2C illustrates the result of using a second optimized polishing pad applied to

wafer

200 to limit surface and dishing defects, according to one embodiment of the present invention. The second optimized pad reduces surface defects relative to the traditional hard pad while simultaneously reducing topography and dishing defects relative to the traditional soft pad, as illustrated by polished surface 206 that includes the surface of the insulation layer 104 and the interconnect lines 110. As shown below in Table 1 and discussed above, the second optimized pad may have optimized physical properties that fall between traditional hard pads and soft pads. For example, the first optimized pad may have a hardness between 78 to 98 shore A and a tensile modulus between 10,000 and 35,000 psi. Because harder pads are more likely to produce surface defects, the second optimized pad is likely to be softer than the first optimized pad.

TABLE 1


Exemplary physical properties of a first and a second optimized pad

	1^stOptimized Pad/	2^ndOptimized Pad
Physical Property	(Intermediate)	(Polishing)

Thickness/mils	20-100	35-55
Hardness/Shore A	78-98	62-78
Density/g/cm³	0.40-0.75	0.35-0.65
Compressibility/%	0.1-7.0	2.0-6.5
Tensile Modulus/psi	10,000-35,000	3,500-10,000
Pore Size/μm	0.5-100	60-100

FIG. 3 illustrates an optimized [0040] polishing pad 300 for use during CMP processing, according to one embodiment of the present invention. Polishing pad 300 includes pore and composition structure 302 and material properties that may be optimized to increase mechanical stiffness and planarity while still maintaining other functions, such as slurry retention and transport.
In one embodiment, polishing [0041] pad 300 may be poromeric polyurethane coating on a polyurethane impregnated polyester felt substrate material. This basic material construction is well known in the industry as synthetic leather and is commonly used for soft-pad polishing applications but may have its pore structure and chemical composition optimized in accordance with the present invention. In other embodiments, the polishing pad 300 may be one of a cast polyurethane material, polyurethane impregnated felt material or a coated polyurethane material on a substrate. The substrate material including pore structure 302 may also be optimized. The measured result is a higher hardness and lower compressibility for high planarity and reduced dishing while maintaining enough softness to reduce surface defects during the third stage of the CMP process.
FIG. 4 illustrates a [0042] composite pad 400 optimized for use during CMP processing, according to one embodiment of the present invention. Composite pad 400 includes a substrate pad 402 coupled to a polishing pad 404. The properties of substrate pad 402 and the polishing pad 404 are chosen such that when coupled together, the composite pad 400 is optimized providing a hardness level and tensile modulus, among other physical properties, that fall between a traditional hard and soft pad as discussed above. The substrate pad 402 and polishing pad may be composed of any of the materials and configurations previously discussed with reference to FIG. 3.
Thus, methods and apparatus for using an optimized polishing pad for CMP applications have been described. Although discussed with reference to several illustrated embodiments, the present invention should only be measured in terms of the claims, which follow. [0043]

Claims

We claim:

1. A polishing pad, comprising a polishing surface to remove material from and maintain a uniform polish rate with respect to a wafer surface, the polishing pad having an associated hardness between 62 and 98 shore A and an associated tensile modulus between 3,500 and 35,000 psi.

2. The polishing pad of claim 1, wherein the polishing pad further comprises a poromeric polyurethane coating on a polyurethane impregnated polyester felt substrate.

3. The polishing pad of claim 1, wherein the polishing pad comprises one of a cast polyurethane material, polyurethane impregnated felt material or a coated polyurethane material on a substrate.

4. The polishing pad of claim 1, wherein the polishing surface further comprises an embossed surface configured to distribute slurry when the polishing pad is used to polish the wafer surface.

5. The polishing pad of claim 1, wherein the polishing pad has a pore size between 0.5 and 100 micro-meters.

6. A composite polishing pad, comprising at least two coupled polishing pads wherein one of the polishing pads has a polishing surface configured to make contact with a wafer surface to remove material from and maintain a uniform polish rate with respect to the wafer surface, and each of the two polishing pads has a hardness between 62 and 98 shore A and a tensile modulus between 3,500 and 35,000 psi.

7. The polishing pad of claim 6, wherein at least one of the coupled polishing pads further comprises a poromeric polyurethane coating on a polyurethane impregnated polyester felt substrate.

8. The polishing pad of claim 6, wherein at least one of the coupled polishing pads comprises one of a cast polyurethane material, polyurethane impregnated felt material or a coated polyurethane material on a substrate.

9. The polishing pad of claim 6, wherein the polishing surface further comprises an embossed surface configured to distribute slurry when the composite polishing pad is used to polish the wafer surface.

10. A method, comprising:

reducing a step height of deposition material corresponding to a pattern of features underlying a top-most deposition layer of a wafer by applying a hard pad to the top-most deposition layer, wherein the hard pad has a hardness between 55 and 70 shore D and a tensile modulus between 45,000 and 90,000 psi;

removing bulk material corresponding to remaining portions of the top-most deposition layer to expose an underlying surface of the wafer by applying a first optimized pad to the remaining portions of the top-most deposition layer, wherein the first optimized pad has a hardness between 78 and 98 shore A and a tensile modulus between 10,000 and 35,000 psi; and

polishing a resulting exposed underlying surface of the wafer to reduce surface defects and maintain planarity by applying a second optimized pad, wherein the second optimized pad has a hardness between 62 and 78 shore A and a tensile modulus between 3,500 and 10,000 psi.

11. The method of claim 10, wherein at least one of the hard pad, the first optimized pad, and the second optimized pad is comprised of a poromeric polyurethane coating on a polyurethane impregnated polyester felt substrate.

12. The method of claim 10, wherein at least one of the hard pad, the first optimized pad, and the second optimized pad is comprised of one of a cast polyurethane material, polyurethane impregnated felt material or a coated polyurethane material on a substrate film.

13. The method of claim 10, wherein a polishing surface of at least one of the hard pad, the first optimized pad, and the second optimized pad further comprises an embossed surface configured to distribute slurry when applied to the wafer surface.

14. The method of claim 10, wherein the first optimized pad is a composite polishing pad further comprising at least two coupled polishing pads, wherein one of the coupled polishing pads has a polishing surface configured to make contact with a wafer surface and each of the coupled polishing pads has a hardness and a tensile modulus, when coupled, of between 78 and 98 shore A and 10,000 and 35,000 psi, respectively.

15. The method of claim 10, wherein the second optimized pad is a composite polishing pad further comprising at least two coupled polishing pads, wherein one of the coupled polishing pads has a polishing surface configured to make contact with a wafer surface and each of the coupled polishing pads has a hardness and a tensile modulus, when coupled, of between 62 and 78 shore A and 3,500 and 10,000 psi, respectively.