US20040238896A1

US20040238896A1 - Semiconductor device

Info

Publication number: US20040238896A1
Application number: US10/449,491
Authority: US
Inventors: Marie Mochizuki
Original assignee: Oki Electric Industry Co Ltd
Current assignee: Oki Electric Industry Co Ltd
Priority date: 2003-06-02
Filing date: 2003-06-02
Publication date: 2004-12-02
Also published as: US20070173009A1; US7566604B2

Abstract

A semiconductor device, includes a semiconductor substrate; a first p-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode, and a gate insulation layer formed between the semiconductor substrate and the gate electrode; and a first n-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode, and a gate insulation layer formed between the semiconductor substrate and the gate electrode. The gate insulation layer of the first p-MOS transistor is of a silicon nitride oxide layer.

Description

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor device including a CMOS-transistor.

BACKGROUND OF THE INVENTION

As described in Publication of Japanese Patent Application No. 2001-2986151, a conventional C-MOSFET includes the same material of gate insulation layer is used both for a PMOSFET and an NMOSFET in order to simplify fabrications process. In recent years of deep-sub-micron generation, in order to reduce a short channel effect and to improve driving performance, an NMOSFET includes a gate electrode of N-type, while a PMOSFET includes a gate electrode of P-type, which is called “Dual-gate structure”. In fabrication, an N-type impurity, such as phosphorus, is ion-implanted into an N-type poly-silicon gate electrode. On the other hand, a P-type impurity, such as boron, is ion-implanted into a P-type poly-silicon gate electrode.

However, in such fabricated PMOSFET, boron atomics may get out of the gate electrode through the gate insulation layer to the silicon substrate, which may be called “cut-through phenomenon”. As a result, the threshold voltage (Vth) of the PMOSFET is changed in level, the reliability of the device is decreased as shown in “Kurasawa et al., IEDM Tech. Digest, p. 895, 1993”.

In order to prevent such Cut-thorough phenomenon of boron, nitrogen may be added into the gate insulation layer. However, nitrogen atomics may be diffused to the interface between the silicon substrate and the gate insulation layer, so that the composition of nitrogen is increased adjacent the interface. When the composition of nitrogen is increased, fixed charge is generated in response to the composition of nitrogen. Such fixed charge lowers the flat band voltage of the MOSFET, and therefore, the threshold voltage of the NMOSFET is lowered and standby current is increased.

According to “S. Takagi et al., IEEE Trans. On Electron Device, Vol. 41, p2357, 1994”, when the nitrogen composition is increased, electron mobility is reduced. Further, there are other problems in that a) the mobility of the MOSFET is decreased and mutual inductance is decreased, “H. Iwai et al., Symp. On VLSI Tech., p131, 1990; b) NBTI (Negative Baias Temperature Instability) is worsened; c) the lifetime of a transistor, used at an I/O portion with a higher power supply voltage, is shortened, N. Kimizuka et al., Symp. On VLSI Tech. Digest, P73, 1999.

In order to prevent the above described problems, according to an invention described in Publication of Japanese Patent Application No. H05-218405 and E. Hasegawa et al., IEDM Tech. Digest, p.327, 1995, the nitrogen composition in the gate insulation layer is controlled to not be higher than 1 atom %. However, when the gate insulation layer is thinner in accordance with minuteness of transistors, the amount of nitrogen in the gate insulation layer is reduced. It becomes difficult to prevent Cut-through phenomenon of boron in a PMOSFET.

According to Publication of Japanese Patent Application No. 2001-291865, nitrogen concentration in a gate insulation layer is controlled not to be higher than 1×10 ²¹cm⁻³, while the nitrogen concentration at the interface between the silicon substrate and the gate insulation layer is controlled not to be higher than 1×10¹⁹cm⁻³. However, the fabrications steps are increased; and mobility of an NMOSFET is still low.

OBJECTS OF THE INVENTION

Accordingly, it is an object of the present invention to provide a semiconductor device in which Cut-through phenomenon of boron is prevented in a PMOS transistor.

Another object of the present invention to provide a semiconductor device, in which lower of mobility of NMOS transistor is prevented.

Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, a semiconductor device includes a semiconductor substrate; a first p-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode, and a gate insulation layer formed between the semiconductor substrate and the gate electrode; and a first n-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode, and a gate insulation layer formed between the semiconductor substrate and the gate electrode. The gate insulation layer of the first p-MOS transistor is of a silicon nitride oxide layer.

Preferably, the semiconductor device further includes a second p-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode and a gate insulation layer formed between the semiconductor substrate and the gate electrode, the gate insulation layer having a thickness of greater than 4 nm; and a second n-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode and a gate insulation layer formed between the semiconductor substrate and the gate electrode, the gate insulation layer having a thickness of greater than 4 nm.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing a semiconductor device according to a first preferred embodiment of the present invention. [0013]
FIG. 2 is a graph showing a characteristic of the first preferred embodiment. [0014]
FIGS. 3A to [0015] 3G are cross-sectional views showing fabricating steps of the semiconductor device according to the first preferred embodiment.
FIGS. 4A to [0016] 4F are cross-sectional views showing fabricating steps of the semiconductor device according to the first preferred embodiment.
FIG. 5 is a cross-sectional view showing a semiconductor device according to a second preferred embodiment of the present invention. [0017]
FIG. 6 is a graph showing a characteristic of the second preferred embodiment. [0018]
FIGS. 7A to [0019] 7G are cross-sectional views showing fabricating steps of the semiconductor device according to the second preferred embodiment.

DETAILED DISCLOSURE OF THE INVENTION

In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These preferred embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other preferred embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and scope of the present inventions is defined only by the appended claims. [0020]
FIG. 1 is a cross-sectional view showing a semiconductor device according to a first preferred embodiment of the present invention. A C-[0021] MOSFET 1 includes an N-MOSFET 2 and a P-MOSFET 3 on the same silicon substrate 4. In the silicon substrate 4, an N-channel region 5 and a P-channel region 6 are formed and electrically separated from each other by a field oxide layer 7. Over the N-channel region 5, a gate insulator 8 of a silicon oxide layer for the N-MOSFET 2 is formed on the silicon substrate 4. On the other hand, over the P-channel region 6, a gate insulator 9 of a silicon nitride oxide layer for the P-MOSFET 3 is formed on the silicon substrate 4.
A [0022] gate electrode 10 of poly-silicon is formed on the gate insulator 8 for the N-MOSFET 2, while a gate electrode 11 of poly-silicon is formed on the gate insulator 9 for the P-MOSFET 3. An N-type of impurity, such as phosphorus, is added into the gate electrode 10 of the N-MOSFET 2, while a P-type of impurity, such as boron, is added into the gate electrode 11 of the N-MOSFET 3. Each of the gate electrodes 10 and 11 is provided with sidewalls of oxide silicon thereon.
In the N-[0023] MOSFET 2, an N-type LDD (Lightly Doped Drain) region 13 and source/drain regions 14 are formed below the gate electrode 10. In the P-MOSFET 3, a P-type LDD (Lightly Doped Drain) region 15 and source/drain regions 16 are formed below the gate electrode 11.
According to the first preferred embodiment, a cut-through phenomenon of born can be prevented in the P-[0024] MOSFET 3, so that variation of the threshold voltage is prevented. Further, the flat band voltage of the N-MOSFET 2 can be prevented from being lowered, so that the substrate concentration in the N-channel region 5 of the N-MOSFET 2 is decreased. Therefore, it can be prevented to lower driving performance (drain current) of the N-MOSFET 2.
FIG. 2 is a graph showing the relation between drain voltage and drain current of an N-MOSFET for different materials of gate insulator. When a gate insulator of silicon oxide layer is used, the driving performance is increased about 24% as compared with a gate insulator of silicon nitride oxide layer. [0025]
FIGS. 3A to [0026] 3G are cross-sectional views showing fabricating steps of the semiconductor device according to the first preferred embodiment, shown in FIG. 1. First, an N-channel region 5, a P-channel region 6 and a filed oxide layer 7 are formed on a silicon substrate 4. Next, in order to control a threshold voltage, an impurity, such as boron or BF2, is implanted into the N-channel region 5, while an impurity, such as arsenic or phosphorus, is implanted into the P-channel region 6. As shown in FIG. 3A, the surface of the silicon substrate 4 is oxidized to form a gate insulator 17 having a thickness of 2.5 nm.
Next, a poly-[0027] silicon 19 is deposited on the entire surface of the silicon substrate 4, then a gate impurity, for example, arsenic or phosphorus, of 2×10¹⁵cm⁻³is ion-implanted. After that, the poly-silicon layer 19 formed on the P-channel region 6 is removed by a photolithographic process so as that the remaining poly-silicon layer 19 has a 60-degree taper portion at an edge thereof. Next, a silicon nitride layer 20 is deposited on the poly-silicon layer 19, then the silicon nitride layer formed on the P-channel region 6 is removed. At this time, the poly-silicon layer 19 on the N-channel region 5 is completely covered with the silicon nitride layer 20. The silicon oxide layer 18 on the P-channel region 6 is removed using the silicon nitride layer 20 as a mask, as shown in FIG. 3B.
Using the poly-[0028] silicon layer 19 and the silicon nitride layer 20 as a mask, the P-channel region 6 is treated in an oxidizing atmosphere at 750° C. to 850° C., and then treated in a NO (Nitriding-Oxidizing) atmosphere at 900° C. for forty minutes to form a silicon nitride oxide layer 21 having a thickness of 2.5 nm on the P-channel region 6, as shown in FIG. 3C. A silicon oxide layer can be used as a mask instead of the silicon nitride layer 20. The gate insulators of the N-MOSFET and P-MOSFET may have the different thickness from each other.
Next, a poly-[0029] silicon layer 22 is formed over the entire surface of the substrate, as shown in FIG. 3D. After that, the poly-silicon layer 22, formed on the N-channel region 5, is removed using a photolithographic technique, as shown in FIG. 3E. Subsequently, the silicon nitride layer 20 is removed, and gate electrodes are shaped using a patterning technique, as shown in FIG. 3F.
Next, sidewall layers [0030] 23 are formed on side surfaces of the gate electrodes. After that, boron or BF2 is ion-implanted into the N-channel region 5 to form an N-type LDD and source-drain regions 24 in the N-channel region 5. On the other hand, arsenic or phosphorus is ion-implanted into the P-channel region 6 to form an P-type LDD and source-drain regions 25 in the P-channel region 6. A C-MOSFET is completed, as shown in FIG. 3G.
According to the above-described fabrication steps, a silicon nitride oxide layer is formed as a gate insulator only the P-MOSFET region, however, a silicon oxide layer, which is a gate insulator of the N-MOSFET region, is not put in an NO atmosphere. As a result, the gate insulator of the N-MOSFET is of a silicon oxide nitride layer, therefore, such a gate insulator prevents a cut-through phenomenon of boron. Further, the gate insulator of the N-MOSFET is of a silicon oxide layer, so that the mobility of the transistor is not decreased and driving performance is expected to improve. [0031]
FIGS. 4A to [0032] 4F are cross-sectional views showing another type of fabricating steps of the semiconductor device according to the first preferred embodiment, shown in FIG. 1. First, an N-channel region 5, a P-channel region 6 and a filed oxide layer 7 are formed on a silicon substrate 4. Next, in order to control a threshold voltage, an impurity, such as boron or BF2, is implanted into the N-channel region 5, while an impurity, such as arsenic or phosphorus, is implanted into the P-channel region 6. After that, the entire surface of the silicon substrate 4 is oxidized and the substrate is treated in an NO atmosphere at 900° C. to form a gate insulator 17, as shown in FIG. 4A.
Next, the [0033] silicon oxide layer 17 on the N-channel region 6 is removed by a photolithographic technique, as shown in FIG. 4B. After that, the substrate is again oxidized to form a silicon oxide layer 19 as a gate insulator on the N-channel region 5, as shown in FIG. 4C. In this process, the gate insulator on the P-MOSFET region 6 is also re-oxidized to increase the thickness thereof. In order to form the gate insulator on the N-MOSFET region 5 having the same thickness as the gate insulator on the P-MOSFET 6, the thickness of the silicon nitride oxide layer 19 in the P-MOSFET would be reduced.
Next, a poly-[0034] silicon 21 is deposited on the entire surface of the silicon substrate 4, then a gate impurity, for example, arsenic or phosphorus, of 2×10¹⁵cm⁻³is ion-implanted into the poly-silicon layer on the N-channel region, as shown in FIG. 4D. After that, gate electrodes are shaped using a patterning technique, as shown in FIG. 4E.
Next, sidewall layers [0035] 23 are formed on side surfaces of the gate electrodes. Subsequently, boron or BF2 is ion-implanted into the N-channel region 5 to form an N-type LDD and source-drain regions 24 in the N-channel region 5. On the other hand, arsenic or phosphorus is ion-implanted into the P-channel region 6 to form an P-type LDD and source-drain regions 25 in the P-channel region 6. A C-MOSFET is completed, as shown in FIG. 4F.
According to the above-described fabrication steps, the silicon [0036] nitride oxide layer 17 is formed on the entire surface of the silicon substrate 4, and then the silicon nitride oxide layer in the N-MOSFET 5 is removed. The substrate is again oxidized to form a silicon oxide layer in the N-MOSFET region 5. As a result, the gate insulator of the N-MOSFET 5 prevents a cut-through phenomenon of boron. Further, the gate insulator of the N-MOSFET is of a silicon oxide layer, so that the mobility of the transistor is not decreased and driving performance is expected to improve.
FIG. 5 is a cross-sectional view showing a semiconductor device according to a second preferred embodiment of the present invention. In this embodiment, a C-[0037] MOSFET 25 includes a first P-MOSFET 29 having a gate insulator of silicon oxide layer having a thickness of more than 4 nm, and a second P-MOSFET 31 having a gate insulator of silicon oxide nitride layer having a thickness not more than 4 nm. The C-MOSFET 25 is composed of a thick-layer MOSFET 26, including gate insulators having a thickness not less than 4 nm, and a thin-layer MOSFET 27, including gate insulators having a thickness not more than 4 nm. The MOSFET 26 includes a first N-MOSFET 28 and the first P-MOSFET 29. The MOSFET 27 includes a second N-MOSFET 30 and the second P-MOSFET 31.
The MOSFETs [0038] 28, 29, 30 and 31 are electrically separated from each other by a field oxide layer 32. On a silicon substrate 33, a first N-channel region 34 and a second N-channel region 35 are formed. The concentrations of those N- channel regions 34 and 35 may be the same and may be different from each other. In the first N-channel region 34, a gate insulator 38 of a silicon nitride oxide layer is formed for the first N-MOSFET 28. In the second N-channel region 35, a gate insulator 39 of a silicon nitride oxide layer is formed for the second N-MOSFET 30. In the first P-channel region 36, a gate insulator 40 of a silicon oxide layer is formed for the first P-MOSFET 29. In the second P-channel region 37, a gate insulator 41 of a silicon nitride oxide layer is formed for the second P-MOSFET 31.
On the [0039] gate insulator 38 of the first N-MOSFET 28, a gate electrode 42 of poly-silicon, into which an N-type impurity, such as phosphorus, is implanted. On the gate insulator 39 of the second N-MOSFET 30, a gate electrode 42 of poly-silicon, into which an N-type impurity, such as phosphorus, is implanted. On the gate insulator 40 of the first P-MOSFET 29, a gate electrode 43 of poly-silicon, into which a P-type impurity, such as boron, is implanted. On the gate insulator 41 of the second P-MOSFET 31, a gate electrode 43 of poly-silicon, into which a P-type impurity, such as boron, is implanted.
Each gate electrode is provided with a [0040] sidewall 44 of oxide silicon thereon. In the first and second N-MOSFETs 28 and 30, an N-type LDD (Lightly Doped Drain) region and source/ drain regions 45 and 46 are formed below the gate electrodes. The concentration of the LDD and the source-drain regions may be the same or different from each other. In the first and second P-MOSFETs 29 and 31, an P-type LDD (Lightly Doped Drain) region and source/ drain regions 47 and 48 are formed below the gate electrodes. The concentration of the LDD and the source-drain regions may be the same or different from each other.
According to the second preferred embodiment, a cut-through phenomenon of born can be prevented in the P-MOSFET [0041] 31, having a gate insulator of not thicker than 4 nm. Further, a NBTI can be prevented from being increased in the P-MOSFET 29, having a gate insulator of not thinner than 4 nm. Especially, the present invention is useful to improve reliability of a P-MOSFET used at an I/O portion with a higher power supply voltage, and to extend a lifetime of the device.
FIG. 6 is a graph showing a characteristic of the second preferred embodiment, which is the stress voltage dependence on the device lifetime. In the graph, lifetimes are compared between a P-MOSFET using a gate insulator of silicon nitride oxide layer and a P-MOSFET using a gate insulator of silicon oxide layer. It can be understood from the graph, the lifetime is longer when a P-MOSFET uses a gate insulator of silicon oxide layer as compared to a P-MOSFET using a gate insulator of silicon nitride oxide layer. [0042]
In the second preferred embodiment, the first P-MOSFET [0043] 29 may employ a silicon oxide layer as a gate insulator of not thinner than 4 nm, and each of the first N-MOSFET 29 and the second N-MOSFET 30 may employ a silicon oxide layer as a gate insulator.
According to the second preferred embodiment, a cut-through phenomenon of born can be prevented in the P-MOSFET [0044] 31, having a gate insulator of not thicker than 4 nm. Further, flat band voltages of the N-MOSFETs 29 and 30 can be prevented from decreasing, and substrate concentration of the N- channel regions 34 and 35 can be reduced. As a result, driving performance (amount of drain current) may be maintained high. Still further, a NBTI can be prevented from being increased in the P-MOSFET 29, having a gate insulator of not thinner than 4 nm. Therefore, it is expected to extend a lifetime of the device.
FIGS. 7A to [0045] 7G are cross-sectional views showing fabricating steps of the semiconductor device according to the second preferred embodiment, shown in FIG. 5. In fabrication, first, first and second N- channel regions 34 and 35, first and second P- channel regions 36 and 37 and a filed oxide layer 32 are formed on a silicon substrate 33. Next, in order to control a threshold voltage, an impurity, such as boron or BF2, is implanted into the first and second N- channel regions 34 and 35, while an impurity, such as arsenic or phosphorus, is implanted into the first and second P- channel regions 36 and 37. Subsequently, the entire surface of the silicon substrate 33 is oxidized to form an oxide layer having a thickness of 60 nm thereon. After that, the silicon oxide layer on the second N-channel region 36 and the second P-channel region 37 is removed, and the substrate 33 is oxidized again to form silicon oxide layers 49 and 50 having a thickness of 7 nm on the first N-channel region 34 and the first P-channel region 36, respectively, and to form silicon oxide layers 51 and 52 having a thickness of 2.5 nm on the second N-channel region 35 and the second P-channel region 37, respectively, as shown in FIG. 7A.
Next, a poly-[0046] silicon 53 is deposited on the first and second N- channel regions 34 and 35 and the first P-channel region 36, then the silicon oxide layer 52 on the P-channel region 37 is removed using a nitride layer 54 as a mask, as shown in FIG. 7B.
After that, boron or BF2 is added into the poly-[0047] silicon layer 53 on the first P-channel region 36, while arsenic or phosphorus is added into the first and second N- channel regions 34 and 35. In the same manner shown in FIG. 3s, a silicon nitride oxide layer 555 is formed on the second P-channel region 37 to have a thickness of 2.5 nm, as shown in FIG. 7C.
Next, a poly-[0048] silicon 56 is deposited over the entire surface of the substrate, as shown in FIG. 7D. After that, the poly-silicon 56 formed on the first and second N- channel regions 34 and 35 and the first P-channel region 36 is removed by a photolithographic technique, as shown in FIG. 7E. Subsequently, the silicon nitride layer 54 is removed, and gate electrodes are shaped by a patterning process, as shown in FIG. 7F.
After that, sidewall layers [0049] 61 are formed on side surfaces of the gate electrodes. After that, boron or BF2 is ion-implanted into the first and second N- channel regions 34 and 35 to form an N-type LDD and source- drain regions 62 and 63. On the other hand, arsenic or phosphorus is ion-implanted into the first and second P- channel regions 36 and 37 to form an P-type LDD and source- drain regions 64 and 65. A C-MOSFET is completed, as shown in FIG. 7G.
According to the above-described fabrication steps, a silicon nitride oxide layer having a thickness of not more than 4 nm is formed as a gate insulator only on the second P-[0050] MOSFET region 37, however, the silicon oxide layers (gate insulators) of the first and second N- MOSFET 34 and 35 and the first P-MOSFET 36 are not nitrided. The gate insulator having a thickness of not more than 4 nm of the second P-MOSFET 37 is of a silicon oxide nitride layer, therefore, such a gate insulator prevents a cut-through phenomenon of boron. Further, the gate insulators of the first N-MOSFET 34 and the second N-MOSFET are of silicon oxide layers, so that the mobility of the transistor is not decreased and driving performance is expected to improve. Still further, the first P-MOSFET having a thicker gate insulator of thicker than 4 nm is made of a silicon oxide layer, so that a NBTI can be prevented from being increased.

Claims

What is claimed is:

1. A semiconductor device, comprising:

a semiconductor substrate;

a first p-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode, and a gate insulation layer formed between the semiconductor substrate and the gate electrode; and

a first n-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode, and a gate insulation layer formed between the semiconductor substrate and the gate electrode, wherein

the gate insulation layer of the first p-MOS transistor is of a silicon nitride oxide layer.

2. A semiconductor device according to claim 1, wherein

the gate electrode of the first p-MOS transistor is of a p-type semiconductor, and

the gate electrode of the first n-MOS transistor is of a n-type semiconductor.

3. A semiconductor device according to claim 1, wherein

the gate insulation layer of the first n-MOS transistor is of a silicon oxide layer.

4. A semiconductor device according to claim 1, wherein

the gate insulation layer of the first p-MOS transistor has a thickness of less than 4 nm, and

the gate insulation layer of the first n-MOS transistor has a thickness of less than 4 nm.

5. A semiconductor device according to claim 1, further comprising:

a second p-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode and a gate insulation layer formed between the semiconductor substrate and the gate electrode, the gate insulation layer having a thickness of greater than 4 nm; and

a second n-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode and a gate insulation layer formed between the semiconductor substrate and the gate electrode, the gate insulation layer having a thickness of greater than 4 nm.

6. A semiconductor device according to claim 5, wherein

the gate insulation layer of the first n-MOS transistor is of a silicon nitride oxide layer;

the gate insulation layer of the second n-MOS transistor is of a silicon nitride oxide layer; and

the gate insulation layer of the second p-MOS transistor is of a silicon oxide layer.

7. A semiconductor device according to claim 5, wherein

the gate insulation layer of the first n-MOS transistor is of a silicon oxide layer;

the gate insulation layer of the second n-MOS transistor is of a silicon oxide layer; and

8. A semiconductor device according to claim 5, wherein

9. A semiconductor device, comprising:

a semiconductor substrate;

a first p-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode, and a gate insulation layer formed between the semiconductor substrate and the gate electrode, the gate insulation layer having a thickness of less than 4 nm;

a first n-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode, and a gate insulation layer formed between the semiconductor substrate and the gate electrode, the gate insulation layer having a thickness of less than 4 nm;

a second n-MOS transistor formed on the semiconductor substrate, which comprises a gate electrode and a gate insulation layer formed between the semiconductor substrate and the gate electrode, the gate insulation layer having a thickness of greater than 4 nm, wherein

the gate insulation layer of the first p-MOS transistor is of a silicon nitride oxide layer, and the gate insulation layers of the second p-MOS, first n-MOS and second n-MOS transistors are of a silicon oxide layers.