US20040250006A1 - Method of accessing data of a computer system - Google Patents

Method of accessing data of a computer system Download PDF

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US20040250006A1
US20040250006A1 US10/707,241 US70724103A US2004250006A1 US 20040250006 A1 US20040250006 A1 US 20040250006A1 US 70724103 A US70724103 A US 70724103A US 2004250006 A1 US2004250006 A1 US 2004250006A1
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memory
address
electrically connected
signal processing
digital signal
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US10/707,241
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Pei-Ying Lin
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Ali Corp
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Ali Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Definitions

  • the present invention relates to a computer system, and more particularly, to a method of accessing data of the computer system with a digital signal processing chip having a static random access memory (SRAM) and a cache memory.
  • SRAM static random access memory
  • DSP digital signal processing
  • FIG. 1 is a function block diagram of a computer system 10 according to the prior art.
  • the computer system 10 comprises a DSP chip 12 and a dynamic random access memory (DRAM) 14 electrically connected to the DSP chip 12 via a plurality of address lines 16 and data lines 18 .
  • the DSP chip 12 is capable of accessing and processing data of the DRAM 14 through the address lines 16 and data lines 18 .
  • time for the DSP chip 12 to access data of the DRAM 14 through the address lines 16 and data lines 18 is approximately six times longer than time needed to process these accessed data (clock cycle).
  • time for the DSP chip 12 to access one set of data is around 48-24 nanoseconds, which is far longer than 4-8 nanoseconds, time for the DSP chip 12 to process these data.
  • how fast the DSP chip 12 accesses data of the DRAM 14 dominates the efficiency of the DSP chip 12 .
  • FIG. 2 is a function block diagram of another computer system 20 according to the prior art.
  • the computer system 20 comprises a DSP chip 22 and a DRAM 24 electrically connected to the DSP chip 22 via a plurality of address lines 26 and data lines 28 .
  • the DSP chip 22 comprises a static random access memory (SRAM) 30 . Because time for the DSP chip 22 to access one set of data of the SRAM 30 is around only 3 nanoseconds, far shorter than 48-24 nanoseconds, data frequently used by the DSP chip 22 can be stored in the SRAM 30 in advance to improve the efficiency of the computer system 30 .
  • SRAM static random access memory
  • the DSP chip 22 with the SRAM 30 embedded still has some shortcomings. For example, if a working space for the DSP chip 22 to store the frequent-used data is 12K words large, the SRAM 30 embedded into the DSP chip 22 also has to have a corresponding storing space of 12K words reserved.
  • a program code the DSP chip 22 manages has a size of 4K words for example, smaller than 12K words, so the SRAM 30 has two thirds of its storing space idled. This idle storing space of the SRAM 30 not only increase cost to produce the DSP chip 22 , since the SRAM 30 occupies major area of the DSP chip 22 , the idle storing space also increases the bulk of the DSP chip 22 .
  • the SRAM 30 having a constant storing space limits the DSP chip 22 to execute an application program demanding a memory space less than 12K words.
  • DMA direct memory access
  • the method is proposed for accessing data of a computer system.
  • the computer system has a first memory, a second memory, an address decoder, a digital signal processing unit electrically connected to the address decoder, a demultiplexer having an input end electrically connected to the digital signal processing unit, a first output end electrically connected to the second memory, and a control end electrically connected to the address decoder, and a multiplexer having an output end electrically connected to the digital signal processing unit, a first input end electrically connected to the second memory, and a control end electrically connected to the address decoder.
  • the method has following steps: (a) providing the digital signal processing unit with a cache memory electrically connected to the first memory, the cache memory having an input end electrically connected to a second output end of the demultiplexer, an output end electrically connected to a second input end of the multiplexer, and a tag stored with an address data; and (b) when the digital signal processing unit generates an address signal, (c) controlling the demultiplexer with the address decoder according to the address signal to transfer the address signal either to the cache memory or to the second memory and to enable the digital signal processing unit to receive contents via the multiplexer either from the cache memory or from the second memory, (d) comparing the address signal with the address data if the address signal is transmitted to the cache memory, and either transmitting contents of the cache memory corresponding to the address signal via the multiplexer to the digital signal processing unit if the address signal matches the address data or updating contents of the cache memory corresponding to the address signal with contents of the first memory corresponding to the address signal, (e) updating the address data with the address signal and
  • the address decoder, the second memory, the digital signal processing unit, the demultiplexer, the multiplexer, and the cache memory are all integrated into a single digital signal processing chip.
  • the first memory is a DRAM and the second memory is an SRAM.
  • a digital signal processing chip has not only an SRAM but also a cache memory embedded and is capable of storing frequently-used data into the cache memory to improve the efficiency of a computer which the digital signal processing chip is installed in.
  • FIG. 1 is a function block diagram of a computer system according to the prior art.
  • FIG. 2 is a function block diagram of another computer system according to the prior art.
  • FIG. 3 is a function block diagram of a computer system of a preferred embodiment according to the present invention.
  • FIG. 4 is a flow chart of a method of accessing data of the computer shown in FIG. 3 according to the present invention.
  • FIG. 3 is a function block diagram of a computer system 40 of the preferred embodiment according of the present invention.
  • the computer system 40 comprises a DSP chip 42 and a DRAM 44 electrically connected to the DSP chip 42 via a plurality of address lines 46 and data lines 48 .
  • the DSP chip 42 comprises an SRAM 50 , an address decoder 52 , a digital signal process unit 54 electrically connected to the address decoder 52 , a delmultiplexer 56 , a multiplexer 58 , and a cache memory 60 having a tag (not shown) for storing address information.
  • the demultiplexer 56 comprises an input end I electrically connected to the digital signal processing unit 54 , a first output end O 1 electrically connected to the SRAM 50 , and a control end D c electrically connected to the address decoder 52 .
  • the multiplexer 58 comprises an output end O electrically connected to the digital signal processing unit 54 , a first input end I 1 electrically connected to the SRAM 50 , and a control end D c electrically connected to the address decoder 52 .
  • the cache memory 60 comprises an input end electrically connected to a second output end O 2 of the delmultiplexer 56 , and an output end electrically connected to a second input end I 2 of the multiplexer 58 .
  • the DSP chip 40 can promote the efficiency of the computer system 40 by selectively storing frequently-used data and program codes to the cache memory 60 .
  • the SRAM 50 has a memory space of 4K
  • the cache memory 60 has a memory space of 4K as well.
  • the SRAM 50 as well as the cache memory 60 can have memory space of a variety of sizes in accordance with practical demands.
  • Address lines 46 and data lines 48 installed in the DSP chip 42 for example address lines connecting the digital signal processing unit 54 and the demultiplexer 56 and data lines connecting the multiplexer 58 and the cache memory 60 or the SRAM 50 , have a Harvard structure. Because time for address calculation is usually no less than that for data calculation in the DSP chip 42 , the DSP chip 42 of the Harvard structure can further comprise an address generator (not shown) to accelerate the address calculation.
  • a method 100 for the DSP chip 42 of the computer system 40 to process data or to execute program codes is described as follows: Please refer to FIG. 4, which is a flow chart of the method 100 of accessing data of the computer system 40 according to the present invention.
  • the method 100 comprises following steps:
  • Step 101 Start;
  • Step 102 Generate a control signal to control the demultiplexer 56 and the multiplexer 58 according to an address signal with the address decoder 52 when the digital signal processing unit 54 outputs the address signal;
  • Step 104 Determine whether or not the address signal corresponds to the SRAM 50 , if yes, go to step 120 , else, go to step 140 ;
  • Step 120 Control the demultiplexer 56 to transfer the address signal via the demultiplexer 56 to the SRAM 50 and control the multiplexer 58 to enable the digital signal processing unit 54 to receive data transferred from the SRAM 50 via the multiplexer 58 ;
  • Step 122 Transfer data of the SRAM 50 corresponding to the address signal via the multiplexer 58 to the digital signal processing unit 54 , go to step 198 ;
  • Step 140 Control the demultiplexer 56 to transfer the address signal via the demultiplexer 56 to the cache memory 60 and control the multiplexer 58 to enable the digital signal processing unit 54 to receive data transferred from the cache memory 60 via the multiplexer 58 ;
  • Step 142 Compare the address signal with the address in-formation stored in the tag of the cache memory 60 ;
  • Step 144 If the address signal hits the address information, then go to step 160 , else (misses) go to step 180 ;
  • Step 160 Transfer data of the cache memory 60 corresponding to the address signal via the multiplexer 58 to the digital signal processing unit 54 , go to step 198 ;
  • Step 180 Update data of the cache memory 60 corresponding to the address signal with data of the DRAM 44 corresponding to the address signal;
  • Step 182 Update the address information of the tag of the cache memory 60 with the address signal:
  • Step 184 Transfer the updated data of the cache memory 60 corresponding to the address signal via the multiplexer 58 to the digital signal processing unit 54 ;
  • Step 198 Ends.
  • the address signal the DSP chip 42 generates can be used to address to a plurality of memory spaces of the DRAM 44 depending on a setting between the DSP chip 42 and the cache memory.
  • the address signal is a logical address corresponding to a physical address of the DRAM 44 , the physical address equal to a sum of the logical address and a configurable base address stored in the cache memory 60 .
  • the present invention can provide a computer system 40 , in which a DSP chip 42 comprises not only an SRAM but also a cache memory. Therefore, as mentioned above, the computer system 40 has advantages of small bulk, low cost, high efficiency, and remarkable expandability. In addition, with slight adjustment of the base address, the DSP chip 42 can further access data stored in another memory space other than the DRAM 44 with the cache memory 60 .

Abstract

A method for accessing data in a computer system. The computer system has a first memory, a second memory, an address decoder, a digital signal processing cell, a demultiplexer, a multiplexer, and a cache memory. The cache memory includes a tag for storing an address. The method includes controlling the demultiplexer with the address decoder according to an address signal generated by the digital signal processing cell to transmit the address signal either to the cache memory or to the second memory via the demultiplexer, and controlling the multiplexer with the address decoder according to the address signal to control the digital signal processing cell to receive data transmitted either from the cache memory or from the second memory via the multiplexer.

Description

    BACKGROUND OF INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a computer system, and more particularly, to a method of accessing data of the computer system with a digital signal processing chip having a static random access memory (SRAM) and a cache memory. [0002]
  • 2. Description of the Prior Art [0003]
  • The dramatic development of communications technologies demands high-efficiency digital signal processing (DSP) chips. A DSP chip is capable of executing a plurality of operations in a single instruction cycle and can substitute for a central processing unit (CPU) to execute complex arithmetic operations, such as convolution and fast Fourier transform (FFT), so that the CPU can concentrate on system control. [0004]
  • Please refer to FIG. 1, which is a function block diagram of a [0005] computer system 10 according to the prior art. The computer system 10 comprises a DSP chip 12 and a dynamic random access memory (DRAM) 14 electrically connected to the DSP chip 12 via a plurality of address lines 16 and data lines 18. The DSP chip 12 is capable of accessing and processing data of the DRAM 14 through the address lines 16 and data lines 18. In general, time for the DSP chip 12 to access data of the DRAM 14 through the address lines 16 and data lines 18 is approximately six times longer than time needed to process these accessed data (clock cycle). For example, if the DSP chip 12 has a clock cycle ranging between 120 MHz to 250 MHz, time for the DSP chip 12 to access one set of data is around 48-24 nanoseconds, which is far longer than 4-8 nanoseconds, time for the DSP chip 12 to process these data. In conclusion, how fast the DSP chip 12 accesses data of the DRAM 14 dominates the efficiency of the DSP chip 12.
  • A concept of embedding an embedded memory is introduced to improve the efficiency of the [0006] DSP chip 12. Please refer to FIG. 2, which is a function block diagram of another computer system 20 according to the prior art. The computer system 20 comprises a DSP chip 22 and a DRAM 24 electrically connected to the DSP chip 22 via a plurality of address lines 26 and data lines 28. The DSP chip 22 comprises a static random access memory (SRAM) 30. Because time for the DSP chip 22 to access one set of data of the SRAM 30 is around only 3 nanoseconds, far shorter than 48-24 nanoseconds, data frequently used by the DSP chip 22 can be stored in the SRAM 30 in advance to improve the efficiency of the computer system 30.
  • However, the [0007] DSP chip 22 with the SRAM 30 embedded still has some shortcomings. For example, if a working space for the DSP chip 22 to store the frequent-used data is 12K words large, the SRAM 30 embedded into the DSP chip 22 also has to have a corresponding storing space of 12K words reserved. In general, a program code the DSP chip 22 manages has a size of 4K words for example, smaller than 12K words, so the SRAM 30 has two thirds of its storing space idled. This idle storing space of the SRAM 30 not only increase cost to produce the DSP chip 22, since the SRAM 30 occupies major area of the DSP chip 22, the idle storing space also increases the bulk of the DSP chip 22.
  • In addition, the [0008] SRAM 30 having a constant storing space (for example 12K words) limits the DSP chip 22 to execute an application program demanding a memory space less than 12K words.
  • Lastly, because a direct memory access (DMA) controller has to be introduced to manage data communications between the [0009] SRAM 30 of the DSP chip 22 and the DRAM 24, a control program code stored in the DSP chip 22 to control the DMA controller has to be changed accordingly if data allocation of the SRAM 30 has changed.
    • SUMMARY OF INVENTION
  • It is therefore a primary objective of the claimed invention to provide a method of accessing data of a computer with a DSP chip having an embedded cache memory and an SRAM. [0010]
  • According to the claimed invention, the method is proposed for accessing data of a computer system. The computer system has a first memory, a second memory, an address decoder, a digital signal processing unit electrically connected to the address decoder, a demultiplexer having an input end electrically connected to the digital signal processing unit, a first output end electrically connected to the second memory, and a control end electrically connected to the address decoder, and a multiplexer having an output end electrically connected to the digital signal processing unit, a first input end electrically connected to the second memory, and a control end electrically connected to the address decoder. The method has following steps: (a) providing the digital signal processing unit with a cache memory electrically connected to the first memory, the cache memory having an input end electrically connected to a second output end of the demultiplexer, an output end electrically connected to a second input end of the multiplexer, and a tag stored with an address data; and (b) when the digital signal processing unit generates an address signal, (c) controlling the demultiplexer with the address decoder according to the address signal to transfer the address signal either to the cache memory or to the second memory and to enable the digital signal processing unit to receive contents via the multiplexer either from the cache memory or from the second memory, (d) comparing the address signal with the address data if the address signal is transmitted to the cache memory, and either transmitting contents of the cache memory corresponding to the address signal via the multiplexer to the digital signal processing unit if the address signal matches the address data or updating contents of the cache memory corresponding to the address signal with contents of the first memory corresponding to the address signal, (e) updating the address data with the address signal and transmitting the updated contents of the cache memory via the multiplexer to the digital signal processing unit, and (f) transmitting contents of the second memory corresponding to the address signal via the multiplexer to the digital signal processing unit if the address signal is transmitted to the second memory. [0011]
  • The address decoder, the second memory, the digital signal processing unit, the demultiplexer, the multiplexer, and the cache memory are all integrated into a single digital signal processing chip. [0012]
  • In the preferred embodiment, the first memory is a DRAM and the second memory is an SRAM. [0013]
  • It is an advantage of the claimed invention that a digital signal processing chip has not only an SRAM but also a cache memory embedded and is capable of storing frequently-used data into the cache memory to improve the efficiency of a computer which the digital signal processing chip is installed in. [0014]
  • These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.[0015]
    • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 is a function block diagram of a computer system according to the prior art. [0016]
  • FIG. 2 is a function block diagram of another computer system according to the prior art. [0017]
  • FIG. 3 is a function block diagram of a computer system of a preferred embodiment according to the present invention. [0018]
  • FIG. 4 is a flow chart of a method of accessing data of the computer shown in FIG. 3 according to the present invention.[0019]
    • DETAILED DESCRIPTION
  • Please refer to FIG. 3, which is a function block diagram of a [0020] computer system 40 of the preferred embodiment according of the present invention. The computer system 40 comprises a DSP chip 42 and a DRAM 44 electrically connected to the DSP chip 42 via a plurality of address lines 46 and data lines 48. The DSP chip 42 comprises an SRAM 50, an address decoder 52, a digital signal process unit 54 electrically connected to the address decoder 52, a delmultiplexer 56, a multiplexer 58, and a cache memory 60 having a tag (not shown) for storing address information. The demultiplexer 56 comprises an input end I electrically connected to the digital signal processing unit 54, a first output end O1 electrically connected to the SRAM 50, and a control end Dc electrically connected to the address decoder 52. The multiplexer 58 comprises an output end O electrically connected to the digital signal processing unit 54, a first input end I1 electrically connected to the SRAM 50, and a control end Dc electrically connected to the address decoder 52. The cache memory 60 comprises an input end electrically connected to a second output end O2 of the delmultiplexer 56, and an output end electrically connected to a second input end I2 of the multiplexer 58.
  • Since time for the digital [0021] signal processing unit 54 to access one set of data of the cache memory 60 is only 4 nanoseconds, far shorter than 42 nanoseconds, time for the digital signal processing unit 54 to access one set of data of the DRAM 44, the DSP chip 40 can promote the efficiency of the computer system 40 by selectively storing frequently-used data and program codes to the cache memory 60.
  • In the preferred embodiment of the present invention, the SRAM [0022] 50 has a memory space of 4K, and the cache memory 60 has a memory space of 4K as well. Of course, the SRAM 50 as well as the cache memory 60 can have memory space of a variety of sizes in accordance with practical demands.
  • [0023] Address lines 46 and data lines 48 installed in the DSP chip 42, for example address lines connecting the digital signal processing unit 54 and the demultiplexer 56 and data lines connecting the multiplexer 58 and the cache memory 60 or the SRAM 50, have a Harvard structure. Because time for address calculation is usually no less than that for data calculation in the DSP chip 42, the DSP chip 42 of the Harvard structure can further comprise an address generator (not shown) to accelerate the address calculation.
  • A [0024] method 100 for the DSP chip 42 of the computer system 40 to process data or to execute program codes is described as follows: Please refer to FIG. 4, which is a flow chart of the method 100 of accessing data of the computer system 40 according to the present invention. The method 100 comprises following steps:
  • Step [0025] 101: Start;
  • Step [0026] 102: Generate a control signal to control the demultiplexer 56 and the multiplexer 58 according to an address signal with the address decoder 52 when the digital signal processing unit 54 outputs the address signal;
  • Step [0027] 104: Determine whether or not the address signal corresponds to the SRAM 50, if yes, go to step 120, else, go to step 140;
  • Step [0028] 120: Control the demultiplexer 56 to transfer the address signal via the demultiplexer 56 to the SRAM 50 and control the multiplexer 58 to enable the digital signal processing unit 54 to receive data transferred from the SRAM 50 via the multiplexer 58;
  • Step [0029] 122: Transfer data of the SRAM 50 corresponding to the address signal via the multiplexer 58 to the digital signal processing unit 54, go to step 198;
  • Step [0030] 140: Control the demultiplexer 56 to transfer the address signal via the demultiplexer 56 to the cache memory 60 and control the multiplexer 58 to enable the digital signal processing unit 54 to receive data transferred from the cache memory 60 via the multiplexer 58;
  • Step [0031] 142: Compare the address signal with the address in-formation stored in the tag of the cache memory 60;
  • Step [0032] 144: If the address signal hits the address information, then go to step 160, else (misses) go to step 180;
  • Step [0033] 160: Transfer data of the cache memory 60 corresponding to the address signal via the multiplexer 58 to the digital signal processing unit 54, go to step 198;
  • Step [0034] 180: Update data of the cache memory 60 corresponding to the address signal with data of the DRAM 44 corresponding to the address signal;
  • Step [0035] 182: Update the address information of the tag of the cache memory 60 with the address signal:
  • Step [0036] 184: Transfer the updated data of the cache memory 60 corresponding to the address signal via the multiplexer 58 to the digital signal processing unit 54; and
  • Step [0037] 198: Ends.
  • In [0038] step 180, the address signal the DSP chip 42 generates can be used to address to a plurality of memory spaces of the DRAM 44 depending on a setting between the DSP chip 42 and the cache memory. The address signal is a logical address corresponding to a physical address of the DRAM 44, the physical address equal to a sum of the logical address and a configurable base address stored in the cache memory 60. These are well known in the prior art, and further description is hereby omitted.
  • In contrast to the prior art, the present invention can provide a [0039] computer system 40, in which a DSP chip 42 comprises not only an SRAM but also a cache memory. Therefore, as mentioned above, the computer system 40 has advantages of small bulk, low cost, high efficiency, and remarkable expandability. In addition, with slight adjustment of the base address, the DSP chip 42 can further access data stored in another memory space other than the DRAM 44 with the cache memory 60.
  • Following the detailed description of the present invention above, those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. [0040]

Claims (8)

What is claimed is:
1. A method for accessing data of a computer system, the computer system comprising:
a first memory;
a second memory;
an address decoder;
a digital signal processing unit electrically connected to the address decoder;
a demultiplexer having an input end electrically connected to the digital signal processing unit, a first output end electrically connected to the second memory, and a control end electrically connected to the address decoder; and
a multiplexer having an output end electrically connected to the digital signal processing unit, a first input end electrically connected to the second memory, and a control end electrically connected to the address decoder; and
the method comprising following steps:
(a) providing the digital signal processing unit with a cache memory electrically connected to the first memory, the cache memory having an input end electrically connected to a second output end of the demultiplexer, an output end electrically connected to a second input end of the multiplexer, and a tag stored with an address data; and (b) when the digital signal processing unit generates an address signal, (c) controlling the demultiplexer with the address decoder according to the address signal to transfer the address signal either to the cache memory or to the second memory and to enable the digital signal processing unit to receive contents via the multiplexer either from the cache memory or from the second memory, (d) comparing the address signal with the address data if the address signal is transmitted to the cache memory, and either transmitting contents of the cache memory corresponding to the address signal via the multiplexer to the digital signal processing unit if the address signal matches the address data or updating contents of the cache memory corresponding to the address signal with contents of the first memory corresponding to the address signal, (e) updating the address data with the address signal and transmitting the updated contents of the cache memory via the multiplexer to the digital signal processing unit, and (f) transmitting contents of the second memory corresponding to the address signal via the multiplexer to the digital signal processing unit if the address signal is transmitted to the second memory.
2. The method of claim 1 wherein the address decoder, the second memory, the digital signal processing unit, the demultiplexer, the multiplexer, and the cache memory are all integrated into a digital signal processing chip.
3. The method of claim 1 wherein the first memory is a dynamic random access memory (DRAM).
4. The method of claim 1 wherein the second memory is a static random access memory (SRAM).
5. A computer system comprising:
a first memory;
a second memory;
an address decoder;
a digital signal processing unit electrically connected to the address decoder;
a demultiplexer having an input end electrically connected to the digital signal processing unit, a first output end electrically connected to the second memory, and a control end electrically connected to the address decoder;
a multiplexer having an output end electrically connected to the digital signal processing unit, a first input end electrically connected to the second memory, and a control end electrically connected to the address decoder; and
a cache memory having an input end electrically connected to a second output end of the demultiplexer, an output end electrically connected to a second input end of the multiplexer, and a tag for storing an address.
6. The computer system of claim 5 wherein the address decoder, the second memory, the digital signal processing unit, the demultiplexer, the multiplexer, and the cache memory are all integrated into a digital signal processing chip.
7. The computer system of claim 5 wherein the first memory is a DRAM.
8. The computer system of claim 5 wherein the second memory is an SRAM.
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