US20050029595A1 - Method and apparatus for preventing microcircuit dynamic thermo-mechanical damage during an esd event - Google Patents

Method and apparatus for preventing microcircuit dynamic thermo-mechanical damage during an esd event Download PDF

Info

Publication number
US20050029595A1
US20050029595A1 US10/635,390 US63539003A US2005029595A1 US 20050029595 A1 US20050029595 A1 US 20050029595A1 US 63539003 A US63539003 A US 63539003A US 2005029595 A1 US2005029595 A1 US 2005029595A1
Authority
US
United States
Prior art keywords
esd
thermo
dynamic
semiconductor substrate
active device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US10/635,390
Other versions
US6853036B1 (en
Inventor
Vladimir Rodov
Wlodzimierz Tworzydlo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ESD Pulse Inc
Original Assignee
ESD Pulse Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ESD Pulse Inc filed Critical ESD Pulse Inc
Priority to US10/635,390 priority Critical patent/US6853036B1/en
Assigned to ESD PULSE, INC. reassignment ESD PULSE, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TWORZYDLO, WLODZIMIERZ WOYTEK, RODOV, VLADIMIR
Application granted granted Critical
Publication of US6853036B1 publication Critical patent/US6853036B1/en
Publication of US20050029595A1 publication Critical patent/US20050029595A1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention pertains generally to microelectronic devices, and specifically, to circuit and network configurations designed to reduce the harmful effects of electrostatic discharge in such devices. More particularly, the present invention relates circuit and network configurations and methods resistant to very fast electrostatic discharge events.
  • Electrostatic Discharge is a significant problem in microelectronic devices. ESD damage results from high voltage and/or current applied to the terminals of microelectronic devices by human or machine contact during device manufacturing, assembly transportation/storage or PC board mounting. The voltage and current spikes are typically of a very short duration and can cause breakdown of such devices, thus rendering them inoperable. This is a problem of increasing importance as smaller and smaller device dimensions render them more susceptible to damage.
  • ESD protection circuits To protect microelectronic devices from the harmful effects of ESD, dedicated ESD protection circuits are commonly employed. Typically, such circuits are designed to divert ESD pulses from the device without affecting its performance under normal operating conditions. The protection circuit itself should be able to survive the ESD pulse. Nonetheless, in practice ESD impulses often destroy both the protection circuit and the protected device, even with ESD protection devices designed using state-of-the-art methods.
  • the present invention provides an integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising a semiconductor substrate; an electrical contact pad; an ESD switch coupled to the pad and having an active device region formed in the semiconductor substrate.
  • ESD Electrostatic Discharge
  • the present invention further includes a dynamic shock absorbing region formed in the semiconductor substrate adjacent to the active device region, the dynamic shock absorbing region is made from a material with thermo-mechanical properties substantially more resistant to shock from dynamic effects of ESD than the active device region.
  • the thermo-mechanical properties include a dynamic loss factor higher than approximately 0.01, a melting temperature higher than approximately 800 °K, and a moderately low stiffness as defined by an elastic modulus approximately in the range of 10 GPa to 100 GPa (Giga Pascals), and a tensile strength higher than approximately 100 MPa.
  • the ESD switch of the present invention has one or more sides, wherein the dynamic shock absorbing region formed in the semiconductor substrate is located in trenches adjacent to the one or more sides of the ESD switch.
  • the dynamic shock absorbing region is configured above, or below the active device region of the ESD switch.
  • the dynamic shock absorbing region is made from a material with thermo-mechanical properties substantially more resistant to dynamic shock than the active device region and may be selected from the group consisting of hard polymers, amorphous carbon, carbon-carbon composite or carbon-polymer composite.
  • the dynamic shock absorbing region is surrounded by a dielectric region.
  • the present invention is an integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising a semiconductor substrate; an ESD switch having an active device region formed in the semiconductor substrate; and a plurality of dynamic shock absorbing regions formed around the active device region.
  • the dynamic shock absorbing region is made from a material with thermo-mechanical properties substantially more resistant to shock from dynamic effects of ESD than the active device region.
  • the thermo-mechanical properties include a dynamic loss factor higher than approximately 0.01, a melting temperature higher than approximately 800 °K, an elastic modulus approximately in the range of 10 GPa and 100 GPa (Giga Pascals), and a moderately high tensile strength higher than approximately 100 MPa.
  • a preferred embodiment includes a dielectric layer formed in between the ESD switch and the dynamic shock absorbing region, and a passivation layer formed above the dynamic shock absorbing region.
  • the ESD switch may also include a gate region wherein the gate region is formed from a thermo-mechanical energy sink material, the thermo-mechanical energy sink material substantially more resistant to thermo-mechanical expansion than the semiconductor substrate.
  • the thermo-mechanical energy sink material has physical properties including a thermal expansion coefficient lower than approximately 5 ⁇ 10 ⁇ 6 °K ⁇ 1 , a melting temperature higher than approximately 2000 °K, a tensile strength higher than approximately 300 MPa (Mega Pascals), and a fracture toughness approximately higher than about 1.0 MPa m 1/2 .
  • a preferred embodiment of the present invention further includes a second dynamic shock absorbing region formed in the semiconductor substrate in thermal contact with the active device region, the second dynamic shock absorbing region made from a material with thermo-mechanical properties substantially more resistant to shock from the dynamic effects of ESD than said active device region.
  • the ESD switch further comprises a third dynamic shock absorbing region located adjacent to one or more sides of the ESD switch.
  • the present invention is an integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising a semiconductor substrate; an ESD circuit comprising a switch having an active device region formed in the semiconductor substrate and one or more passive circuit components; and means for absorbing dynamic shock from at least one of the switch and one or more passive components in response to an ESD event.
  • the means for absorbing shock may comprise a region above the active device region made from a material with thermo-mechanical properties resistant to shock from dynamic effects of ESD.
  • a second dynamic shock absorbing region is formed below the active device region, the second dynamic shock absorbing region is made from a material with thermo-mechanical properties resistant to shock from the dynamic effects of ESD.
  • a third dynamic shock absorbing region may be formed adjacent to the one or more sides of the ESD switch.
  • the present invention is further a method of fabricating an ESD device on a semiconductor substrate, the method comprising fabricating a switch from connectors and active device regions formed in the semiconductor substrate; providing a dynamic shock absorbing region formed in the semiconductor substrate adjacent to said active device regions.
  • the dynamic shock absorbing region is made from a material with thermo-mechanical properties substantially resistant to shock from dynamic effects of ESD.
  • FIG. 1 is an illustration of a prior art integrated circuit incorporating an electrostatic discharge (ESD) protection device that has undergone thermo-mechanical damage due to a fast ESD event;
  • ESD electrostatic discharge
  • FIG. 2 is a circuit block diagram of a microelectronic circuit employing improved ESD protection in accordance with the present invention
  • FIG. 3 is an illustration showing a vertical portion of a cross section of the microelectronic circuit of FIG. 2 ;
  • FIG. 4 is a schematic drawing of another microelectronic circuit layout employing improved ESD protection in accordance with the present invention.
  • FIG. 5 is an illustration showing a vertical cross section of an ESD protection circuit in accordance with a first embodiment of the present invention where a dynamic shock absorber layer is inserted into the sides of the silicon device;
  • FIG. 6 is an illustration showing a vertical cross section of an ESD protection circuit in accordance with another embodiment of the present invention wherein a dynamic shock absorber is inserted above the device;
  • FIG. 7 is an illustration showing a vertical cross section of an ESD protection circuit of the present invention wherein a dynamic shock absorber is included in the substrate below the device;
  • FIG. 8 is an illustration showing a vertical cross section of an ESD protection circuit in accordance with another embodiment of the present invention wherein previous examples are combined to essentially surround the entire ESD protection switch;
  • FIG. 9 is an illustration showing a vertical cross section of an ESD protection circuit in accordance with another embodiment of the present invention wherein the integrated circuit employs dynamic shock absorber material and also material resistant to thermo-mechanical stress.
  • the Human Body Model representative of a charged person touching the electronic device, assumes that a human is charged to around several kilovolts (KV) and is represented by a capacitance of about several hundred Pico Farads that can discharge through a resistor of a few kilo ohms. For example, such an arrangement can generate a 4 KV pulse with a maximum current of 2.6 A and about 150 ns event time.
  • KV Human Body Model
  • MM Machine Model
  • CDM Charged Device Model
  • the Machine Model representative of a charged tool touching the device as a typical example, assumes that a 400 V pulse is discharged with a maximum current of 7 A and an event duration of 10 to 50 ns.
  • the event time is extremely short (about 0.25 ns) with voltages reaching about 1 KV and currents on the order of 10 A.
  • thermo-mechanical effects 1. and 2. may surpass the strength of the integrated circuit (IC) chip materials and/or interfaces between different layers, leading to plastic deformation, cracking and/or delamination within the chip.
  • the cracks provide an additional barrier to current flow and/or heat dissipation in consecutive ESD events and thus compound the destructive effects.
  • the ESD protection device of FIG. 1 is a typical example of a MOSFET switch used in an ESD protection circuit.
  • the MOSFET switch is formed in substrate 110 , part of an IC substrate typically of single crystal silicon.
  • the gate contact 120 and drain contact 118 (or source 122 ) are coupled to the IC pad and ideally the switch will turn on and shunt ESD current harmlessly to ground in an ESD event on the pad.
  • the components of the MOSFET device also include, source 112 , channel 114 , drain 116 , gate 124 , and dielectric material 126 .
  • the connectors are typically aluminum or aluminum-silicon-copper alloy and the dielectric is typically silicon dioxide (SiO 2 ).
  • a thin contact diffusion barrier 128 e.g. titanium nitride TiN
  • the types of thermo-mechanical damage illustrated include delamination 138 and separation of connectors 118 , 120 , 122 and other elements of the device. Also leading to thermo-mechanical failure is crack propagation 136 from high-stress areas, especially from connectors 118 , 120 , 122 , and adjacent etched or deposited areas formed during fabrication.
  • the present invention provides circuit designs and methods that minimize the thermo-mechanical effects of ESD discharge, particularly therm-mechanical damage due to fast ESD discharge on the components of the ESD device.
  • FIG. 2 a block diagram of a microelectronic circuit 200 having improved ESD protection in accordance with the present invention is illustrated.
  • the circuit 200 may comprise any type of microelectronic circuit requiring ESD protection and will typically comprise an IC having core circuitry 220 having many thousands or millions of devices on an IC substrate.
  • Input/output ESD protection circuitry 214 , 216 , 226 , 228 protects the core circuitry 220 from ESD pulses applied to pads 210 , 212 .
  • the protection circuitry shields the I/O buffers 218 , 230 from the stress by clamping the voltage at I/O pads 210 , 212 below the breakdown level.
  • the protection circuitry effectively shunts the ESD current to the ground 222 without going through internal circuitry 220 .
  • a variety of devices such as diodes, bipolar transistors, SCRs or MOSFETs can be used in circuitry 214 , 216 , 226 and 228 , usually in conjunction with resistors, as efficient input protection switches.
  • One specific switch configuration is shown in FIG. 4 .
  • the present invention is not limited to a specific switch, however, since the main purpose of any switch is to release the ESD energy into surrounding materials where it can be dissipated.
  • the thermo-mechanical damage modes shown above and respective remedies discussed below apply to any such switch.
  • the modifications can be applied to other components of the ESD protection circuit, such as capacitor 412 and resistor 414 .
  • FIG. 3 illustrates generally the physical arrangement of an ESD protection circuit 214 in relation to the IC substrate.
  • the figure shows a vertical cross section of a microelectronic circuit 200 implemented as an IC chip 300 .
  • the ESD protection circuit 214 is typically located below the input pad 310 and is spaced apart from the main circuitry 220 (usually at a distance of at least ten or more microns).
  • IC substrate 322 may be single crystal silicon or other known IC substrate.
  • the active devices in core region 220 will include doped regions in the substrate 322 as known in the art. For example, if they contain MOSFET devices, they may generally have the form shown in FIG. 1 .
  • Connectors 316 may be conventional materials such as aluminum or copper.
  • Connectors 314 i.e. the portion of the electrical connection within a distance from the pad 210 subject to thermo-mechanical effects, may be a hybrid structure including at least a portion of a thermo-mechanical damage resistive material, as discussed below in relation in FIGS.
  • FIG. 4 shows a specific example of an input protection circuit that uses a resistor 414 and a capacitor 412 along with an nMOS transistor 416 .
  • the nMOS transistor 416 acts as a switch and is off during normal operation.
  • the nMOS transistor 416 enters into the ESD protection mode, clamping the voltage on the pad 410 below the breakdown levels.
  • the additional resistor 414 and capacitor 412 serve to adjust the breakdown voltage that activates ESD protection.
  • the ESD protection circuit 214 may thus comprise transistor 416 , resistor 414 and capacitor 412 in an embodiment.
  • the present invention includes specific focus to improve ESD resistance to very fast ESD events that cause dynamic shock effects (e.g. oscillations, elastic waves, dynamic crack propagation). Such dynamic shock effects caused by fast discharge are applicable to the CD model and some frequencies within HBM and MM, especially for larger devices.
  • the present invention may also combine these approaches with an approach directed to improve ESD resistance to slower ESD events, which relates to thermo-mechanical failure under all conditions (i.e. HBM, MM, CDM). This approach is disclosed in detail in the U.S. Patent Application entitled: Method And Apparatus for Preventing Microcircuit Thermo-Mechanical Damage During An ESD Event, filed contemporaneously herewith, and by the same inventors as the present invention, which is incorporated by reference herein, in its entirety.
  • the present invention provides in the vicinity of the heated area a “shock absorber” or a number of shock absorbers that will absorb the energy of dynamic effects.
  • the shock absorbing material of the present invention can be in either of the following three classes:
  • Examples of desirable damping materials for shock absorbing material are: polymers and amorphous carbon.
  • shock absorbers examples include diamond, hard carbon (also known as diamond-like carbon, amorphous carbon), boron nitride, and silicon carbide.
  • FIG. 5 A preferred embodiment showing a manner in which shock absorbers 528 , 530 are employed in an ESD device 500 is shown in FIG. 5 .
  • the specific structure corresponds to a MOSFET switch such as switch 416 shown in FIG. 4 .
  • the modifications can equally be applied to any other switch type, such as bipolar transistor, SCR or other known ESD switch type.
  • the active device region of an ESD switch comprises a source 512 and a drain 516 region connected by a channel 514 region, formed in substrate 510 .
  • the switch also has a gate 524 . Connecting the active device regions are source 522 , gate 520 and drain 518 connectors.
  • shock absorbers 528 , 530 are inserted into deep grooves in the silicon on both sides of the device. This particular embodiment can be accomplished by anisotropic etching in the substrate 510 , followed by isotropic deposition of a shock absorbing material (e.g. carbon) followed by an anisotropic planarizing etch. If needed, shock-absorbing material can be surrounded by dielectric material (not shown) such as Silicon Oxide or Silicon Nitride.
  • FIG. 6 Another embodiment is represented in FIG. 6 .
  • the embodiment of FIG. 6 also shows a MOSFET switch comprising source 612 , channel 614 , drain 616 , formed in substrate 610 , associated source and drain contacts 618 , 622 , gate 624 , gate contact 620 and dielectric 626 .
  • a shock absorber layer 630 is inserted below a passivation layer 632 and above the remaining portion of the ESD protection device 600 .
  • a thin dielectric layer 628 such as Si Oxide or Si Nitride, is introduced between the shock absorber 630 and the remainder of the device 600 .
  • the entire passivation layer 632 is made of shock absorber material.
  • the embodiment of FIG. 6 also includes a gate region 624 made of material resistant to thermo-mechanical expansion due to local heating from discharges with slower event times such as those modeled by the HBM and MM.
  • FIG. 7 Yet another embodiment is represented in FIG. 7 .
  • the embodiment of FIG. 7 illustrate a MOSFET switch comprising source 712 , channel 714 , and drain 716 formed in substrate 710 and associated contacts 722 , 718 , a gate 724 , gate contact 720 and dielectric 726 .
  • a shock absorber 728 is placed within the semiconductor substrate 710 below the active area of the ESD switch comprising the source, channel and drain regions.
  • the active area of the ESD switch also may be defined as the area within the switch where the electric field is substantially non-zero.
  • the shock absorber 728 may be located below each individual switch or stretch under a number of switches on an ESD protection pad.
  • the shock-absorbing layer 728 can be surrounded by a dielectric such as Si Oxide or Si Nitride if needed.
  • FIG. 8 Another embodiment is illustrated in FIG. 8 .
  • a MOSFET switch comprising source 812 , channel 814 , drain 816 , formed in substrate 810 , drain contact 818 , source contact 822 , gate 824 , gate contact 820 and dielectric 826 .
  • a dielectric layer 832 and passivation layer are also shown as in the prior embodiment.
  • the shock absorbers 828 , 830 , 834 , and 836 as shown in previous examples are combined to essentially surround the entire ESD protection switch and/or its components that may include individual MOSFETS, diodes, and resistors, etc. If needed, a connection is left between the active area and bulk semiconductor 810 to allow release of current to the ground.
  • FIG. 9 Another embodiment is shown of a MOSFET switch surrounded by shock absorber 928 , 930 , 934 and 936 .
  • the FIG. 9 embodiment combines these dynamic shock absorber materials with material resistant to thermo-mechanical expansion applicable to the HBM and MM models.
  • the mechanism of failure is through thermal expansion of materials and associated intense mechanical stress and deformation.
  • the basic idea for preventing ESD device failure due to slower discharge events is to replace vulnerable materials (aluminum, copper, silicon) with thermo-mechanical energy sink material that can withstand thermo-mechanical expansion and stress.
  • the materials resistant to thermo-mechanical expansion have the following physical properties, in comparison to materials presently used.
  • the connectors 918 , 920 , and 922 should be fabricated from material with the following properties.
  • connectors 918 , 920 , 922 may comprise an alloy containing significant portions of such material used in conjunction with aluminum or copper.
  • the thickness of the material (e.g. TiN, graphite or C) used in connectors 918 , 920 , 922 should be approximately one half of the length of the active device region.
  • the thickness of the layer can vary from 50 A to 5,000 A; however, this range may easily change henceforth, because microelectronic devices continually get smaller with advancement.
  • the active area 914 of the semiconductor substrate 910 should be fabricated from material resistant to thermo-mechanical expansion with the following physical properties.
  • Some examples of preferred semiconductor, resistor and capacitor materials include: diamond, hard carbon (i.e. diamond-like carbon, amorphous carbon), boron nitride, and less preferably, silicon carbide. All materials may be doped as needed for electrical properties.
  • a first fabrication process is a method for inserting a material with desirable thermo-mechanical properties, such as hard carbon or diamond-like carbon, amorphous carbon, boron nitride, silicon carbide, or polymers, under the ESD protection switch.
  • the method first employs depositing an oxide layer onto a semiconductor substrate.
  • the next step is to deposit the material, e.g. hard carbon, onto the oxide layer at a pre-determined thickness.
  • a photo resist layer is deposited on the substrate that forms the area where the ESD switch is located (i.e. adjacent to the region of the IC where the pad(s) will be formed).
  • the remaining portions where the hard carbon and oxide layer were deposited are next etched away to leave the area where the ESD switch is to be located.
  • Another oxide layer is then deposited on the hard carbon on the area of interest followed by another photo resist layer.
  • the excess portions are again etched leaving the hard carbon encapsulated in oxide with a strip of silicon neighboring the enveloped hard carbon.
  • amorphous silicon is then deposited into the envelope followed by an epitaxial silicon layer wherein the active region of the ESD switch is formed.
  • the excess amorphous silicon and unneeded oxide are etched from the rest of the wafer.
  • a second method of the invention provides for surrounding an ESD protection switch area with a trench and filling the trench with a material resistant to dynamic shock (e.g. hard carbon).
  • the first step is to apply a photo resist layer around and area to be etched away to form a trench.
  • an oxide layer and the hard carbon material are isotropically deposited into the trench.
  • the excess hard carbon is then anisotropically reactive ion etched until only the trench is filled with hard carbon.
  • another oxide layer is deposited and etched leaving the hard carbon encapsulated in oxide.
  • ESD devices should be achieved so that mechanically strong bonds are formed between the different materials contained within the device.
  • Specific deposition techniques for example, are employed to assure strong bonding between consecutive deposited layers.
  • a first technique is to use a uniform deposition temperature for all materials, appropriately near 400° C., for example.
  • the invention minimizes fabrication stresses between the material layers caused by different thermal expansion coefficients of materials.
  • the present invention aims to optimize the range of thermal stresses so that they are not too high, either at room temperature or during an ESD event.
  • the basic principle is that inter-layer thermal stresses increase with the departure from stress-free deposition temperature.
  • Prolonged annealing is another technique to improve the strength and ductility of materials in the manufacturing of ESD devices.
  • a preferred annealing temperature for exemplary materials of the present invention is approximately 600° C.
  • An additional manufacturing and design technique is to eliminate sharp corners when fabricating and etching the components of the ESD device. By using appropriate deposition and etching techniques, sharp corners between adjoining materials should be minimized in favor of rounded corners. Generally, the geometry of corners and notches should be as smooth as practically achievable to minimize the mechanical stress at which crack propagation occurs.
  • An alternative technique contemplated by the present invention is to apply a passivation layer that is stiff and strong with an optimal thickness. A strong passivation layer will contain the expansive thermal stresses and maintain them within the compressive, rather than tensile, range. This helps prevent delamination, material separation and crack propagation. Further, the passivation layer should be ductile, rather than brittle, to prevent the layer from cracking and provide some damping of elastic waves caused by fast ESD events.

Abstract

A method and apparatus for preventing thermo-mechanical damage to an electrostatic discharge (ESD) protection device is disclosed. The method and apparatus of the invention focus on preventing ESD protection circuit failure due to elastic waves within the materials of an integrated circuit. The elastic waves are specifically caused by very fast ESD discharge events. Disclosed are ESD protection circuits incorporating materials with superior thermo-mechanical properties, in particular, material damping, melting temperature, material stiffness, elastic modulus, tensile strength and fracture toughness. Also disclosed is the use of thermo-mechanical energy absorber material that is designed to protect ESD devices from failure due to slower ESD events.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention pertains generally to microelectronic devices, and specifically, to circuit and network configurations designed to reduce the harmful effects of electrostatic discharge in such devices. More particularly, the present invention relates circuit and network configurations and methods resistant to very fast electrostatic discharge events.
  • 2. Description of the Related Art
  • Electrostatic Discharge (ESD) is a significant problem in microelectronic devices. ESD damage results from high voltage and/or current applied to the terminals of microelectronic devices by human or machine contact during device manufacturing, assembly transportation/storage or PC board mounting. The voltage and current spikes are typically of a very short duration and can cause breakdown of such devices, thus rendering them inoperable. This is a problem of increasing importance as smaller and smaller device dimensions render them more susceptible to damage.
  • To protect microelectronic devices from the harmful effects of ESD, dedicated ESD protection circuits are commonly employed. Typically, such circuits are designed to divert ESD pulses from the device without affecting its performance under normal operating conditions. The protection circuit itself should be able to survive the ESD pulse. Nonetheless, in practice ESD impulses often destroy both the protection circuit and the protected device, even with ESD protection devices designed using state-of-the-art methods.
  • One of the underlying reasons for failure of prior art ESD protection devices is that their design is based on an incomplete understanding of the mechanisms by which an ESD pulse destroys the device. It is commonly understood in the prior art that the damage due to ESD pulses happens via:
      • 1. Electrical breakdown of electronic structure due to high current that changes operating characteristics of the device; followed by
      • 2. Thermal breakdown, wherein the high temperature induced by the pulse causes local current instabilities (e.g. current filamentation) and consequently melting of the semiconductor, contacts and/or other elements of the device.
  • For ESD protection circuits, it is the thermal breakdown that is typically used as the design criterion. However, experimental evidence indicates that there must exist other phenomena that contribute to failure of ESD protection circuits even before the melting point has been reached. This is confirmed by poor reliability and unpredictable performance of ESD protection circuits designed according to the prior art.
  • Accordingly, in view of the problems and deficiencies of the prior art, a need exists to improve the reliability and performance of ESD protection devices, and improve the survivability of microelectronic devices subjected to ESD events. In addition, it is important that such an improved approach be relatively inexpensive to implement.
    • SUMMARY OF THE INVENTION
  • The present invention provides an integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising a semiconductor substrate; an electrical contact pad; an ESD switch coupled to the pad and having an active device region formed in the semiconductor substrate. The present invention further includes a dynamic shock absorbing region formed in the semiconductor substrate adjacent to the active device region, the dynamic shock absorbing region is made from a material with thermo-mechanical properties substantially more resistant to shock from dynamic effects of ESD than the active device region. The thermo-mechanical properties include a dynamic loss factor higher than approximately 0.01, a melting temperature higher than approximately 800 °K, and a moderately low stiffness as defined by an elastic modulus approximately in the range of 10 GPa to 100 GPa (Giga Pascals), and a tensile strength higher than approximately 100 MPa.
  • In a preferred embodiment, the ESD switch of the present invention has one or more sides, wherein the dynamic shock absorbing region formed in the semiconductor substrate is located in trenches adjacent to the one or more sides of the ESD switch. Alternatively, the dynamic shock absorbing region is configured above, or below the active device region of the ESD switch. The dynamic shock absorbing region is made from a material with thermo-mechanical properties substantially more resistant to dynamic shock than the active device region and may be selected from the group consisting of hard polymers, amorphous carbon, carbon-carbon composite or carbon-polymer composite. Alternatively, the dynamic shock absorbing region is surrounded by a dielectric region.
  • In another aspect, the present invention is an integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising a semiconductor substrate; an ESD switch having an active device region formed in the semiconductor substrate; and a plurality of dynamic shock absorbing regions formed around the active device region. The dynamic shock absorbing region is made from a material with thermo-mechanical properties substantially more resistant to shock from dynamic effects of ESD than the active device region. The thermo-mechanical properties include a dynamic loss factor higher than approximately 0.01, a melting temperature higher than approximately 800 °K, an elastic modulus approximately in the range of 10 GPa and 100 GPa (Giga Pascals), and a moderately high tensile strength higher than approximately 100 MPa. A preferred embodiment includes a dielectric layer formed in between the ESD switch and the dynamic shock absorbing region, and a passivation layer formed above the dynamic shock absorbing region.
  • The ESD switch may also include a gate region wherein the gate region is formed from a thermo-mechanical energy sink material, the thermo-mechanical energy sink material substantially more resistant to thermo-mechanical expansion than the semiconductor substrate. The thermo-mechanical energy sink material has physical properties including a thermal expansion coefficient lower than approximately 5×10−6 °K−1, a melting temperature higher than approximately 2000 °K, a tensile strength higher than approximately 300 MPa (Mega Pascals), and a fracture toughness approximately higher than about 1.0 MPa m1/2. A preferred embodiment of the present invention further includes a second dynamic shock absorbing region formed in the semiconductor substrate in thermal contact with the active device region, the second dynamic shock absorbing region made from a material with thermo-mechanical properties substantially more resistant to shock from the dynamic effects of ESD than said active device region. Alternatively, the ESD switch further comprises a third dynamic shock absorbing region located adjacent to one or more sides of the ESD switch.
  • In another aspect, the present invention is an integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising a semiconductor substrate; an ESD circuit comprising a switch having an active device region formed in the semiconductor substrate and one or more passive circuit components; and means for absorbing dynamic shock from at least one of the switch and one or more passive components in response to an ESD event. The means for absorbing shock may comprise a region above the active device region made from a material with thermo-mechanical properties resistant to shock from dynamic effects of ESD. Alternatively, a second dynamic shock absorbing region is formed below the active device region, the second dynamic shock absorbing region is made from a material with thermo-mechanical properties resistant to shock from the dynamic effects of ESD. Similarly, a third dynamic shock absorbing region may be formed adjacent to the one or more sides of the ESD switch.
  • The present invention is further a method of fabricating an ESD device on a semiconductor substrate, the method comprising fabricating a switch from connectors and active device regions formed in the semiconductor substrate; providing a dynamic shock absorbing region formed in the semiconductor substrate adjacent to said active device regions. As in previous embodiments, the dynamic shock absorbing region is made from a material with thermo-mechanical properties substantially resistant to shock from dynamic effects of ESD.
  • Further objects, advantages and features of the present invention will become apparent to those skilled in the art from the following detailed description, when read in conjunction with the accompanying drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is an illustration of a prior art integrated circuit incorporating an electrostatic discharge (ESD) protection device that has undergone thermo-mechanical damage due to a fast ESD event;
  • FIG. 2 is a circuit block diagram of a microelectronic circuit employing improved ESD protection in accordance with the present invention;
  • FIG. 3 is an illustration showing a vertical portion of a cross section of the microelectronic circuit of FIG. 2;
  • FIG. 4 is a schematic drawing of another microelectronic circuit layout employing improved ESD protection in accordance with the present invention;
  • FIG. 5 is an illustration showing a vertical cross section of an ESD protection circuit in accordance with a first embodiment of the present invention where a dynamic shock absorber layer is inserted into the sides of the silicon device;
  • FIG. 6 is an illustration showing a vertical cross section of an ESD protection circuit in accordance with another embodiment of the present invention wherein a dynamic shock absorber is inserted above the device;
  • FIG. 7 is an illustration showing a vertical cross section of an ESD protection circuit of the present invention wherein a dynamic shock absorber is included in the substrate below the device;
  • FIG. 8 is an illustration showing a vertical cross section of an ESD protection circuit in accordance with another embodiment of the present invention wherein previous examples are combined to essentially surround the entire ESD protection switch;
  • FIG. 9 is an illustration showing a vertical cross section of an ESD protection circuit in accordance with another embodiment of the present invention wherein the integrated circuit employs dynamic shock absorber material and also material resistant to thermo-mechanical stress.
    • DETAILED DESCRIPTION OF THE INVENTION
  • First, the modeling of ESD damage underlying the approach of the present invention will be described.
  • There are three basic models conventionally used to describe different types of ESD events: the Human Body Model (HBM), the Machine Model (MM) and the Charged Device Model (CDM). The Human Body Model, representative of a charged person touching the electronic device, assumes that a human is charged to around several kilovolts (KV) and is represented by a capacitance of about several hundred Pico Farads that can discharge through a resistor of a few kilo ohms. For example, such an arrangement can generate a 4 KV pulse with a maximum current of 2.6 A and about 150 ns event time. The Machine Model, representative of a charged tool touching the device as a typical example, assumes that a 400 V pulse is discharged with a maximum current of 7 A and an event duration of 10 to 50 ns. In the Charged Device Model corresponding to contact or grounding of charged devices, the event time is extremely short (about 0.25 ns) with voltages reaching about 1 KV and currents on the order of 10 A.
  • As discussed above, prior approaches to modeling ESD and designing ESD protection focus on electrical breakdown and melting due to localized high currents. Such approaches fail to appreciate and compensate for a different class of microelectronic device damage due to ESD. In particular, the present inventors have discovered that ESD damage also occurs through a thermo-mechanical mechanism as described below. This discovery was confirmed through analytical and numerical ESD event simulations incorporating mechanical deformation analysis of the device structure.
      • 1. ESD discharge causes very fast local heating, which occurs within relatively small volumes. The local heating causes, through thermal expansion of materials, intense mechanical stress and deformation. Such effects will typically occur in all three types of ESD events; i.e. HBM, MM and CDM events.
      • 2. Depending upon the rate of temperature increase, mechanical vibrations or elastic waves may be triggered in the device, further compounding mechanical stress intensity. These effects will typically become more significant for fast ESD events such as MM events and in particular, CDM events.
  • The stress intensity caused by thermo-mechanical effects 1. and 2. may surpass the strength of the integrated circuit (IC) chip materials and/or interfaces between different layers, leading to plastic deformation, cracking and/or delamination within the chip. The cracks provide an additional barrier to current flow and/or heat dissipation in consecutive ESD events and thus compound the destructive effects. These thermo-mechanical mechanisms can destroy chips, or begin a process of destruction of chips, at temperatures well below the melting point recognized in the prior art.
  • More specifically, referring to FIG. 1, the primary areas and types of thermo-mechanical damage that can be caused by effects 1. and 2. above during a very fast ESD event are illustrated. The ESD protection device of FIG. 1 is a typical example of a MOSFET switch used in an ESD protection circuit. The MOSFET switch is formed in substrate 110, part of an IC substrate typically of single crystal silicon. The gate contact 120 and drain contact 118 (or source 122) are coupled to the IC pad and ideally the switch will turn on and shunt ESD current harmlessly to ground in an ESD event on the pad. By way of reference, as will be appreciated by those skilled in the art, the components of the MOSFET device also include, source 112, channel 114, drain 116, gate 124, and dielectric material 126. The connectors are typically aluminum or aluminum-silicon-copper alloy and the dielectric is typically silicon dioxide (SiO2). A thin contact diffusion barrier 128 (e.g. titanium nitride TiN) is also shown. The types of thermo-mechanical damage illustrated include delamination 138 and separation of connectors 118, 120, 122 and other elements of the device. Also leading to thermo-mechanical failure is crack propagation 136 from high-stress areas, especially from connectors 118, 120, 122, and adjacent etched or deposited areas formed during fabrication. Crack propagation also occurs in the (silicon) substrate 110 due to dynamic oscillations and elastic waves induced by fast heating. Another type of damage is plastic deformation 134 of the substrate 110 around the heated area epicenter 132 with resulting destruction of its single-crystal structure. The elastic waves induced by fast heating can also cause damage (not shown) further from the heating area 132.
  • The present invention provides circuit designs and methods that minimize the thermo-mechanical effects of ESD discharge, particularly therm-mechanical damage due to fast ESD discharge on the components of the ESD device.
  • In FIG. 2, a block diagram of a microelectronic circuit 200 having improved ESD protection in accordance with the present invention is illustrated. The circuit 200 may comprise any type of microelectronic circuit requiring ESD protection and will typically comprise an IC having core circuitry 220 having many thousands or millions of devices on an IC substrate. Input/output ESD protection circuitry 214, 216, 226, 228 protects the core circuitry 220 from ESD pulses applied to pads 210, 212. The protection circuitry shields the I/O buffers 218, 230 from the stress by clamping the voltage at I/ O pads 210, 212 below the breakdown level. At the same time, the protection circuitry effectively shunts the ESD current to the ground 222 without going through internal circuitry 220. A variety of devices, such as diodes, bipolar transistors, SCRs or MOSFETs can be used in circuitry 214, 216, 226 and 228, usually in conjunction with resistors, as efficient input protection switches. One specific switch configuration is shown in FIG. 4. The present invention is not limited to a specific switch, however, since the main purpose of any switch is to release the ESD energy into surrounding materials where it can be dissipated. Hence, the thermo-mechanical damage modes shown above and respective remedies discussed below, apply to any such switch. Similarly, the modifications can be applied to other components of the ESD protection circuit, such as capacitor 412 and resistor 414.
  • FIG. 3 illustrates generally the physical arrangement of an ESD protection circuit 214 in relation to the IC substrate. The figure shows a vertical cross section of a microelectronic circuit 200 implemented as an IC chip 300. The ESD protection circuit 214 is typically located below the input pad 310 and is spaced apart from the main circuitry 220 (usually at a distance of at least ten or more microns). IC substrate 322 may be single crystal silicon or other known IC substrate. The active devices in core region 220 will include doped regions in the substrate 322 as known in the art. For example, if they contain MOSFET devices, they may generally have the form shown in FIG. 1. Connectors 316 may be conventional materials such as aluminum or copper. Connectors 314, i.e. the portion of the electrical connection within a distance from the pad 210 subject to thermo-mechanical effects, may be a hybrid structure including at least a portion of a thermo-mechanical damage resistive material, as discussed below in relation in FIGS. 6 and 9.
  • FIG. 4 shows a specific example of an input protection circuit that uses a resistor 414 and a capacitor 412 along with an nMOS transistor 416. The nMOS transistor 416 acts as a switch and is off during normal operation. During an ESD event, the nMOS transistor 416 enters into the ESD protection mode, clamping the voltage on the pad 410 below the breakdown levels. The additional resistor 414 and capacitor 412 serve to adjust the breakdown voltage that activates ESD protection. Cross-referencing to FIGS. 2 and 3, the ESD protection circuit 214 may thus comprise transistor 416, resistor 414 and capacitor 412 in an embodiment.
  • The present invention includes specific focus to improve ESD resistance to very fast ESD events that cause dynamic shock effects (e.g. oscillations, elastic waves, dynamic crack propagation). Such dynamic shock effects caused by fast discharge are applicable to the CD model and some frequencies within HBM and MM, especially for larger devices. The present invention may also combine these approaches with an approach directed to improve ESD resistance to slower ESD events, which relates to thermo-mechanical failure under all conditions (i.e. HBM, MM, CDM). This approach is disclosed in detail in the U.S. Patent Application entitled: Method And Apparatus for Preventing Microcircuit Thermo-Mechanical Damage During An ESD Event, filed contemporaneously herewith, and by the same inventors as the present invention, which is incorporated by reference herein, in its entirety.
  • To minimize propagation of the dynamic effects due to fast thermal expansion, the present invention provides in the vicinity of the heated area a “shock absorber” or a number of shock absorbers that will absorb the energy of dynamic effects. The shock absorbing material of the present invention can be in either of the following three classes:
      • 1. Damping materials, with the following properties:
        • a. High material damping coefficient that dissipates mechanical energy. The desired range of material damping is defined by the value of the Dynamic Loss Factor that is the ratio of the mechanical energy dissipated during one cycle to the maximum strain energy during the cycle. According to the invention, shock-absorbing material should have a loss factor higher than approximately 0.01, more preferably higher than 0.04.
        • b. Moderate melting temperature defined by a Melting Point above approximately 800 °K.
        • c. Moderately low stiffness as compared to silicon defined by a preferred Modulus of Elasticity between approximately 10 GPa (Giga Pascals) and 100 GPa.
        • d. Moderate to high strength defined by a Tensile Strength higher than approximately 100 MPa.
  • Examples of desirable damping materials for shock absorbing material are: polymers and amorphous carbon.
      • 2. High-Strength materials with the following properties:
        • a. Modulus of Elasticity that is higher than approximately 100 GPa.
        • b. Tensile Strength for bulk material (samples of cross-section of 2 mm or higher), the tensile strength preferably higher than approximately 300 MPa.
        • c. Fracture Toughness that is higher than approximately 1.0 MPa m1/2.
  • Examples of desirable high-strength materials for shock absorbers are: diamond, hard carbon (also known as diamond-like carbon, amorphous carbon), boron nitride, and silicon carbide.
      • 3. Dynamic shock absorbers can be made as a composite that includes Damping Materials and High-Strength Materials.
  • It should be noted that material properties usually change with temperature—for example material strength typically decreases as melting temperature is approached. Hence, while it is desirable that the materials maintain the specified properties at the whole range of operating temperatures, the values given in this application refer to standard measurements at room temperature.
  • A preferred embodiment showing a manner in which shock absorbers 528, 530 are employed in an ESD device 500 is shown in FIG. 5. It should be noted that the preferred embodiments disclosed herein could be employed in various combinations. The specific structure corresponds to a MOSFET switch such as switch 416 shown in FIG. 4. However, the modifications can equally be applied to any other switch type, such as bipolar transistor, SCR or other known ESD switch type. By way of example, the active device region of an ESD switch comprises a source 512 and a drain 516 region connected by a channel 514 region, formed in substrate 510. The switch also has a gate 524. Connecting the active device regions are source 522, gate 520 and drain 518 connectors.
  • In the embodiment illustrated in FIG. 5, shock absorbers 528, 530 are inserted into deep grooves in the silicon on both sides of the device. This particular embodiment can be accomplished by anisotropic etching in the substrate 510, followed by isotropic deposition of a shock absorbing material (e.g. carbon) followed by an anisotropic planarizing etch. If needed, shock-absorbing material can be surrounded by dielectric material (not shown) such as Silicon Oxide or Silicon Nitride.
  • Another embodiment is represented in FIG. 6. The embodiment of FIG. 6 also shows a MOSFET switch comprising source 612, channel 614, drain 616, formed in substrate 610, associated source and drain contacts 618, 622, gate 624, gate contact 620 and dielectric 626. In this embodiment a shock absorber layer 630 is inserted below a passivation layer 632 and above the remaining portion of the ESD protection device 600. Again, if needed a thin dielectric layer 628, such as Si Oxide or Si Nitride, is introduced between the shock absorber 630 and the remainder of the device 600. As a special case, the entire passivation layer 632 is made of shock absorber material. The embodiment of FIG. 6 also includes a gate region 624 made of material resistant to thermo-mechanical expansion due to local heating from discharges with slower event times such as those modeled by the HBM and MM.
  • Yet another embodiment is represented in FIG. 7. The embodiment of FIG. 7 illustrate a MOSFET switch comprising source 712, channel 714, and drain 716 formed in substrate 710 and associated contacts 722, 718, a gate 724, gate contact 720 and dielectric 726. In this embodiment, a shock absorber 728 is placed within the semiconductor substrate 710 below the active area of the ESD switch comprising the source, channel and drain regions. The active area of the ESD switch also may be defined as the area within the switch where the electric field is substantially non-zero. The shock absorber 728 may be located below each individual switch or stretch under a number of switches on an ESD protection pad. As in previous embodiments, the shock-absorbing layer 728 can be surrounded by a dielectric such as Si Oxide or Si Nitride if needed.
  • Another embodiment is illustrated in FIG. 8. As in the previous embodiments, a MOSFET switch comprising source 812, channel 814, drain 816, formed in substrate 810, drain contact 818, source contact 822, gate 824, gate contact 820 and dielectric 826. A dielectric layer 832 and passivation layer are also shown as in the prior embodiment. In the embodiment shown in FIG. 8, the shock absorbers 828, 830, 834, and 836 as shown in previous examples are combined to essentially surround the entire ESD protection switch and/or its components that may include individual MOSFETS, diodes, and resistors, etc. If needed, a connection is left between the active area and bulk semiconductor 810 to allow release of current to the ground.
  • Another embodiment is shown of a MOSFET switch surrounded by shock absorber 928, 930, 934 and 936. The FIG. 9 embodiment combines these dynamic shock absorber materials with material resistant to thermo-mechanical expansion applicable to the HBM and MM models. For these slower ESD modes, the mechanism of failure is through thermal expansion of materials and associated intense mechanical stress and deformation. The basic idea for preventing ESD device failure due to slower discharge events is to replace vulnerable materials (aluminum, copper, silicon) with thermo-mechanical energy sink material that can withstand thermo-mechanical expansion and stress. Ideally, the materials resistant to thermo-mechanical expansion have the following physical properties, in comparison to materials presently used.
      • 1. Very low thermal expansion. This minimizes the thermal stresses and the dynamic energy induced by fast heating. The less thermal expansion, the less thermo-mechanical stress.
      • 2. High strength and, preferably, low brittleness.
      • 3. High melting temperature. Although this is not directly related to the thermo-mechanical damage mechanisms described here, it is generally desirable for such materials to have high melting temperature, to effectively resist the currently recognized “melting” mechanism of failure under ESD discharge.
  • As will be appreciated by those skilled in the art, different material types are used to perform different functions in ESD switches for a particular IC. Therefore, the desired “low” or “high” material properties are relative, depending on the materials commonly used in the application which are replaced for increased thermo-mechanical failure resistance. Specific examples will be provided below to clarify these material properties although these should not be viewed as limiting in nature. Referring to FIG. 9, the connectors 918, 920, and 922, should be fabricated from material with the following properties.
      • 1. Low thermal expansion that is defined by the Coefficient of Thermal Expansion (CTE) being lower than 10.0×10−6 °K−1 (per degree Kelvin) and, more preferably, lower than 5.0×10−6 °K−1.
      • 2. High melting temperature that is defined by a melting point being higher than 1500 °K and, more preferably, higher than 3000 °K.
      • 3. High strength that is defined by the Tensile Strength for bulk material (samples that have cross-section of 2 mm or higher) being higher than 200 MPa (Mega Pascals) and a Fracture Toughness being higher than 1.0 MPa m1/2. It should be noted that the strength criterion is of lesser importance for connectors than the other two criteria.
  • Examples of desirable connector materials are titanium nitride (TiN), graphite, and carbon (C). Alternatively, connectors 918, 920, 922 may comprise an alloy containing significant portions of such material used in conjunction with aluminum or copper.
  • In this embodiment, aluminum (Al) or copper (Cu) connectors 918, 920, 922 in the vicinity of the heated area are replaced by a conductor with high resistance to thermo-mechanical stress as defined above. As a result, a hybrid connector structure is formed as Al or Cu connectors 918, 920, and 922 are still used in the present invention to facilitate connections with the core circuitry and external wires (not shown). In relative terms, the thickness of the material (e.g. TiN, graphite or C) used in connectors 918, 920, 922, for example, should be approximately one half of the length of the active device region. In absolute terms, the thickness of the layer can vary from 50 A to 5,000 A; however, this range may easily change henceforth, because microelectronic devices continually get smaller with advancement.
  • The active area 914 of the semiconductor substrate 910, and the components such as resistors and capacitors therein, should be fabricated from material resistant to thermo-mechanical expansion with the following physical properties.
      • 1. Low thermal expansion that is defined by the Coefficient of Thermal Expansion (CTE) being lower than 5.0×10−6 K−1, more preferably lower than 2.0×10−6 K−1, and ideally lower than 0.5×10−6 K−1.
      • 2. High melting temperature that is defined by Melting Point being higher than 2000 °K and, more preferably, higher than 3500 °K.
      • 3. High strength that is defined by Tensile Strength for bulk material (samples of cross-section of 2 mm or higher) being higher than 300 MPa (Mega Pascals) and Fracture Toughness being higher than 1.0 MPa m1/2. More preferably, a tensile strength of bulk material above 600 MPa and fracture toughness above 3.0 MPa m1/2 is desired.
  • Some examples of preferred semiconductor, resistor and capacitor materials include: diamond, hard carbon (i.e. diamond-like carbon, amorphous carbon), boron nitride, and less preferably, silicon carbide. All materials may be doped as needed for electrical properties.
  • Fabrication processes for an ESD protection device with improved resistance to thermo-mechanical stress are also provided by to the present invention. A first fabrication process is a method for inserting a material with desirable thermo-mechanical properties, such as hard carbon or diamond-like carbon, amorphous carbon, boron nitride, silicon carbide, or polymers, under the ESD protection switch. The method first employs depositing an oxide layer onto a semiconductor substrate. The next step is to deposit the material, e.g. hard carbon, onto the oxide layer at a pre-determined thickness. Next, a photo resist layer is deposited on the substrate that forms the area where the ESD switch is located (i.e. adjacent to the region of the IC where the pad(s) will be formed). The remaining portions where the hard carbon and oxide layer were deposited are next etched away to leave the area where the ESD switch is to be located. Another oxide layer is then deposited on the hard carbon on the area of interest followed by another photo resist layer. The excess portions are again etched leaving the hard carbon encapsulated in oxide with a strip of silicon neighboring the enveloped hard carbon. Next, amorphous silicon is then deposited into the envelope followed by an epitaxial silicon layer wherein the active region of the ESD switch is formed. Lastly, the excess amorphous silicon and unneeded oxide are etched from the rest of the wafer. The foregoing fabrication method may be applied to the embodiment discussed in FIGS. 7-9, for example.
  • A second method of the invention provides for surrounding an ESD protection switch area with a trench and filling the trench with a material resistant to dynamic shock (e.g. hard carbon). The first step is to apply a photo resist layer around and area to be etched away to form a trench. Next, an oxide layer and the hard carbon material are isotropically deposited into the trench. The excess hard carbon is then anisotropically reactive ion etched until only the trench is filled with hard carbon. Lastly, another oxide layer is deposited and etched leaving the hard carbon encapsulated in oxide. The foregoing fabrication method may be applied to the embodiment discussed in FIG. 5, 8 and 9, for example.
  • Additional fabrication techniques are also contemplated by the present invention. First, the manufacturing of ESD devices should be achieved so that mechanically strong bonds are formed between the different materials contained within the device. Specific deposition techniques, for example, are employed to assure strong bonding between consecutive deposited layers.
  • A first technique is to use a uniform deposition temperature for all materials, appropriately near 400° C., for example. By using the same deposition temperature for all materials, the invention minimizes fabrication stresses between the material layers caused by different thermal expansion coefficients of materials. By choosing the deposition temperature to be between room temperature and that achieved during ESD, the present invention aims to optimize the range of thermal stresses so that they are not too high, either at room temperature or during an ESD event. The basic principle is that inter-layer thermal stresses increase with the departure from stress-free deposition temperature. Prolonged annealing is another technique to improve the strength and ductility of materials in the manufacturing of ESD devices. A preferred annealing temperature for exemplary materials of the present invention is approximately 600° C.
  • An additional manufacturing and design technique is to eliminate sharp corners when fabricating and etching the components of the ESD device. By using appropriate deposition and etching techniques, sharp corners between adjoining materials should be minimized in favor of rounded corners. Generally, the geometry of corners and notches should be as smooth as practically achievable to minimize the mechanical stress at which crack propagation occurs. An alternative technique contemplated by the present invention is to apply a passivation layer that is stiff and strong with an optimal thickness. A strong passivation layer will contain the expansive thermal stresses and maintain them within the compressive, rather than tensile, range. This helps prevent delamination, material separation and crack propagation. Further, the passivation layer should be ductile, rather than brittle, to prevent the layer from cracking and provide some damping of elastic waves caused by fast ESD events.
  • It should be appreciated that the foregoing description of the preferred embodiments of the present invention may be modified in a variety of different ways, which should be apparent to those skilled in the art from the above teachings. Accordingly, the present invention should not be limited in any way to the illustrated embodiments as the present invention in its various aspects encompasses all such modifications and variations thereof which are too numerous to describe in specific detail herein. While the invention has been illustrated and described by means of specific embodiments, it is to be understood that numerous changes and modifications may be made therein without departing from the intent and scope of the invention as defined in the appended claims.

Claims (31)

1. canceled
2. An integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising:
a semiconductor substrate:
an electrical contact pad:
an ESD switch coupled to the Pad and having an active device region formed in the semiconductor substrate: and
a dynamic shock absorbing region formed in the semiconductor substrate adjacent to said active device region said dynamic shock absorbing region made from a material with thermo-mechanical properties substantially more resistant to shock from dynamic effects of ESD than said active device region, wherein said thermo-mechanical properties include a dynamic loss factor higher than approximately 0.01.
3. An integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising:
a semiconductor substrate;
an electrical contact pad;
an ESD switch coupled to the pad and having an active device region formed in the semiconductor substrate: and
a dynamic shock absorbing region formed in the semiconductor substrate adjacent to said active device region, said dynamic shock absorbing region made from a material with thermo-mechanical properties substantially more resistant to shock from dynamic effects of ESD than said active device region, wherein said thermo-mechanical properties further include a melting temperature higher than approximately 800 °K.
4. An integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising:
a semiconductor substrate;
an electrical contact pad;
an ESD switch coupled to the Pad and having an active device region formed in the semiconductor substrate; and
a dynamic shock absorbing region formed in the semiconductor substrate adjacent to said active device region, said dynamic shock absorbing region made from a material with thermo-mechanical properties substantially more resistant to shock from dynamic effects of ESD than said active device region, wherein said thermo-mechanical properties further include a moderately low stiffness as defined by an elastic modulus approximately in the range of 10 GPa and 100 GPa (Giga Pascals).
5. An integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising:
a semiconductor substrate:
an electrical contact pad;
an ESD switch coupled to the Pad and having an active device region formed in the semiconductor substrate; and
a dynamic shock absorbing region formed in the semiconductor substrate adjacent to said active device region, said dynamic shock absorbing region made from a material with thermo-mechanical properties substantially more resistant to shock from dynamic effects of ESD than said active device region, wherein said thermo-mechanical properties further include a tensile strength higher than approximately 100 MPa.
6. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claims 2, 3, 4 or 5, wherein the ESD switch has one or more sides, and wherein the dynamic shock absorbing region formed in the semiconductor substrate is located in trenches adjacent to the one or more sides of the ESD switch.
7. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claims 2, 3, 4 or 5, wherein the ESD switch is a transistor.
8. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claims 2, 3, 4 or 5, wherein the dynamic shock absorbing region is configured above the active device region.
9. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claims 1, 2, 3 or 4, wherein the dynamic shock absorbing region is configured below the active device region of the ESD switch.
10. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claims 2, 3, 4 or 5, wherein said dynamic shock absorbing region made from a material with thermo-mechanical properties substantially more resistant to dynamic shock than said active device region is selected from the group consisting of hard polymers, amorphous carbon, carbon-carbon composite or carbon-polymer composite.
11. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claims 2, 3, 4 or 5, wherein said dynamic shock absorbing region is surrounded by a dielectric region.
12. canceled
13. An integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising:
a semiconductor substrate:
an ESD switch having an active device region formed in the semiconductor substrate; and
a plurality of dynamic shock absorbing regions formed around the active device region, said dynamic shock absorbing region made from a material with thermo-mechanical properties substantially more resistant to shock from dynamic effects of ESD than said active device region, wherein said thermo-mechanical properties include a dynamic loss factor higher than approximately 0.01.
14. An integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising:
a semiconductor substrate;
an ESD switch having an active device region formed in the semiconductor substrate: and
a plurality of dynamic shock absorbing regions formed around the active device region, said dynamic shock absorbing region made from a material with thermo-mechanical Properties substantially more resistant to shock from dynamic effects of ESD than said active device region, wherein said thermo-mechanical properties further include a melting temperature higher than approximately 800 °K.
15. An integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising:
a semiconductor substrate;
an ESD switch having an active device region formed in the semiconductor substrate: and
a plurality of dynamic shock absorbing regions formed around the active device region, said dynamic shock absorbing region made from a material with thermo-mechanical properties substantially more resistant to shock from dynamic effects of ESD than said active device region, wherein said thermo-mechanical properties further include a moderately low stiffness as defined by an elastic modulus approximately in the range of 10 GPa and 100 GPa (Giga Pascals).
16. An integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising:
a semiconductor substrate:
an ESD switch having an active device region formed in the semiconductor substrate; and
a plurality of dynamic shock absorbing regions formed around the active device region, said dynamic shock absorbing region made from a material with thermo-mechanical properties substantially more resistant to shock from dynamic effects of ESD than said active device region, wherein said thermo-mechanical properties further include a moderately high tensile strength higher than approximately 100 MPa.
17. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claims 13, 14, 15 or 16, further comprising a dielectric layer formed in between said ESD switch and said dynamic shock absorbing region.
18. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claims 13, 14, 15 or 16 and further comprising a passivation layer formed above said dynamic shock absorbing region.
19. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claims 13, 14, 15 or 16, wherein said ESD switch has a gate region formed from a thermo-mechanical energy sink material, and wherein said thermo-mechanical energy sink material is substantially more resistant to thermo-mechanical expansion than the semiconductor substrate.
20. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claim 19, wherein said thermo-mechanical energy sink material has physical properties including a high melting temperature higher than approximately 2000 °K.
21. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claim 19, wherein said thermo-mechanical energy sink material has physical properties further including a high tensile strength higher than approximately 300 MPa.
22. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claim 19, wherein said thermo-mechanical energy sink material has physical properties further including a low thermal expansion coefficient lower than approximately 5×10−6° K−1.
23. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claims 13, 14, 15 or 16, further comprising a second dynamic shock absorbing region formed in the semiconductor substrate in thermal contact with said active device region, said second dynamic shock absorbing region made from a material with thermo-mechanical properties substantially more resistant to shock from the dynamic effects of ESD than said active device region.
24. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claims 13, 14, 15 or 16, wherein the ESD switch has one or more sides, the device further comprising a third dynamic shock absorbing region located adjacent to the one or more sides of the ESD switch.
25. canceled
26. An integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising:
a semiconductor substrate;
an ESD circuit comprising a switch having an active device region formed in the semiconductor substrate and one or more passive circuit components; and
means for absorbing dynamic shock from at least one of the switch and one or more passive components in response to an ESD event, wherein said means for absorbing shock comprises a region above the active device region made from a material with thermo-mechanical properties resistant to shock from dynamic effects of ESD, the thermo-mechanical properties including a high material dynamic loss factor higher than approximately 0.01.
27. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claim 26, and further comprising a second dynamic shock absorbing region formed below the active device region, said second dynamic shock absorbing region made from a material with thermo-mechanical properties resistant to shock from the dynamic effects of ESD, the thermo-mechanical properties including a high material dynamic loss factor higher than approximately 0.01.
28. The integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claim 27, wherein the ESD switch also has one or more sides, wherein the means for absorbing shock further comprises a third dynamic shock absorbing region formed adjacent to the one or more sides of the ESD switch, said third dynamic shock absorbing region made from a material with thermo-mechanical properties resistant to shock from the dynamic effects of ESD, the thermo-mechanical properties including a high material dynamic loss factor higher than approximately 0.01.
29. An integrated circuit incorporating an Electrostatic Discharge (ESD) protection device comprising:
a semiconductor substrate;
an ESD circuit comprising a switch having an active device region formed in the semiconductor substrate and one or more passive circuit components, wherein said switch has a gate region and wherein said gate region is formed from a thermo-mechanical energy sink material, said thermo-mechanical energy sink material being substantially resistant to thermo-mechanical expansion and having physical properties including a low thermal expansion coefficient lower than approximately 5×10−6° K−1 and
means for absorbing dynamic shock from at least one of the switch and one or more passive components in response to an ESD event.
30. An integrated circuit incorporating an Electrostatic Discharge (ESD) protection device according to claim 25 comprising:
a semiconductor substrate;
an ESD circuit comprising a switch having an active device region formed in the semiconductor substrate and one or more passive circuit components, wherein said active device region of said switch is formed from a thermo-mechanical energy sink material, said thermo-mechanical energy sink material substantially resistant to thermo-mechanical expansion and having physical properties including a low thermal expansion coefficient lower than approximately 5×10−6° K−1; and
means for absorbing dynamic shock from at least one of the switch and one or more passive components in response to an ESD event.
31-35. (canceled)
US10/635,390 2003-08-06 2003-08-06 Method and apparatus for preventing microcircuit dynamic thermo-mechanical damage during an ESD event Expired - Fee Related US6853036B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/635,390 US6853036B1 (en) 2003-08-06 2003-08-06 Method and apparatus for preventing microcircuit dynamic thermo-mechanical damage during an ESD event

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/635,390 US6853036B1 (en) 2003-08-06 2003-08-06 Method and apparatus for preventing microcircuit dynamic thermo-mechanical damage during an ESD event

Publications (2)

Publication Number Publication Date
US6853036B1 US6853036B1 (en) 2005-02-08
US20050029595A1 true US20050029595A1 (en) 2005-02-10

Family

ID=34104620

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/635,390 Expired - Fee Related US6853036B1 (en) 2003-08-06 2003-08-06 Method and apparatus for preventing microcircuit dynamic thermo-mechanical damage during an ESD event

Country Status (1)

Country Link
US (1) US6853036B1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050248896A1 (en) * 2001-11-30 2005-11-10 Veris Industries, Llc Power monitoring system
US20060181827A1 (en) * 2005-02-16 2006-08-17 Dudnikov George Jr Selective deposition of embedded transient protection for printed circuit boards
US20060199390A1 (en) * 2005-03-04 2006-09-07 Dudnikov George Jr Simultaneous and selective partitioning of via structures using plating resist
US7375543B2 (en) * 2005-07-21 2008-05-20 Lsi Corporation Electrostatic discharge testing
US20100100859A1 (en) * 2008-10-21 2010-04-22 Lsi Corporation Design methodology for preventing functional failure caused by cdm esd
US9781830B2 (en) 2005-03-04 2017-10-03 Sanmina Corporation Simultaneous and selective wide gap partitioning of via structures using plating resist
US20190355413A1 (en) * 2018-04-19 2019-11-21 Micron Technology, Inc. Permutation coding for improved memory cell operations

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7489493B2 (en) * 2003-12-01 2009-02-10 Magnecomp Corporation Method to form electrostatic discharge protection on flexible circuits using a diamond-like carbon material
JP4991134B2 (en) * 2005-09-15 2012-08-01 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US8148748B2 (en) * 2007-09-26 2012-04-03 Stmicroelectronics N.V. Adjustable field effect rectifier
EP2232559B1 (en) 2007-09-26 2019-05-15 STMicroelectronics N.V. Adjustable field effect rectifier
EP2384518B1 (en) 2009-01-06 2019-09-04 STMicroelectronics N.V. Self-bootstrapping field effect diode structures and methods
WO2010127370A2 (en) * 2009-05-01 2010-11-04 Lakota Technologies, Inc. Series current limiting device
US8598593B2 (en) * 2011-07-15 2013-12-03 Infineon Technologies Ag Chip comprising an integrated circuit, fabrication method and method for locally rendering a carbonic layer conductive

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6259139B1 (en) * 1999-12-31 2001-07-10 United Microelectronics Corp. Embedded well diode MOS ESD protection circuit
US6353236B1 (en) * 1998-09-17 2002-03-05 Hitachi, Ltd. Semiconductor surge absorber, electrical-electronic apparatus, and power module using the same
US20020070424A1 (en) * 2000-12-12 2002-06-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6436744B1 (en) * 2001-03-16 2002-08-20 International Business Machines Corporation Method and structure for creating high density buried contact for use with SOI processes for high performance logic
US6560105B1 (en) * 2001-10-23 2003-05-06 Di/Dt, Inc. Composite low flow impedance voltage guard for electronic assemblies
US6674129B1 (en) * 1999-12-17 2004-01-06 Koninklijke Phillips Electronics N.V. ESD diode structure
US6734093B1 (en) * 1999-03-17 2004-05-11 Intel Corporation Method for placing active circuits beneath active bonding pads

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5392185A (en) 1992-05-29 1995-02-21 Texas Instruments Incorporated Electrostatic discharge protection device
US5477414A (en) 1993-05-03 1995-12-19 Xilinx, Inc. ESD protection circuit
US6034388A (en) 1998-05-15 2000-03-07 International Business Machines Corporation Depleted polysilicon circuit element and method for producing the same
US6157530A (en) 1999-01-04 2000-12-05 International Business Machines Corporation Method and apparatus for providing ESD protection
US6153913A (en) 1999-06-30 2000-11-28 United Microelectronics Corp. Electrostatic discharge protection circuit
US6268286B1 (en) 2000-02-01 2001-07-31 International Business Machines Corporation Method of fabricating MOSFET with lateral resistor with ballasting
US6331726B1 (en) 2000-03-21 2001-12-18 International Business Machines Corporation SOI voltage dependent negative-saturation-resistance resistor ballasting element for ESD protection of receivers and driver circuitry

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6353236B1 (en) * 1998-09-17 2002-03-05 Hitachi, Ltd. Semiconductor surge absorber, electrical-electronic apparatus, and power module using the same
US6734093B1 (en) * 1999-03-17 2004-05-11 Intel Corporation Method for placing active circuits beneath active bonding pads
US6674129B1 (en) * 1999-12-17 2004-01-06 Koninklijke Phillips Electronics N.V. ESD diode structure
US6259139B1 (en) * 1999-12-31 2001-07-10 United Microelectronics Corp. Embedded well diode MOS ESD protection circuit
US20020070424A1 (en) * 2000-12-12 2002-06-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6436744B1 (en) * 2001-03-16 2002-08-20 International Business Machines Corporation Method and structure for creating high density buried contact for use with SOI processes for high performance logic
US6560105B1 (en) * 2001-10-23 2003-05-06 Di/Dt, Inc. Composite low flow impedance voltage guard for electronic assemblies

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050248896A1 (en) * 2001-11-30 2005-11-10 Veris Industries, Llc Power monitoring system
US7593203B2 (en) 2005-02-16 2009-09-22 Sanmina-Sci Corporation Selective deposition of embedded transient protection for printed circuit boards
US20060181827A1 (en) * 2005-02-16 2006-08-17 Dudnikov George Jr Selective deposition of embedded transient protection for printed circuit boards
US20060181826A1 (en) * 2005-02-16 2006-08-17 Dudnikov George Jr Substantially continuous layer of embedded transient protection for printed circuit boards
US7688598B2 (en) 2005-02-16 2010-03-30 Sanmina-Sci Corporation Substantially continuous layer of embedded transient protection for printed circuit boards
US20060199390A1 (en) * 2005-03-04 2006-09-07 Dudnikov George Jr Simultaneous and selective partitioning of via structures using plating resist
US9781830B2 (en) 2005-03-04 2017-10-03 Sanmina Corporation Simultaneous and selective wide gap partitioning of via structures using plating resist
US10667390B2 (en) 2005-03-04 2020-05-26 Sanmina Corporation Simultaneous and selective wide gap partitioning of via structures using plating resist
US11765827B2 (en) 2005-03-04 2023-09-19 Sanmina Corporation Simultaneous and selective wide gap partitioning of via structures using plating resist
US7375543B2 (en) * 2005-07-21 2008-05-20 Lsi Corporation Electrostatic discharge testing
US20100100859A1 (en) * 2008-10-21 2010-04-22 Lsi Corporation Design methodology for preventing functional failure caused by cdm esd
US9239896B2 (en) * 2008-10-21 2016-01-19 Avago Technologies General Ip (Singapore) Pte. Ltd. Methodology for preventing functional failure caused by CDM ESD
US20190355413A1 (en) * 2018-04-19 2019-11-21 Micron Technology, Inc. Permutation coding for improved memory cell operations

Also Published As

Publication number Publication date
US6853036B1 (en) 2005-02-08

Similar Documents

Publication Publication Date Title
US20060097323A1 (en) Method and apparatus for preventing microcircuit thermo-mechanical damage during an ESD event
US6853036B1 (en) Method and apparatus for preventing microcircuit dynamic thermo-mechanical damage during an ESD event
US9431550B2 (en) Trench polysilicon diode
US7273770B2 (en) Compliant passivated edge seal for low-k interconnect structures
US10679935B2 (en) Structure and method for improving high voltage breakdown reliability of a microelectronic device
US5404041A (en) Source contact placement for efficient ESD/EOS protection in grounded substrate MOS integrated circuit
US10504772B2 (en) Field emission devices and methods of making thereof
US7129545B2 (en) Charge modulation network for multiple power domains for silicon-on-insulator technology
US7479699B2 (en) Seal ring structures with unlanded via stacks
JP2011049393A (en) Semiconductor device and method of manufacturing the same
US7872352B2 (en) Carbon nanotube bond pad structure and method therefor
US20220165727A1 (en) Semiconductor device and method of manufacturing the same
US6376881B1 (en) Protective element formed in an SOI substrate for preventing a breakdown in an oxide film located below a diffused resistor
US9472544B2 (en) Semiconductor device comprising electrostatic discharge protection structure
US6407445B1 (en) MOSFET-based electrostatic discharge (ESD) protection structure with a floating heat sink
EP2204843A2 (en) Semiconductor device and its manufacturing method
US6888248B2 (en) Extended length metal line for improved ESD performance
JP3729082B2 (en) Semiconductor protection circuit
JP2004040091A (en) Esd protection for noise isolation capacitor
CN112397502A (en) Electrostatic discharge protection circuit and structure thereof
US6208493B1 (en) Method and system for protecting integrated circuits against a variety of transients
Ker et al. Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
EP1494284A1 (en) Overvoltage protection device
US20060023387A1 (en) ESD device for high speed data communication system with improved bandwidth
US11817403B2 (en) Electrostatic discharge (ESD) array with circuit controlled switches

Legal Events

Date Code Title Description
AS Assignment

Owner name: ESD PULSE, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RODOV, VLADIMIR;TWORZYDLO, WLODZIMIERZ WOYTEK;REEL/FRAME:014382/0463;SIGNING DATES FROM 20030729 TO 20030802

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 8

SULP Surcharge for late payment

Year of fee payment: 7

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20170208