US20050029683A1 - Gettering using voids formed by surface transformation - Google Patents

Gettering using voids formed by surface transformation Download PDF

Info

Publication number
US20050029683A1
US20050029683A1 US10/931,344 US93134404A US2005029683A1 US 20050029683 A1 US20050029683 A1 US 20050029683A1 US 93134404 A US93134404 A US 93134404A US 2005029683 A1 US2005029683 A1 US 2005029683A1
Authority
US
United States
Prior art keywords
voids
wafer
region
precisely
gettering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/931,344
Inventor
Leonard Forbes
Joseph Geusic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to US10/931,344 priority Critical patent/US20050029683A1/en
Publication of US20050029683A1 publication Critical patent/US20050029683A1/en
Priority to US11/606,479 priority patent/US7544984B2/en
Priority to US11/606,503 priority patent/US7564082B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3223Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering using cavities formed by hydrogen or noble gas ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/913Active solid-state devices, e.g. transistors, solid-state diodes with means to absorb or localize unwanted impurities or defects from semiconductors, e.g. heavy metal gettering

Definitions

  • This disclosure relates generally to integrated circuits, and more particularly, to strained semiconductor structures.
  • Unwanted crystalline defects and impurities can be introduced during crystal growth or subsequent wafer fabrication processes. These defect and impurities can degrade device characteristics and overall yield. Gettering has been described as a process for moving contaminants and/or defects in a semiconductor into its bulk and away from its top surface to create a denuded zone cleared from contaminants and/or defects. Preferably, devices are built in the denuded zone.
  • extrinsic backside gettering was used to getter silicon wafers.
  • Various extrinsic backside gettering processes involve damaging the backside of the wafer mechanically or by implanting argon, germanium, hydrogen or other implants, or providing a gettering layer on the backside of the wafer using a phophorosilicate glass or oxide backside layer, a polysilicon backside layer, and a silicon germanium (SiGe) backside epitaxial layer.
  • “intrinsic” gettering was developed, which employed oxygen precipitation and “bulk microdefects” precipitated into the bulk of the wafer after the surface was “denuded” of oxygen.
  • gettering processes depend on the diffusion of unwanted impurities over significant distances from desired device regions to the gettering sites.
  • modem low temperature processes have small thermal budgets, and do not afford an opportunity for significant diffusion of dopants and/or unwanted impurities.
  • Implanting helium forms cavities that function to getter impurities.
  • This helium implantation technique has been proposed to getter both bulk and silicon-on-insulator devices.
  • the location and density of these cavities formed by implanting helium is random.
  • One problem associated with the random location and density of cavities is that the effectiveness of the gettering unwanted impurities from the desired device regions is inconsistent.
  • Other problems associated with the random location and density of cavities involves the varying strain in the substrate and the varying ability of the substrate to withstand mechanical strain. The inconsistent effectiveness of gettering, the inconsistent strain and the inconsistent ability to withstand strain can negatively affect the ability to precisely form devices as the semiconductor industry strives to fabricate smaller and thinner devices.
  • Various aspects and embodiments of the present invention getter a semiconductor wafer by precisely forming voids, such as nano-sized voids, at desired locations in the wafers.
  • precisely-formed gettering void patterns are formed in selected regions below where devices are fabricated on semiconductor wafers. Numerous dangling bonds are present at the internal surfaces of the voids such that these internal surfaces are highly chemically reactive.
  • various embodiments form the voids and void patterns to have a large surface to volume ratio to increase gettering of impurities.
  • One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer.
  • a predetermined arrangement of a plurality of holes is formed in the semiconductor wafer through a surface of the wafer.
  • the wafer is annealed such that the wafer undergoes a surface transformation to transform the arrangement of the plurality of holes into a predetermined arrangement of at least one empty space of a predetermined size within the wafer to form the gettering site.
  • the wafer includes at least one device region, and at least one gettering region located proximate to the at least one device region.
  • the gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids that are formed within the wafer using a surface transformation process.
  • FIG. 1 illustrates a semiconductor structure having a gettering region with precisely formed voids at precise locations, according to various embodiments of the present invention.
  • FIG. 2 illustrates a semiconductor structure having a gettering region with precisely formed voids at precise locations, according to various embodiments of the present invention.
  • FIG. 3 illustrates a transistor formed in a device region proximate to a gettering region with precisely formed voids at precise locations, according to various embodiments of the present invention.
  • FIGS. 4A-4F illustrate a process to form a sphere-shaped empty space in a gettering region, according to various embodiments of the present invention.
  • FIGS. 5A-5C illustrate a process to form a pipe-shaped empty space in a gettering region, according to various embodiments of the present invention.
  • FIGS. 6A-6B illustrate a process to form a plate-shaped empty space in a gettering region, according to various embodiments of the present invention.
  • FIGS. 7A-7E illustrate the formation of empty spheres in a gettering region from initial cylindrical holes with the same radii and with varying length, according to various embodiments of the present invention.
  • FIG. 8 illustrates a transformation formed stack of empty plates in a gettering region, according to various embodiments of the present invention.
  • FIG. 9 illustrates fourteen representative unit cells of space lattices which the voids in the gettering region can form, according to various embodiments of the present invention.
  • FIG. 10 illustrates a void pattern in a gettering region arranged to form the cubic P unit cell shown among the fourteen representative unit cells of FIG. 9 .
  • FIGS. 11A-11B illustrate a process for forming a cubic P lattice of spherical empty spaces, according to various embodiments of the present invention.
  • FIGS. 12A-12D illustrate a process for forming a simple unit of empty spheres having two radii in a gettering region, according to various embodiments of the present invention.
  • FIG. 13 illustrates a process for forming semiconductor devices, according to various embodiments of the present invention.
  • FIG. 14 illustrates a process for precisely forming voids in a substrate located to getter a device region as performed in the process for forming semiconductor devices of FIG. 13 .
  • FIG. 15 is a simplified block diagram of a high-level organization of a memory device, according to various embodiments of the present invention.
  • FIG. 16 is a simplified block diagram of a high-level organization of an electronic system, according to various embodiments of the present invention.
  • wafer and substrate are interchangeably used to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art.
  • aspects of the present invention precisely form voids at desired location using a surface transformation process to getter semiconductor wafers.
  • Various embodiments precisely form patterns of nano-voids (voids having a diameter on the order of a nanometer) as a proximity gettering region to effectively and consistently getter impurities from device regions.
  • FIG. 1 illustrates a semiconductor structure having a gettering region with precisely formed voids at precise locations, according to various embodiments of the present invention.
  • the illustrated structure 100 includes a semiconductor wafer, also referred to here as a substrate 101 .
  • a proximity gettering region 102 is located near to a device region 103 such that unwanted impurities can travel a short distance from the device region 103 to the gettering region 102 , even with modern low temperature processes.
  • the gettering region 102 includes a number of precisely formed and located voids 104 formed by surface transformation. Surface transformation is described in detail below.
  • the present invention is not limited to gettering regions having a particular pattern, shape or size of voids.
  • the device region 103 includes crystalline silicon.
  • Semiconductor devices such as transistors, are fabricated in the crystalline silicon. Other crystalline semiconductor materials can be used to form the device region 103 . Thus, it is desired to getter unwanted impurities from the device region.
  • the voids 104 in the gettering region 102 generate defects that getter impurities from the device region 103 .
  • the internal surfaces of the voids have numerous dangling bonds, and thus are highly chemically reactive, which serves to getter impurities from the device region 103 .
  • FIG. 2 illustrates a semiconductor structure having a gettering region with precisely formed voids at precise locations, according to various embodiments of the present invention.
  • the illustrated structure 200 includes a semiconductor wafer, also referred to here as a substrate 201 .
  • a number of proximity gettering regions 202 are located near to a number of device regions 203 such that unwanted impurities can travel a short distance from the device regions 203 to the gettering regions 202 , even with modern low temperature processes.
  • the gettering region 202 includes a number of precisely formed and located voids 204 .
  • the present invention is not limited to gettering regions having the illustrated pattern, size or shape of voids.
  • the voids create defects that are highly chemically reactive and serve to getter impurities from the device region 203 .
  • FIG. 3 illustrates a transistor formed in a device region proximate to a gettering region with precisely formed voids at precise locations, according to various embodiments of the present invention.
  • the illustrated transistor 305 is fabricated over a proximity gettering region 302 .
  • the gettering region 302 has a predetermined and precise arrangement of precisely formed voids 304 .
  • a gate oxide 306 is formed on the substrate 301 , and a gate is formed over the gate oxide.
  • First and second diffusion regions 308 and 309 are formed.
  • a transistor channel region 310 is formed between the first and second diffusion regions 308 and 309 .
  • Other devices such as capacitors and diodes, can be formed in device regions proximate to a gettering region.
  • These gettering regions and device regions can be formed in both bulk and semiconductor-on-insulator (SOI) technology. Furthermore, these gettering regions can be used to getter both strained and unstrained device regions.
  • SOI semiconductor-on-insulator
  • the precisely-determined arrangement of voids provides the gettering region with voids that are more uniformly spaced and with a majority of voids that are closed voids.
  • the uniformity, density, and space symmetry of the voids in the gettering region is precisely determined by controlling the diameter, depth and position of an initial arrangement of cylindrical holes formed through a surface of a solid (e.g. a surface of a semiconductor wafer).
  • the holes have a generally-elongated shape extending into the volume away from the surface.
  • the holes have a generally cylindrical shape. The present subject matter is not so limited, however.
  • the voids in the gettering region generate defects that getter impurities from the device region.
  • the internal surfaces of the voids have numerous dangling bonds, and thus are highly chemically reactive which serves to getter impurities from the device region.
  • various embodiments for voids and voids patterns to have a large surface to volume ratio to increase the gettering of impurities.
  • the precisely-determined arrangement of voids provides the semiconductor wafer with a predictable mechanical failure for a given force.
  • the precisely-determined arrangement of voids provides the semiconductor wafer with an anisotropic stiffness.
  • holes When a solid is heated to a higher temperature, a solid with a hole that is beyond a critical length ( ⁇ c ) becomes unstable.
  • ⁇ c critical length
  • the holes are referred to as cylindrical holes.
  • the cylindrical hole is transformed into one or more empty spheres formed along the cylinder axis.
  • the number (N) of spheres formed depends on the length (L) and radius (R C ) of the cylinder.
  • Two models of diffusion are the surface diffusion model and the pure volume diffusion model. With respect to the surface diffusion model, for example, the relation between the cylinder length (L), cylinder radius (R C ), and number of spheres (N) is expressed by the following equation: 8.89 ⁇ R C ⁇ N ⁇ L ⁇ 8.89 ⁇ R C ⁇ ( N +1). (1) Equation (1) predicts that no empty spheres will form if L ⁇ 8.89 ⁇ R C .
  • the pure volume diffusion model provides similar results, with slightly different constants. For example, depending on the exact magnitude of the diffusion parameters, ⁇ C can vary from 9.02 ⁇ R C to 12.96 ⁇ R C .
  • ⁇ C can vary from 9.02 ⁇ R C to 12.96 ⁇ R C .
  • the diffusion model is capable of being determined by experiment. The remainder of this disclosure uses the surface diffusion model.
  • One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to apply this disclosure to another diffusion model.
  • Various shaped empty spaces or voids such as sphere-shaped voids, pipe-shaped voids, and plate-shaped voids are capable of being formed under the surface of a semiconductor substrate or wafer with a well-defined melting temperature.
  • the shape of the empty spaces formed during the annealing conditions depends on the size, number and spacing of the cylindrical holes that are initially formed at a lower temperature.
  • Various predetermined arrangements of empty spaces or voids are capable of being formed under the surface of a semiconductor substrate or wafer with a well-defined melting temperature. For example, an appropriately-sized deep trench in a material with a well-defined melting temperature is transformed into empty spheres along the axis of the original trench at an annealing temperature within a predetermined a range below the melting temperature. The empty spheres are uniformly sized and spaced. Other predetermined arrangements are provided below.
  • FIGS. 4A-4F illustrate a process to form a sphere-shaped empty space in a gettering region, according to various embodiments of the present invention.
  • a cylindrical hole 411 is formed through the surface 412 of a semiconductor volume where at least part of the volume forms a gettering region 402 .
  • the term hole refers to a void that extends from a surface of the volume into the solid material and that is defined by the solid material.
  • the semiconductor volume 402 is heated (annealed) and undergoes the transformation illustrated in FIGS. 4B through 4F .
  • the desired annealing temperature is dependent on the well-defined melting temperature of the semiconductor material.
  • the result of the surface transformation process is an empty sphere 413 formed below the surface 412 of the semiconductor volume 402 .
  • the center-to-center spacing (D NT ) between the initial cylindrical holes will satisfy the following equation: 2 ⁇ R C ⁇ D NT ⁇ 3.76 R C . (4) Satisfying this equation prevents the adjacent initial cylindrical holes from touching, yet allows the adjacent surface-transformed spheres to combine and form pipe and plate empty spaces, as shown in FIGS. 5A-5C and FIGS. 6A-6B and described below.
  • FIGS. 5A-5C illustrate a process to form a pipe-shaped empty space in a gettering region, according to various embodiments of the present invention.
  • a linear array of cylindrical holes 511 is formed through a surface 512 of a semiconductor volume where at least part of the volume forms a gettering region 502 .
  • the cylindrical holes 511 have a center-to-center spacing (D NT ) as calculated using equation (4).
  • the semiconductor material 502 is heated (annealed) and undergoes the transformation illustrated in FIGS. 5B through 5C .
  • the result of the surface transformation process is an empty pipe-shaped void 514 formed below the surface 512 of the semiconductor volume 502 .
  • FIGS. 6A-6B illustrate a process to form a plate-shaped empty space in a gettering region, according to various embodiments of the present invention.
  • a two-dimensional array of cylindrical holes 611 is formed in a surface 612 of a semiconductor volume where at least part of the volume forms a gettering region 602 .
  • the cylindrical holes 611 have a center-to-center spacing (D NT ) as calculated using equation (4).
  • the material 602 is heated (annealed) and undergoes the transformation illustrated in FIGS. 6B .
  • the result of the surface transformation process is an empty plate-shaped void 615 formed below the surface 612 of the volume of material 602 .
  • the voids are formed in a gettering region using surface transformation.
  • a precisely-determined arrangement of voids is formed using surface transformation to provide a large interior void surface to volume ratio and to provide a desired distribution of the voids throughout the gettering region.
  • the voids in the gettering region include nano-sized voids (“nano-voids”).
  • the present subject matter forms a precisely-determined arrangement of voids using surface transformation to provide a cellular material with a predictable mechanical failure for a given force.
  • the present subject matter forms a precisely-determined arrangement of voids using surface transformation to provide a cellular material with an anisotropic stiffness.
  • the size, shape and spacing of empty spaces is controlled by the diameter, depth and spacing of holes (or trenches) initially formed in a semiconductor material that has a defined melting temperature.
  • Empty spaces or voids are formed after annealing the material in a temperature range below and near the defined melting temperature.
  • the empty spaces or voids are capable of being formed with a spherical shape, a pipe shape, plate shape, various combinations of these shape types, and/or various dimensions for the various shape type and combinations of shape type.
  • the volume of air incorporated in the surface transformed empty spaces is equal to the volume of air within the initial starting pattern of cylindrical holes. Thus, the surface transformed empty spaces do not cause additional stress in the material or a tendency for the material to crack.
  • the surface of the semiconductor volume will be smooth after the surface transformed empty spaces are formed if the initial cylinder length (L) is equal to an integer of a critical length ( ⁇ c ) such as 1 ⁇ c to form one sphere, 2 ⁇ c to form two spheres, 3 ⁇ c to form three spheres, etc. If the cylinder length (L) is not equal to an integer of a critical length ( ⁇ c ), then the surface will have dimples caused by air in the cylinder attributable to the length beyond an integer of a critical length ( ⁇ c ). That is, for a given length L and ⁇ c , the number of spheres formed is the integer of L/ ⁇ c , and the remainder of L/ ⁇ c contributes to the dimples on the surface.
  • a critical length ⁇ c
  • FIGS. 7A-7E illustrate the formation of empty spheres in a gettering region from initial cylindrical holes with the same radii and with varying length, according to various embodiments of the present invention.
  • Initial cylindrical holes are represented using dashed lines 711 .
  • These initial cylindrical holes 711 have the same radius (R C ) and are drilled or otherwise formed to different depths as represented by FIGS. 7A, 7B , 7 C, 7 D and 7 E.
  • the resulting surface-transformed spheres 713 are illustrated with a solid line, as are the surface dimples 716 that form when the cylindrical hole depth is not an integer multiple of ⁇ C .
  • These surface dimples can be removed using a simple polishing process to leave a smooth surface with uniform and closed spherical voids within the material.
  • a crystalline semiconductor can be formed over the polished gettering region for use in fabricating semiconductor devices. The vertical position and number of the spherical voids is determined by the depth of the initial cylindrical holes.
  • the gettering region of the semiconductor substrate is formed by appropriately spacing the initially-formed holes such that, upon annealing the semiconductor material to provide the surface transformation process, the resulting voids are uniformly spaced (or approximately uniformly spaced) throughout the gettering region.
  • the uniformly spaced voids provide the gettering region with the ability to getter a device region with more uniformity. Smaller voids provide more gettering uniformity. With more predictable gettering of device regions, the performance of the devices formed therein is more predictable, thus providing better yield.
  • a gettering region with voids it is desirable to provide a gettering region with voids to provide a high internal void surface to volume ratio to improve gettering.
  • the interior void surfaces have dangling bonds that are highly chemically reactive, and are useful to getter impurities.
  • FIG. 8 illustrates a transformation formed stack of empty plates 815 in a gettering region 802 , according to various embodiments of the present invention.
  • the illustrated filling factor, f is approximately equal to 0.78, which provides a relatively high porosity, a relatively low density, and a relatively high internal void surface to volume ratio.
  • the surface transformation produces a vertical stack of empty plates in the materials. The number of empty plates formed depends on the length of the holes.
  • Various embodiments of the vertical stack includes one ore more empty plates. From equation (6), it is determined that the thickness T P of the empty plate has a maximum value of 6.95 ⁇ R C when D NT is near the minimum allowed value of 2 ⁇ R C as inferred from equation (4). From equation (3), the center-to-center spacing ( ⁇ ) of empty plates is 8.89 ⁇ R C . It can be calculated that f ⁇ 0.78.
  • a plurality of space group symmetries of empty spheres of equal size are formed in a solid material.
  • FIG. 9 illustrates fourteen representative unit cells of space lattices which the voids in the gettering region can form, according to various embodiments of the present invention.
  • a 0 lattice constant
  • FIG. 9 illustrates fourteen representative unit cells of space lattices which the voids in the gettering region can form, according to various embodiments of the present invention.
  • Each void in the unit cell can be the same shape (e.g. sphere-shaped, plate-shaped or pipe-shaped voids).
  • the unit cell includes different combinations of sphere-shaped, plate-shaped, or pipe-shaped voids.
  • FIG. 10 illustrates a void pattern in a gettering region arranged to form the cubic P unit cell shown among the fourteen representative unit cells of FIG. 9 .
  • a defined set of cylindrical holes are drilled or otherwise formed into the gettering region to form empty spheres 1013 of the same radius in the solid material at each of the illustrated unit cell lattice positions.
  • the formation of one unit cell in the x-y plane and n unit cells in the z direction is discussed. Additional unit cells in the x-y planes are formed by repeatedly translating the hole pattern for the unit cell in the x and y directions.
  • FIGS. 11A-11B illustrate a process for forming a cubic P lattice of spherical empty spaces, according to various embodiments of the present invention.
  • the four cylindrical holes 1111 A, 1111 B, 1111 C and 1111 D are spaced apart along the x and y axes at a distance a 0 .
  • the solid material is annealed near its melting temperature to form sphere-shaped empty spaces 1113 A, 1113 B, 1113 C, 1113 D, 1113 E, 1113 F, 1113 G and 1113 H by surface transformation at desired sites of the cubic P unit cell as is shown in FIG. 11B .
  • each primitive lattice in FIG. 6 can be formed to have equal sized empty spheres at each lattice site by forming in the Z direction an appropriate pattern of cylindrical holes of the same diameter in the x-y plane. The prescribed depths for these unit cells will generally be different.
  • space lattices having more than one size of empty spheres in the unit cell are formed by forming initial cylindrical holes of more than one radius. In various embodiments, the holes are formed in more than one direction. The number of surface transformation annealing steps used to form the space lattice depends on the structure to be formed. A method to form a simple illustrative structural unit of empty spheres is described below.
  • FIGS. 12A-12D illustrate a process for forming a simple unit of empty spheres having two radii in a gettering region, according to various embodiments of the present invention.
  • the process to form the above-described structure is illustrated in FIGS. 12A, 12B , 12 C and 12 D.
  • FIG. 12D Another method for forming the structure in FIG. 12D involves forming the cellular material in various deposition layers and forming the voids using a surface transformation process (i.e. hole formation and annealing) for each layer before a successive layer of material is deposited.
  • a surface transformation process i.e. hole formation and annealing
  • the structure illustrated in FIG. 12D is formed by a first deposition process, a first surface transformation process, a second deposition process, a second surface transformation process, a third deposition process, a third surface transformation process, a fourth deposition process, and a fourth surface transformation process.
  • Each surface transformation step includes hole formation and annealing.
  • the hole formation pattern is calculated to achieve the desired spacing of resulting voids, both between and within layers, after the layer is annealed.
  • a cellular material can include a number of sphere-shaped voids, a number of pipe-shaped voids, a number of plate-shaped voids, and various combinations of sphere-shaped void(s), pipe-shaped void(s), and plate-shaped void(s).
  • each stack of voids can include various shapes.
  • the precisely-determined arrangement of empty spaces is determined by the position, depth and diameter of the holes formed prior to the annealing process.
  • FIG. 13 illustrates a process for forming semiconductor devices, according to various embodiments of the present invention.
  • voids are precisely formed and are located to getter a device region.
  • subsequent semiconductor fabrication processes are performed, As represented at 1322 , these subsequent semiconductor fabrication processes include forming a semiconductor device in a device region.
  • An example of a semiconductor device is a transistor.
  • these semiconductor processes include depositing a semiconductor such as crystalline silicon on the gettering region, and forming a transistor using the crystalline silicon.
  • the voids are formed in a crystalline semiconductor volume, and the devices are formed using the crystalline semiconductor above the voids.
  • the voids are formed in a crystalline semiconductor volume, and the devices are formed using the crystalline semiconductor adjacent to the voids.
  • FIG. 14 illustrates a process for precisely forming voids in a substrate located to getter a device region as performed in the process for forming semiconductor devices of FIG. 13 .
  • the illustrated process 1420 generally corresponds to the 1320 in FIG. 13 .
  • holes are formed to extend from a substrate surface and into a semiconductor substrate at 1423 .
  • the holes have a predetermined size and shape, and are formed in a predetermined location or pattern of locations in the substrate.
  • the holes have a generally cylindrical shape.
  • the substrate is annealed to form predetermined voids in the substrate.
  • the substrate has a well-defined melting temperature, and the annealing temperature is slightly below the melting temperature.
  • the voids can include sphere-shape voids, a pipe-shape voids and/or plate-shaped voids.
  • the present subject matter provides the ability to form gettering regions with a precisely-determined arrangement of precisely-formed voids using surface transformation.
  • the precisely-determined arrangement of precisely-formed voids include uniformly spaced and closed voids that provide the gettering region with uniform gettering characteristics and with a large internal surface to volume ratio to provide a large number of uniformly distributed dangling bonds (defects in the crystalline structure) in proximity to a device region to effectively getter the device region.
  • semiconductor devices are cable of being precisely fabricated.
  • FIG. 15 is a simplified block diagram of a high-level organization of a memory device, according to various embodiments of the present invention.
  • the illustrated memory device 1530 includes a memory array 1531 and read/write control circuitry 1532 to perform operations on the memory array via communication line(s) 1533 .
  • the illustrated memory device 1530 may be a memory card or a memory module such as a single inline memory module (SIMM) and dual inline memory module (DIMM).
  • SIMM single inline memory module
  • DIMM dual inline memory module
  • the memory array 1531 includes a number of memory cells 1534 .
  • the memory cells in the array are arranged in rows and columns.
  • word lines 1535 connect the memory cells in the rows
  • bit lines 1536 connect the memory cells in the columns.
  • the read/write control circuitry 1532 includes word line select circuitry 1537 , which functions to select a desired row.
  • the read/write control circuitry 1532 further includes bit line select circuitry 1538 , which functions to select a desired column.
  • FIG. 16 is a simplified block diagram of a high-level organization of an electronic system, according to various embodiments of the present invention.
  • the system 1640 is a computer system, a process control system or other system that employs a processor and associated memory.
  • the electronic system 1640 has functional elements, including a processor or arithmetic/logic unit (ALU) 1641 , a control unit 1642 , a memory device unit 1643 (such as illustrated at 1530 in FIG. 15 ) and an input/output (I/O) device 1644 .
  • ALU arithmetic/logic unit
  • the control unit 1642 coordinates all operations of the processor 1641 , the memory device 1643 and the I/O devices 1644 by continuously cycling through a set of operations that cause instructions to be fetched from the memory device 1643 and executed.
  • the memory device 1643 includes, but is not limited to, random access memory (RAM) devices, read-only memory (ROM) devices, and peripheral devices such as a floppy disk drive and a compact disk CD-ROM drive.
  • RAM random access memory
  • ROM read-only memory
  • peripheral devices such as a floppy disk drive and a compact disk CD-ROM drive.
  • the illustration of the system 1640 is intended to provide a general understanding of one application for the structure and circuitry, and is not intended to serve as a complete description of all the elements and features of an electronic system using proximity gettering regions according to the various embodiments of the present invention.
  • an electronic system can be fabricated in single-package processing units, or even on a single semiconductor chip, in order to reduce the communication time between the processor and the memory device.
  • Applications containing a gettering region as described in this disclosure include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems.
  • Various embodiments disclosed herein getter a semiconductor wafer by precisely forming voids, such as nano-voids, at desired locations in the wafers. Various embodiments form an even distribution of voids across the wafer below device regions. In various embodiments, precisely-formed gettering void patterns are formed proximate to selected regions where devices are fabricated on the semiconductor wafer. Various embodiments precisely form the void patterns below device regions. Numerous dangling bonds are present at the internal surfaces of the voids such that these internal surfaces are highly chemically reactive. Thus, various embodiments form the voids and void patterns to have the greatest surface to volume ratio to increase the gettering of impurities.

Abstract

One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of a plurality of holes is formed in the semiconductor wafer through a surface of the wafer. The wafer is annealed such that the wafer undergoes a surface transformation to transform the arrangement of the plurality of holes into a predetermined arrangement of at least one empty space of a predetermined size within the wafer to form the gettering site. One aspect relates to a semiconductor wafer. In various embodiments, the wafer includes at least one device region, and at least one gettering region located proximate to the at least one device region. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids that are formed within the wafer using a surface transformation process. Other aspects and embodiments are provided herein.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional under 37 C.F.R. 1.153(b) of U.S. application Ser. No. 10/623,794, filed on Jul. 21, 2003.
  • This application is related to the following commonly assigned U.S. patent applications which are herein incorporated by reference in their entirety: “Cellular Materials Formed Using Surface Transformation,” application Ser. No. 10/382,246, filed Mar. 5, 2003; “Gettering of Silicon On Insulator Using Relaxed Silicon Germanium Epitaxial Proximity Layers,” application Ser. No. 10/443,337, filed May 21, 2003; and “Wafer Gettering Using Relaxed Silicon Germanium Epitaxial Proximity Layers,” application Ser. No. 10/443,339, filed May 21, 2003.
  • TECHNICAL FIELD
  • This disclosure relates generally to integrated circuits, and more particularly, to strained semiconductor structures.
  • BACKGROUND
  • Unwanted crystalline defects and impurities can be introduced during crystal growth or subsequent wafer fabrication processes. These defect and impurities can degrade device characteristics and overall yield. Gettering has been described as a process for moving contaminants and/or defects in a semiconductor into its bulk and away from its top surface to create a denuded zone cleared from contaminants and/or defects. Preferably, devices are built in the denuded zone.
  • Historically, extrinsic backside gettering was used to getter silicon wafers. Various extrinsic backside gettering processes involve damaging the backside of the wafer mechanically or by implanting argon, germanium, hydrogen or other implants, or providing a gettering layer on the backside of the wafer using a phophorosilicate glass or oxide backside layer, a polysilicon backside layer, and a silicon germanium (SiGe) backside epitaxial layer. Subsequently, “intrinsic” gettering was developed, which employed oxygen precipitation and “bulk microdefects” precipitated into the bulk of the wafer after the surface was “denuded” of oxygen. The precipitation process, the gettering effects, and the electrical characterization of defects and gettering silicon wafers have been investigated. Recently, intrinsic gettering modifications have been developed, including neutron irradiation, high boron doping, nitrogen doping, and the use of magnetic fields during crystal growth.
  • These gettering processes depend on the diffusion of unwanted impurities over significant distances from desired device regions to the gettering sites. However, modem low temperature processes have small thermal budgets, and do not afford an opportunity for significant diffusion of dopants and/or unwanted impurities. Thus, it is desirable to reduce the distance between the gettering sites and the device area. It has been previously proposed to implant various impurities in proximity to the device areas, to co-implant oxygen and silicon to form a gettering layer in close proximity to the device area, to implant helium to form cavities close to the device areas which getter impurities, and to getter material in trench isolation areas in close proximity to the device areas.
  • Implanting helium forms cavities that function to getter impurities. This helium implantation technique has been proposed to getter both bulk and silicon-on-insulator devices. However, the location and density of these cavities formed by implanting helium is random. One problem associated with the random location and density of cavities is that the effectiveness of the gettering unwanted impurities from the desired device regions is inconsistent. Other problems associated with the random location and density of cavities involves the varying strain in the substrate and the varying ability of the substrate to withstand mechanical strain. The inconsistent effectiveness of gettering, the inconsistent strain and the inconsistent ability to withstand strain can negatively affect the ability to precisely form devices as the semiconductor industry strives to fabricate smaller and thinner devices.
  • SUMMARY
  • The above mentioned problems are addressed and will be understood by reading and studying this specification. Various aspects and embodiments of the present invention getter a semiconductor wafer by precisely forming voids, such as nano-sized voids, at desired locations in the wafers. Thus, precisely-formed gettering void patterns are formed in selected regions below where devices are fabricated on semiconductor wafers. Numerous dangling bonds are present at the internal surfaces of the voids such that these internal surfaces are highly chemically reactive. Thus, various embodiments form the voids and void patterns to have a large surface to volume ratio to increase gettering of impurities.
  • One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of a plurality of holes is formed in the semiconductor wafer through a surface of the wafer. The wafer is annealed such that the wafer undergoes a surface transformation to transform the arrangement of the plurality of holes into a predetermined arrangement of at least one empty space of a predetermined size within the wafer to form the gettering site.
  • One aspect relates to a semiconductor wafer. In various embodiments, the wafer includes at least one device region, and at least one gettering region located proximate to the at least one device region. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids that are formed within the wafer using a surface transformation process. Other aspects and embodiments are provided herein.
  • This Summary is an overview of some of the teachings of the present application and not intended to be an exclusive or exhaustive treatment of the present subject matter. Further details are found in the detailed description and appended claims. Other aspects will be apparent to persons skilled in the art upon reading and understanding the following detailed description and viewing the drawings that form a part thereof, each of which are not to be taken in a limiting sense. The scope of the present invention is defined by the appended claims and their legal equivalents.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates a semiconductor structure having a gettering region with precisely formed voids at precise locations, according to various embodiments of the present invention.
  • FIG. 2 illustrates a semiconductor structure having a gettering region with precisely formed voids at precise locations, according to various embodiments of the present invention.
  • FIG. 3 illustrates a transistor formed in a device region proximate to a gettering region with precisely formed voids at precise locations, according to various embodiments of the present invention.
  • FIGS. 4A-4F illustrate a process to form a sphere-shaped empty space in a gettering region, according to various embodiments of the present invention.
  • FIGS. 5A-5C illustrate a process to form a pipe-shaped empty space in a gettering region, according to various embodiments of the present invention.
  • FIGS. 6A-6B illustrate a process to form a plate-shaped empty space in a gettering region, according to various embodiments of the present invention.
  • FIGS. 7A-7E illustrate the formation of empty spheres in a gettering region from initial cylindrical holes with the same radii and with varying length, according to various embodiments of the present invention.
  • FIG. 8 illustrates a transformation formed stack of empty plates in a gettering region, according to various embodiments of the present invention.
  • FIG. 9 illustrates fourteen representative unit cells of space lattices which the voids in the gettering region can form, according to various embodiments of the present invention.
  • FIG. 10 illustrates a void pattern in a gettering region arranged to form the cubic P unit cell shown among the fourteen representative unit cells of FIG. 9.
  • FIGS. 11A-11B illustrate a process for forming a cubic P lattice of spherical empty spaces, according to various embodiments of the present invention.
  • FIGS. 12A-12D illustrate a process for forming a simple unit of empty spheres having two radii in a gettering region, according to various embodiments of the present invention.
  • FIG. 13 illustrates a process for forming semiconductor devices, according to various embodiments of the present invention.
  • FIG. 14 illustrates a process for precisely forming voids in a substrate located to getter a device region as performed in the process for forming semiconductor devices of FIG. 13.
  • FIG. 15 is a simplified block diagram of a high-level organization of a memory device, according to various embodiments of the present invention.
  • FIG. 16 is a simplified block diagram of a high-level organization of an electronic system, according to various embodiments of the present invention.
  • DETAILED DESCRIPTION
  • The following detailed description refers to the accompanying drawings which show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. The various embodiments are not necessarily mutually exclusive as aspects of one embodiment can be combined with aspects of another embodiment. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. In the following description, the terms wafer and substrate are interchangeably used to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art. The terms “horizontal” and “vertical”, as well as prepositions such as “on”, “over” and “under” are used in relation to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. References to “an”, “one”, or “various” embodiments in this disclosure are not necessarily to the same embodiment, and such references contemplate more than one embodiment. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
  • Aspects of the present invention precisely form voids at desired location using a surface transformation process to getter semiconductor wafers. Various embodiments precisely form patterns of nano-voids (voids having a diameter on the order of a nanometer) as a proximity gettering region to effectively and consistently getter impurities from device regions.
  • FIG. 1 illustrates a semiconductor structure having a gettering region with precisely formed voids at precise locations, according to various embodiments of the present invention. The illustrated structure 100 includes a semiconductor wafer, also referred to here as a substrate 101. A proximity gettering region 102 is located near to a device region 103 such that unwanted impurities can travel a short distance from the device region 103 to the gettering region 102, even with modern low temperature processes. The gettering region 102 includes a number of precisely formed and located voids 104 formed by surface transformation. Surface transformation is described in detail below. The present invention is not limited to gettering regions having a particular pattern, shape or size of voids. In various embodiments, the device region 103 includes crystalline silicon. Semiconductor devices, such as transistors, are fabricated in the crystalline silicon. Other crystalline semiconductor materials can be used to form the device region 103. Thus, it is desired to getter unwanted impurities from the device region. The voids 104 in the gettering region 102 generate defects that getter impurities from the device region 103. The internal surfaces of the voids have numerous dangling bonds, and thus are highly chemically reactive, which serves to getter impurities from the device region 103.
  • FIG. 2 illustrates a semiconductor structure having a gettering region with precisely formed voids at precise locations, according to various embodiments of the present invention. The illustrated structure 200 includes a semiconductor wafer, also referred to here as a substrate 201. A number of proximity gettering regions 202 are located near to a number of device regions 203 such that unwanted impurities can travel a short distance from the device regions 203 to the gettering regions 202, even with modern low temperature processes. The gettering region 202 includes a number of precisely formed and located voids 204. The present invention is not limited to gettering regions having the illustrated pattern, size or shape of voids. The voids create defects that are highly chemically reactive and serve to getter impurities from the device region 203.
  • FIG. 3 illustrates a transistor formed in a device region proximate to a gettering region with precisely formed voids at precise locations, according to various embodiments of the present invention. The illustrated transistor 305 is fabricated over a proximity gettering region 302. The gettering region 302 has a predetermined and precise arrangement of precisely formed voids 304. A gate oxide 306 is formed on the substrate 301, and a gate is formed over the gate oxide. First and second diffusion regions 308 and 309 are formed. A transistor channel region 310 is formed between the first and second diffusion regions 308 and 309. Other devices, such as capacitors and diodes, can be formed in device regions proximate to a gettering region. These gettering regions and device regions can be formed in both bulk and semiconductor-on-insulator (SOI) technology. Furthermore, these gettering regions can be used to getter both strained and unstrained device regions.
  • In various embodiments, the precisely-determined arrangement of voids provides the gettering region with voids that are more uniformly spaced and with a majority of voids that are closed voids. The uniformity, density, and space symmetry of the voids in the gettering region is precisely determined by controlling the diameter, depth and position of an initial arrangement of cylindrical holes formed through a surface of a solid (e.g. a surface of a semiconductor wafer). In various embodiments, the holes have a generally-elongated shape extending into the volume away from the surface. In various embodiments, the holes have a generally cylindrical shape. The present subject matter is not so limited, however.
  • The voids in the gettering region generate defects that getter impurities from the device region. The internal surfaces of the voids have numerous dangling bonds, and thus are highly chemically reactive which serves to getter impurities from the device region. Thus, various embodiments for voids and voids patterns to have a large surface to volume ratio to increase the gettering of impurities. In various embodiments, the precisely-determined arrangement of voids provides the semiconductor wafer with a predictable mechanical failure for a given force. In various embodiments, the precisely-determined arrangement of voids provides the semiconductor wafer with an anisotropic stiffness.
  • When a solid is heated to a higher temperature, a solid with a hole that is beyond a critical length (λc) becomes unstable. For the purposes of the analysis provided below, the holes are referred to as cylindrical holes. Upon reading and comprehending this disclosure, one of ordinary skill in the art will understand that holes which are not geometrically cylindrical can be used in a surface transformation process, and further will understand how to form a predetermined arrangement of voids using holes that are not geometrically cylindrical.
  • The cylindrical hole is transformed into one or more empty spheres formed along the cylinder axis. The number (N) of spheres formed depends on the length (L) and radius (RC) of the cylinder. Two models of diffusion are the surface diffusion model and the pure volume diffusion model. With respect to the surface diffusion model, for example, the relation between the cylinder length (L), cylinder radius (RC), and number of spheres (N) is expressed by the following equation:
    8.89×R C ×N≦L<8.89×R C×(N+1).  (1)
    Equation (1) predicts that no empty spheres will form if L<8.89×RC. Each empty sphere that forms has a radius (RS) expressed by the following equation:
    R S=1.88×R C.  (2)
    If the cylinder has sufficient length L to form two spheres, the center-to-center spacing between the spheres corresponds to the critical length (λC) and is provided by the equation:
    λC=8.89×R C.  (3)
    The pure volume diffusion model provides similar results, with slightly different constants. For example, depending on the exact magnitude of the diffusion parameters, λC can vary from 9.02×RC to 12.96×RC. One of ordinary skill in the art will understand, upon reading and understanding this disclosure, that the diffusion model is capable of being determined by experiment. The remainder of this disclosure uses the surface diffusion model. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to apply this disclosure to another diffusion model.
  • Various shaped empty spaces or voids such as sphere-shaped voids, pipe-shaped voids, and plate-shaped voids are capable of being formed under the surface of a semiconductor substrate or wafer with a well-defined melting temperature. The shape of the empty spaces formed during the annealing conditions depends on the size, number and spacing of the cylindrical holes that are initially formed at a lower temperature.
  • Various predetermined arrangements of empty spaces or voids are capable of being formed under the surface of a semiconductor substrate or wafer with a well-defined melting temperature. For example, an appropriately-sized deep trench in a material with a well-defined melting temperature is transformed into empty spheres along the axis of the original trench at an annealing temperature within a predetermined a range below the melting temperature. The empty spheres are uniformly sized and spaced. Other predetermined arrangements are provided below.
  • FIGS. 4A-4F illustrate a process to form a sphere-shaped empty space in a gettering region, according to various embodiments of the present invention. A cylindrical hole 411 is formed through the surface 412 of a semiconductor volume where at least part of the volume forms a gettering region 402. As used here, the term hole refers to a void that extends from a surface of the volume into the solid material and that is defined by the solid material. The semiconductor volume 402 is heated (annealed) and undergoes the transformation illustrated in FIGS. 4B through 4F. One of ordinary skill in the art would understand, upon reading and comprehending this disclosure, that the desired annealing temperature is dependent on the well-defined melting temperature of the semiconductor material. The result of the surface transformation process is an empty sphere 413 formed below the surface 412 of the semiconductor volume 402.
  • In order to form a single sphere, which holds true for forming a single pipe (FIGS. 5A-5C) or plate (FIGS. 6A-6B), the length (L) and radius (RC) of the cylindrical holes are chosen such that equation (1) with N=1 is satisfied. A vertical stacking of N empty spaces results if the length of the cylindrical holes is such that equation (1) is satisfied.
  • In order for single surface-transformed spheres to combine with other surface-transformed spheres, the center-to-center spacing (DNT) between the initial cylindrical holes will satisfy the following equation:
    2×R C <D NT<3.76R C.  (4)
    Satisfying this equation prevents the adjacent initial cylindrical holes from touching, yet allows the adjacent surface-transformed spheres to combine and form pipe and plate empty spaces, as shown in FIGS. 5A-5C and FIGS. 6A-6B and described below.
  • FIGS. 5A-5C illustrate a process to form a pipe-shaped empty space in a gettering region, according to various embodiments of the present invention. A linear array of cylindrical holes 511 is formed through a surface 512 of a semiconductor volume where at least part of the volume forms a gettering region 502. The cylindrical holes 511 have a center-to-center spacing (DNT) as calculated using equation (4). The semiconductor material 502 is heated (annealed) and undergoes the transformation illustrated in FIGS. 5B through 5C. The result of the surface transformation process is an empty pipe-shaped void 514 formed below the surface 512 of the semiconductor volume 502. The radius (RP) of the pipe-shaped void 514 is provided by the following equation: R p = 8.86 × R C 3 D NT . ( 5 )
  • FIGS. 6A-6B illustrate a process to form a plate-shaped empty space in a gettering region, according to various embodiments of the present invention. A two-dimensional array of cylindrical holes 611 is formed in a surface 612 of a semiconductor volume where at least part of the volume forms a gettering region 602. The cylindrical holes 611 have a center-to-center spacing (DNT) as calculated using equation (4). The material 602 is heated (annealed) and undergoes the transformation illustrated in FIGS. 6B. The result of the surface transformation process is an empty plate-shaped void 615 formed below the surface 612 of the volume of material 602. The thickness (TP) of a plate 320 is given by the following equation: T p = 27.83 × R C 3 D NT 2 ( 6 )
  • The voids are formed in a gettering region using surface transformation. In various embodiments, a precisely-determined arrangement of voids is formed using surface transformation to provide a large interior void surface to volume ratio and to provide a desired distribution of the voids throughout the gettering region. In various embodiments, the voids in the gettering region include nano-sized voids (“nano-voids”). In various embodiments, the present subject matter forms a precisely-determined arrangement of voids using surface transformation to provide a cellular material with a predictable mechanical failure for a given force. In various embodiments, the present subject matter forms a precisely-determined arrangement of voids using surface transformation to provide a cellular material with an anisotropic stiffness.
  • The size, shape and spacing of empty spaces is controlled by the diameter, depth and spacing of holes (or trenches) initially formed in a semiconductor material that has a defined melting temperature. Empty spaces or voids are formed after annealing the material in a temperature range below and near the defined melting temperature. The empty spaces or voids are capable of being formed with a spherical shape, a pipe shape, plate shape, various combinations of these shape types, and/or various dimensions for the various shape type and combinations of shape type. The volume of air incorporated in the surface transformed empty spaces is equal to the volume of air within the initial starting pattern of cylindrical holes. Thus, the surface transformed empty spaces do not cause additional stress in the material or a tendency for the material to crack.
  • The surface of the semiconductor volume will be smooth after the surface transformed empty spaces are formed if the initial cylinder length (L) is equal to an integer of a critical length (λc) such as 1×λc to form one sphere, 2×λc to form two spheres, 3×λc to form three spheres, etc. If the cylinder length (L) is not equal to an integer of a critical length (λc), then the surface will have dimples caused by air in the cylinder attributable to the length beyond an integer of a critical length (λc). That is, for a given length L and λc, the number of spheres formed is the integer of L/λc, and the remainder of L/λc contributes to the dimples on the surface.
  • FIGS. 7A-7E illustrate the formation of empty spheres in a gettering region from initial cylindrical holes with the same radii and with varying length, according to various embodiments of the present invention. Initial cylindrical holes are represented using dashed lines 711. These initial cylindrical holes 711 have the same radius (RC) and are drilled or otherwise formed to different depths as represented by FIGS. 7A, 7B, 7C, 7D and 7E. The resulting surface-transformed spheres 713 are illustrated with a solid line, as are the surface dimples 716 that form when the cylindrical hole depth is not an integer multiple of λC. These surface dimples can be removed using a simple polishing process to leave a smooth surface with uniform and closed spherical voids within the material. A crystalline semiconductor can be formed over the polished gettering region for use in fabricating semiconductor devices. The vertical position and number of the spherical voids is determined by the depth of the initial cylindrical holes.
  • In various embodiments of the present subject matter, the gettering region of the semiconductor substrate is formed by appropriately spacing the initially-formed holes such that, upon annealing the semiconductor material to provide the surface transformation process, the resulting voids are uniformly spaced (or approximately uniformly spaced) throughout the gettering region. The uniformly spaced voids provide the gettering region with the ability to getter a device region with more uniformity. Smaller voids provide more gettering uniformity. With more predictable gettering of device regions, the performance of the devices formed therein is more predictable, thus providing better yield.
  • In various embodiments, it is desirable to provide a gettering region with voids to provide a high internal void surface to volume ratio to improve gettering. The interior void surfaces have dangling bonds that are highly chemically reactive, and are useful to getter impurities.
  • FIG. 8 illustrates a transformation formed stack of empty plates 815 in a gettering region 802, according to various embodiments of the present invention. For example, the illustrated filling factor, f, is approximately equal to 0.78, which provides a relatively high porosity, a relatively low density, and a relatively high internal void surface to volume ratio. In the illustrated example, the surface transformation produces a vertical stack of empty plates in the materials. The number of empty plates formed depends on the length of the holes. Various embodiments of the vertical stack includes one ore more empty plates. From equation (6), it is determined that the thickness TP of the empty plate has a maximum value of 6.95×RC when DNT is near the minimum allowed value of 2×RC as inferred from equation (4). From equation (3), the center-to-center spacing (λ) of empty plates is 8.89×RC. It can be calculated that f≈0.78.
  • In various embodiments of the present subject matter, a plurality of space group symmetries of empty spheres of equal size are formed in a solid material.
  • FIG. 9 illustrates fourteen representative unit cells of space lattices which the voids in the gettering region can form, according to various embodiments of the present invention. For simplicity, only the cubic P unit cell of FIG. 9 with a lattice constant “a0” is discussed below. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to form void patterns for the other unit cells illustrated in FIG. 9. Each void in the unit cell can be the same shape (e.g. sphere-shaped, plate-shaped or pipe-shaped voids). In various embodiments, the unit cell includes different combinations of sphere-shaped, plate-shaped, or pipe-shaped voids.
  • FIG. 10 illustrates a void pattern in a gettering region arranged to form the cubic P unit cell shown among the fourteen representative unit cells of FIG. 9. A defined set of cylindrical holes are drilled or otherwise formed into the gettering region to form empty spheres 1013 of the same radius in the solid material at each of the illustrated unit cell lattice positions. For simplicity, the formation of one unit cell in the x-y plane and n unit cells in the z direction is discussed. Additional unit cells in the x-y planes are formed by repeatedly translating the hole pattern for the unit cell in the x and y directions. From equations (2) and (3), spheres are created with periodicity a0 in the Z direction by drilling or otherwise forming the holes in the Z direction such that the radius of the holes (RC) are represented by the following equation: R C = a 0 8.89 0.11 × a 0 . ( 7 )
    After surface transformation, the radius, RS of each formed empty sphere is: R S = 1.88 8.89 × a 0 0.212 × a 0 . ( 8 )
    In order to form n unit cells in the Z direction through surface transformation, the depth (Ln) of the initial cylinder in the Z direction is:
    L n=(n+1)×α0=(n+1)×8.99×R C.  (9)
    To form a single cubic P unit cell in the Z direction, n is set to 1 for the two deep arrangement of spheres such that the cylindrical holes are formed to the following hole depth:
    L 1=2×8.89×R C=2×α0.  (10)
  • FIGS. 11A-11B illustrate a process for forming a cubic P lattice of spherical empty spaces, according to various embodiments of the present invention. Referring to FIG. 11A, four cylindrical holes 1111A, 1111B, 1111C and 1111D of radius Rc=0.11×a0 are formed into the semiconductor volume 1102 from a surface 1112 to a depth L=2×a0. The four cylindrical holes 1111A, 1111B, 1111C and 1111D are spaced apart along the x and y axes at a distance a0. The solid material is annealed near its melting temperature to form sphere-shaped empty spaces 1113A, 1113B, 1113C, 1113D, 1113E, 1113F, 1113G and 1113H by surface transformation at desired sites of the cubic P unit cell as is shown in FIG. 11B.
  • One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that the unit cells of each primitive lattice in FIG. 6 can be formed to have equal sized empty spheres at each lattice site by forming in the Z direction an appropriate pattern of cylindrical holes of the same diameter in the x-y plane. The prescribed depths for these unit cells will generally be different.
  • In various embodiments, space lattices having more than one size of empty spheres in the unit cell are formed by forming initial cylindrical holes of more than one radius. In various embodiments, the holes are formed in more than one direction. The number of surface transformation annealing steps used to form the space lattice depends on the structure to be formed. A method to form a simple illustrative structural unit of empty spheres is described below.
  • FIGS. 12A-12D illustrate a process for forming a simple unit of empty spheres having two radii in a gettering region, according to various embodiments of the present invention. The desired structure has four empty spheres of radius RS=0.212×a0, and four empty spheres of radius RS′=½×RS=0.106×a0. All of the empty spheres have a closest center-to-center spacing of a0/2. The process to form the above-described structure is illustrated in FIGS. 12A, 12B, 12C and 12D.
  • In FIG. 12A, two cylindrical holes 1211A of radius, RC=0.11×a0 and of length L=2×a0 are formed in the Z direction. The solid material is annealed to effect surface transformation and form the four spheres 1213A with RS=0.212×a0, as shown in FIG. 12B.
  • In FIG. 12C, two cylindrical holes 1211B are drilled in the y-direction. These holes 1211B have a radius RC′=0.055a0, and a length L′=a0. Again the material is annealed to effect surface transformation and the four smaller empty spheres 1213B to form the desired structure shown in FIG. 12D. The second annealing step only effects the cylindrical holes since they are not energetically stable. The four previously formed larger empty spheres are stable since they were formed during the first annealing.
  • Another method for forming the structure in FIG. 12D involves forming the cellular material in various deposition layers and forming the voids using a surface transformation process (i.e. hole formation and annealing) for each layer before a successive layer of material is deposited. Using this method, the structure illustrated in FIG. 12D is formed by a first deposition process, a first surface transformation process, a second deposition process, a second surface transformation process, a third deposition process, a third surface transformation process, a fourth deposition process, and a fourth surface transformation process. Each surface transformation step includes hole formation and annealing. For each layer, the hole formation pattern is calculated to achieve the desired spacing of resulting voids, both between and within layers, after the layer is annealed.
  • One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that a number of void arrangements are capable of being formed, a number of void sizes are capable of being formed, and that various combinations of void arrangements and void sizes are capable of being formed. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that various different shapes of empty spaces can be formed, and that these various different shapes of empty spaces can be combined with other shapes of empty spaces. For example, a cellular material can include a number of sphere-shaped voids, a number of pipe-shaped voids, a number of plate-shaped voids, and various combinations of sphere-shaped void(s), pipe-shaped void(s), and plate-shaped void(s). One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that the various shapes can be stacked, and that various different shapes can be stacked together. For example, an arrangement of spheres can be stacked on top of an arrangement of plates. Additionally, each stack of voids can include various shapes. The precisely-determined arrangement of empty spaces is determined by the position, depth and diameter of the holes formed prior to the annealing process.
  • The figures presented and described above are useful to illustrate method aspects of the present subject matter. Some of these method aspects are described below. The methods described below are nonexclusive as other methods may be understood from the specification and the figures described above.
  • FIG. 13 illustrates a process for forming semiconductor devices, according to various embodiments of the present invention. At 1320, voids are precisely formed and are located to getter a device region. At 1321, subsequent semiconductor fabrication processes are performed, As represented at 1322, these subsequent semiconductor fabrication processes include forming a semiconductor device in a device region. An example of a semiconductor device is a transistor. In various embodiments, these semiconductor processes include depositing a semiconductor such as crystalline silicon on the gettering region, and forming a transistor using the crystalline silicon. In various embodiments, the voids are formed in a crystalline semiconductor volume, and the devices are formed using the crystalline semiconductor above the voids. In various embodiments, the voids are formed in a crystalline semiconductor volume, and the devices are formed using the crystalline semiconductor adjacent to the voids.
  • FIG. 14 illustrates a process for precisely forming voids in a substrate located to getter a device region as performed in the process for forming semiconductor devices of FIG. 13. The illustrated process 1420 generally corresponds to the 1320 in FIG. 13. In the illustrated embodiment, holes are formed to extend from a substrate surface and into a semiconductor substrate at 1423. The holes have a predetermined size and shape, and are formed in a predetermined location or pattern of locations in the substrate. In various embodiments, the holes have a generally cylindrical shape. At 1424, the substrate is annealed to form predetermined voids in the substrate. The substrate has a well-defined melting temperature, and the annealing temperature is slightly below the melting temperature. Depending on the size, shape and pattern of holes formed at 1423, the voids can include sphere-shape voids, a pipe-shape voids and/or plate-shaped voids.
  • The present subject matter provides the ability to form gettering regions with a precisely-determined arrangement of precisely-formed voids using surface transformation. In various embodiments, the precisely-determined arrangement of precisely-formed voids include uniformly spaced and closed voids that provide the gettering region with uniform gettering characteristics and with a large internal surface to volume ratio to provide a large number of uniformly distributed dangling bonds (defects in the crystalline structure) in proximity to a device region to effectively getter the device region. Thus, by effectively removing impurities from device regions, semiconductor devices are cable of being precisely fabricated.
  • System Level
  • FIG. 15 is a simplified block diagram of a high-level organization of a memory device, according to various embodiments of the present invention. The illustrated memory device 1530 includes a memory array 1531 and read/write control circuitry 1532 to perform operations on the memory array via communication line(s) 1533. The illustrated memory device 1530 may be a memory card or a memory module such as a single inline memory module (SIMM) and dual inline memory module (DIMM). One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that semiconductor components in the memory array 1531 and/or the control circuitry 1532 are able to be fabricated using the gettering regions having precise patterns of voids formed by surface transformation, as described above.
  • The memory array 1531 includes a number of memory cells 1534. The memory cells in the array are arranged in rows and columns. In various embodiments, word lines 1535 connect the memory cells in the rows, and bit lines 1536 connect the memory cells in the columns. The read/write control circuitry 1532 includes word line select circuitry 1537, which functions to select a desired row. The read/write control circuitry 1532 further includes bit line select circuitry 1538, which functions to select a desired column.
  • FIG. 16 is a simplified block diagram of a high-level organization of an electronic system, according to various embodiments of the present invention. In various embodiments, the system 1640 is a computer system, a process control system or other system that employs a processor and associated memory. The electronic system 1640 has functional elements, including a processor or arithmetic/logic unit (ALU) 1641, a control unit 1642, a memory device unit 1643 (such as illustrated at 1530 in FIG. 15) and an input/output (I/O) device 1644. Generally such an electronic system 1640 will have a native set of instructions that specify operations to be performed on data by the processor 1641 and other interactions between the processor 1641, the memory device unit 1643 and the I/O devices 1644. The control unit 1642 coordinates all operations of the processor 1641, the memory device 1643 and the I/O devices 1644 by continuously cycling through a set of operations that cause instructions to be fetched from the memory device 1643 and executed. According to various embodiments, the memory device 1643 includes, but is not limited to, random access memory (RAM) devices, read-only memory (ROM) devices, and peripheral devices such as a floppy disk drive and a compact disk CD-ROM drive. As one of ordinary skill in the art will understand, upon reading and comprehending this disclosure, any of the illustrated electrical components are capable of being fabricated to include the silicon germanium proximity gettering region in accordance with various embodiments of the present invention.
  • The illustration of the system 1640 is intended to provide a general understanding of one application for the structure and circuitry, and is not intended to serve as a complete description of all the elements and features of an electronic system using proximity gettering regions according to the various embodiments of the present invention. As one of ordinary skill in the art will understand, such an electronic system can be fabricated in single-package processing units, or even on a single semiconductor chip, in order to reduce the communication time between the processor and the memory device.
  • Applications containing a gettering region as described in this disclosure include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems.
  • CONCLUSION
  • Various embodiments disclosed herein getter a semiconductor wafer by precisely forming voids, such as nano-voids, at desired locations in the wafers. Various embodiments form an even distribution of voids across the wafer below device regions. In various embodiments, precisely-formed gettering void patterns are formed proximate to selected regions where devices are fabricated on the semiconductor wafer. Various embodiments precisely form the void patterns below device regions. Numerous dangling bonds are present at the internal surfaces of the voids such that these internal surfaces are highly chemically reactive. Thus, various embodiments form the voids and void patterns to have the greatest surface to volume ratio to increase the gettering of impurities.
  • This disclosure includes several processes, circuit diagrams, and structures. The present invention is not limited to a particular process order or logical arrangement. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover adaptations or variations. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments, will be apparent to those of skill in the art upon reviewing the above description. The scope of the present invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims (26)

1. A semiconductor wafer, comprising:
at least one device region; and
at least one gettering region located proximate to the at least one device region, the at least one gettering region including a precisely-determined arrangement of a plurality of precisely-formed voids formed within the wafer using a surface transformation process.
2. The wafer of claim 1, wherein the at least one gettering region includes one gettering region to getter the entire wafer.
3. The wafer of claim 1, wherein the at least one gettering region includes a plurality of gettering regions positioned under a plurality of device regions.
4. The wafer of claim 1, wherein the precisely-determined arrangement of a plurality of voids is uniformly distributed through the at least one gettering region.
5. The wafer of claim 1, wherein the plurality of voids are separated by a critical length (λC) that is dependent on a radius (RC) of a number of holes used to form the plurality of voids using a surface transformation process.
6. The wafer of claim 1, wherein each of the voids has an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region.
7. The wafer of claim 6, wherein:
the at least one gettering region has a volume; and
the precisely-determined arrangement of the plurality of precisely-formed voids is formed to provide a large ratio between the interior surface of the plurality of precisely-formed voids and the volume to enhance gettering.
8. The wafer of claim 1, wherein the plurality of precisely-formed voids includes a sphere-shaped void.
9. The wafer of claim 1, wherein the plurality of precisely-formed voids includes a pipe-shaped void.
10. The wafer of claim 1, wherein the plurality of precisely-formed voids includes a plate-shaped void.
11. The wafer of claim 1, wherein the at least one device region includes a plurality of device regions and the at least one gettering region includes a plurality of gettering regions.
12. The wafer of claim 1, wherein the at least one device region extends across a majority of a wafer area.
13. A semiconductor structure, comprising:
a gettering region proximate to a device region in a semiconductor wafer;
the gettering region including a precisely-determined arrangement of a plurality of precisely-formed voids through a surface transformation process, each of the voids having an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region;
a transistor formed using the device region, the transistor including
a gate dielectric over the device region;
a gate over the gate dielectric; and
a first diffusion region and a second diffusion region formed in the
device region, the first and second diffusion regions being separated by a channel region formed in the device region between the gate and the proximity gettering region.
14. The structure of claim 13, wherein the plurality of voids are separated by a critical length (λC) that is dependent on the radius (RC) of a number of holes used to form the plurality of voids using the surface transformation process.
15. The structure of claim 13, wherein the precisely-determined arrangement of a plurality of voids is uniformly distributed through the at least one gettering region.
16. The wafer of claim 13, wherein the plurality of precisely-formed voids includes a sphere-shaped void.
17. The wafer of claim 13, wherein the plurality of precisely-formed voids includes a pipe-shaped void.
18. The wafer of claim 13, wherein the plurality of precisely-formed voids includes a plate-shaped void.
19. A memory device, comprising:
at least one gettering region formed in a semiconductor substrate, the gettering region including a precise arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate;
a memory array formed in the crystalline semiconductor region, including a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells;
a plurality of word lines, each word line being connected to a row of memory cells;
a plurality of bit lines, each bit line being connected to a column of memory cells; and
control circuitry, including word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations.
20. The device of claim 1, wherein the precise arrangement of the plurality of voids is uniformly distributed through the gettering region.
21. The device of claim 1, wherein the plurality of voids are separated by a critical length (λC) that is dependent on a radius (RC) of a number of holes used to form the plurality of voids using a surface transformation process.
22. The device of claim 1, wherein each of the voids has an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region.
23. The device of claim 22, wherein:
the gettering region has a volume; and
the precisely-determined arrangement of the plurality of precisely-formed voids is formed to provide a large ratio between the interior surface of the plurality of precisely-formed voids and the volume to enhance gettering of the crystalline semiconductor region.
24. The wafer of claim 1, wherein the plurality of precisely-formed voids includes a sphere-shaped void.
25. The wafer of claim 1, wherein the plurality of precisely-formed voids includes a pipe-shaped void.
26. The wafer of claim 1, wherein the plurality of precisely-formed voids includes a plate-shaped void.
US10/931,344 2003-07-21 2004-08-31 Gettering using voids formed by surface transformation Abandoned US20050029683A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/931,344 US20050029683A1 (en) 2003-07-21 2004-08-31 Gettering using voids formed by surface transformation
US11/606,479 US7544984B2 (en) 2003-07-21 2006-11-30 Gettering using voids formed by surface transformation
US11/606,503 US7564082B2 (en) 2003-07-21 2006-11-30 Gettering using voids formed by surface transformation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/623,794 US6929984B2 (en) 2003-07-21 2003-07-21 Gettering using voids formed by surface transformation
US10/931,344 US20050029683A1 (en) 2003-07-21 2004-08-31 Gettering using voids formed by surface transformation

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/623,794 Division US6929984B2 (en) 2003-07-21 2003-07-21 Gettering using voids formed by surface transformation

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US11/606,479 Division US7544984B2 (en) 2003-07-21 2006-11-30 Gettering using voids formed by surface transformation
US11/606,503 Division US7564082B2 (en) 2003-07-21 2006-11-30 Gettering using voids formed by surface transformation

Publications (1)

Publication Number Publication Date
US20050029683A1 true US20050029683A1 (en) 2005-02-10

Family

ID=34079863

Family Applications (5)

Application Number Title Priority Date Filing Date
US10/623,794 Expired - Fee Related US6929984B2 (en) 2003-07-21 2003-07-21 Gettering using voids formed by surface transformation
US10/931,344 Abandoned US20050029683A1 (en) 2003-07-21 2004-08-31 Gettering using voids formed by surface transformation
US11/167,894 Expired - Lifetime US7326597B2 (en) 2003-07-21 2005-06-27 Gettering using voids formed by surface transformation
US11/606,479 Expired - Fee Related US7544984B2 (en) 2003-07-21 2006-11-30 Gettering using voids formed by surface transformation
US11/606,503 Expired - Fee Related US7564082B2 (en) 2003-07-21 2006-11-30 Gettering using voids formed by surface transformation

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/623,794 Expired - Fee Related US6929984B2 (en) 2003-07-21 2003-07-21 Gettering using voids formed by surface transformation

Family Applications After (3)

Application Number Title Priority Date Filing Date
US11/167,894 Expired - Lifetime US7326597B2 (en) 2003-07-21 2005-06-27 Gettering using voids formed by surface transformation
US11/606,479 Expired - Fee Related US7544984B2 (en) 2003-07-21 2006-11-30 Gettering using voids formed by surface transformation
US11/606,503 Expired - Fee Related US7564082B2 (en) 2003-07-21 2006-11-30 Gettering using voids formed by surface transformation

Country Status (1)

Country Link
US (5) US6929984B2 (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020070419A1 (en) * 2000-12-13 2002-06-13 Farrar Paul A. Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials
US20040173798A1 (en) * 2003-03-05 2004-09-09 Micron Technology, Inc. Micro-mechanically strained semiconductor film
US20040217896A1 (en) * 2003-01-24 2004-11-04 Stmicroelectronics S.R.L Multistage analog-to-digital converter
US20040232487A1 (en) * 2003-05-21 2004-11-25 Micron Technology, Inc. Ultra-thin semiconductors bonded on glass substrates
US20040232422A1 (en) * 2003-05-21 2004-11-25 Micron Technology, Inc. Wafer gettering using relaxed silicon germanium epitaxial proximity layers
US20040232488A1 (en) * 2003-05-21 2004-11-25 Micron Technology, Inc. Silicon oxycarbide substrates for bonded silicon on insulator
US20050029619A1 (en) * 2003-08-05 2005-02-10 Micron Technology, Inc. Strained Si/SiGe/SOI islands and processes of making same
US20050070036A1 (en) * 2001-05-16 2005-03-31 Geusic Joseph E. Method of forming mirrors by surface transformation of empty spaces in solid state materials
US20050176222A1 (en) * 2002-05-08 2005-08-11 Atsushi Ogura Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods
US20060138708A1 (en) * 2002-01-17 2006-06-29 Micron Technology, Inc. Cellular materials formed using surface transformation
US20060258063A1 (en) * 2003-05-21 2006-11-16 Micron Technology, Inc. Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
US20070075401A1 (en) * 2003-07-21 2007-04-05 Micron Technology, Inc. Gettering using voids formed by surface transformation
US20070161219A1 (en) * 2005-11-14 2007-07-12 Infineon Technologies Ag Method of producing a semiconductor element and semiconductor element
US20070187683A1 (en) * 2006-02-16 2007-08-16 Micron Technology, Inc. Localized compressive strained semiconductor
US20090014773A1 (en) * 2007-07-10 2009-01-15 Ching-Nan Hsiao Two bit memory structure and method of making the same
US20090256243A1 (en) * 2002-03-25 2009-10-15 Micron Technology, Inc. Low k interconnect dielectric using surface transformation

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7041575B2 (en) * 2003-04-29 2006-05-09 Micron Technology, Inc. Localized strained semiconductor on insulator
US7220656B2 (en) * 2003-04-29 2007-05-22 Micron Technology, Inc. Strained semiconductor by wafer bonding with misorientation
US7115480B2 (en) * 2003-05-07 2006-10-03 Micron Technology, Inc. Micromechanical strained semiconductor by wafer bonding
US7439158B2 (en) 2003-07-21 2008-10-21 Micron Technology, Inc. Strained semiconductor by full wafer bonding
US7179719B2 (en) * 2004-09-28 2007-02-20 Sharp Laboratories Of America, Inc. System and method for hydrogen exfoliation
US7071047B1 (en) * 2005-01-28 2006-07-04 International Business Machines Corporation Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions
US8552616B2 (en) * 2005-10-25 2013-10-08 The Curators Of The University Of Missouri Micro-scale power source
GB2437995A (en) * 2006-05-11 2007-11-14 X Fab Semiconductor Foundries Semiconductor processing
US7687304B2 (en) * 2006-11-29 2010-03-30 Innovative Micro Technology Current-driven device using NiMn alloy and method of manufacture
KR100834742B1 (en) * 2006-11-30 2008-06-05 삼성전자주식회사 Semiconductor Substrate including plural insulating regions in the substrate, semiconductor device using thereof and manufacturing method the same
KR100837280B1 (en) * 2007-03-12 2008-06-11 삼성전자주식회사 Semiconductor devices including a getting region and methods of forming the same
US8128749B2 (en) * 2007-10-04 2012-03-06 International Business Machines Corporation Fabrication of SOI with gettering layer
US20090189159A1 (en) * 2008-01-28 2009-07-30 Atmel Corporation Gettering layer on substrate
US20100187572A1 (en) * 2009-01-26 2010-07-29 Cho Hans S Suspended mono-crystalline structure and method of fabrication from a heteroepitaxial layer
US8692310B2 (en) 2009-02-09 2014-04-08 Spansion Llc Gate fringing effect based channel formation for semiconductor device
US8698244B2 (en) * 2009-11-30 2014-04-15 International Business Machines Corporation Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method
US8471340B2 (en) 2009-11-30 2013-06-25 International Business Machines Corporation Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure
US20150017466A1 (en) * 2012-03-09 2015-01-15 Arturo A. Ayon Self-aligned tunable metamaterials
US20160085311A1 (en) * 2014-09-24 2016-03-24 Sony Corporation Control unit and method of interacting with a graphical user interface
EA032292B1 (en) 2015-03-24 2019-05-31 Везувиус Ю-Эс-Эй Корпорэйшн Metallurgical vessel lining with configured perforation structure
US10833175B2 (en) * 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon
CN105890827B (en) * 2016-01-18 2019-05-21 广东合微集成电路技术有限公司 A kind of capacitance pressure transducer, and its manufacturing method
TWI750205B (en) * 2016-08-24 2021-12-21 美商維蘇威美國公司 Metallurgical vessel lining with enclosed metal layer and process for minimization of oxidation of molten metal
WO2019188613A1 (en) * 2018-03-29 2019-10-03 日本碍子株式会社 Gas sensor element
WO2020014458A1 (en) * 2018-07-11 2020-01-16 Monsanto Technology Llc Extraction of polynucleotides
US11243071B2 (en) * 2020-02-03 2022-02-08 The Boeing Company Sub-surface patterning for diffraction-based strain measurement and damage detection in structures

Citations (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4053925A (en) * 1975-08-07 1977-10-11 Ibm Corporation Method and structure for controllng carrier lifetime in semiconductor devices
US4314595A (en) * 1979-01-19 1982-02-09 Vlsi Technology Research Association Method of forming nondefective zone in silicon single crystal wafer by two stage-heat treatment
US4589928A (en) * 1984-08-21 1986-05-20 At&T Bell Laboratories Method of making semiconductor integrated circuits having backside gettered with phosphorus
US4717681A (en) * 1986-05-19 1988-01-05 Texas Instruments Incorporated Method of making a heterojunction bipolar transistor with SIPOS
US4962061A (en) * 1988-02-12 1990-10-09 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing a multilayer wiring structure employing metal fillets at step portions
US5098852A (en) * 1989-07-05 1992-03-24 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device by mega-electron volt ion implantation
US5240876A (en) * 1991-02-22 1993-08-31 Harris Corporation Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process
US5298452A (en) * 1986-09-12 1994-03-29 International Business Machines Corporation Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
US5344524A (en) * 1993-06-30 1994-09-06 Honeywell Inc. SOI substrate fabrication
US5426061A (en) * 1994-09-06 1995-06-20 Midwest Research Institute Impurity gettering in semiconductors
US5443661A (en) * 1993-07-27 1995-08-22 Nec Corporation SOI (silicon on insulator) substrate with enhanced gettering effects
US5482869A (en) * 1993-03-01 1996-01-09 Kabushiki Kaisha Toshiba Gettering of unwanted metal impurity introduced into semiconductor substrate during trench formation
US5489792A (en) * 1994-04-07 1996-02-06 Regents Of The University Of California Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
US5526449A (en) * 1993-01-08 1996-06-11 Massachusetts Institute Of Technology Optoelectronic integrated circuits and method of fabricating and reducing losses using same
US5534713A (en) * 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
US5646053A (en) * 1995-12-20 1997-07-08 International Business Machines Corporation Method and structure for front-side gettering of silicon-on-insulator substrates
US5661044A (en) * 1993-11-24 1997-08-26 Lockheed Martin Energy Systems, Inc. Processing method for forming dislocation-free SOI and other materials for semiconductor use
US5723896A (en) * 1994-02-17 1998-03-03 Lsi Logic Corporation Integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate
US5739796A (en) * 1995-10-30 1998-04-14 The United States Of America As Represented By The Secretary Of The Army Ultra-wideband photonic band gap crystal having selectable and controllable bad gaps and methods for achieving photonic band gaps
US5759898A (en) * 1993-10-29 1998-06-02 International Business Machines Corporation Production of substrate for tensilely strained semiconductor
US5773152A (en) * 1994-10-13 1998-06-30 Nec Corporation SOI substrate having a high heavy metal gettering effect for semiconductor device
US5789859A (en) * 1996-11-25 1998-08-04 Micron Display Technology, Inc. Field emission display with non-evaporable getter material
US5818761A (en) * 1996-09-10 1998-10-06 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor memory device capable of high speed programming/erasure
US5879996A (en) * 1996-09-18 1999-03-09 Micron Technology, Inc. Silicon-germanium devices for CMOS formed by ion implantation and solid phase epitaxial regrowth
US5891769A (en) * 1997-04-07 1999-04-06 Motorola, Inc. Method for forming a semiconductor device having a heteroepitaxial layer
US5900652A (en) * 1994-07-25 1999-05-04 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Apparatus for the localized reduction of the lifetime of charge carriers, particularly in integrated electronic devices
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US5961877A (en) * 1994-11-10 1999-10-05 Robinson; Mcdonald Wet chemical etchants
US5963817A (en) * 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
US6022793A (en) * 1997-10-21 2000-02-08 Seh America, Inc. Silicon and oxygen ion co-implantation for metallic gettering in epitaxial wafers
US6054808A (en) * 1997-03-19 2000-04-25 Micron Technology, Inc. Display device with grille having getter material
US6075640A (en) * 1997-11-26 2000-06-13 Massachusetts Institute Of Technology Signal processing by optically manipulating polaritons
US6083324A (en) * 1998-02-19 2000-07-04 Silicon Genesis Corporation Gettering technique for silicon-on-insulator wafers
US6093624A (en) * 1997-12-23 2000-07-25 Philips Electronics North America Corporation Method of providing a gettering scheme in the manufacture of silicon-on-insulator (SOI) integrated circuits
US6093623A (en) * 1998-08-04 2000-07-25 Micron Technology, Inc. Methods for making silicon-on-insulator structures
US6172456B1 (en) * 1995-02-10 2001-01-09 Micron Technology, Inc. Field emission display
US6174784B1 (en) * 1996-09-04 2001-01-16 Micron Technology, Inc. Technique for producing small islands of silicon on insulator
US6185144B1 (en) * 1997-09-16 2001-02-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with reduced power consumption and stable operation in data holding state
US6204145B1 (en) * 1996-11-12 2001-03-20 Micron Technology, Inc. Silicon-on-insulator islands and method for their formation
US6228694B1 (en) * 1999-06-28 2001-05-08 Intel Corporation Method of increasing the mobility of MOS transistors by use of localized stress regions
US6243299B1 (en) * 1998-02-27 2001-06-05 Micron Technology, Inc. Flash memory system having fast erase operation
US20010003269A1 (en) * 1998-04-10 2001-06-14 Kenneth C. Wu Etch stop layer system
US6261876B1 (en) * 1999-11-04 2001-07-17 International Business Machines Corporation Planar mixed SOI-bulk substrate for microelectronic applications
US6274460B1 (en) * 1998-05-21 2001-08-14 Intersil Corporation Defect gettering by induced stress
US6337260B1 (en) * 1999-09-24 2002-01-08 Advanced Micro Devices, Inc. Use of knocked-on oxygen atoms for reduction of transient enhanced diffusion
US6339011B1 (en) * 2001-03-05 2002-01-15 Micron Technology, Inc. Method of forming semiconductive active area having a proximity gettering region therein and method of processing a monocrystalline silicon substrate to have a proximity gettering region
US6338805B1 (en) * 1999-07-14 2002-01-15 Memc Electronic Materials, Inc. Process for fabricating semiconductor wafers with external gettering
US20020017330A1 (en) * 2000-08-04 2002-02-14 Armenia John G. Double wall safety hose
US6368938B1 (en) * 1999-10-05 2002-04-09 Silicon Wafer Technologies, Inc. Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate
US6376336B1 (en) * 2001-02-01 2002-04-23 Advanced Micro Devices, Inc. Frontside SOI gettering with phosphorus doping
US6377070B1 (en) * 2001-02-09 2002-04-23 Micron Technology, Inc. In-service programmable logic arrays with ultra thin vertical body transistors
US6383924B1 (en) * 2000-12-13 2002-05-07 Micron Technology, Inc. Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials
US6391738B2 (en) * 1998-07-22 2002-05-21 Micron Technology, Inc. Semiconductor processing method and trench isolation method
US20020062782A1 (en) * 2000-11-28 2002-05-30 Norris David J. Self-assembled photonic crystals and methods for manufacturing same
US20020070421A1 (en) * 1997-12-31 2002-06-13 Ashburn Stanton Petree Embedded gettering layer in shallow trench isolation structure
US20020076896A1 (en) * 2000-12-15 2002-06-20 Farrar Paul A. Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials
US6423613B1 (en) * 1998-11-10 2002-07-23 Micron Technology, Inc. Low temperature silicon wafer bond process with bulk material bond strength
US6424001B1 (en) * 2001-02-09 2002-07-23 Micron Technology, Inc. Flash memory with ultra thin vertical body transistors
US6436187B1 (en) * 1999-09-01 2002-08-20 Agere Systems Guardian Corp. Process for fabricating article having substantial three-dimensional order
US6437375B1 (en) * 2000-06-05 2002-08-20 Micron Technology, Inc. PD-SOI substrate with suppressed floating body effect and method for its fabrication
US6444534B1 (en) * 2001-01-30 2002-09-03 Advanced Micro Devices, Inc. SOI semiconductor device opening implantation gettering method
US6448601B1 (en) * 2001-02-09 2002-09-10 Micron Technology, Inc. Memory address and decode circuits with ultra thin body transistors
US6448157B1 (en) * 1999-02-02 2002-09-10 Nec Corporation Fabrication process for a semiconductor device
US6451672B1 (en) * 1999-04-15 2002-09-17 Stmicroelectronics S.R.L. Method for manufacturing electronic devices in semiconductor substrates provided with gettering sites
US6452713B1 (en) * 2000-12-29 2002-09-17 Agere Systems Guardian Corp. Device for tuning the propagation of electromagnetic energy
US20030027406A1 (en) * 2001-08-01 2003-02-06 Malone Farris D. Gettering of SOI wafers without regions of heavy doping
US6531727B2 (en) * 2001-02-09 2003-03-11 Micron Technology, Inc. Open bit line DRAM with ultra thin body transistors
US6541356B2 (en) * 2001-05-21 2003-04-01 International Business Machines Corporation Ultimate SIMOX
US6542682B2 (en) * 2000-08-15 2003-04-01 Corning Incorporated Active photonic crystal waveguide device
US6559491B2 (en) * 2001-02-09 2003-05-06 Micron Technology, Inc. Folded bit line DRAM with ultra thin body transistors
US6566682B2 (en) * 2001-02-09 2003-05-20 Micron Technology, Inc. Programmable memory address and decode circuits with ultra thin vertical body transistors
US6583437B2 (en) * 2000-03-17 2003-06-24 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6582512B2 (en) * 2001-05-22 2003-06-24 Micron Technology, Inc. Method of forming three-dimensional photonic band structures in solid materials
US6593625B2 (en) * 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US20030131782A1 (en) * 2002-01-17 2003-07-17 Micron Technology, Inc. Three-dimensional complete bandgap photonic crystal formed by crystal modification
US20030133683A1 (en) * 2002-01-17 2003-07-17 Micron Technology, Inc. Three-dimensional photonic crystal waveguide structure and method
US6597203B2 (en) * 2001-03-14 2003-07-22 Micron Technology, Inc. CMOS gate array with vertical transistors
US20030181018A1 (en) * 2002-03-25 2003-09-25 Micron Technology, Inc. Low k interconnect dielectric using surface transformation
US6740913B2 (en) * 1999-06-28 2004-05-25 Intel Corporation MOS transistor using mechanical stress to control short channel effects
US20040135138A1 (en) * 2003-01-15 2004-07-15 Sharp Laboratories Of America, Inc. System and method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications
US20040171196A1 (en) * 2002-08-08 2004-09-02 Walitzki Hans J. Method and apparatus for transferring a thin layer of semiconductor material
US20040176483A1 (en) * 2003-03-05 2004-09-09 Micron Technology, Inc. Cellular materials formed using surface transformation
US20050017273A1 (en) * 2003-07-21 2005-01-27 Micron Technology, Inc. Gettering using voids formed by surface transformation
US20050070036A1 (en) * 2001-05-16 2005-03-31 Geusic Joseph E. Method of forming mirrors by surface transformation of empty spaces in solid state materials

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5721856B2 (en) 1977-11-28 1982-05-10 Nippon Telegraph & Telephone Semiconductor and its manufacture
US4962051A (en) * 1988-11-18 1990-10-09 Motorola, Inc. Method of forming a defect-free semiconductor layer on insulator
US5229306A (en) 1989-12-27 1993-07-20 Texas Instruments Incorporated Backside gettering method employing a monocrystalline germanium-silicon layer
US5187461A (en) 1991-02-15 1993-02-16 Karl Brommer Low-loss dielectric resonator having a lattice structure with a resonant defect
JPH04304653A (en) * 1991-04-02 1992-10-28 Fujitsu Ltd Semiconductor device and manufacture thereof
US5840590A (en) 1993-12-01 1998-11-24 Sandia Corporation Impurity gettering in silicon using cavities formed by helium implantation and annealing
US5697825A (en) 1995-09-29 1997-12-16 Micron Display Technology, Inc. Method for evacuating and sealing field emission displays
WO1998035248A1 (en) 1997-02-11 1998-08-13 Massachusetts Institute Of Technology Polymeric photonic band gap materials
JPH10223640A (en) 1997-02-12 1998-08-21 Nec Corp Semiconductor substrate and its manufacture
JPH10256261A (en) 1997-03-12 1998-09-25 Nec Corp Manufacture of semiconductor device
US6133123A (en) * 1997-08-21 2000-10-17 Micron Technology, Inc. Fabrication of semiconductor gettering structures by ion implantation
US6350704B1 (en) * 1997-10-14 2002-02-26 Micron Technology Inc. Porous silicon oxycarbide integrated circuit insulator
US5999308A (en) 1998-04-01 1999-12-07 Massachusetts Institute Of Technology Methods and systems for introducing electromagnetic radiation into photonic crystals
KR20000003975A (en) * 1998-06-30 2000-01-25 김영환 Method for manufacturing bonding-type soi wafer having a field oxide
KR100588098B1 (en) 1998-08-31 2006-06-09 신에쯔 한도타이 가부시키가이샤 Silicon single crystal wafer, epitaxial silicon wafer, and method for producing them
US6139626A (en) 1998-09-04 2000-10-31 Nec Research Institute, Inc. Three-dimensionally patterned materials and methods for manufacturing same using nanocrystals
US6409907B1 (en) 1999-02-11 2002-06-25 Lucent Technologies Inc. Electrochemical process for fabricating article exhibiting substantial three-dimensional order and resultant article
US6656822B2 (en) * 1999-06-28 2003-12-02 Intel Corporation Method for reduced capacitance interconnect system using gaseous implants into the ILD
JP3980801B2 (en) 1999-09-16 2007-09-26 株式会社東芝 Three-dimensional structure and manufacturing method thereof
JP2001093887A (en) 1999-09-22 2001-04-06 Toshiba Corp Method for manufacturing semiconductor device
US6461933B2 (en) 2000-12-30 2002-10-08 Texas Instruments Incorporated SPIMOX/SIMOX combination with ITOX option
US6496034B2 (en) 2001-02-09 2002-12-17 Micron Technology, Inc. Programmable logic arrays with ultra thin body transistors
US6649476B2 (en) 2001-02-15 2003-11-18 Micron Technology, Inc. Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array
US6433640B1 (en) 2001-05-25 2002-08-13 Motorola, Inc. Methods and apparatus for amplifying a telecommunication signal
US6855649B2 (en) 2001-06-12 2005-02-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
KR100423752B1 (en) * 2001-11-12 2004-03-22 주식회사 실트론 A Semiconductor Silicon Wafer and a Method for making thereof
US7022604B2 (en) 2002-04-09 2006-04-04 Micron Technology, Inc. Method of forming spatial regions of a second material in a first material
US6900521B2 (en) 2002-06-10 2005-05-31 Micron Technology, Inc. Vertical transistors and output prediction logic circuits containing same
US7662701B2 (en) 2003-05-21 2010-02-16 Micron Technology, Inc. Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
US7501329B2 (en) * 2003-05-21 2009-03-10 Micron Technology, Inc. Wafer gettering using relaxed silicon germanium epitaxial proximity layers
US7439158B2 (en) * 2003-07-21 2008-10-21 Micron Technology, Inc. Strained semiconductor by full wafer bonding
EP1538650B1 (en) * 2003-12-02 2017-11-08 Schneider Electric Energy Manufacturing Italia S.r.l. Isolator/circuit-breaker device for electric substations

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4053925A (en) * 1975-08-07 1977-10-11 Ibm Corporation Method and structure for controllng carrier lifetime in semiconductor devices
US4314595A (en) * 1979-01-19 1982-02-09 Vlsi Technology Research Association Method of forming nondefective zone in silicon single crystal wafer by two stage-heat treatment
US4589928A (en) * 1984-08-21 1986-05-20 At&T Bell Laboratories Method of making semiconductor integrated circuits having backside gettered with phosphorus
US4717681A (en) * 1986-05-19 1988-01-05 Texas Instruments Incorporated Method of making a heterojunction bipolar transistor with SIPOS
US5298452A (en) * 1986-09-12 1994-03-29 International Business Machines Corporation Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
US4962061A (en) * 1988-02-12 1990-10-09 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing a multilayer wiring structure employing metal fillets at step portions
US5098852A (en) * 1989-07-05 1992-03-24 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device by mega-electron volt ion implantation
US5240876A (en) * 1991-02-22 1993-08-31 Harris Corporation Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process
US5526449A (en) * 1993-01-08 1996-06-11 Massachusetts Institute Of Technology Optoelectronic integrated circuits and method of fabricating and reducing losses using same
US5482869A (en) * 1993-03-01 1996-01-09 Kabushiki Kaisha Toshiba Gettering of unwanted metal impurity introduced into semiconductor substrate during trench formation
US5344524A (en) * 1993-06-30 1994-09-06 Honeywell Inc. SOI substrate fabrication
US5443661A (en) * 1993-07-27 1995-08-22 Nec Corporation SOI (silicon on insulator) substrate with enhanced gettering effects
US5759898A (en) * 1993-10-29 1998-06-02 International Business Machines Corporation Production of substrate for tensilely strained semiconductor
US5661044A (en) * 1993-11-24 1997-08-26 Lockheed Martin Energy Systems, Inc. Processing method for forming dislocation-free SOI and other materials for semiconductor use
US5723896A (en) * 1994-02-17 1998-03-03 Lsi Logic Corporation Integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate
US5489792A (en) * 1994-04-07 1996-02-06 Regents Of The University Of California Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
US5534713A (en) * 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
US5900652A (en) * 1994-07-25 1999-05-04 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Apparatus for the localized reduction of the lifetime of charge carriers, particularly in integrated electronic devices
US5426061A (en) * 1994-09-06 1995-06-20 Midwest Research Institute Impurity gettering in semiconductors
US5773152A (en) * 1994-10-13 1998-06-30 Nec Corporation SOI substrate having a high heavy metal gettering effect for semiconductor device
US5961877A (en) * 1994-11-10 1999-10-05 Robinson; Mcdonald Wet chemical etchants
US6172456B1 (en) * 1995-02-10 2001-01-09 Micron Technology, Inc. Field emission display
US5739796A (en) * 1995-10-30 1998-04-14 The United States Of America As Represented By The Secretary Of The Army Ultra-wideband photonic band gap crystal having selectable and controllable bad gaps and methods for achieving photonic band gaps
US5646053A (en) * 1995-12-20 1997-07-08 International Business Machines Corporation Method and structure for front-side gettering of silicon-on-insulator substrates
US6174784B1 (en) * 1996-09-04 2001-01-16 Micron Technology, Inc. Technique for producing small islands of silicon on insulator
US20020001965A1 (en) * 1996-09-04 2002-01-03 Leonard Forbes Technique for producing small islands of silicon on insulator
US5818761A (en) * 1996-09-10 1998-10-06 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor memory device capable of high speed programming/erasure
US5879996A (en) * 1996-09-18 1999-03-09 Micron Technology, Inc. Silicon-germanium devices for CMOS formed by ion implantation and solid phase epitaxial regrowth
US6204145B1 (en) * 1996-11-12 2001-03-20 Micron Technology, Inc. Silicon-on-insulator islands and method for their formation
US5789859A (en) * 1996-11-25 1998-08-04 Micron Display Technology, Inc. Field emission display with non-evaporable getter material
US6054808A (en) * 1997-03-19 2000-04-25 Micron Technology, Inc. Display device with grille having getter material
US5891769A (en) * 1997-04-07 1999-04-06 Motorola, Inc. Method for forming a semiconductor device having a heteroepitaxial layer
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US6185144B1 (en) * 1997-09-16 2001-02-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with reduced power consumption and stable operation in data holding state
US5963817A (en) * 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
US6251751B1 (en) * 1997-10-16 2001-06-26 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
US6022793A (en) * 1997-10-21 2000-02-08 Seh America, Inc. Silicon and oxygen ion co-implantation for metallic gettering in epitaxial wafers
US6075640A (en) * 1997-11-26 2000-06-13 Massachusetts Institute Of Technology Signal processing by optically manipulating polaritons
US6093624A (en) * 1997-12-23 2000-07-25 Philips Electronics North America Corporation Method of providing a gettering scheme in the manufacture of silicon-on-insulator (SOI) integrated circuits
US20020070421A1 (en) * 1997-12-31 2002-06-13 Ashburn Stanton Petree Embedded gettering layer in shallow trench isolation structure
US6083324A (en) * 1998-02-19 2000-07-04 Silicon Genesis Corporation Gettering technique for silicon-on-insulator wafers
US6243299B1 (en) * 1998-02-27 2001-06-05 Micron Technology, Inc. Flash memory system having fast erase operation
US20010003269A1 (en) * 1998-04-10 2001-06-14 Kenneth C. Wu Etch stop layer system
US6274460B1 (en) * 1998-05-21 2001-08-14 Intersil Corporation Defect gettering by induced stress
US6391738B2 (en) * 1998-07-22 2002-05-21 Micron Technology, Inc. Semiconductor processing method and trench isolation method
US6093623A (en) * 1998-08-04 2000-07-25 Micron Technology, Inc. Methods for making silicon-on-insulator structures
US6538330B1 (en) * 1998-08-04 2003-03-25 Micron Technology, Inc. Multilevel semiconductor-on-insulator structures and circuits
US6423613B1 (en) * 1998-11-10 2002-07-23 Micron Technology, Inc. Low temperature silicon wafer bond process with bulk material bond strength
US6448157B1 (en) * 1999-02-02 2002-09-10 Nec Corporation Fabrication process for a semiconductor device
US6451672B1 (en) * 1999-04-15 2002-09-17 Stmicroelectronics S.R.L. Method for manufacturing electronic devices in semiconductor substrates provided with gettering sites
US6740913B2 (en) * 1999-06-28 2004-05-25 Intel Corporation MOS transistor using mechanical stress to control short channel effects
US6228694B1 (en) * 1999-06-28 2001-05-08 Intel Corporation Method of increasing the mobility of MOS transistors by use of localized stress regions
US6338805B1 (en) * 1999-07-14 2002-01-15 Memc Electronic Materials, Inc. Process for fabricating semiconductor wafers with external gettering
US6436187B1 (en) * 1999-09-01 2002-08-20 Agere Systems Guardian Corp. Process for fabricating article having substantial three-dimensional order
US6337260B1 (en) * 1999-09-24 2002-01-08 Advanced Micro Devices, Inc. Use of knocked-on oxygen atoms for reduction of transient enhanced diffusion
US6368938B1 (en) * 1999-10-05 2002-04-09 Silicon Wafer Technologies, Inc. Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate
US6261876B1 (en) * 1999-11-04 2001-07-17 International Business Machines Corporation Planar mixed SOI-bulk substrate for microelectronic applications
US6583437B2 (en) * 2000-03-17 2003-06-24 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6437375B1 (en) * 2000-06-05 2002-08-20 Micron Technology, Inc. PD-SOI substrate with suppressed floating body effect and method for its fabrication
US6746937B2 (en) * 2000-06-05 2004-06-08 Micron Technology, Inc. PD-SOI substrate with suppressed floating body effect and method for its fabrication
US20020017330A1 (en) * 2000-08-04 2002-02-14 Armenia John G. Double wall safety hose
US6542682B2 (en) * 2000-08-15 2003-04-01 Corning Incorporated Active photonic crystal waveguide device
US20020062782A1 (en) * 2000-11-28 2002-05-30 Norris David J. Self-assembled photonic crystals and methods for manufacturing same
US6383924B1 (en) * 2000-12-13 2002-05-07 Micron Technology, Inc. Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials
US20020070419A1 (en) * 2000-12-13 2002-06-13 Farrar Paul A. Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials
US20020076896A1 (en) * 2000-12-15 2002-06-20 Farrar Paul A. Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials
US20030157780A1 (en) * 2000-12-15 2003-08-21 Farrar Paul A. Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials
US20030042627A1 (en) * 2000-12-15 2003-03-06 Farrar Paul A. Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials
US6579738B2 (en) * 2000-12-15 2003-06-17 Micron Technology, Inc. Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials
US6452713B1 (en) * 2000-12-29 2002-09-17 Agere Systems Guardian Corp. Device for tuning the propagation of electromagnetic energy
US6444534B1 (en) * 2001-01-30 2002-09-03 Advanced Micro Devices, Inc. SOI semiconductor device opening implantation gettering method
US6376336B1 (en) * 2001-02-01 2002-04-23 Advanced Micro Devices, Inc. Frontside SOI gettering with phosphorus doping
US6559491B2 (en) * 2001-02-09 2003-05-06 Micron Technology, Inc. Folded bit line DRAM with ultra thin body transistors
US6448601B1 (en) * 2001-02-09 2002-09-10 Micron Technology, Inc. Memory address and decode circuits with ultra thin body transistors
US6566682B2 (en) * 2001-02-09 2003-05-20 Micron Technology, Inc. Programmable memory address and decode circuits with ultra thin vertical body transistors
US6531727B2 (en) * 2001-02-09 2003-03-11 Micron Technology, Inc. Open bit line DRAM with ultra thin body transistors
US6377070B1 (en) * 2001-02-09 2002-04-23 Micron Technology, Inc. In-service programmable logic arrays with ultra thin vertical body transistors
US6424001B1 (en) * 2001-02-09 2002-07-23 Micron Technology, Inc. Flash memory with ultra thin vertical body transistors
US6339011B1 (en) * 2001-03-05 2002-01-15 Micron Technology, Inc. Method of forming semiconductive active area having a proximity gettering region therein and method of processing a monocrystalline silicon substrate to have a proximity gettering region
US6597203B2 (en) * 2001-03-14 2003-07-22 Micron Technology, Inc. CMOS gate array with vertical transistors
US20050070036A1 (en) * 2001-05-16 2005-03-31 Geusic Joseph E. Method of forming mirrors by surface transformation of empty spaces in solid state materials
US6541356B2 (en) * 2001-05-21 2003-04-01 International Business Machines Corporation Ultimate SIMOX
US6582512B2 (en) * 2001-05-22 2003-06-24 Micron Technology, Inc. Method of forming three-dimensional photonic band structures in solid materials
US20050105869A1 (en) * 2001-05-22 2005-05-19 Micron Technology, Inc. Three-dimensional photonic crystal waveguide structure and method
US6593625B2 (en) * 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US20030027406A1 (en) * 2001-08-01 2003-02-06 Malone Farris D. Gettering of SOI wafers without regions of heavy doping
US20030131782A1 (en) * 2002-01-17 2003-07-17 Micron Technology, Inc. Three-dimensional complete bandgap photonic crystal formed by crystal modification
US20030133683A1 (en) * 2002-01-17 2003-07-17 Micron Technology, Inc. Three-dimensional photonic crystal waveguide structure and method
US20060138708A1 (en) * 2002-01-17 2006-06-29 Micron Technology, Inc. Cellular materials formed using surface transformation
US6898362B2 (en) * 2002-01-17 2005-05-24 Micron Technology Inc. Three-dimensional photonic crystal waveguide structure and method
US20030181018A1 (en) * 2002-03-25 2003-09-25 Micron Technology, Inc. Low k interconnect dielectric using surface transformation
US20040171196A1 (en) * 2002-08-08 2004-09-02 Walitzki Hans J. Method and apparatus for transferring a thin layer of semiconductor material
US20040135138A1 (en) * 2003-01-15 2004-07-15 Sharp Laboratories Of America, Inc. System and method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications
US20040176483A1 (en) * 2003-03-05 2004-09-09 Micron Technology, Inc. Cellular materials formed using surface transformation
US20050017273A1 (en) * 2003-07-21 2005-01-27 Micron Technology, Inc. Gettering using voids formed by surface transformation
US6929984B2 (en) * 2003-07-21 2005-08-16 Micron Technology Inc. Gettering using voids formed by surface transformation
US20070075401A1 (en) * 2003-07-21 2007-04-05 Micron Technology, Inc. Gettering using voids formed by surface transformation
US20070080335A1 (en) * 2003-07-21 2007-04-12 Micron Technology, Inc. Gettering using voids formed by surface transformation
US7326597B2 (en) * 2003-07-21 2008-02-05 Micron Technology, Inc. Gettering using voids formed by surface transformation

Cited By (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020070419A1 (en) * 2000-12-13 2002-06-13 Farrar Paul A. Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials
US20070036196A1 (en) * 2001-05-16 2007-02-15 Geusic Joseph E Method of forming mirrors by surface transformation of empty spaces in solid state materials
US20050175058A1 (en) * 2001-05-16 2005-08-11 Geusic Joseph E. Method of forming mirrors by surface transformation of empty spaces in solid state materials
US20050070036A1 (en) * 2001-05-16 2005-03-31 Geusic Joseph E. Method of forming mirrors by surface transformation of empty spaces in solid state materials
US20060138708A1 (en) * 2002-01-17 2006-06-29 Micron Technology, Inc. Cellular materials formed using surface transformation
US7964124B2 (en) 2002-01-17 2011-06-21 Micron Technology, Inc. Method of forming cellular material
US20090256243A1 (en) * 2002-03-25 2009-10-15 Micron Technology, Inc. Low k interconnect dielectric using surface transformation
US7605443B2 (en) * 2002-05-08 2009-10-20 Nec Corporation Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods
US20050176222A1 (en) * 2002-05-08 2005-08-11 Atsushi Ogura Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods
US20040217896A1 (en) * 2003-01-24 2004-11-04 Stmicroelectronics S.R.L Multistage analog-to-digital converter
US7202530B2 (en) 2003-03-05 2007-04-10 Micron Technology, Inc. Micro-mechanically strained semiconductor film
US20070164361A1 (en) * 2003-03-05 2007-07-19 Micron Technology, Inc. Micro-mechanically strained semiconductor film
US7198974B2 (en) 2003-03-05 2007-04-03 Micron Technology, Inc. Micro-mechanically strained semiconductor film
US20060011982A1 (en) * 2003-03-05 2006-01-19 Micron Technology, Inc. Micro-mechanically strained semiconductor film
US20040173798A1 (en) * 2003-03-05 2004-09-09 Micron Technology, Inc. Micro-mechanically strained semiconductor film
US20050023612A1 (en) * 2003-05-21 2005-02-03 Micron Technology, Inc. Ultra-thin semiconductors bonded on glass substrates
US20060263994A1 (en) * 2003-05-21 2006-11-23 Micron Technology, Inc. Semiconductors bonded on glass substrates
US20060258063A1 (en) * 2003-05-21 2006-11-16 Micron Technology, Inc. Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
US20060001094A1 (en) * 2003-05-21 2006-01-05 Micron Technology, Inc. Semiconductor on insulator structure
US20040232488A1 (en) * 2003-05-21 2004-11-25 Micron Technology, Inc. Silicon oxycarbide substrates for bonded silicon on insulator
US7687329B2 (en) 2003-05-21 2010-03-30 Micron Technology, Inc. Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
US20040232422A1 (en) * 2003-05-21 2004-11-25 Micron Technology, Inc. Wafer gettering using relaxed silicon germanium epitaxial proximity layers
US7662701B2 (en) 2003-05-21 2010-02-16 Micron Technology, Inc. Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
US20040232487A1 (en) * 2003-05-21 2004-11-25 Micron Technology, Inc. Ultra-thin semiconductors bonded on glass substrates
US20070075401A1 (en) * 2003-07-21 2007-04-05 Micron Technology, Inc. Gettering using voids formed by surface transformation
US20070080335A1 (en) * 2003-07-21 2007-04-12 Micron Technology, Inc. Gettering using voids formed by surface transformation
US7544984B2 (en) 2003-07-21 2009-06-09 Micron Technology, Inc. Gettering using voids formed by surface transformation
US20050087842A1 (en) * 2003-08-05 2005-04-28 Micron Technology, Inc. Strained Si/SiGe/SOI islands and processes of making same
US20050029619A1 (en) * 2003-08-05 2005-02-10 Micron Technology, Inc. Strained Si/SiGe/SOI islands and processes of making same
US20070161219A1 (en) * 2005-11-14 2007-07-12 Infineon Technologies Ag Method of producing a semiconductor element and semiconductor element
US7825016B2 (en) * 2005-11-14 2010-11-02 Infineon Technologies Ag Method of producing a semiconductor element
US20090218566A1 (en) * 2006-02-16 2009-09-03 Micron Technology, Inc. Localized compressive strained semiconductor
US7544584B2 (en) 2006-02-16 2009-06-09 Micron Technology, Inc. Localized compressive strained semiconductor
US20070187683A1 (en) * 2006-02-16 2007-08-16 Micron Technology, Inc. Localized compressive strained semiconductor
US8124977B2 (en) 2006-02-16 2012-02-28 Micron Technology, Inc. Localized compressive strained semiconductor
US8227309B2 (en) 2006-02-16 2012-07-24 Micron Technology, Inc. Localized compressive strained semiconductor
US8435850B2 (en) 2006-02-16 2013-05-07 Micron Technology, Inc. Localized compressive strained semiconductor
US20090014773A1 (en) * 2007-07-10 2009-01-15 Ching-Nan Hsiao Two bit memory structure and method of making the same

Also Published As

Publication number Publication date
US6929984B2 (en) 2005-08-16
US20070075401A1 (en) 2007-04-05
US7326597B2 (en) 2008-02-05
US20050017273A1 (en) 2005-01-27
US7564082B2 (en) 2009-07-21
US20050250274A1 (en) 2005-11-10
US20070080335A1 (en) 2007-04-12
US7544984B2 (en) 2009-06-09

Similar Documents

Publication Publication Date Title
US7326597B2 (en) Gettering using voids formed by surface transformation
US7202530B2 (en) Micro-mechanically strained semiconductor film
US7023051B2 (en) Localized strained semiconductor on insulator
US7888744B2 (en) Strained semiconductor, devices and systems and methods of formation
US7994595B2 (en) Strained semiconductor by full wafer bonding
JP5229635B2 (en) Nanowire transistor with surrounding gate
US7368790B2 (en) Strained Si/SiGe/SOI islands and processes of making same
US7045874B2 (en) Micromechanical strained semiconductor by wafer bonding
CN100405534C (en) Hetero-integrated strained silicon n-and p-mosfets
US8791506B2 (en) Semiconductor devices, assemblies and constructions
CN102640273B (en) Method for forming finfets
TWI755650B (en) Methods of forming dislocation enhanced strain in nmos structures
KR20230002818A (en) Three-dimensional memory device with a hydrogen-rich semiconductor channel
US20220140143A1 (en) Device isolation
CN113437138A (en) Static Random Access Memory (SRAM) bitcell with trench fill reduction
WO2019139622A1 (en) Ferroelectric field-effect transistors for 3d memory arrays and methods of manufacturing the same
WO2005091339A2 (en) Method of fabricating a semiconductor structure
US8072022B2 (en) Apparatus and methods for improved flash cell characteristics

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION