US20050091618A1 - Method and apparatus for decomposing and verifying configurable hardware - Google Patents
Method and apparatus for decomposing and verifying configurable hardware Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318314—Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G—PHYSICS
- G21—NUCLEAR PHYSICS; NUCLEAR ENGINEERING
- G21C—NUCLEAR REACTORS
- G21C17/00—Monitoring; Testing ; Maintaining
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E30/00—Energy generation of nuclear origin
- Y02E30/30—Nuclear fission reactors
Definitions
- the present invention pertains to hardware verification. More particularly, the present invention relates to verifying configurable hardware.
- Configurable hardware or “parameterized hardware” describes hardware systems that are customized automatically at design creation time by using specified values for a set of parameters or attributes. Such hardware may also support changes at run-time depending on parameter settings. Configurable hardware systems typically provide better performance than software running on a general-purpose computer system and greater flexibility than conventional application specific integrated circuits (ASICs) without increasing circuit size and cost.
- ASICs application specific integrated circuits
- Configurable hardware systems can be verified using this type of conventional hierarchical decomposition. However, because each instance of a configurable hardware system is different, each time a configuration parameter is modified, the system and its components must be manually verified. The cost of repeatedly manually verifying a system and its components often offsets the advantages of configurable hardware.
- the present invention includes a method and apparatus for decomposing and verifying configurable hardware.
- the method includes automatically decomposing a hardware system into a set of one or more units, creating a testbench for each of the sets of units, and verifying each of the set of units before verifying the hardware system design.
- FIG. 1 is a block diagram for decomposing and verifying configurable hardware according to one embodiment of the invention
- FIG. 2 is a block diagram illustrating a system for creating and verifying configurable hardware according to one embodiment of the invention
- FIG. 3 is a flow diagram illustrating the creation of a system, according to embodiments of the invention.
- FIG. 4 is a conceptual block diagram of a system design according to embodiments of the invention.
- FIG. 5 is a flow diagram illustrating operations for decomposing and verifying a configurable hardware system according to embodiments of the invention
- FIG. 6 is a block diagram illustrating a testbench for verifying a unit according to embodiments of the invention.
- FIG. 7 illustrates an exemplary system for decomposing and verifying configurable hardware, according to embodiments of the invention.
- references to “one embodiment” or “an embodiment” mean that the feature being referred to is included in at least one embodiment of the invention. Further, separate references to “one embodiment” in this description do not necessarily refer to the same embodiment; however, neither are such embodiments mutually exclusive, unless so stated and except as will be readily apparent to those skilled in the art. Thus, the present invention can include any variety of combinations and/or integrations of the embodiments described herein.
- block diagrams illustrate exemplary embodiments of the invention.
- flow diagrams illustrate operations of the exemplary embodiments of the invention. The operations of the flow diagrams, will be described with reference to the exemplary embodiments shown in the block diagrams. However, it should be understood that the operations of the flow diagrams could be performed by embodiments of the invention other than those discussed with reference to the block diagrams, and embodiments discussed with references to the block diagrams could perform operations different than those discussed with reference to the flow diagrams.
- a generation and verification unit generates a configurable hardware system based on configuration data and a configurable hardware library.
- the configurable hardware system is made up of a number of units.
- the generation and verification unit hierarchically decomposes a configurable hardware system into units that make up the system design. Configuration data is applied to each unit so that it can be removed and verified or analyzed outside of the system without changing the unit itself.
- the generation and verification unit creates a testbench, tests, and controlling scripts for each unit.
- FIG. 1 is a block diagram for decomposing and verifying configurable hardware according to one embodiment of the invention.
- FIG. 1 includes a generation and verification unit 103 , which further includes a generation module 107 , decomposition module 109 , and verification module 111 .
- the generation and verification unit 103 is connected to a configurable hardware library 101 , and a configuration data storage unit 105 .
- the configuration data storage unit 105 includes configuration data 113 .
- the generation and verification unit 103 generates a configurable hardware system 104 and its constituent units (illustrated as units 1 -N).
- system refers to the composition of units at a particular hierarchy level, where details of the units are hidden. Therefore, at a particular level in a configurable hardware system design hierarchy, units are indivisible components. However, at lower hierarchy levels, the units from a higher level have their details and internal components exposed. For example, referring to FIG. 1 , at one design hierarchy level, the system 104 is viewed as a “black box” unit of a larger system, where the details about units 1 -N are concealed. However, at a lower design hierarchy level, the system 104 is viewed as including units 1 -N, where the unit connection details are exposed. At even lower levels of the configurable hardware system design hierarchy, the internal details of units 1 -N are exposed. At the lowest hierarchy level, a unit cannot be decomposed. The generation of system 104 and units 1 -N will be described in more detail below in FIG. 4 .
- the configuration data storage unit 105 includes configuration data 113 , which hierarchically describes a configurable hardware system.
- the configuration data 113 specifies the system and unit parameters at all relevant hierarchy levels. While the end user sets most parameters in the configuration data 113 , the generation and verification unit 103 sets some parameters during the hardware integration and/or decomposition process.
- the configuration data 113 may be represented by any suitable electronic design automation scripting language, according to embodiments of the invention. In one embodiment of the invention, the configuration data 113 is represented in the tool control language (TCL) scripting language.
- TCL tool control language
- the configuration data 113 may include a TCL text file defining a system design name, system-level parameters, unit-level names and parameters, unit-level connection parameters (e.g., number of wires in a signal bundle, handshaking protocols, pipelining behavior, etc.), and interface statements for binding unit instances to particular connections.
- this system information could be represented in the extensible markup language (XML) format or in a relational database.
- each unit instance is uniquely named in the configuration data 113 .
- different instances of the same unit can be configured differently. For example, one instance of a FIFO may be configured to have a depth of 10 bytes, while another instance of a FIFO may be configured to have a depth of 100 bytes.
- the configurable hardware library 101 describes all possible configurations of the system's hardware components.
- the configuration hardware library 101 may describe all possible configurations of a FIFO, including its depth, width, and other configurable parameters.
- the configurable hardware library includes hardware description language (HDL) code (e.g. Verilog or VHDL) embedded with preprocessing statements that describe how to interpret the configuration data 113 .
- HDL hardware description language
- FIG. 2 is a flow diagram illustrating the creation, decomposition, and verification of a configurable hardware system, according to embodiments of the invention.
- the operations of the flow diagram 200 will be described with reference to the block diagram of FIG. 1 .
- the configuration data is read.
- the generation module 107 of the generation and verification unit 103 reads the configuration data 113 from the configuration data storage unit 105 .
- the configuration data 113 may be a TCL file that hierarchically defines a configurable hardware system. Control continues at block 204 .
- the configurable hardware library is analyzed.
- the generation module 107 analyzes the configurable hardware library 101 to determine the possible configurations of the hardware components necessary for generating the hardware system defined by the configuration data 113 .
- Control continues at block 206 .
- a configurable hardware system is created.
- the generation module 107 creates a configurable hardware system based on the configuration data 113 and the configurable hardware library 101 .
- the operation of block 206 is further described below with reference to FIG. 3 .
- Control continues at block 208 .
- the system is decomposed and the system and its components are verified.
- the decomposition module 109 and the verification module 111 decompose and verify the system components. The operation in block 208 will be described in more detail below in the discussion of FIG. 5 .
- the operations described in the flow diagram 200 could be repeated for generating and verifying hardware at any level in the hierarchical system design. For example, to verify a system at a particular hierarchy level, all of the system's components must be verified. This may require verifying lower level systems, which may in turn require verifying even lower level systems. Once the lowest level system is verified, the higher level systems may in turn be verified. Hence, the operations set forth in the flow diagram 200 can be repeated for creating and verifying systems and/or components at any design hierarchy level.
- FIG. 3 is a flow diagram illustrating the creation of a system, according to embodiments of the invention. The operations of the flow diagram 300 will be described with reference to the exemplary embodiment illustrated in FIG. 1 .
- decision block 302 it is determined whether the configuration data conforms to rules for syntax and semantics.
- the integration module 109 determines whether configuration data 113 from the configuration data storage unit 105 conforms to rules for syntax and semantics.
- the integration module 109 determines whether the TCL file conforms to the syntax and semantics rules of the HDL used by the configurable hardware library 101 .
- the integration module 109 employs a high-level language program (e.g., a C++, Python, or Java program) to analyze a TCL file for syntax and semantics. If the configuration data file conforms to the syntax and semantics rules, control continues at block 304 . Otherwise, the flow ends with an error report. Control continues at block 304 .
- a high-level language program e.g., a C++, Python, or Java program
- parameters are derived.
- the integration module 109 derives system parameters from the configuration data 113 .
- the integration module 109 derives the system's parameters by analyzing a TCL file, which defines a configurable hardware system.
- a system parameter may specify the minimum bandwidth required for an internal communications path. From this setting, parameters for specifying the number of wires used at various connection points in the system are derived according to the rules in the configuration data. Control continues at block 306 .
- the preprocessing statements are configured based on the derived parameters.
- the integration module 109 configures HDL code preprocessing statements (stored in the configurable hardware library 101 ) that are affected by the specified and derived parameters. In doing this, the integration module 109 may impart particular values or control structures to preprocessor statements embedded in the HDL code. Control continues at block 308 .
- the HDL source code is preprocessed.
- the integration module 109 preprocesses the HDL source code that was configured according to the derived parameters.
- the integration module 109 includes a macro language preprocessor (e.g., a C preprocessor, an M4 preprocessor, or a SIMPLE preprocessor) for preprocessing the embedded HDL source code.
- a macro language preprocessor e.g., a C preprocessor, an M4 preprocessor, or a SIMPLE preprocessor
- the HDL code for the configurable hardware system specified in the configuration data is generated.
- the integration module 109 generates the HDL code for the system specified in the configuration data 113 using HDL code from the configurable hardware library 101 . From block 310 , control ends.
- FIG. 4 is a conceptual block diagram of a system design according to embodiments of the invention. As described above, according to an embodiment of the invention, the operations of FIG. 3 produce a system design represented in HDL code. FIG. 4 provides a graphical representation of such a system.
- FIG. 4 includes system 400 , which includes unit 1 , unit 2 , unit 3 , and unit 4 .
- unit 1 communicates to systems outside of the system 400 over a communication path 410 .
- Unit 1 is coupled to unit 2 and unit 3 with communication paths 401 and 403 , respectively.
- Unit 2 communicates with systems outside of system 400 through communication path 411 .
- Unit 3 is coupled to unit 4 with communication paths 405 and 408 .
- Unit 3 is also coupled to unit 2 with a communication path 409 .
- Unit 2 is an optional unit in the system 400 .
- Connection paths 401 and 409 are also optional.
- a unit or connection path is optional when it is unknown whether factors external to the system will require the optional unit's functionality (e.g., a system at a higher level in the design hierarchy).
- unit 2 would be optional if it's functionality were required by the first mode, but not by the second mode.
- FIGS. 5 and 6 illustrate how system 400 is decomposed and verified according to embodiments of the invention.
- FIG. 5 is a flow diagram illustrating operations for decomposing and verifying a configurable hardware system according to embodiments of the invention.
- FIG. 6 is a block diagram illustrating a testbench for verifying a unit according to embodiments of the invention. FIGS. 5 and 6 will be described with reference to the exemplary system of FIG. 4 and the exemplary embodiment of FIG. 1 .
- the configuration data 113 is mapped onto a selected unit's parameters.
- the decomposition module 109 maps the configuration data 113 defining system 400 onto the parameters of a unit of system 400 (e.g., unit 1 ).
- the decomposition module 109 analyzes the configuration data 113 to determine how unit 1 's parameters should be configured to meet the requirements of system 400 . Control continues at block 504 .
- the verification module 111 analyzes the configuration data 113 to determine the connections for the selected unit (e.g., unit 1 ).
- the decomposition module 109 couples a model to the unit, which may include an interface driver model, an interface monitor, and/or a protocol checker. This operation is conceptually illustrated in FIG. 6 .
- model A is connected to unit 1 through communication path 403
- model B is connected to unit 1 through communication path 401
- Model C is connected to unit 1 through communication path 410 .
- the test stimulus and response checking unit 415 is connected to models A, B, and C.
- the test stimulus and response checking unit 415 monitors and facilitates testing operations.
- models are used for sending and receiving information to the unit being verified.
- models A and B will receive streams of data from unit 1 according to unit 1 's parameters (e.g., according to the particular communication protocol defined for the particular communication path).
- model C will transmit data to unit 1 according to unit 1 's parameters.
- the particular data to be transmitted to and from the unit will be determined by the tests used for verifying the unit. These tests will be discussed in more detail below. From block 504 , control continues at block 506 .
- the configuration data is generated.
- decomposition module 109 generates configuration data 113 specifying the selected unit's parameters.
- the decomposition module 109 generates configuration data 113 in the form of a TCL file, as described above in the discussion of FIG. 1 .
- the decomposition module 109 generates configuration data 113 in the form of an XML file.
- a design based on the configuration data 113 is generated.
- the generation module 107 uses the configurable hardware library 101 to generate a configurable hardware system design based on the configuration data 113 . This operation is described in more detail above, in the discussion of FIG. 3 .
- the design is represented by HDL code. Control continues at block 510 .
- tests and scripts and/or inputs to an analysis tool are generated.
- the verification module 111 generates tests and scripts for running the tests and/or inputs to analysis tools. From block 510 , control continues at block 512 .
- the verification module 111 may use preexisting tests that are known to verify the functionality of a particular unit or it may generate customized tests based on an analysis of the unit configuration. These tests will exercise and verify the functionality of the configured unit being tested.
- the verification module 111 generates tests that are capable of verifying any configuration of the unit. In this embodiment, the tests read the configuration data 113 and modify their stimulus accordingly while the test is running, rather than before testing begins.
- the verification module 111 can also generate scripts for automatically performing the tests.
- the verification module 111 provides the design to an analysis tool, which performs a static analysis of the design.
- the verification module 111 provides the unit design represented by HDL code to a static verification tool that analyzes the HDL code for errors.
- the static verification tool generates warnings and or error messages based on its analysis of the HDL code.
- the scripts are executed.
- the verification module 111 executes the scripts, which automatically test and verify the selected unit.
- the generation and verification unit 103 , configurable hardware library 101 , and configuration data storage unit 105 may be implemented in the form of a conventional computing platform, including one or more processors, application specific integrated circuits (ASICs), memories, and/or machine readable media whereon instructions are stored for performing operations according to embodiments of the invention.
- Machine readable media includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine (e.g., a computer).
- a machine-readable medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.); etc.
- the units shown in FIG. 1 are machine readable media executing on a processor to carryout the operations described herein.
- the units of FIG. 1 are other types of logic (e.g., digital logic) for executing the operations described herein.
- the generation and verification unit 103 , configurable hardware library 101 , and configuration data storage unit 105 can include one or more separate computer systems. It should also be understood that, according to embodiments of the invention, the components illustrated in FIG. 1 could be distributed over a number of networked computers, wherein they could be remotely controlled and operated.
- FIG. 7 illustrates an exemplary system for decomposing and verifying configurable hardware, according to embodiments of the invention.
- computer system 700 comprises processor(s) 702 .
- Computer system 700 also includes a memory 732 , processor bus 710 and input/output controller hub (ICH) 740 .
- the processor(s) 702 , memory 732 and ICH 740 are coupled to the processor bus 710 .
- the processor(s) 702 may comprise any suitable processor architecture.
- computer system 700 may comprise one, two, three, or more processors, any of which may execute a set of instructions that are in accordance with embodiments of the present invention.
- the memory 732 stores data and/or instructions, and may comprise any suitable memory, such as a dynamic random access memory (DRAM), for example.
- DRAM dynamic random access memory
- the configuration hardware library 101 , generation and verification unit 103 , and configuration data storage unit 105 are stored in memory 732 . However, they may be stored in any or all IDE drive(s) 742 , memory 732 , and/or other suitable storage devices.
- a graphics controller 734 controls the display of information on a display device 737 , according to embodiments of the invention.
- the input/output controller hub (ICH) 740 provides an interface to I/O devices or peripheral components for computer system 700 .
- the ICH 740 may comprise any suitable interface controllers to provide for any suitable communication link to the processor(s) 702 , memory 732 and/or to any suitable device or component in communication with the ICH 740 .
- the ICH 740 provides suitable arbitration and buffering for each interface.
- the ICH 740 provides an interface to one or more suitable integrated drive electronics (IDE) drives 742 , such as a hard disk drive (HDD) or compact disc read only memory (CD ROM) drive for example, to store data and/or instructions for example, one or more suitable universal serial bus (USB) devices through one or more USB ports 744 .
- IDE integrated drive electronics
- the ICH 740 also provides an interface to a keyboard 751 , a mouse 752 , a floppy disk drive 755 , one or more suitable devices through one or more parallel ports 753 (e.g., a printer), and one or more suitable devices through one or more serial ports 754 .
- the ICH 740 also provides a network interface 756 though which the computer system 700 can communicate with other computer and/or devices.
- computer system 700 includes a machine-readable medium on which is stored a set of instructions (i.e., software) embodying any one, or all, of the methodologies described herein.
- software can reside, completely or at least partially, within memory 732 and/or within processor(s) 702 .
Abstract
Description
- The present invention pertains to hardware verification. More particularly, the present invention relates to verifying configurable hardware.
- “Configurable hardware” or “parameterized hardware” describes hardware systems that are customized automatically at design creation time by using specified values for a set of parameters or attributes. Such hardware may also support changes at run-time depending on parameter settings. Configurable hardware systems typically provide better performance than software running on a general-purpose computer system and greater flexibility than conventional application specific integrated circuits (ASICs) without increasing circuit size and cost.
- In conventional hardware systems, it is necessary to verify a system's functionality by testing the system and its components. Typically, the complexity of verifying a system's functionality increases with the number of components that make up the system. Therefore, the conventional approach is to manually verify each unit individually and then to assemble the “known good units” into a system. If hardware is hierarchically arranged, verification must be performed for each level in the hierarchy. If each individual unit has been verified before assembling the system, verifying system functionality can focus on potential problems with interactions between components rather than on each component's capabilities.
- Configurable hardware systems can be verified using this type of conventional hierarchical decomposition. However, because each instance of a configurable hardware system is different, each time a configuration parameter is modified, the system and its components must be manually verified. The cost of repeatedly manually verifying a system and its components often offsets the advantages of configurable hardware.
- The present invention includes a method and apparatus for decomposing and verifying configurable hardware. In one embodiment, the method includes automatically decomposing a hardware system into a set of one or more units, creating a testbench for each of the sets of units, and verifying each of the set of units before verifying the hardware system design.
- The present invention is illustrated by way of example and not limitation in the Figures of the accompanying drawings, in which like references indicate similar elements and in which:
-
FIG. 1 is a block diagram for decomposing and verifying configurable hardware according to one embodiment of the invention; -
FIG. 2 is a block diagram illustrating a system for creating and verifying configurable hardware according to one embodiment of the invention; -
FIG. 3 is a flow diagram illustrating the creation of a system, according to embodiments of the invention; -
FIG. 4 is a conceptual block diagram of a system design according to embodiments of the invention; -
FIG. 5 is a flow diagram illustrating operations for decomposing and verifying a configurable hardware system according to embodiments of the invention; -
FIG. 6 is a block diagram illustrating a testbench for verifying a unit according to embodiments of the invention; -
FIG. 7 illustrates an exemplary system for decomposing and verifying configurable hardware, according to embodiments of the invention; - A method and apparatus for decomposing and verifying configurable hardware are described. Note that in this description, references to “one embodiment” or “an embodiment” mean that the feature being referred to is included in at least one embodiment of the invention. Further, separate references to “one embodiment” in this description do not necessarily refer to the same embodiment; however, neither are such embodiments mutually exclusive, unless so stated and except as will be readily apparent to those skilled in the art. Thus, the present invention can include any variety of combinations and/or integrations of the embodiments described herein.
- Herein, block diagrams illustrate exemplary embodiments of the invention. Also herein, flow diagrams illustrate operations of the exemplary embodiments of the invention. The operations of the flow diagrams, will be described with reference to the exemplary embodiments shown in the block diagrams. However, it should be understood that the operations of the flow diagrams could be performed by embodiments of the invention other than those discussed with reference to the block diagrams, and embodiments discussed with references to the block diagrams could perform operations different than those discussed with reference to the flow diagrams.
- In one embodiment of the invention, a generation and verification unit generates a configurable hardware system based on configuration data and a configurable hardware library. The configurable hardware system is made up of a number of units. In one embodiment of the invention, the generation and verification unit hierarchically decomposes a configurable hardware system into units that make up the system design. Configuration data is applied to each unit so that it can be removed and verified or analyzed outside of the system without changing the unit itself. The generation and verification unit creates a testbench, tests, and controlling scripts for each unit.
-
FIG. 1 is a block diagram for decomposing and verifying configurable hardware according to one embodiment of the invention.FIG. 1 includes a generation andverification unit 103, which further includes ageneration module 107, decomposition module 109, and verification module 111. The generation andverification unit 103 is connected to aconfigurable hardware library 101, and a configurationdata storage unit 105. The configurationdata storage unit 105 includes configuration data 113. The generation andverification unit 103 generates aconfigurable hardware system 104 and its constituent units (illustrated as units 1-N). - In a configurable hardware system design hierarchy, the term “system” refers to the composition of units at a particular hierarchy level, where details of the units are hidden. Therefore, at a particular level in a configurable hardware system design hierarchy, units are indivisible components. However, at lower hierarchy levels, the units from a higher level have their details and internal components exposed. For example, referring to
FIG. 1 , at one design hierarchy level, thesystem 104 is viewed as a “black box” unit of a larger system, where the details about units 1-N are concealed. However, at a lower design hierarchy level, thesystem 104 is viewed as including units 1-N, where the unit connection details are exposed. At even lower levels of the configurable hardware system design hierarchy, the internal details of units 1-N are exposed. At the lowest hierarchy level, a unit cannot be decomposed. The generation ofsystem 104 and units 1-N will be described in more detail below inFIG. 4 . - The configuration
data storage unit 105 includes configuration data 113, which hierarchically describes a configurable hardware system. For example, the configuration data 113 specifies the system and unit parameters at all relevant hierarchy levels. While the end user sets most parameters in the configuration data 113, the generation andverification unit 103 sets some parameters during the hardware integration and/or decomposition process. The configuration data 113 may be represented by any suitable electronic design automation scripting language, according to embodiments of the invention. In one embodiment of the invention, the configuration data 113 is represented in the tool control language (TCL) scripting language. In particular, the configuration data 113 may include a TCL text file defining a system design name, system-level parameters, unit-level names and parameters, unit-level connection parameters (e.g., number of wires in a signal bundle, handshaking protocols, pipelining behavior, etc.), and interface statements for binding unit instances to particular connections. In an alternative embodiment of the invention, this system information could be represented in the extensible markup language (XML) format or in a relational database. - Because multiple instances of any particular hardware unit can be included in a hardware system, each unit instance is uniquely named in the configuration data 113. Moreover, different instances of the same unit can be configured differently. For example, one instance of a FIFO may be configured to have a depth of 10 bytes, while another instance of a FIFO may be configured to have a depth of 100 bytes.
- The
configurable hardware library 101 describes all possible configurations of the system's hardware components. For example, theconfiguration hardware library 101 may describe all possible configurations of a FIFO, including its depth, width, and other configurable parameters. In one embodiment of the invention, the configurable hardware library includes hardware description language (HDL) code (e.g. Verilog or VHDL) embedded with preprocessing statements that describe how to interpret the configuration data 113. -
FIG. 2 is a flow diagram illustrating the creation, decomposition, and verification of a configurable hardware system, according to embodiments of the invention. The operations of the flow diagram 200 will be described with reference to the block diagram ofFIG. 1 . Atprocess block 202, the configuration data is read. For example, according to the embodiment of the invention illustrated inFIG. 1 , thegeneration module 107 of the generation andverification unit 103 reads the configuration data 113 from the configurationdata storage unit 105. As noted above, the configuration data 113 may be a TCL file that hierarchically defines a configurable hardware system. Control continues atblock 204. - At
block 204, the configurable hardware library is analyzed. For example, thegeneration module 107 analyzes theconfigurable hardware library 101 to determine the possible configurations of the hardware components necessary for generating the hardware system defined by the configuration data 113. Control continues atblock 206. - As shown in
block 206, a configurable hardware system is created. For example, thegeneration module 107 creates a configurable hardware system based on the configuration data 113 and theconfigurable hardware library 101. The operation ofblock 206 is further described below with reference toFIG. 3 . Control continues atblock 208. - At
block 208, the system is decomposed and the system and its components are verified. For example, the decomposition module 109 and the verification module 111 decompose and verify the system components. The operation inblock 208 will be described in more detail below in the discussion ofFIG. 5 . - It should be evident to one of ordinary skill in the art that the operations described in the flow diagram 200 could be repeated for generating and verifying hardware at any level in the hierarchical system design. For example, to verify a system at a particular hierarchy level, all of the system's components must be verified. This may require verifying lower level systems, which may in turn require verifying even lower level systems. Once the lowest level system is verified, the higher level systems may in turn be verified. Hence, the operations set forth in the flow diagram 200 can be repeated for creating and verifying systems and/or components at any design hierarchy level.
-
FIG. 3 is a flow diagram illustrating the creation of a system, according to embodiments of the invention. The operations of the flow diagram 300 will be described with reference to the exemplary embodiment illustrated inFIG. 1 . Atdecision block 302, it is determined whether the configuration data conforms to rules for syntax and semantics. For example, the integration module 109 determines whether configuration data 113 from the configurationdata storage unit 105 conforms to rules for syntax and semantics. As a more specific example, in an embodiment where the configuration data 113 is represented by a TCL text file, the integration module 109 determines whether the TCL file conforms to the syntax and semantics rules of the HDL used by theconfigurable hardware library 101. In one embodiment, the integration module 109 employs a high-level language program (e.g., a C++, Python, or Java program) to analyze a TCL file for syntax and semantics. If the configuration data file conforms to the syntax and semantics rules, control continues atblock 304. Otherwise, the flow ends with an error report. Control continues atblock 304. - At
block 304, parameters are derived. For example, the integration module 109 derives system parameters from the configuration data 113. As a more specific example, in one embodiment, the integration module 109 derives the system's parameters by analyzing a TCL file, which defines a configurable hardware system. For example, a system parameter may specify the minimum bandwidth required for an internal communications path. From this setting, parameters for specifying the number of wires used at various connection points in the system are derived according to the rules in the configuration data. Control continues atblock 306. - As shown in
block 306, the preprocessing statements are configured based on the derived parameters. For example, in one embodiment of the invention, the integration module 109 configures HDL code preprocessing statements (stored in the configurable hardware library 101) that are affected by the specified and derived parameters. In doing this, the integration module 109 may impart particular values or control structures to preprocessor statements embedded in the HDL code. Control continues atblock 308. - As shown in
block 308, the HDL source code is preprocessed. For example, the integration module 109 preprocesses the HDL source code that was configured according to the derived parameters. In one embodiment of the invention, the integration module 109 includes a macro language preprocessor (e.g., a C preprocessor, an M4 preprocessor, or a SIMPLE preprocessor) for preprocessing the embedded HDL source code. Control continues atblock 310. - At
block 310, the HDL code for the configurable hardware system specified in the configuration data is generated. For example, the integration module 109 generates the HDL code for the system specified in the configuration data 113 using HDL code from theconfigurable hardware library 101. Fromblock 310, control ends. -
FIG. 4 is a conceptual block diagram of a system design according to embodiments of the invention. As described above, according to an embodiment of the invention, the operations ofFIG. 3 produce a system design represented in HDL code.FIG. 4 provides a graphical representation of such a system.FIG. 4 includessystem 400, which includesunit 1,unit 2,unit 3, andunit 4. Insystem 400,unit 1 communicates to systems outside of thesystem 400 over acommunication path 410.Unit 1 is coupled tounit 2 andunit 3 withcommunication paths Unit 2 communicates with systems outside ofsystem 400 throughcommunication path 411.Unit 3 is coupled tounit 4 withcommunication paths Unit 3 is also coupled tounit 2 with acommunication path 409. -
Unit 2, illustrated with broken lines, is an optional unit in thesystem 400.Connection paths system 400 could be configured to operate in two different modes,unit 2 would be optional if it's functionality were required by the first mode, but not by the second mode. -
FIGS. 5 and 6 illustrate howsystem 400 is decomposed and verified according to embodiments of the invention.FIG. 5 is a flow diagram illustrating operations for decomposing and verifying a configurable hardware system according to embodiments of the invention.FIG. 6 is a block diagram illustrating a testbench for verifying a unit according to embodiments of the invention.FIGS. 5 and 6 will be described with reference to the exemplary system ofFIG. 4 and the exemplary embodiment ofFIG. 1 . - Referring to the flow diagram of
FIG. 5 , at block 502, the configuration data 113 is mapped onto a selected unit's parameters. For example, the decomposition module 109 maps the configuration data 113 definingsystem 400 onto the parameters of a unit of system 400 (e.g., unit 1). As a more specific example, the decomposition module 109 analyzes the configuration data 113 to determine howunit 1's parameters should be configured to meet the requirements ofsystem 400. Control continues atblock 504. - At
block 504, for each connection to other units, interface models, monitors, and/or protocol checkers are added to the unit. For example, the verification module 111 analyzes the configuration data 113 to determine the connections for the selected unit (e.g., unit 1). For each connection (e.g., communication path), the decomposition module 109 couples a model to the unit, which may include an interface driver model, an interface monitor, and/or a protocol checker. This operation is conceptually illustrated inFIG. 6 . InFIG. 6 , model A is connected tounit 1 throughcommunication path 403, while model B is connected tounit 1 throughcommunication path 401. Model C is connected tounit 1 throughcommunication path 410. The test stimulus and response checking unit 415 is connected to models A, B, and C. The test stimulus and response checking unit 415 monitors and facilitates testing operations. In the testbench, models are used for sending and receiving information to the unit being verified. For example, models A and B will receive streams of data fromunit 1 according tounit 1's parameters (e.g., according to the particular communication protocol defined for the particular communication path). Similarly, model C will transmit data tounit 1 according tounit 1's parameters. The particular data to be transmitted to and from the unit will be determined by the tests used for verifying the unit. These tests will be discussed in more detail below. Fromblock 504, control continues at block 506. - At block 506, the configuration data is generated. For example, decomposition module 109 generates configuration data 113 specifying the selected unit's parameters. According to one embodiment of the invention, the decomposition module 109 generates configuration data 113 in the form of a TCL file, as described above in the discussion of
FIG. 1 . According to an alternative embodiment, the decomposition module 109 generates configuration data 113 in the form of an XML file. - At block 508, a design based on the configuration data 113 is generated. For example, the
generation module 107 uses theconfigurable hardware library 101 to generate a configurable hardware system design based on the configuration data 113. This operation is described in more detail above, in the discussion ofFIG. 3 . In one embodiment, the design is represented by HDL code. Control continues atblock 510. - At
block 510, tests and scripts and/or inputs to an analysis tool are generated. For example, the verification module 111 generates tests and scripts for running the tests and/or inputs to analysis tools. Fromblock 510, control continues atblock 512. In generating the tests, the verification module 111 may use preexisting tests that are known to verify the functionality of a particular unit or it may generate customized tests based on an analysis of the unit configuration. These tests will exercise and verify the functionality of the configured unit being tested. According to an embodiment of the invention, the verification module 111 generates tests that are capable of verifying any configuration of the unit. In this embodiment, the tests read the configuration data 113 and modify their stimulus accordingly while the test is running, rather than before testing begins. The verification module 111 can also generate scripts for automatically performing the tests. - As an additional or alternative form of testing, the verification module 111 provides the design to an analysis tool, which performs a static analysis of the design. For example, according to one embodiment of the invention, the verification module 111 provides the unit design represented by HDL code to a static verification tool that analyzes the HDL code for errors. In one embodiment, the static verification tool generates warnings and or error messages based on its analysis of the HDL code.
- As shown in
block 512, the scripts are executed. For example, the verification module 111 executes the scripts, which automatically test and verify the selected unit. - It should be apparent to one of ordinary skill in the art that the operations described in the flow diagram of
FIG. 5 can be repeated to verify any unit/system at any level in a design hierarchy. - Referring to
FIG. 1 , the generation andverification unit 103,configurable hardware library 101, and configurationdata storage unit 105 may be implemented in the form of a conventional computing platform, including one or more processors, application specific integrated circuits (ASICs), memories, and/or machine readable media whereon instructions are stored for performing operations according to embodiments of the invention. Machine readable media includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.); etc. In one embodiment, the units shown inFIG. 1 are machine readable media executing on a processor to carryout the operations described herein. However, in alternative embodiments, the units ofFIG. 1 are other types of logic (e.g., digital logic) for executing the operations described herein. Alternatively, according to one embodiment of the invention, the generation andverification unit 103,configurable hardware library 101, and configurationdata storage unit 105 can include one or more separate computer systems. It should also be understood that, according to embodiments of the invention, the components illustrated inFIG. 1 could be distributed over a number of networked computers, wherein they could be remotely controlled and operated. -
FIG. 7 illustrates an exemplary system for decomposing and verifying configurable hardware, according to embodiments of the invention. As illustrated inFIG. 7 ,computer system 700 comprises processor(s) 702.Computer system 700 also includes amemory 732, processor bus 710 and input/output controller hub (ICH) 740. The processor(s) 702,memory 732 andICH 740 are coupled to the processor bus 710. The processor(s) 702 may comprise any suitable processor architecture. For other embodiments of the invention,computer system 700 may comprise one, two, three, or more processors, any of which may execute a set of instructions that are in accordance with embodiments of the present invention. - The
memory 732 stores data and/or instructions, and may comprise any suitable memory, such as a dynamic random access memory (DRAM), for example. In one embodiment of the invention, theconfiguration hardware library 101, generation andverification unit 103, and configurationdata storage unit 105 are stored inmemory 732. However, they may be stored in any or all IDE drive(s) 742,memory 732, and/or other suitable storage devices. Agraphics controller 734 controls the display of information on adisplay device 737, according to embodiments of the invention. - The input/output controller hub (ICH) 740 provides an interface to I/O devices or peripheral components for
computer system 700. TheICH 740 may comprise any suitable interface controllers to provide for any suitable communication link to the processor(s) 702,memory 732 and/or to any suitable device or component in communication with theICH 740. For one embodiment of the invention, theICH 740 provides suitable arbitration and buffering for each interface. - For one embodiment of the invention, the
ICH 740 provides an interface to one or more suitable integrated drive electronics (IDE) drives 742, such as a hard disk drive (HDD) or compact disc read only memory (CD ROM) drive for example, to store data and/or instructions for example, one or more suitable universal serial bus (USB) devices through one or more USB ports 744. For one embodiment of the invention, theICH 740 also provides an interface to akeyboard 751, a mouse 752, afloppy disk drive 755, one or more suitable devices through one or more parallel ports 753 (e.g., a printer), and one or more suitable devices through one or moreserial ports 754. For one embodiment of the invention, theICH 740 also provides anetwork interface 756 though which thecomputer system 700 can communicate with other computer and/or devices. - Accordingly,
computer system 700 includes a machine-readable medium on which is stored a set of instructions (i.e., software) embodying any one, or all, of the methodologies described herein. For example, software can reside, completely or at least partially, withinmemory 732 and/or within processor(s) 702. - While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described. The method and apparatus of the invention can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting on the invention.
Claims (14)
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US7299155B2 (en) | 2007-11-20 |
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EP1563386A1 (en) | 2005-08-17 |
JP2006506710A (en) | 2006-02-23 |
US6816814B2 (en) | 2004-11-09 |
US20050198611A1 (en) | 2005-09-08 |
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