US20050106790A1 - Strained silicon on a SiGe on SOI substrate - Google Patents
Strained silicon on a SiGe on SOI substrate Download PDFInfo
- Publication number
- US20050106790A1 US20050106790A1 US10/706,061 US70606103A US2005106790A1 US 20050106790 A1 US20050106790 A1 US 20050106790A1 US 70606103 A US70606103 A US 70606103A US 2005106790 A1 US2005106790 A1 US 2005106790A1
- Authority
- US
- United States
- Prior art keywords
- layer
- substrate
- forming
- channel
- void
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 47
- 229910052710 silicon Inorganic materials 0.000 title claims description 31
- 239000010703 silicon Substances 0.000 title claims description 30
- 229910000577 Silicon-germanium Inorganic materials 0.000 title abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 45
- 239000012212 insulator Substances 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052681 coesite Inorganic materials 0.000 claims abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract 2
- 239000000377 silicon dioxide Substances 0.000 claims abstract 2
- 229910052682 stishovite Inorganic materials 0.000 claims abstract 2
- 229910052905 tridymite Inorganic materials 0.000 claims abstract 2
- 229910006990 Si1-xGex Inorganic materials 0.000 claims description 87
- 229910007020 Si1−xGex Inorganic materials 0.000 claims description 87
- 238000000034 method Methods 0.000 claims description 68
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 34
- 239000011800 void material Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 17
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 14
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 claims description 12
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000012545 processing Methods 0.000 claims description 8
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 3
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 230000008719 thickening Effects 0.000 claims 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims 1
- 229910017604 nitric acid Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 151
- 230000008569 process Effects 0.000 description 28
- 235000012431 wafers Nutrition 0.000 description 17
- 230000015572 biosynthetic process Effects 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 229910052732 germanium Inorganic materials 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
Definitions
- the invention generally relates to a semiconductor device and method of manufacture and, more particularly, to a semiconductor device that includes strained silicon on a SiGe on a silicon-on-insulator substrate.
- One technique involves introducing strain.
- Strained silicon exhibits improved semiconductor performance due to enhanced transport properties.
- Biaxial distortion of the crystal lattice in strained silicon improves electron and hole mobility.
- Another performance enhancement technique involves providing a semiconductor layer separated from the substrate by an insulating layer. Also known as silicon-on-insulator (SOI), such structures exhibit reduced parasitic capacitance, thereby enabling a semiconductor to function at significantly higher speeds with reduced electrical losses. The result is an appreciable increase in performance and a reduction in power consumption.
- SOI silicon-on-insulator
- the SIMOX method entails implantation of very high doses of oxygen ions at high energy. Upon annealing, the oxygen forms an oxide layer under the surface of the semiconductor. A problem with SIMOX is that it is relatively costly procedure. Another problem is that the high SIMOX annealing temperature (1350° C.) limits the concentration of germanium in SiGe-on-insulator substrates. For wafer bonding, which is another method, there are several technical hurdles including optimization of chemical mechanical polish, bonding conditions and the reduction in dislocation density.
- the invention is directed to overcoming one or more of the problems as set forth above.
- the invention solves the problems and/or overcomes the drawbacks and disadvantages of the prior art by providing a semiconductor device with an undercut relaxed SiGe layer. Voids beneath the SiGe layer are filled with dielectric. A strained Si layer is formed on the relaxed SiGe layer. The resulting semiconductor structure thus combines the benefits of a defect-free strained Si surface and a silicon-on-insulator substrate.
- a method of fabricating a semiconductor structure entails forming a Si 1-x Ge x layer on a substrate. A plurality of channels is then formed in the Si 1-x Ge x layer and the substrate. Next, a portion of the substrate underneath the Si 1-x Ge x layer is removed to form a void in the substrate. The SiGe layer above the void is relaxed. The void and channels are then filled with a dielectric material. A strained Si layer may subsequently be formed on the relaxed SiGe layer.
- the method includes forming a Si 1-x Ge x layer on a silicon-on-insulator substrate having a first silicon layer, a second SiO 2 layer and a substrate.
- a first channel and a second channel are formed. Each channel extends through the Si 1-x Ge x layer to the bottom of the first silicon layer of the substrate.
- the first channel and second channel are substantially parallel.
- the Si 1-x Ge x layer is undercut to form a void in the first silicon layer of the substrate from the first channel to the second channel.
- the first and second channels and the void are filled with a dielectric material.
- a strained silicon layer is formed on the Si 1-x Ge x layer.
- an intermediate semiconductor structure is formed on a substrate.
- the structure includes a semiconductor substrate and a relaxed Si 1-x Ge x portion on a semiconductor substrate.
- the relaxed Si 1-x Ge x portion includes one or more channel or trench regions.
- the structure includes at least one void between the Si 1-x Ge x portion and the substrate. Voids beneath the Si 1-x Ge x layer may be formed by undercutting. The voids may subsequently be filled with dielectric.
- the semiconductor structure includes a first layer comprised of a strained semiconductor.
- a second layer comprised of Si 1-x Ge x is provided beneath the first layer.
- a third layer comprised of a silicon portion and a dielectric portion is provided beneath the second Si 1-x Ge x layer.
- a fourth layer comprised of an insulator is provided beneath the third layer.
- a fifth layer comprised of a substrate is provided beneath the fourth layer.
- FIG. 1 shows a silicon-on-insulator wafer for use in accordance with the principles of the invention
- FIG. 2 shows a semiconductor structure with a top layer of SiGe in accordance with the principles of the invention
- FIG. 3 shows a semiconductor structure with a layer of SiGe capped with a dielectric layer and trenches in accordance with the principles of the invention
- FIG. 4 shows a semiconductor structure with a layer of SiGe capped with a dielectric layer and having trenches in accordance with the principles of the invention
- FIG. 5 shows a semiconductor structure with a layer of SiGe capped with a dielectric layer, trenches, and an undercut SiGe island in accordance with the principles of the invention
- FIG. 6 shows a top view of a cut away section of a structure capped with a dielectric layer, trenches and an undercut SiGe island in accordance with the principles of the invention
- FIG. 7 shows a semiconductor structure that is capped with a dielectric layer and has an underlying layer of SiGe, trenches and an undercut area filled with dielectric in accordance with the principles of the invention
- FIG. 8 shows a semiconductor structure with a layer of SiGe, trenches and an undercut area filled with dielectric, and dielectric extending vertically above the surface of the SiGe layer into a layer that previously included a dielectric cap;
- FIG. 9 shows a semiconductor structure with a top layer of strained semiconductor layer formed selectively on SiGe in accordance with the principles of the invention.
- FIG. 10 shows a semiconductor structure with a top layer of strained silicon formed non-selectively over the entire surface in accordance with the principles of the invention
- FIG. 11 shows a field effect transistor formed on a semiconductor structure in accordance with the principles of the invention.
- FIG. 12 is a flowchart of a method for producing a strained silicon layer on a SiGe-on-insulator substrate in accordance with the principles of the invention.
- the invention enables fabrication of a strained silicon layer on a SiGe-on-insulator substrate.
- An exemplary methodology in accordance with the invention entails undercutting a SiGe layer to form a relaxed SiGe island, filling the voids with a dielectric and epitaxially growing Si on the relaxed SiGe.
- the strained Si thus formed can be free of dislocations and misfits.
- the resulting structure can also be fabricated cost effectively using conventional processing equipment and materials. Additionally, the structure allows a thin SiGe layer, which enables shallow junctions and enhanced device performance.
- a silicon-on-insulator (SOI) wafer is shown.
- SOI silicon-on-insulator
- the wafer includes a buried silicon oxide (BOX) layer 120 extending across the entire wafer, just below a thin (e.g., 5 to 200 nm) surface layer of device-quality single-crystal silicon 130 .
- the BOX layer 120 provides robust vertical isolation from the substrate 110 .
- the substrate 110 may be silicon, germanium, silicon germanium, aluminum oxide, or any other suitable semiconductor or insulator.
- Providing an SOI wafer is a first step 1210 of an exemplary process flow as shown in the flowchart of FIG. 12 .
- the SOI wafer may be fabricated using any of various techniques known in the art.
- the SOI wafer may be fabricated using the SIMOX (Separation by IMplanted OXygen) process, which employs high dose ion implantation of oxygen and high temperature annealing to form the BOX layer in a bulk wafer.
- the SOI wafer can be fabricated by bonding a device quality silicon wafer to another wafer (the substrate layer) that has an oxide layer on its surface. The pair is then split apart, using a process that leaves a thin (relative to the thickness of the starting wafer), device-quality layer of single crystal silicon on top of the oxide layer (which has now become the BOX) on the substrate layer.
- the SOI wafer may also be formed using other processes. The method of fabricating the SOI wafer is not critical to this invention.
- a thin device-quality silicon germanium layer (SiGe or Si 1-x Ge x ) 210 is formed on the device-quality single-crystal silicon layer 130 .
- the Si 1-x Ge x layer 210 may be deposited or grown on the Si layer using conventional techniques such as chemical vapor deposition methods.
- UHVCVD ultrahigh vacuum chemical vapor deposition
- Other conventional techniques include rapid thermal chemical vapor deposition (RTCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD) and molecular beam epitaxy (MBE).
- RTCVD rapid thermal chemical vapor deposition
- LPCVD low-pressure chemical vapor deposition
- LPCVD limited reaction processing CVD
- MBE molecular beam epitaxy
- Growth of a Si 1-x Ge x layer is a second step 1220 of an exemplary process flow in accordance with the principles of the invention as shown in FIG. 12 .
- the thickness of the Si 1-x Ge x layer 210 is below the critical thickness, as is known in the art.
- the critical thickness which depends upon parameters such as growth rate, growth temperature, germanium concentration and the thickness of the underneath silicon layer, is the thickness beyond which defects such as dislocations and misfits form.
- a thickness of approximately 5 to 100 nm would be less than the critical thickness for many fabrications.
- a cap layer 310 may be formed on the Si 1-x Ge x layer 210 .
- the cap layer 310 protects the top surface of the Si 1-x Ge x layer 210 from etching as described more filly below.
- the cap layer 310 may be comprised of a dielectric material such as silicon nitride (Si 3 N 4 ) or Si 3 N 4 atop an oxide (SiO 2 ) layer.
- the Si 3 N 4 layer may be approximately 20 nm to 100 nm thick. If the cap 210 includes a SiO 2 layer, the SiO 2 layer may be approximately 3 nm to 20 nm thick.
- the SiO 2 and Si 3 N 4 layer may be formed by thermal growth on the Si 1-x Ge x layer 210 or by a conventional deposition technique such as low pressure CVD, plasma-assisted CVD, high-density plasma CVD or other suitable processes.
- the cap layer 310 is shown as a single layer in FIG. 3 .
- Cap formation is a third step 1230 of an exemplary process flow in accordance with the principles of the invention as shown in FIG. 12 .
- channels or trenches 410 and 420 are formed in the cap 310 , Si 1-x Ge x 210 and silicon 130 layers, stopping on the BOX layer 120 , using conventional dry or wet etching processes.
- a conventional photoresist mask (not shown), combined with an optional hardmask (not shown), for example, SiO 2 , may be formed atop the cap layer 310 .
- the photoresist mask may be patterned utilizing conventional lithography including resist exposure and development.
- Trenches 410 and 420 are formed using the patterned photoresist and conventional etching such as dry etching processes, e.g., reactive ion etching (RIE), ion-beam etching, plasma-etching or any combination thereof.
- Photoresist may be stripped after etching the hardmask, after etching the cap layer or after etching the entire trenches. The remaining SiO 2 hardmask, if any, may be stripped after forming the trenches.
- the trenches 410 and 420 are dimensioned and spaced to accommodate active regions of the device. Spacing between trenches may, for example, be approximately 100 to 200 nm.
- Trench or channel formation is a fourth step 1240 of an exemplary process flow in accordance with the principles of the invention as shown in FIG. 12 .
- a portion of the SOI beneath the Si 1-x Ge x 210 layer is removed to form a void 520 beneath the Si 1-x Ge x layer 210 .
- the portion 510 of the Si 1-x G ex layer 210 above the void 520 and between the trenches 410 and 420 becomes relaxed upon removal of the underlying SOI.
- the SOI may be removed using a conventional selective timed etching process, such as an ammonia, ammonia-based etchant (e.g., tetramethyl ammonium hydroxide (TMAH)), or a mixture of nitric and hydrofluoric acids, for example.
- TMAH tetramethyl ammonium hydroxide
- the etch time is predetermined by the etch rate and the spacing between the trenches.
- the etch rate which depends heavily upon various factors including concentration, temperature and crystallographic orientation, may vary from approximately 0.01 to 1.5 ⁇ m/minute.
- the difference in etch rate between Si 1-x Ge x and pure silicon is attributed to the change in energy band structure by the addition of germanium.
- the composition of the Si 1-x Ge x layer 210 may be engineered, such that the bottom surface is considerably more resistant to the etchant than the remaining portion of the Si 1-x Ge x layer 210 .
- the bottom surface may (or may not) have a higher germanium concentration.
- the cap layer 310 protects the top surface of the Si 1-x Ge x layer 210 from being etched in the process of removing the SOI layer.
- the timed etch proceeds for sufficient time to remove enough SOI from below the Si 1-x Ge x layer 210 to form a relaxed Si 1-x Ge x portion 510 that is large enough to define or include an active area.
- the removal of SOI also referred to as undercutting, is a fifth step 1250 of an exemplary process flow in accordance with the principles of the invention as shown in FIG. 12 .
- FIG. 6 a top view of a portion of the structure with cap layer 310 over the Si 1-x Ge x layer 210 is shown. Channels 410 and 420 extend parallel or substantially parallel to each other.
- the dashed border 610 conceptually defines a portion undercut beneath the relaxed Si 1-x Ge x island 510 . Un-etched SOI of layer 130 remains outside of the dashed border 610 , thus providing structural support beneath the Si 1-x Ge x layer 210 . Within the dashed border 610 , SOI from layer 130 has been removed by etching as described above. While the dashed border 610 exhibits a square or rectangular shape as shown in FIG.
- etching may proceed in all directions, possibly at uneven rates depending upon the etchant, etching parameters, crystallographic orientation, and etched material.
- the invention is not limited to an etching border of any particular shape.
- the Si 1-x Ge x layer 210 may be thermally annealed at a temperature of about 600 to 900° C. to ensure that it is relaxed.
- the anneal can be either a furnace anneal, which may require several minutes, or a rapid thermal anneal (RTA), which may require 1 to 100 seconds.
- RTA rapid thermal anneal
- the trenches and undercut areas are filled with a dielectric, such as SiO 2 710, as shown in FIG. 7 .
- the dielectric may be applied in a conventional manner, such as by using an atmospheric CVD process, a low-pressure CVD process or a high-density plasma CVD process, or other suitable methodologies.
- SiO 2 exhibits good isotropic properties, even the void 520 beneath the Si 1-x Ge x island 510 may be filled.
- the surface may then be planarized to remove the excess SiO 2 and leave the vertical channel portions 720 and 730 of the SiO 2 substantially planar with the cap layer 310 .
- the planarization may be achieved by chemically mechanical polishing (CMP) or other suitable planarization methods.
- CMP chemically mechanical polishing
- the filling of trenches and undercut voids is a sixth step 1260 of an exemplary process flow in accordance with the principles of the invention as shown in FIG. 12 .
- the cap layer 310 is removed to expose the relaxed Si 1-x Ge x layer 210 .
- a conventional wet or dry etch may be performed to remove the cap layer, leaving behind the vertical channel portions 720 and 730 of the SiO 2 .
- a plurality of wet or dry etch steps may be performed to remove the material.
- Si 3 N 4 in the cap layer may be etched by a mixture of hydrofluoric and ethylene glycol (HF/EG), or hot phosphoric acid (H 3 PO 4 ).
- SiO 2 if previously formed in the cap layer, may be etched by buffered hydrofluoric (BHF) or diluted hydrofluoric (DHF).
- the SiO 2 in the cap layer may be stripped along with Si 3 N 4 by a single step of HF/EG etch.
- the vertical channel portions 720 and 730 that extend above the Si 1-x Ge x layer 210 may (or may not) be removed.
- the removal of the cap is a seventh step 1270 of an exemplary process flow in accordance with the principles of the invention as shown in FIG. 12 .
- a strained Si layer 910 is formed on the relaxed Si 1-x Ge x layer 210 .
- the strained Si layer may be formed epitaxially on the relaxed Si 1-x Ge x layer 210 using conventional techniques.
- UHVCVD ultrahigh vacuum chemical vapor deposition
- Other suitable techniques include rapid thermal chemical vapor deposition (RTCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD) and molecular beam epitaxy (MBE).
- RTCVD rapid thermal chemical vapor deposition
- LPCVD low-pressure chemical vapor deposition
- LPCVD limited reaction processing CVD
- MBE molecular beam epitaxy
- an epitaxial growth or deposition of additional Si 1-x Ge x may be performed after the cap layer 310 is removed and before formation of the strained Si layer 910 .
- the strained Si layer 910 may then be formed on the thick Si 1-x Ge x layer.
- Si has a smaller lattice constant (i.e., atom spacing) than Ge
- the Si is strained in tension. Due to enhanced mobility of electrons and holes, the strained Si layer provides an attractive platform for fabricating high performance integrated circuits. For example, nFET mobility increases substantially with strain, with the enhancement beginning to saturate at higher strain (e.g., greater than 1.3%).
- pFET mobility initially exhibits a slight degradation at low amount of tensile strain, but increases linearly with higher strain.
- FIG. 9 shows an embodiment in which the strained Si layer 910 is grown selectively on Si 1-x Ge x layer 210 , not on the vertical channel portion 720 and 730 of the SiO 2 , using a process such as molecular beam epitaxy.
- FIG. 10 shows an alternative embodiment in which the strained Si layer 910 is formed in a non-selective manner over the entire surface. In this case, the Si layer 910 also includes the portion 1010 formed above the vertical channel portions 720 and 730 of the SiO 2 .
- the surface may be planarized by chemical mechanical polishing (CMP) or any other suitable processes.
- CMP chemical mechanical polishing
- Si 1-y C y carbon-doped silicon
- the value of y in Si 1-y C y may, by way of example, be approximately 0.001 to 0.02.
- the layer 710 is referred to and shown as a strained Si layer or Si layer hereinafter.
- a suitable thickness for the strained Si layer 910 is below the critical thickness, which is the maximum thickness that strained Si can grow on the Si 1-x Ge x layer 210 without forming defects in the crystal structure (e.g., dislocations).
- the strained Si layer 910 may be approximately 5 to 100 nm thick.
- the epitaxial growth of the Si layer 910 is an eighth step 1280 of an exemplary process flow in accordance with the principles of the invention as shown in FIG. 12 .
- the structures formed, as shown in FIGS. 4 through 10 are intermediate structures that accommodate formation of semiconductor devices, such as pFETs and nFETs, in accordance with the principles of the invention.
- One intermediate structure exhibits a void 520 undercut beneath a portion (e.g., island) 510 of the Si 1-x Ge x layer to relax the undercut Si 1-x Ge x portion, as shown in FIG. 5 .
- Another intermediate structure exhibits a thin strained semiconductor layer (e.g., a Si layer) 910 epitaxially grown on the Si 1-x Ge x layer 210 , as shown in FIG. 9 .
- the intermediate structures thus combine the benefits of a thin strained semiconductor layer with the benefits of SOI.
- the undercutting step obviates the need for costly and potentially problematic process steps, such as SIMOX or wafer bonding, to create the relaxed Si 1-x Ge x layer on SiO 2 .
- the formation of a thin strained Si layer 910 on the relaxed Si 1-x Ge x layer 210 is less conducive to defect formation in the strained Si layer 910 , than in conventional processes.
- CMOS processes may be performed to form devices such as field effect transistors on the structure as shown in FIG. 11 .
- the device includes source 1110 and drain 1120 regions separated by a strained Si channel 1160 situated on a Si 1-x Ge x layer 1170 .
- a gate oxide 1150 is provided atop the strained Si channel 1160
- a gate conductor 1180 is provided on top of the gate oxide 1150 .
- Spacers 1130 and 1140 are also provided. These components are found in typical field effect transistors and further explanation is not needed for one of ordinary skill in the art to readily understand the fabrication process of the FET device.
- Active device formation is a final step 1290 of an exemplary process flow in accordance with the principles of the invention as shown in FIG. 12 .
- a process according to the principles of the invention may include steps in addition to those described above and illustrated in the flowchart of FIG. 12 .
- a strained Si or Si 1-y C y on Si 1-x Ge x structure formed according to the principles of the invention may be used to support various integrated circuit devices, including devices other than the field effect transistor shown in FIG. 11 .
- the invention provides a semiconductor device with an undercut relaxed SiGe layer. Voids beneath the SiGe layer may be filled with dielectric. A strained Si layer may be deposited on the relaxed SiGe layer.
- the resulting semiconductor structure combines the benefits of a defect-free strained Si surface and a silicon-on-insulator substrate. The structure may be fabricated cost effectively using conventional processing equipment and materials. Additionally, because the relaxed SiGe layer may be relatively thin, the structure accommodates shallow junctions which reduce junction capacitance.
Abstract
Description
- 1. Field of the Invention
- The invention generally relates to a semiconductor device and method of manufacture and, more particularly, to a semiconductor device that includes strained silicon on a SiGe on a silicon-on-insulator substrate.
- 2. Background Description
- Various techniques have emerged to improve performance of state of the art semiconductors. One technique involves introducing strain. Strained silicon exhibits improved semiconductor performance due to enhanced transport properties. Biaxial distortion of the crystal lattice in strained silicon improves electron and hole mobility.
- Another performance enhancement technique involves providing a semiconductor layer separated from the substrate by an insulating layer. Also known as silicon-on-insulator (SOI), such structures exhibit reduced parasitic capacitance, thereby enabling a semiconductor to function at significantly higher speeds with reduced electrical losses. The result is an appreciable increase in performance and a reduction in power consumption.
- By combining strained silicon with SOI the substantial benefits of both technologies may be realized. Unfortunately, however, current methods for forming strained silicon on SOI suffer drawbacks. One such method, the SIMOX method entails implantation of very high doses of oxygen ions at high energy. Upon annealing, the oxygen forms an oxide layer under the surface of the semiconductor. A problem with SIMOX is that it is relatively costly procedure. Another problem is that the high SIMOX annealing temperature (1350° C.) limits the concentration of germanium in SiGe-on-insulator substrates. For wafer bonding, which is another method, there are several technical hurdles including optimization of chemical mechanical polish, bonding conditions and the reduction in dislocation density.
- The invention is directed to overcoming one or more of the problems as set forth above.
- The invention solves the problems and/or overcomes the drawbacks and disadvantages of the prior art by providing a semiconductor device with an undercut relaxed SiGe layer. Voids beneath the SiGe layer are filled with dielectric. A strained Si layer is formed on the relaxed SiGe layer. The resulting semiconductor structure thus combines the benefits of a defect-free strained Si surface and a silicon-on-insulator substrate.
- In a first aspect of the invention, a method of fabricating a semiconductor structure is provided. The method entails forming a Si1-xGex layer on a substrate. A plurality of channels is then formed in the Si1-xGex layer and the substrate. Next, a portion of the substrate underneath the Si1-xGex layer is removed to form a void in the substrate. The SiGe layer above the void is relaxed. The void and channels are then filled with a dielectric material. A strained Si layer may subsequently be formed on the relaxed SiGe layer.
- In a second aspect of the invention, the method includes forming a Si1-xGex layer on a silicon-on-insulator substrate having a first silicon layer, a second SiO2 layer and a substrate. Next, a first channel and a second channel are formed. Each channel extends through the Si1-xGex layer to the bottom of the first silicon layer of the substrate. The first channel and second channel are substantially parallel. Next, the Si1-xGex layer is undercut to form a void in the first silicon layer of the substrate from the first channel to the second channel. Subsequently, the first and second channels and the void are filled with a dielectric material. Then a strained silicon layer is formed on the Si1-xGex layer.
- In a third aspect of the invention, an intermediate semiconductor structure is formed on a substrate. The structure includes a semiconductor substrate and a relaxed Si1-xGex portion on a semiconductor substrate. The relaxed Si1-xGex portion includes one or more channel or trench regions. The structure includes at least one void between the Si1-xGex portion and the substrate. Voids beneath the Si1-xGex layer may be formed by undercutting. The voids may subsequently be filled with dielectric.
- In a fourth aspect of the invention, the semiconductor structure includes a first layer comprised of a strained semiconductor. A second layer comprised of Si1-xGex is provided beneath the first layer. A third layer comprised of a silicon portion and a dielectric portion is provided beneath the second Si1-xGex layer. A fourth layer comprised of an insulator is provided beneath the third layer. A fifth layer comprised of a substrate is provided beneath the fourth layer.
-
FIG. 1 shows a silicon-on-insulator wafer for use in accordance with the principles of the invention; -
FIG. 2 shows a semiconductor structure with a top layer of SiGe in accordance with the principles of the invention; -
FIG. 3 shows a semiconductor structure with a layer of SiGe capped with a dielectric layer and trenches in accordance with the principles of the invention; -
FIG. 4 shows a semiconductor structure with a layer of SiGe capped with a dielectric layer and having trenches in accordance with the principles of the invention; -
FIG. 5 shows a semiconductor structure with a layer of SiGe capped with a dielectric layer, trenches, and an undercut SiGe island in accordance with the principles of the invention; -
FIG. 6 , shows a top view of a cut away section of a structure capped with a dielectric layer, trenches and an undercut SiGe island in accordance with the principles of the invention; -
FIG. 7 shows a semiconductor structure that is capped with a dielectric layer and has an underlying layer of SiGe, trenches and an undercut area filled with dielectric in accordance with the principles of the invention; -
FIG. 8 shows a semiconductor structure with a layer of SiGe, trenches and an undercut area filled with dielectric, and dielectric extending vertically above the surface of the SiGe layer into a layer that previously included a dielectric cap; -
FIG. 9 shows a semiconductor structure with a top layer of strained semiconductor layer formed selectively on SiGe in accordance with the principles of the invention; -
FIG. 10 shows a semiconductor structure with a top layer of strained silicon formed non-selectively over the entire surface in accordance with the principles of the invention; -
FIG. 11 shows a field effect transistor formed on a semiconductor structure in accordance with the principles of the invention; and -
FIG. 12 is a flowchart of a method for producing a strained silicon layer on a SiGe-on-insulator substrate in accordance with the principles of the invention. - The invention enables fabrication of a strained silicon layer on a SiGe-on-insulator substrate. An exemplary methodology in accordance with the invention entails undercutting a SiGe layer to form a relaxed SiGe island, filling the voids with a dielectric and epitaxially growing Si on the relaxed SiGe. The strained Si thus formed can be free of dislocations and misfits. The resulting structure can also be fabricated cost effectively using conventional processing equipment and materials. Additionally, the structure allows a thin SiGe layer, which enables shallow junctions and enhanced device performance.
- Referring now to
FIG. 1 , a silicon-on-insulator (SOI) wafer is shown. Such wafers are commercially available starting substrates for various discrete and integrated circuit (IC) semiconductor device applications. The wafer includes a buried silicon oxide (BOX)layer 120 extending across the entire wafer, just below a thin (e.g., 5 to 200 nm) surface layer of device-quality single-crystal silicon 130. TheBOX layer 120 provides robust vertical isolation from thesubstrate 110. Thesubstrate 110 may be silicon, germanium, silicon germanium, aluminum oxide, or any other suitable semiconductor or insulator. Providing an SOI wafer is afirst step 1210 of an exemplary process flow as shown in the flowchart ofFIG. 12 . - The SOI wafer may be fabricated using any of various techniques known in the art. By way of example and not limitation, the SOI wafer may be fabricated using the SIMOX (Separation by IMplanted OXygen) process, which employs high dose ion implantation of oxygen and high temperature annealing to form the BOX layer in a bulk wafer. As another example, the SOI wafer can be fabricated by bonding a device quality silicon wafer to another wafer (the substrate layer) that has an oxide layer on its surface. The pair is then split apart, using a process that leaves a thin (relative to the thickness of the starting wafer), device-quality layer of single crystal silicon on top of the oxide layer (which has now become the BOX) on the substrate layer. The SOI wafer may also be formed using other processes. The method of fabricating the SOI wafer is not critical to this invention.
- Next, as shown in
FIG. 2 , a thin device-quality silicon germanium layer (SiGe or Si1-xGex) 210 is formed on the device-quality single-crystal silicon layer 130. The Si1-x Gex layer 210 may be deposited or grown on the Si layer using conventional techniques such as chemical vapor deposition methods. For example, ultrahigh vacuum chemical vapor deposition (UHVCVD) may be used in a conventional manner to grow a device quality Si1-xGex layer. Other conventional techniques include rapid thermal chemical vapor deposition (RTCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD) and molecular beam epitaxy (MBE). Growth of a Si1-xGexlayer is asecond step 1220 of an exemplary process flow in accordance with the principles of the invention as shown inFIG. 12 . - In an exemplary implementation, the thickness of the Si1-xGexlayer 210 is below the critical thickness, as is known in the art. The critical thickness, which depends upon parameters such as growth rate, growth temperature, germanium concentration and the thickness of the underneath silicon layer, is the thickness beyond which defects such as dislocations and misfits form. By way of example, a thickness of approximately 5 to 100 nm would be less than the critical thickness for many fabrications.
- Referring to
FIG. 3 , acap layer 310, may be formed on the Si1-xGex layer 210. Thecap layer 310 protects the top surface of the Si1-xGex layer 210 from etching as described more filly below. Thecap layer 310 may be comprised of a dielectric material such as silicon nitride (Si3N4) or Si3N4 atop an oxide (SiO2) layer. The Si3N4 layer may be approximately 20 nm to 100 nm thick. If thecap 210 includes a SiO2 layer, the SiO2 layer may be approximately 3 nm to 20 nm thick. The SiO2 and Si3N4 layer may be formed by thermal growth on the Si1-xGex layer 210 or by a conventional deposition technique such as low pressure CVD, plasma-assisted CVD, high-density plasma CVD or other suitable processes. For clarity, thecap layer 310 is shown as a single layer inFIG. 3 . Cap formation is athird step 1230 of an exemplary process flow in accordance with the principles of the invention as shown inFIG. 12 . - Referring now to
FIG. 4 , channels ortrenches cap 310, Si1-xGex 210 andsilicon 130 layers, stopping on theBOX layer 120, using conventional dry or wet etching processes. After forming thecap layer 310 atop the Si1-xGex 210, a conventional photoresist mask (not shown), combined with an optional hardmask (not shown), for example, SiO2, may be formed atop thecap layer 310. The photoresist mask may be patterned utilizing conventional lithography including resist exposure and development.Trenches trenches fourth step 1240 of an exemplary process flow in accordance with the principles of the invention as shown inFIG. 12 . - Referring now to
FIG. 5 , a portion of the SOI beneath the Si1-xGex 210 layer is removed to form avoid 520 beneath the Si1-xGex layer 210. Theportion 510 of the Si1-xGex layer 210 above thevoid 520 and between thetrenches cap layer 310 protects the top surface of the Si1-xGex layer 210 from being etched in the process of removing the SOI layer. The timed etch proceeds for sufficient time to remove enough SOI from below the Si1-xGex layer 210 to form a relaxed Si1-xGex portion 510 that is large enough to define or include an active area. The removal of SOI, also referred to as undercutting, is afifth step 1250 of an exemplary process flow in accordance with the principles of the invention as shown inFIG. 12 . - Referring now to
FIG. 6 , a top view of a portion of the structure withcap layer 310 over the Si1-xGex layer 210 is shown.Channels border 610 conceptually defines a portion undercut beneath the relaxed Si1-xGex island 510. Un-etched SOI oflayer 130 remains outside of the dashedborder 610, thus providing structural support beneath the Si1-xGex layer 210. Within the dashedborder 610, SOI fromlayer 130 has been removed by etching as described above. While the dashedborder 610 exhibits a square or rectangular shape as shown inFIG. 6 , those skilled in the art will appreciate that etching may proceed in all directions, possibly at uneven rates depending upon the etchant, etching parameters, crystallographic orientation, and etched material. Thus, the invention is not limited to an etching border of any particular shape. - Optionally, after undercutting, the Si1-xGex layer 210 may be thermally annealed at a temperature of about 600 to 900° C. to ensure that it is relaxed. The anneal can be either a furnace anneal, which may require several minutes, or a rapid thermal anneal (RTA), which may require 1 to 100 seconds.
- Next, the trenches and undercut areas are filled with a dielectric, such as
SiO 2 710, as shown inFIG. 7 . The dielectric may be applied in a conventional manner, such as by using an atmospheric CVD process, a low-pressure CVD process or a high-density plasma CVD process, or other suitable methodologies. As SiO2 exhibits good isotropic properties, even the void 520 beneath the Si1-xGex island 510 may be filled. The surface may then be planarized to remove the excess SiO2 and leave thevertical channel portions cap layer 310. The planarization may be achieved by chemically mechanical polishing (CMP) or other suitable planarization methods. The filling of trenches and undercut voids is asixth step 1260 of an exemplary process flow in accordance with the principles of the invention as shown inFIG. 12 . - Referring now to
FIG. 8 , thecap layer 310 is removed to expose the relaxed Si1-xGex layer 210. A conventional wet or dry etch may be performed to remove the cap layer, leaving behind thevertical channel portions vertical channel portions seventh step 1270 of an exemplary process flow in accordance with the principles of the invention as shown inFIG. 12 . - Referring now to
FIG. 9 , astrained Si layer 910 is formed on the relaxed Si1-xGex layer 210. The strained Si layer may be formed epitaxially on the relaxed Si1-xGex layer 210 using conventional techniques. For example, ultrahigh vacuum chemical vapor deposition (UHVCVD) may be used in a conventional manner to grow a device quality Si1-xGex layer. Other suitable techniques include rapid thermal chemical vapor deposition (RTCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD) and molecular beam epitaxy (MBE). Formation of the strained Si layer is aneighth step 1280 of an exemplary process flow in accordance with the principles of the invention as shown inFIG. 12 . - If a thick underlying Si1-xGex layer is desired, an epitaxial growth or deposition of additional Si1-xGex may be performed after the
cap layer 310 is removed and before formation of thestrained Si layer 910. Thestrained Si layer 910 may then be formed on the thick Si1-xGex layer. - Because Si has a smaller lattice constant (i.e., atom spacing) than Ge, when Si is grown on the Si1-xGex layer 210, the Si is strained in tension. Due to enhanced mobility of electrons and holes, the strained Si layer provides an attractive platform for fabricating high performance integrated circuits. For example, nFET mobility increases substantially with strain, with the enhancement beginning to saturate at higher strain (e.g., greater than 1.3%). On the other hand, pFET mobility initially exhibits a slight degradation at low amount of tensile strain, but increases linearly with higher strain.
-
FIG. 9 shows an embodiment in which thestrained Si layer 910 is grown selectively on Si1-xGex layer 210, not on thevertical channel portion FIG. 10 shows an alternative embodiment in which thestrained Si layer 910 is formed in a non-selective manner over the entire surface. In this case, theSi layer 910 also includes theportion 1010 formed above thevertical channel portions strained Si layer 910, if necessary, the surface may be planarized by chemical mechanical polishing (CMP) or any other suitable processes. - A small amount of carbon may optionally be added during Si growth to form a carbon-doped silicon (Si1-yCy) layer in which the strain is increased further. The value of y in Si1-yCy may, by way of example, be approximately 0.001 to 0.02. For simplicity, the
layer 710 is referred to and shown as a strained Si layer or Si layer hereinafter. - A suitable thickness for the
strained Si layer 910 is below the critical thickness, which is the maximum thickness that strained Si can grow on the Si1-xGex layer 210 without forming defects in the crystal structure (e.g., dislocations). By way of example but not limitation, thestrained Si layer 910 may be approximately 5 to 100 nm thick. The epitaxial growth of theSi layer 910 is aneighth step 1280 of an exemplary process flow in accordance with the principles of the invention as shown inFIG. 12 . - The structures formed, as shown in
FIGS. 4 through 10 , are intermediate structures that accommodate formation of semiconductor devices, such as pFETs and nFETs, in accordance with the principles of the invention. One intermediate structure exhibits a void 520 undercut beneath a portion (e.g., island) 510 of the Si1-xGex layer to relax the undercut Si1-xGex portion, as shown inFIG. 5 . Another intermediate structure, by way of example, exhibits a thin strained semiconductor layer (e.g., a Si layer) 910 epitaxially grown on the Si1-xGex layer 210, as shown inFIG. 9 . The intermediate structures thus combine the benefits of a thin strained semiconductor layer with the benefits of SOI. Furthermore, the undercutting step obviates the need for costly and potentially problematic process steps, such as SIMOX or wafer bonding, to create the relaxed Si1-xGex layer on SiO2. Moreover, the formation of a thinstrained Si layer 910 on the relaxed Si1-xGex layer 210 is less conducive to defect formation in thestrained Si layer 910, than in conventional processes. - Next, standard CMOS processes may be performed to form devices such as field effect transistors on the structure as shown in
FIG. 11 . The device includessource 1110 and drain 1120 regions separated by astrained Si channel 1160 situated on a Si1-xGex layer 1170. Agate oxide 1150 is provided atop thestrained Si channel 1160, and agate conductor 1180 is provided on top of thegate oxide 1150.Spacers final step 1290 of an exemplary process flow in accordance with the principles of the invention as shown inFIG. 12 . - Those skilled in the art will appreciate that a process according to the principles of the invention may include steps in addition to those described above and illustrated in the flowchart of
FIG. 12 . Those skilled in the art will also appreciate that a strained Si or Si1-yCy on Si1-xGex structure formed according to the principles of the invention may be used to support various integrated circuit devices, including devices other than the field effect transistor shown inFIG. 11 . - Advantageously, the invention provides a semiconductor device with an undercut relaxed SiGe layer. Voids beneath the SiGe layer may be filled with dielectric. A strained Si layer may be deposited on the relaxed SiGe layer. The resulting semiconductor structure combines the benefits of a defect-free strained Si surface and a silicon-on-insulator substrate. The structure may be fabricated cost effectively using conventional processing equipment and materials. Additionally, because the relaxed SiGe layer may be relatively thin, the structure accommodates shallow junctions which reduce junction capacitance.
- While the invention has been described in terms of exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.
Claims (24)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/706,061 US7029964B2 (en) | 2003-11-13 | 2003-11-13 | Method of manufacturing a strained silicon on a SiGe on SOI substrate |
CNB2004100923060A CN100362618C (en) | 2003-11-13 | 2004-11-08 | A semiconductor device and making method thereof |
US11/061,444 US7468538B2 (en) | 2003-11-13 | 2005-02-22 | Strained silicon on a SiGe on SOI substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/706,061 US7029964B2 (en) | 2003-11-13 | 2003-11-13 | Method of manufacturing a strained silicon on a SiGe on SOI substrate |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/061,444 Division US7468538B2 (en) | 2003-11-13 | 2005-02-22 | Strained silicon on a SiGe on SOI substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
US20050106790A1 true US20050106790A1 (en) | 2005-05-19 |
US7029964B2 US7029964B2 (en) | 2006-04-18 |
Family
ID=34573385
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/706,061 Expired - Lifetime US7029964B2 (en) | 2003-11-13 | 2003-11-13 | Method of manufacturing a strained silicon on a SiGe on SOI substrate |
US11/061,444 Active 2024-08-02 US7468538B2 (en) | 2003-11-13 | 2005-02-22 | Strained silicon on a SiGe on SOI substrate |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/061,444 Active 2024-08-02 US7468538B2 (en) | 2003-11-13 | 2005-02-22 | Strained silicon on a SiGe on SOI substrate |
Country Status (2)
Country | Link |
---|---|
US (2) | US7029964B2 (en) |
CN (1) | CN100362618C (en) |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060261327A1 (en) * | 2003-06-26 | 2006-11-23 | Rj Mears, Llc | Semiconductor device having a semiconductor-on-insulator configuration and a superlattice |
WO2007131119A1 (en) * | 2006-05-05 | 2007-11-15 | Mears Technologies, Inc. | Semiconductor device having a semiconductor-on-insulator configuration and a superlattice and associated methods |
US20080026540A1 (en) * | 2006-07-25 | 2008-01-31 | Chartered Semiconductor Manufacturing, Ltd | Integration for buried epitaxial stressor |
US20100264424A1 (en) * | 2007-12-13 | 2010-10-21 | Shoji Akiyama | GaN LAYER CONTAINING MULTILAYER SUBSTRATE, PROCESS FOR PRODUCING SAME, AND DEVICE |
EP2628172A1 (en) * | 2010-10-11 | 2013-08-21 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Field-effect transistor on a self-assembled semiconductor well |
GB2501307A (en) * | 2012-04-19 | 2013-10-23 | Univ Warwick | Suspended Ge or Si-Ge semiconductor structure on mono-crystal line Si substrate |
CN105702728A (en) * | 2014-11-28 | 2016-06-22 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
US9391198B2 (en) * | 2014-09-11 | 2016-07-12 | Globalfoundries Inc. | Strained semiconductor trampoline |
US20170154961A1 (en) * | 2015-11-30 | 2017-06-01 | International Business Machines Corporation | Semiconductor device including a strain relief buffer |
WO2017171737A1 (en) * | 2016-03-30 | 2017-10-05 | Hewlett Packard Enterprise Development Lp | Devices having substrates with selective airgap regions |
US10366883B2 (en) | 2014-07-30 | 2019-07-30 | Hewlett Packard Enterprise Development Lp | Hybrid multilayer device |
US10381801B1 (en) | 2018-04-26 | 2019-08-13 | Hewlett Packard Enterprise Development Lp | Device including structure over airgap |
CN110383456A (en) * | 2017-03-21 | 2019-10-25 | 索泰克公司 | The method for being used in particular for the semiconductor on insulator type structure of front type imager and manufacturing this structure |
US10586847B2 (en) | 2016-01-15 | 2020-03-10 | Hewlett Packard Enterprise Development Lp | Multilayer device |
US10658177B2 (en) | 2015-09-03 | 2020-05-19 | Hewlett Packard Enterprise Development Lp | Defect-free heterogeneous substrates |
US11502106B2 (en) * | 2020-02-11 | 2022-11-15 | Globalfoundries U.S. Inc. | Multi-layered substrates of semiconductor devices |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7304336B2 (en) * | 2003-02-13 | 2007-12-04 | Massachusetts Institute Of Technology | FinFET structure and method to make the same |
FR2881273B1 (en) * | 2005-01-21 | 2007-05-04 | St Microelectronics Sa | METHOD FOR FORMING INTEGRATED CIRCUIT SEMICONDUCTOR SUBSTRATE |
KR100637692B1 (en) * | 2005-06-27 | 2006-10-25 | 주식회사 하이닉스반도체 | Semiconductor device and method for fabrication of the same |
JP2007165677A (en) * | 2005-12-15 | 2007-06-28 | Seiko Epson Corp | Method of manufacturing semiconductor substrate and semiconductor device |
US7569434B2 (en) * | 2006-01-19 | 2009-08-04 | International Business Machines Corporation | PFETs and methods of manufacturing the same |
US7638398B2 (en) * | 2006-03-31 | 2009-12-29 | Hynix Semiconductor Inc. | Semiconductor device with increased channel area and fabrication method thereof |
JP4625793B2 (en) * | 2006-09-08 | 2011-02-02 | 株式会社東芝 | Semiconductor device |
KR100937599B1 (en) * | 2007-12-17 | 2010-01-20 | 한국전자통신연구원 | Semiconductor device and method of forming the same |
CN102790004B (en) * | 2011-05-16 | 2014-06-11 | 中国科学院上海微系统与信息技术研究所 | Preparation method of full-isolation mixed crystal orientation crystal orientation silicon-on-insulator (SOI) |
US8617968B1 (en) | 2012-06-18 | 2013-12-31 | International Business Machines Corporation | Strained silicon and strained silicon germanium on insulator metal oxide semiconductor field effect transistors (MOSFETs) |
US8859348B2 (en) * | 2012-07-09 | 2014-10-14 | International Business Machines Corporation | Strained silicon and strained silicon germanium on insulator |
US9484423B2 (en) | 2013-11-01 | 2016-11-01 | Samsung Electronics Co., Ltd. | Crystalline multiple-nanosheet III-V channel FETs |
US9570609B2 (en) | 2013-11-01 | 2017-02-14 | Samsung Electronics Co., Ltd. | Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same |
US9647098B2 (en) | 2014-07-21 | 2017-05-09 | Samsung Electronics Co., Ltd. | Thermionically-overdriven tunnel FETs and methods of fabricating the same |
US9679899B2 (en) * | 2015-08-24 | 2017-06-13 | Stmicroelectronics, Inc. | Co-integration of tensile silicon and compressive silicon germanium |
CN108063112B (en) * | 2017-11-15 | 2020-06-16 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing localized SOI region |
US10573755B1 (en) | 2018-09-12 | 2020-02-25 | International Business Machines Corporation | Nanosheet FET with box isolation on substrate |
Citations (77)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3602841A (en) * | 1970-06-18 | 1971-08-31 | Ibm | High frequency bulk semiconductor amplifiers and oscillators |
US4665415A (en) * | 1985-04-24 | 1987-05-12 | International Business Machines Corporation | Semiconductor device with hole conduction via strained lattice |
US4853076A (en) * | 1983-12-29 | 1989-08-01 | Massachusetts Institute Of Technology | Semiconductor thin films |
US4952524A (en) * | 1989-05-05 | 1990-08-28 | At&T Bell Laboratories | Semiconductor device manufacture including trench formation |
US4958213A (en) * | 1987-12-07 | 1990-09-18 | Texas Instruments Incorporated | Method for forming a transistor base region under thick oxide |
US5060030A (en) * | 1990-07-18 | 1991-10-22 | Raytheon Company | Pseudomorphic HEMT having strained compensation layer |
US5081513A (en) * | 1991-02-28 | 1992-01-14 | Xerox Corporation | Electronic device with recovery layer proximate to active layer |
US5108843A (en) * | 1988-11-30 | 1992-04-28 | Ricoh Company, Ltd. | Thin film semiconductor and process for producing the same |
US5134085A (en) * | 1991-11-21 | 1992-07-28 | Micron Technology, Inc. | Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories |
US5310446A (en) * | 1990-01-10 | 1994-05-10 | Ricoh Company, Ltd. | Method for producing semiconductor film |
US5324683A (en) * | 1993-06-02 | 1994-06-28 | Motorola, Inc. | Method of forming a semiconductor structure having an air region |
US5354695A (en) * | 1992-04-08 | 1994-10-11 | Leedy Glenn J | Membrane dielectric isolation IC fabrication |
US5371399A (en) * | 1991-06-14 | 1994-12-06 | International Business Machines Corporation | Compound semiconductor having metallic inclusions and devices fabricated therefrom |
US5391510A (en) * | 1992-02-28 | 1995-02-21 | International Business Machines Corporation | Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps |
US5459346A (en) * | 1988-06-28 | 1995-10-17 | Ricoh Co., Ltd. | Semiconductor substrate with electrical contact in groove |
US5557122A (en) * | 1995-05-12 | 1996-09-17 | Alliance Semiconductors Corporation | Semiconductor electrode having improved grain structure and oxide growth properties |
US5561302A (en) * | 1994-09-26 | 1996-10-01 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
US5679965A (en) * | 1995-03-29 | 1997-10-21 | North Carolina State University | Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same |
US5861651A (en) * | 1997-02-28 | 1999-01-19 | Lucent Technologies Inc. | Field effect devices and capacitors with improved thin film dielectrics and method for making same |
US5880040A (en) * | 1996-04-15 | 1999-03-09 | Macronix International Co., Ltd. | Gate dielectric based on oxynitride grown in N2 O and annealed in NO |
US5898978A (en) * | 1997-03-03 | 1999-05-04 | John D. Hollingsworth On Wheels, Inc. | Metallic clothing for carding segments and flats |
US5940736A (en) * | 1997-03-11 | 1999-08-17 | Lucent Technologies Inc. | Method for forming a high quality ultrathin gate oxide layer |
US5960297A (en) * | 1997-07-02 | 1999-09-28 | Kabushiki Kaisha Toshiba | Shallow trench isolation structure and method of forming the same |
US6008126A (en) * | 1992-04-08 | 1999-12-28 | Elm Technology Corporation | Membrane dielectric isolation IC fabrication |
US6025280A (en) * | 1997-04-28 | 2000-02-15 | Lucent Technologies Inc. | Use of SiD4 for deposition of ultra thin and controllable oxides |
US6046464A (en) * | 1995-03-29 | 2000-04-04 | North Carolina State University | Integrated heterostructures of group III-V nitride semiconductor materials including epitaxial ohmic contact comprising multiple quantum well |
US6066545A (en) * | 1997-12-09 | 2000-05-23 | Texas Instruments Incorporated | Birdsbeak encroachment using combination of wet and dry etch for isolation nitride |
US6090684A (en) * | 1998-07-31 | 2000-07-18 | Hitachi, Ltd. | Method for manufacturing semiconductor device |
US6107143A (en) * | 1998-03-02 | 2000-08-22 | Samsung Electronics Co., Ltd. | Method for forming a trench isolation structure in an integrated circuit |
US6117722A (en) * | 1999-02-18 | 2000-09-12 | Taiwan Semiconductor Manufacturing Company | SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof |
US6133071A (en) * | 1997-10-15 | 2000-10-17 | Nec Corporation | Semiconductor device with plate heat sink free from cracks due to thermal stress and process for assembling it with package |
US6165383A (en) * | 1998-04-10 | 2000-12-26 | Organic Display Technology | Useful precursors for organic electroluminescent materials and devices made from such materials |
US6204145B1 (en) * | 1996-11-12 | 2001-03-20 | Micron Technology, Inc. | Silicon-on-insulator islands and method for their formation |
US6221735B1 (en) * | 2000-02-15 | 2001-04-24 | Philips Semiconductors, Inc. | Method for eliminating stress induced dislocations in CMOS devices |
US6228694B1 (en) * | 1999-06-28 | 2001-05-08 | Intel Corporation | Method of increasing the mobility of MOS transistors by use of localized stress regions |
US6255169B1 (en) * | 1999-02-22 | 2001-07-03 | Advanced Micro Devices, Inc. | Process for fabricating a high-endurance non-volatile memory device |
US6261964B1 (en) * | 1997-03-14 | 2001-07-17 | Micron Technology, Inc. | Material removal method for forming a structure |
US6265317B1 (en) * | 2001-01-09 | 2001-07-24 | Taiwan Semiconductor Manufacturing Company | Top corner rounding for shallow trench isolation |
US20010009784A1 (en) * | 1998-01-09 | 2001-07-26 | Yanjun Ma | Structure and method of making a sub-micron MOS transistor |
US6274444B1 (en) * | 1999-07-30 | 2001-08-14 | United Microelectronics Corp. | Method for forming mosfet |
US6281532B1 (en) * | 1999-06-28 | 2001-08-28 | Intel Corporation | Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering |
US6284626B1 (en) * | 1999-04-06 | 2001-09-04 | Vantis Corporation | Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench |
US6284623B1 (en) * | 1999-10-25 | 2001-09-04 | Peng-Fei Zhang | Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect |
US6319794B1 (en) * | 1998-10-14 | 2001-11-20 | International Business Machines Corporation | Structure and method for producing low leakage isolation devices |
US6361885B1 (en) * | 1998-04-10 | 2002-03-26 | Organic Display Technology | Organic electroluminescent materials and device made from such materials |
US6362082B1 (en) * | 1999-06-28 | 2002-03-26 | Intel Corporation | Methodology for control of short channel effects in MOS transistors |
US6368931B1 (en) * | 2000-03-27 | 2002-04-09 | Intel Corporation | Thin tensile layers in shallow trench isolation and method of making same |
US6403486B1 (en) * | 2001-04-30 | 2002-06-11 | Taiwan Semiconductor Manufacturing Company | Method for forming a shallow trench isolation |
US6403975B1 (en) * | 1996-04-09 | 2002-06-11 | Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev | Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates |
US6406973B1 (en) * | 1999-06-29 | 2002-06-18 | Hyundai Electronics Industries Co., Ltd. | Transistor in a semiconductor device and method of manufacturing the same |
US20020086472A1 (en) * | 2000-12-29 | 2002-07-04 | Brian Roberds | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel |
US20020086497A1 (en) * | 2000-12-30 | 2002-07-04 | Kwok Siang Ping | Beaker shape trench with nitride pull-back for STI |
US20020090791A1 (en) * | 1999-06-28 | 2002-07-11 | Brian S. Doyle | Method for reduced capacitance interconnect system using gaseous implants into the ild |
US6461936B1 (en) * | 2002-01-04 | 2002-10-08 | Infineon Technologies Ag | Double pullback method of filling an isolation trench |
US6461903B2 (en) * | 2000-06-28 | 2002-10-08 | Hynix Semiconductor Inc. | Method for fabricating a part depletion type SOI device preventing a floating body effect |
US6476462B2 (en) * | 1999-12-28 | 2002-11-05 | Texas Instruments Incorporated | MOS-type semiconductor device and method for making same |
US6493497B1 (en) * | 2000-09-26 | 2002-12-10 | Motorola, Inc. | Electro-optic structure and process for fabricating same |
US6498358B1 (en) * | 2001-07-20 | 2002-12-24 | Motorola, Inc. | Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating |
US6501121B1 (en) * | 2000-11-15 | 2002-12-31 | Motorola, Inc. | Semiconductor structure |
US6506652B2 (en) * | 1998-11-13 | 2003-01-14 | Intel Corporation | Method of recessing spacers to improved salicide resistance on polysilicon gates |
US20030032261A1 (en) * | 2001-08-08 | 2003-02-13 | Ling-Yen Yeh | Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation |
US6521694B2 (en) * | 1998-08-11 | 2003-02-18 | Dsm N.V. | Process for hydrogenation of carbon-carbon double bonds of an unsaturated polymer |
US20030040158A1 (en) * | 2001-08-21 | 2003-02-27 | Nec Corporation | Semiconductor device and method of fabricating the same |
US6531369B1 (en) * | 2000-03-01 | 2003-03-11 | Applied Micro Circuits Corporation | Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe) |
US6531740B2 (en) * | 2001-07-17 | 2003-03-11 | Motorola, Inc. | Integrated impedance matching and stability network |
US20030057184A1 (en) * | 2001-09-22 | 2003-03-27 | Shiuh-Sheng Yu | Method for pull back SiN to increase rounding effect in a shallow trench isolation process |
US20030067305A1 (en) * | 2001-10-05 | 2003-04-10 | Shepeck Matthew A. | Motor terminal fixture |
US20030162350A1 (en) * | 2000-05-05 | 2003-08-28 | Karl-Heinz Muller | Method for producing a bipolar transistor |
US20030215989A1 (en) * | 2001-04-12 | 2003-11-20 | Sang-Su Kim | Semiconductor device having gate all around type transistor and method of forming the same |
US6670798B1 (en) * | 2002-09-25 | 2003-12-30 | Pitney Bowes Inc. | Auto power-on, hot-pluggable user interface controller for mailing machines |
US6723541B2 (en) * | 2001-07-12 | 2004-04-20 | Hitachi, Ltd. | Method of producing semiconductor device and semiconductor substrate |
US20040235264A1 (en) * | 2003-05-21 | 2004-11-25 | Micron Technology, Inc. | Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers |
US20040235262A1 (en) * | 2003-05-20 | 2004-11-25 | Sharp Laboratories Of America, Inc. | Silicon-on-nothing fabrication process |
US6831292B2 (en) * | 2001-09-21 | 2004-12-14 | Amberwave Systems Corporation | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
US20050037603A1 (en) * | 2003-08-12 | 2005-02-17 | Stmicroelectronics S.A. | Method for forming, under a thin layer of a first material, portions of another material and/or empty areas |
US20050093076A1 (en) * | 2003-11-05 | 2005-05-05 | International Business Machines Corporation | METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES |
US6930375B2 (en) * | 2001-06-22 | 2005-08-16 | Memc Electronic Materials, Inc. | Silicon on insulator structure having an epitaxial layer and intrinsic gettering |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0219641B1 (en) | 1985-09-13 | 1991-01-09 | Siemens Aktiengesellschaft | Integrated circuit comprising bipolar and complementary mos transistors on a common substrate, and method of making the same |
US5006913A (en) | 1988-11-05 | 1991-04-09 | Mitsubishi Denki Kabushiki Kaisha | Stacked type semiconductor device |
US5989978A (en) | 1998-07-16 | 1999-11-23 | Chartered Semiconductor Manufacturing, Ltd. | Shallow trench isolation of MOSFETS with reduced corner parasitic currents |
US6483171B1 (en) | 1999-08-13 | 2002-11-19 | Micron Technology, Inc. | Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same |
US7312485B2 (en) | 2000-11-29 | 2007-12-25 | Intel Corporation | CMOS fabrication process utilizing special transistor orientation |
US6656798B2 (en) | 2001-09-28 | 2003-12-02 | Infineon Technologies, Ag | Gate processing method with reduced gate oxide corner and edge thinning |
US6936869B2 (en) * | 2002-07-09 | 2005-08-30 | International Rectifier Corporation | Heterojunction field effect transistors using silicon-germanium and silicon-carbon alloys |
US6825529B2 (en) | 2002-12-12 | 2004-11-30 | International Business Machines Corporation | Stress inducing spacers |
US6717216B1 (en) | 2002-12-12 | 2004-04-06 | International Business Machines Corporation | SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device |
US6974981B2 (en) | 2002-12-12 | 2005-12-13 | International Business Machines Corporation | Isolation structures for imposing stress patterns |
US6887798B2 (en) | 2003-05-30 | 2005-05-03 | International Business Machines Corporation | STI stress modification by nitrogen plasma treatment for improving performance in small width devices |
US7279746B2 (en) | 2003-06-30 | 2007-10-09 | International Business Machines Corporation | High performance CMOS device structures and method of manufacture |
US7119403B2 (en) | 2003-10-16 | 2006-10-10 | International Business Machines Corporation | High performance strained CMOS devices |
US8008724B2 (en) | 2003-10-30 | 2011-08-30 | International Business Machines Corporation | Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers |
US6977194B2 (en) | 2003-10-30 | 2005-12-20 | International Business Machines Corporation | Structure and method to improve channel mobility by gate electrode stress modification |
US7015082B2 (en) | 2003-11-06 | 2006-03-21 | International Business Machines Corporation | High mobility CMOS circuits |
US7122849B2 (en) | 2003-11-14 | 2006-10-17 | International Business Machines Corporation | Stressed semiconductor device structures having granular semiconductor material |
US7247912B2 (en) | 2004-01-05 | 2007-07-24 | International Business Machines Corporation | Structures and methods for making strained MOSFETs |
US7205206B2 (en) | 2004-03-03 | 2007-04-17 | International Business Machines Corporation | Method of fabricating mobility enhanced CMOS devices |
-
2003
- 2003-11-13 US US10/706,061 patent/US7029964B2/en not_active Expired - Lifetime
-
2004
- 2004-11-08 CN CNB2004100923060A patent/CN100362618C/en not_active Expired - Fee Related
-
2005
- 2005-02-22 US US11/061,444 patent/US7468538B2/en active Active
Patent Citations (90)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3602841A (en) * | 1970-06-18 | 1971-08-31 | Ibm | High frequency bulk semiconductor amplifiers and oscillators |
US4853076A (en) * | 1983-12-29 | 1989-08-01 | Massachusetts Institute Of Technology | Semiconductor thin films |
US4665415A (en) * | 1985-04-24 | 1987-05-12 | International Business Machines Corporation | Semiconductor device with hole conduction via strained lattice |
US4958213A (en) * | 1987-12-07 | 1990-09-18 | Texas Instruments Incorporated | Method for forming a transistor base region under thick oxide |
US5459346A (en) * | 1988-06-28 | 1995-10-17 | Ricoh Co., Ltd. | Semiconductor substrate with electrical contact in groove |
US5565697A (en) * | 1988-06-28 | 1996-10-15 | Ricoh Company, Ltd. | Semiconductor structure having island forming grooves |
US5108843A (en) * | 1988-11-30 | 1992-04-28 | Ricoh Company, Ltd. | Thin film semiconductor and process for producing the same |
US4952524A (en) * | 1989-05-05 | 1990-08-28 | At&T Bell Laboratories | Semiconductor device manufacture including trench formation |
US5310446A (en) * | 1990-01-10 | 1994-05-10 | Ricoh Company, Ltd. | Method for producing semiconductor film |
US5060030A (en) * | 1990-07-18 | 1991-10-22 | Raytheon Company | Pseudomorphic HEMT having strained compensation layer |
US5081513A (en) * | 1991-02-28 | 1992-01-14 | Xerox Corporation | Electronic device with recovery layer proximate to active layer |
US5471948A (en) * | 1991-06-14 | 1995-12-05 | International Business Machines Corporation | Method of making a compound semiconductor having metallic inclusions |
US5371399A (en) * | 1991-06-14 | 1994-12-06 | International Business Machines Corporation | Compound semiconductor having metallic inclusions and devices fabricated therefrom |
US5134085A (en) * | 1991-11-21 | 1992-07-28 | Micron Technology, Inc. | Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories |
US5391510A (en) * | 1992-02-28 | 1995-02-21 | International Business Machines Corporation | Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps |
US5840593A (en) * | 1992-04-08 | 1998-11-24 | Elm Technology Corporation | Membrane dielectric isolation IC fabrication |
US5354695A (en) * | 1992-04-08 | 1994-10-11 | Leedy Glenn J | Membrane dielectric isolation IC fabrication |
US5571741A (en) * | 1992-04-08 | 1996-11-05 | Leedy; Glenn J. | Membrane dielectric isolation IC fabrication |
US5592018A (en) * | 1992-04-08 | 1997-01-07 | Leedy; Glenn J. | Membrane dielectric isolation IC fabrication |
US5592007A (en) * | 1992-04-08 | 1997-01-07 | Leedy; Glenn J. | Membrane dielectric isolation transistor fabrication |
US5946559A (en) * | 1992-04-08 | 1999-08-31 | Elm Technology Corporation | Membrane dielectric isolation IC fabrication |
US6008126A (en) * | 1992-04-08 | 1999-12-28 | Elm Technology Corporation | Membrane dielectric isolation IC fabrication |
US5324683A (en) * | 1993-06-02 | 1994-06-28 | Motorola, Inc. | Method of forming a semiconductor structure having an air region |
US5561302A (en) * | 1994-09-26 | 1996-10-01 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
US5683934A (en) * | 1994-09-26 | 1997-11-04 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
US5679965A (en) * | 1995-03-29 | 1997-10-21 | North Carolina State University | Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same |
US6046464A (en) * | 1995-03-29 | 2000-04-04 | North Carolina State University | Integrated heterostructures of group III-V nitride semiconductor materials including epitaxial ohmic contact comprising multiple quantum well |
US5557122A (en) * | 1995-05-12 | 1996-09-17 | Alliance Semiconductors Corporation | Semiconductor electrode having improved grain structure and oxide growth properties |
US6403975B1 (en) * | 1996-04-09 | 2002-06-11 | Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev | Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates |
US5880040A (en) * | 1996-04-15 | 1999-03-09 | Macronix International Co., Ltd. | Gate dielectric based on oxynitride grown in N2 O and annealed in NO |
US6204145B1 (en) * | 1996-11-12 | 2001-03-20 | Micron Technology, Inc. | Silicon-on-insulator islands and method for their formation |
US5861651A (en) * | 1997-02-28 | 1999-01-19 | Lucent Technologies Inc. | Field effect devices and capacitors with improved thin film dielectrics and method for making same |
US5898978A (en) * | 1997-03-03 | 1999-05-04 | John D. Hollingsworth On Wheels, Inc. | Metallic clothing for carding segments and flats |
US5940736A (en) * | 1997-03-11 | 1999-08-17 | Lucent Technologies Inc. | Method for forming a high quality ultrathin gate oxide layer |
US6246095B1 (en) * | 1997-03-11 | 2001-06-12 | Agere Systems Guardian Corp. | System and method for forming a uniform thin gate oxide layer |
US6261964B1 (en) * | 1997-03-14 | 2001-07-17 | Micron Technology, Inc. | Material removal method for forming a structure |
US6025280A (en) * | 1997-04-28 | 2000-02-15 | Lucent Technologies Inc. | Use of SiD4 for deposition of ultra thin and controllable oxides |
US5960297A (en) * | 1997-07-02 | 1999-09-28 | Kabushiki Kaisha Toshiba | Shallow trench isolation structure and method of forming the same |
US6133071A (en) * | 1997-10-15 | 2000-10-17 | Nec Corporation | Semiconductor device with plate heat sink free from cracks due to thermal stress and process for assembling it with package |
US6066545A (en) * | 1997-12-09 | 2000-05-23 | Texas Instruments Incorporated | Birdsbeak encroachment using combination of wet and dry etch for isolation nitride |
US20010009784A1 (en) * | 1998-01-09 | 2001-07-26 | Yanjun Ma | Structure and method of making a sub-micron MOS transistor |
US6107143A (en) * | 1998-03-02 | 2000-08-22 | Samsung Electronics Co., Ltd. | Method for forming a trench isolation structure in an integrated circuit |
US6165383A (en) * | 1998-04-10 | 2000-12-26 | Organic Display Technology | Useful precursors for organic electroluminescent materials and devices made from such materials |
US6361885B1 (en) * | 1998-04-10 | 2002-03-26 | Organic Display Technology | Organic electroluminescent materials and device made from such materials |
US6090684A (en) * | 1998-07-31 | 2000-07-18 | Hitachi, Ltd. | Method for manufacturing semiconductor device |
US6521694B2 (en) * | 1998-08-11 | 2003-02-18 | Dsm N.V. | Process for hydrogenation of carbon-carbon double bonds of an unsaturated polymer |
US6319794B1 (en) * | 1998-10-14 | 2001-11-20 | International Business Machines Corporation | Structure and method for producing low leakage isolation devices |
US6509618B2 (en) * | 1998-11-13 | 2003-01-21 | Intel Corporation | Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates |
US6506652B2 (en) * | 1998-11-13 | 2003-01-14 | Intel Corporation | Method of recessing spacers to improved salicide resistance on polysilicon gates |
US6117722A (en) * | 1999-02-18 | 2000-09-12 | Taiwan Semiconductor Manufacturing Company | SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof |
US6255169B1 (en) * | 1999-02-22 | 2001-07-03 | Advanced Micro Devices, Inc. | Process for fabricating a high-endurance non-volatile memory device |
US6284626B1 (en) * | 1999-04-06 | 2001-09-04 | Vantis Corporation | Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench |
US20020090791A1 (en) * | 1999-06-28 | 2002-07-11 | Brian S. Doyle | Method for reduced capacitance interconnect system using gaseous implants into the ild |
US6281532B1 (en) * | 1999-06-28 | 2001-08-28 | Intel Corporation | Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering |
US6362082B1 (en) * | 1999-06-28 | 2002-03-26 | Intel Corporation | Methodology for control of short channel effects in MOS transistors |
US6228694B1 (en) * | 1999-06-28 | 2001-05-08 | Intel Corporation | Method of increasing the mobility of MOS transistors by use of localized stress regions |
US20020074598A1 (en) * | 1999-06-28 | 2002-06-20 | Doyle Brian S. | Methodology for control of short channel effects in MOS transistors |
US6406973B1 (en) * | 1999-06-29 | 2002-06-18 | Hyundai Electronics Industries Co., Ltd. | Transistor in a semiconductor device and method of manufacturing the same |
US6274444B1 (en) * | 1999-07-30 | 2001-08-14 | United Microelectronics Corp. | Method for forming mosfet |
US6284623B1 (en) * | 1999-10-25 | 2001-09-04 | Peng-Fei Zhang | Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect |
US6476462B2 (en) * | 1999-12-28 | 2002-11-05 | Texas Instruments Incorporated | MOS-type semiconductor device and method for making same |
US6221735B1 (en) * | 2000-02-15 | 2001-04-24 | Philips Semiconductors, Inc. | Method for eliminating stress induced dislocations in CMOS devices |
US6531369B1 (en) * | 2000-03-01 | 2003-03-11 | Applied Micro Circuits Corporation | Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe) |
US6368931B1 (en) * | 2000-03-27 | 2002-04-09 | Intel Corporation | Thin tensile layers in shallow trench isolation and method of making same |
US6855612B2 (en) * | 2000-05-05 | 2005-02-15 | Infineon Technologies Ag | Method for fabricating a bipolar transistor |
US20030162350A1 (en) * | 2000-05-05 | 2003-08-28 | Karl-Heinz Muller | Method for producing a bipolar transistor |
US6461903B2 (en) * | 2000-06-28 | 2002-10-08 | Hynix Semiconductor Inc. | Method for fabricating a part depletion type SOI device preventing a floating body effect |
US6493497B1 (en) * | 2000-09-26 | 2002-12-10 | Motorola, Inc. | Electro-optic structure and process for fabricating same |
US6501121B1 (en) * | 2000-11-15 | 2002-12-31 | Motorola, Inc. | Semiconductor structure |
US20020086472A1 (en) * | 2000-12-29 | 2002-07-04 | Brian Roberds | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel |
US20020086497A1 (en) * | 2000-12-30 | 2002-07-04 | Kwok Siang Ping | Beaker shape trench with nitride pull-back for STI |
US6265317B1 (en) * | 2001-01-09 | 2001-07-24 | Taiwan Semiconductor Manufacturing Company | Top corner rounding for shallow trench isolation |
US6794306B2 (en) * | 2001-04-12 | 2004-09-21 | Samsung Electronics Co., Ltd. | Semiconductor device having gate all around type transistor and method of forming the same |
US20030215989A1 (en) * | 2001-04-12 | 2003-11-20 | Sang-Su Kim | Semiconductor device having gate all around type transistor and method of forming the same |
US6403486B1 (en) * | 2001-04-30 | 2002-06-11 | Taiwan Semiconductor Manufacturing Company | Method for forming a shallow trench isolation |
US6930375B2 (en) * | 2001-06-22 | 2005-08-16 | Memc Electronic Materials, Inc. | Silicon on insulator structure having an epitaxial layer and intrinsic gettering |
US6723541B2 (en) * | 2001-07-12 | 2004-04-20 | Hitachi, Ltd. | Method of producing semiconductor device and semiconductor substrate |
US6531740B2 (en) * | 2001-07-17 | 2003-03-11 | Motorola, Inc. | Integrated impedance matching and stability network |
US6498358B1 (en) * | 2001-07-20 | 2002-12-24 | Motorola, Inc. | Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating |
US20030032261A1 (en) * | 2001-08-08 | 2003-02-13 | Ling-Yen Yeh | Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation |
US20030040158A1 (en) * | 2001-08-21 | 2003-02-27 | Nec Corporation | Semiconductor device and method of fabricating the same |
US6831292B2 (en) * | 2001-09-21 | 2004-12-14 | Amberwave Systems Corporation | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
US20030057184A1 (en) * | 2001-09-22 | 2003-03-27 | Shiuh-Sheng Yu | Method for pull back SiN to increase rounding effect in a shallow trench isolation process |
US20030067305A1 (en) * | 2001-10-05 | 2003-04-10 | Shepeck Matthew A. | Motor terminal fixture |
US6461936B1 (en) * | 2002-01-04 | 2002-10-08 | Infineon Technologies Ag | Double pullback method of filling an isolation trench |
US6670798B1 (en) * | 2002-09-25 | 2003-12-30 | Pitney Bowes Inc. | Auto power-on, hot-pluggable user interface controller for mailing machines |
US20040235262A1 (en) * | 2003-05-20 | 2004-11-25 | Sharp Laboratories Of America, Inc. | Silicon-on-nothing fabrication process |
US20040235264A1 (en) * | 2003-05-21 | 2004-11-25 | Micron Technology, Inc. | Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers |
US20050037603A1 (en) * | 2003-08-12 | 2005-02-17 | Stmicroelectronics S.A. | Method for forming, under a thin layer of a first material, portions of another material and/or empty areas |
US20050093076A1 (en) * | 2003-11-05 | 2005-05-05 | International Business Machines Corporation | METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES |
Cited By (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060261327A1 (en) * | 2003-06-26 | 2006-11-23 | Rj Mears, Llc | Semiconductor device having a semiconductor-on-insulator configuration and a superlattice |
US7586116B2 (en) | 2003-06-26 | 2009-09-08 | Mears Technologies, Inc. | Semiconductor device having a semiconductor-on-insulator configuration and a superlattice |
WO2007131119A1 (en) * | 2006-05-05 | 2007-11-15 | Mears Technologies, Inc. | Semiconductor device having a semiconductor-on-insulator configuration and a superlattice and associated methods |
US20080026540A1 (en) * | 2006-07-25 | 2008-01-31 | Chartered Semiconductor Manufacturing, Ltd | Integration for buried epitaxial stressor |
US7863141B2 (en) | 2006-07-25 | 2011-01-04 | Chartered Semiconductor Manufacturing, Ltd. | Integration for buried epitaxial stressor |
US20100264424A1 (en) * | 2007-12-13 | 2010-10-21 | Shoji Akiyama | GaN LAYER CONTAINING MULTILAYER SUBSTRATE, PROCESS FOR PRODUCING SAME, AND DEVICE |
EP2628172A1 (en) * | 2010-10-11 | 2013-08-21 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Field-effect transistor on a self-assembled semiconductor well |
GB2501307A (en) * | 2012-04-19 | 2013-10-23 | Univ Warwick | Suspended Ge or Si-Ge semiconductor structure on mono-crystal line Si substrate |
US10366883B2 (en) | 2014-07-30 | 2019-07-30 | Hewlett Packard Enterprise Development Lp | Hybrid multilayer device |
US9391198B2 (en) * | 2014-09-11 | 2016-07-12 | Globalfoundries Inc. | Strained semiconductor trampoline |
CN105702728A (en) * | 2014-11-28 | 2016-06-22 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
US11004681B2 (en) | 2015-09-03 | 2021-05-11 | Hewlett Packard Enterprise Development Lp | Defect-free heterogeneous substrates |
US10658177B2 (en) | 2015-09-03 | 2020-05-19 | Hewlett Packard Enterprise Development Lp | Defect-free heterogeneous substrates |
US20170154961A1 (en) * | 2015-11-30 | 2017-06-01 | International Business Machines Corporation | Semiconductor device including a strain relief buffer |
US20170154775A1 (en) * | 2015-11-30 | 2017-06-01 | International Business Machines Corporation | Method for forming a strained semiconductor layer including replacing an etchable material formed under the strained semiconductor layer with a dielectric layer |
US9859371B2 (en) * | 2015-11-30 | 2018-01-02 | International Business Machines Corporation | Semiconductor device including a strain relief buffer |
US9875896B2 (en) * | 2015-11-30 | 2018-01-23 | International Business Machines Corporation | Method for forming a strained semiconductor layer including replacing an etchable material formed under the strained semiconductor layer with a dielectric layer |
US10586847B2 (en) | 2016-01-15 | 2020-03-10 | Hewlett Packard Enterprise Development Lp | Multilayer device |
WO2017171737A1 (en) * | 2016-03-30 | 2017-10-05 | Hewlett Packard Enterprise Development Lp | Devices having substrates with selective airgap regions |
US11088244B2 (en) | 2016-03-30 | 2021-08-10 | Hewlett Packard Enterprise Development Lp | Devices having substrates with selective airgap regions |
CN110383456A (en) * | 2017-03-21 | 2019-10-25 | 索泰克公司 | The method for being used in particular for the semiconductor on insulator type structure of front type imager and manufacturing this structure |
US10381801B1 (en) | 2018-04-26 | 2019-08-13 | Hewlett Packard Enterprise Development Lp | Device including structure over airgap |
US11502106B2 (en) * | 2020-02-11 | 2022-11-15 | Globalfoundries U.S. Inc. | Multi-layered substrates of semiconductor devices |
Also Published As
Publication number | Publication date |
---|---|
US7468538B2 (en) | 2008-12-23 |
CN1630025A (en) | 2005-06-22 |
US20050142700A1 (en) | 2005-06-30 |
CN100362618C (en) | 2008-01-16 |
US7029964B2 (en) | 2006-04-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7468538B2 (en) | Strained silicon on a SiGe on SOI substrate | |
US7247534B2 (en) | Silicon device on Si:C-OI and SGOI and method of manufacture | |
US7198995B2 (en) | Strained finFETs and method of manufacture | |
US7439110B2 (en) | Strained HOT (hybrid orientation technology) MOSFETs | |
US7781800B2 (en) | Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer | |
US7435639B2 (en) | Dual surface SOI by lateral epitaxial overgrowth | |
US8076194B2 (en) | Method of fabricating metal oxide semiconductor transistor | |
US8643061B2 (en) | Structure of high-K metal gate semiconductor transistor | |
US8513718B2 (en) | Stress enhanced transistor devices and methods of making | |
US7544548B2 (en) | Trench liner for DSO integration | |
JP2007258485A (en) | Semiconductor device and its manufacturing method | |
WO2005109509A1 (en) | Fabrication of active areas of different natures directly onto an insulator: application to the single or double gate mos transistor | |
US8440539B2 (en) | Isolation trench processing for strain control | |
US7109096B2 (en) | Semiconductor device and method of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHENG, KANGGUO;CHIDAMBARRAO, DURESETI;REEL/FRAME:014701/0003 Effective date: 20031104 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 8 |
|
SULP | Surcharge for late payment |
Year of fee payment: 7 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553) Year of fee payment: 12 |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:054633/0001 Effective date: 20201022 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |