US20050108587A1 - Demand-based method and system of CPU power management - Google Patents
Demand-based method and system of CPU power management Download PDFInfo
- Publication number
- US20050108587A1 US20050108587A1 US11/006,872 US687204A US2005108587A1 US 20050108587 A1 US20050108587 A1 US 20050108587A1 US 687204 A US687204 A US 687204A US 2005108587 A1 US2005108587 A1 US 2005108587A1
- Authority
- US
- United States
- Prior art keywords
- utilization
- processing unit
- central processing
- performance mode
- processor performance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
A demand-based method and system of central processing unit power management. The utilization of a central processing unit (CPU) during a sampling time interval is determined by measuring a time quantum within the sampling time interval during which a central processing unit clock signal is active within a processor core of the CPU. The total number of cycles of the central processing unit clock signal that are applied to the processor core and the period of the central processing unit clock signal are used to determine the time quantum. The utilization may then be expressed in terms of a ratio of the time quantum to the total time interval and used to select a processor performance mode. The CPU is then operated in the selected processor performance mode.
Description
- This application is a continuation of U.S. patent application Ser. No. 09/751,759 entitled “Demand-Based Method and System of CPU Power Management,” assigned to the assignee of the present invention and filed Dec. 30, 2000.
- The field of the invention relates generally to central processing units (CPUs). More particularly the field invention relates to CPU power management. Still more particularly, the field of the invention relates to a demand-based method and system of CPU power management.
- As battery-dependent portable computing devices (notebook computers, personal digital assistants, etc.) have become more prevalent, the conservation of battery power or “power management” has become more and more important. In many power management systems, some or all system components may be deactivated or “powered down” to conserve power. This method however, requires that the devices powered down be inactive or unused for a sufficiently long period of time to justify the latency associated with their re-activation. Therefore, a number of methods have been implemented to decrease device power consumption within the active or “powered on” state. Since, the power dissipated by a device is dependent both on its applied voltage and on the frequency with which device transitions or “switching” occurs, conventional power management techniques typically focus on one or both of these factors.
- Modern power management systems implement a variety of voltage and frequency reduction or “scaling” techniques. Although substantial power savings can be realized by reducing a device's voltage, special hardware is often required to correctly operate such devices using low and variable voltages. Such voltage reduction techniques also currently limit the maximum frequency at which a device may be operated. Similar power savings may be realized by scaling a device's operating frequency or “clock”. In conventional power management systems, a device's operating frequency may be altered in a variety of ways. In one approach, the applied clock signal is periodically stopped and restarted such that the average or effective operating frequency is lowered (throttling). In another approach, a lower frequency clock signal, generated independently or derived from an existing clock, is applied to a device. Although these approaches may be used alone or in combination to reduce a device's or system's power consumption, this frequency scaling technique reduces the operating frequency of the device, and consequently the number of operations or tasks it can perform.
- In the past, several approaches have been taken to control the activation of the above-described power management techniques such as the user selection of a pre-defined power mode, the occurrence of environmental events such as the application or removal of an A/C (alternating current) power source, or the detection of a system or device temperature. More recently, power management systems have looked to device utilization or “idleness” to trigger the application or removal of such techniques in an effort to conserve power in a more user-transparent manner. When a utilization-based power managed device is idle for a pre-determined period of time, power reduction techniques such as voltage and frequency scaling are applied to decrease the amount of power consumed. The greatest difficulty traditionally associated with such demand-based systems has been in determining a device's current utilization, particularly for processing devices such as the central processing unit (CPU) of a data processing system.
- In a conventional operating system (OS), CPU utilization is determined by accumulating CPU idle time across a sampling interval to determine the percentage of time the processor is inactive. To accomplish this, a list of tasks or threads is maintained by the OS which are ready-to-run, i.e., not waiting for some event to resume execution. When this ready-to-run list is empty, no tasks are being executed and the processor is idle. Accordingly, a CPU-independent timer is read and the processor is placed in a low power state. When a new task is added to the ready-to-run list, the processor is placed in an active state and the timer is read again. The difference between the first and second timer reads (multiplied by the timer's period) then represents the CPU's idle time. The accumulation of this time across a sampling interval is then used to determine the CPU utilization (what percentage of the CPU's time is spent idle). Unfortunately, neither this measure of CPU utilization nor the state of the ready-to-run task list is available outside of the OS through a supported application programming interface (API). Consequently, this OS-generated CPU utilization metric cannot be utilized in a “demand” or utilization-based power management system.
- The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which
-
FIG. 1 a illustrates a conventional data processing system useable with the present invention; -
FIG. 1 b illustrates a prior art architecture of the data processing system depicted inFIG. 1 a; -
FIG. 2 illustrates a portion of the architecture depicted inFIG. 1 b in greater detail; -
FIG. 3 illustrates an architectural system diagram depicting the operation of a data processing system according to the present invention; -
FIG. 4 illustrates a high-level logic flowchart of a first embodiment of the method of the present invention; -
FIG. 5 illustrates a high-level logic flowchart of a second embodiment of the method of the present invention; -
FIG. 6 illustrates a high-level logic flowchart of a third embodiment of the method of the present invention; -
FIG. 7 illustrates a high-level logic flowchart of a method of determining the utilization of a central processing unit according to one embodiment of the present invention. - A demand-based method and system of CPU power management is disclosed. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that these specific details need not be used to practice the present invention. In other circumstances, well-known structures, materials, circuits, processes and interfaces have not been shown or described in detail in order not to unnecessarily obscure the present invention.
- Referring now to
FIG. 1 a, a conventionaldata processing system 100 useable with the present invention is illustrated. Data processing orcomputer system 100 is comprised of asystem unit 102, output devices such asdisplay 104 andprinter 110, and input devices such askeyboard 108, andmouse 106.Data processing system 100 receives data for processing by the manipulation ofinput devices disk 112 and network connection interfaces (not shown).Data processing system 100 then processes data and presents resulting output data via output devices such asdisplay 104,printer 110, fixed or removable media storage devices likedisk 112 or network connection interfaces. - Referring now to
FIG. 1 b, there is depicted a high-level block diagram of the components of adata processing system 100 such as that illustrated byFIG. 1 a. In a conventional computer system,system unit 102 includes a processing device such as central processing unit (CPU) 120 connected to a level two (L2)cache 122 over a processor system bus (PSB) 114.Processor system bus 114 is in turn coupled to an expansion bus such aslocal bus 116 and amemory 126 via anorth bridge circuit 124.Local bus 116 may include a peripheral component interconnect (PCI), Video Electronics Standards Association (VESA) bus or the like, tightly coupled to theprocessor 120 and theprocessor system bus 114 to permit high-speed access to select devices such asdisplay device 128. -
Memory 126 may include read-only (ROM) and/or random access (RAM) memory devices such as a synchronous dynamic random access memory (SDRAM) module capable of storing data as well as instructions to be executed byCPU 120. Access to data and instructions stored withinmemory 126 is provided via a memory controller (not shown) withinnorth bridge circuit 124.L2 cache 122 is similarly used, typically in a hierarchical manner, to store data and instructions for direct access byCPU 120.Display device 128 may include a cathode ray tube (CRT) display such asdisplay 104, liquid crystal display (LCD), or a similar device for displaying various kinds of data to a computer user. For example, image, graphical, or textual information may be presented to the user ondisplay device 128.System unit 102 ofdata processing system 100 also features an expansion or “compatibility”bus 118 such as the Industry Standard Architecture (ISA) bus, and asouth bridge circuit 134 coupling it tolocal bus 116 to facilitate the attachment of other, relatively slower devices to thesystem 100. Southbridge circuit 134 includes a universal serial bus (USB)port 138 as well as other direct connections for devices such as anetwork interface card 130, a data storage device, such as a magnetichard disk drive 132, and anaudio device 140 such as a speaker or sound card. - Other devices not directly coupled to
south bridge 134 may be connected to thesystem 100 via theexpansion bus 118 as illustrated. A floppy disk drive (FDD) 144 providing additional data storage capacity on removable media storage devices such asdisk 112, and input devices such as akeyboard 108 and acursor control device 136 are each coupled toexpansion bus 118 in this manner to communicate data, instructions, and/or command selections tocentral processing unit 120.Cursor control device 136 may comprise a conventional mouse such asmouse 106 ofFIG. 1 a, a trackball, or any other device capable of conveying desired cursor manipulation. Similarly,expansion bus 118 includes an input/output (I/O) controller having standard serial and parallel port functionality for connecting other I/O devices such asprinter 110 to the system. - The system of the present invention includes software, information processing hardware, and various processing steps, which will be described below. The features and process steps of the present invention may be embodied in machine or computer executable instructions embodied within media such as
disk 112. The instructions can be used to cause a general purpose or special purpose processor such asCPU 120, which is programmed with the instructions to perform the described methods of the present invention. Alternatively, the features or steps of the present invention may be performed by specific hardware components that contain hard-wired logic for performing the steps, or by any combination of programmed computer components and custom hardware components. - Referring now to
FIG. 2 , a portion of the architecture depicted inFIG. 1 b is illustrated in greater detail.Processor 120 is shown in communication withmemory 126 over theprocessor system bus 114 utilizing amemory controller 226 ofnorth bridge circuit 124. A common system clock, (BClk) 216 is generated by aclock generator 208 and applied to a clock control phase lock loop (PLL) 218 ofCPU 120 and tomemory controller 226. Acore voltage 206 is similarly applied toCPU 120 in the illustrated embodiment, providing necessary operating power. While theBClk signal 216 is applied, accesses to and frommemory 126 occur at its frequency of approximately 100 megahertz (MHz). Thecentral processing unit 120 however, is capable of performing tasks at much greater speeds than this and accordingly, a bus ratio ormultiplier 212 is selected using a clock control signal,GHI# 202 and a higher frequency central processing unit clock signal is generated utilizingPLL 218. So for example, if the system orfront side clock 216 has a frequency of 100 MHz, and aratio 212 of 5 to 1 is selected using theGHI# signal 202, then the generated CPU clock will have a frequency of approximately 500 MHz. Alternatively, a higher multiplier orratio 212 ofsay 7 to 1 could be selected, yielding a CPU clock frequency of approximately 700 MHz. - The generated central processing unit clock signal is then applied to
clock throttling logic 220 before being passed toprocessor core 200. Throttling is a technique by which the CPU clock is deasserted or “gated off” from the processor core to prevent functional units within the core from operating.Throttling logic 220 therefore acts as a switch, actuated by a stop clock (Stp_Clk)control signal 204, between thePLL 218 and theprocessor core 200. Atime stamp counter 224 is also included within theCPU 120 and incremented for each cycle (sometimes called ticks or pulses) of the CPU clock which is “gated through” or applied to the processor core as shown. Becausetime stamp counter 224 tracks the number of clock ticks or cycles applied to the functional units of theprocessor core 200 such as instruction decoders, floating point and integer execution units, etc. it provides an extremely accurate representation of the actual work performed byCPU 120. One additional chipset architecture component illustrated inFIG. 2 isindependent timer 210. Systemindependent timer 210 runs independently ofCPU 120 and its associatedsystem clock 216, unaffected byStp_Clk signal 204 throttling or BClk signal 216 frequency modifications. Using the number of ticks ofindependent timer 210 elapsed between reads and its fixed frequency, an accurate measure of the passage of time may be obtained. In one embodiment, a Windows™ high performance counter, exported via the Win32 Application Programming Interface (API) as the QueryPerformanceCounter( ) function can be used asindependent timer 210. In an alternative, Advanced Configuration and Power Interface (ACPI) compliant embodiment, a power management timer may be utilized. Although in the illustrated embodimentindependent timer 210 is depicted as being integrated withclock generator circuit 208, in alternative embodiments thetimer 210 may be generated in a separate device or integrated circuit. - Referring now to
FIG. 3 , an architectural system diagram depicting the operation of a data processing system according to the present invention is illustrated. In the illustrated embodiment, a plurality ofapplication programs 302 such aspower management application 304 interact with variousplatform hardware devices 308 including aCPU 120 via anoperating system 300 such as the Windows™ operating system from Microsoft Corporation, one ormore device drivers 306, and basic input/output system (BIOS)code 310. The illustrated system is interrupt-driven both with respect to the multitasking of thevarious applications 302 and communication betweenapplications 302 andplatform hardware 308. - Accordingly, in one embodiment of the present invention, an
application 302 request for a hardware resource from withinplatform hardware 308 can cause an interrupt, such as a System Control Interrupt (SCI) or a System Management Interrupt (SMI) to be generated and an interrupt handler routine to be responsively executed. Interaction betweenoperating system 300 andplatform hardware 308 is then facilitated by adevice driver 306 andBIOS 310. In the illustrated embodiment,BIOS 310 contains information such as physical device addresses of thevarious devices 308 attached to thedata processing system 100 and is useful with respect to the actual transmission of data. By contrast,device driver 306 is typically specific to a particular hardware device and is usually concerned with the translation of data between various device formats. - Referring now to
FIG. 4 , a high-level logic flowchart of a first embodiment of the method of the present invention is illustrated. InFIG. 4 there is depicted a technique by which a demand-based transition between two processor performance states is executed. Atblock 400, the illustrated process is begun and thereafter a CPU utilization status request is received from a power management application (block 402). The described utilization request may be periodic or may occur in response to relevant power management events such as thermal or processor workload events, the connection of an alternating current power supply or the like. Once the CPU utilization has been established (block 404), a determination is then made whether the calculated utilization exceeds a utilization threshold (block 406). In the illustrated embodiment, a relatively high utilization threshold of 95% is selected to identify the execution of demand-intensive applications such as DVD movie players, personal computer games, and performance benchmark tests. It should be readily appreciated however that the various utilization thresholds described herein have been selected for illustrative purposes only and that a wide range of threshold values could be substituted therefore without departing from the spirit and scope of the present invention. If the utilization threshold is exceeded, the CPU is transitioned to a maximum performance processor performance mode (block 408) and operated at a higher performance level to ensure that the execution performance of such demand-intensive application programs is not degraded. - If the utilization of the CPU is not above or equal to the 95% utilization threshold, it is then determined whether the CPU's utilization falls at or below a second utilization threshold of, in the illustrated embodiment, 75% (block 410). The processor performance level may then be matched to its current utilization level by switching the CPU to a battery optimized processor performance mode (block 412) to conserve power when the utilization level falls below this figure and a decrease in performance will be less noticeable to the end user. Otherwise the process is terminated (block 414) with the processor performance mode of the central processing unit remaining unchanged. Power may be conserved and the maximum performance mode distinguished from the battery optimized mode by the frequency at which the processor is operated. While numerous other power and performance management techniques are known and within the scope of the present invention, in one embodiment utilization of the maximum performance processor performance mode entails the operation of the central processing unit at an operating frequency of 600 MHz while the battery optimized mode entails the application of a 500 MHz central processing unit clock signal. Following any transition to either maximum performance or battery optimized mode, the process is terminated (block 414). In an alternative embodiment, factors other than an instantaneous CPU utilization and a utilization threshold may be used to select an appropriate processor performance mode such as the duration of time that the examined CPU remains at a particular utilization level or within a particular range of utilization levels.
- Referring now to
FIG. 5 , a high-level logic flowchart of a second embodiment of the method of the present invention is illustrated. After the process is begun (block 500) a user-specified power management profile is received (block 502) in which power conservation and system performance are prioritized generally or a specific, preferred processor performance mode may be designated. In the illustrated embodiment, a maximum battery or ultra battery optimized profile is received conveying that power conservation is to be favored over execution speed. Then an executing power management software or firmware application generates a system management interrupt (SMI) (block 504) in response to the receipt of the user power management profile which in turn transitions the CPU to battery optimized mode if necessary from whatever prior state the processor was operating in. Subsequently, the power management application issues a request for the current CPU utilization status (block 508) which is determined either by the generated SMI or directly by the power management application itself (block 510) by a method which will be described in greater detail with reference toFIG. 7 herein. In alternative embodiment, the described system management interrupt is used only to transition the system from one performance or power mode to another with both CPU utilization detection and other related tasks being performed directly by the power management application. - The user-specified power management profile is then checked to ensure that maximum battery mode is still currently enabled (block 512). If so, the resolved CPU utilization is examined to determine whether it exceeds a utilization threshold of 20% (block 514) in this embodiment. If not, the process is terminated (block 518). If the current utilization of the CPU exceeds the tuneable threshold, the CPU is transitioned from battery optimized mode to a virtual maximum battery performance mode by engaging throttling of the central processing unit clock signal at a particular frequency (block 516). Otherwise, the process ends (block 518) and the battery optimized performance mode is utilized until another transition-precipitating event occurs. Using the illustrated process allows small, bursty tasks or code segments which can be completed within the sampling time interval of the CPU utilization determination to be executed at the full, battery optimized performance level without enabling CPU clock signal throttling. Such tasks can be completed faster at this non-throttled rate, allowing the system to transition after their completion to an even lower power state than can be achieved with clock throttling, conserving more power overall.
- Referring now to
FIG. 6 , a high-level logic flowchart of a third embodiment of the method of the present invention is illustrated. The beginning of the process is depicted atblock 600 and thereafter a CPU utilization status request is received from a power management application (block 602). Once the CPU utilization has been established (block 604), a determination is made whether the calculated utilization exceeds a utilization threshold (block 606). In the illustrated embodiment, a relatively high utilization threshold of 95% is selected for this first utilization threshold as illustrated. If the utilization threshold is exceeded, any previously applied CPU clock signal throttling is disabled (block 608) and the CPU is transitioned to a maximum performance processor performance mode (block 610) and operated at a higher performance level to ensure that the execution performance of demand-intensive application programs is not degraded. - If the utilization of the CPU is not above or equal to the 95% utilization threshold, it is then determined whether the CPU's utilization falls at or below a second utilization threshold of, in the illustrated embodiment, 20% (block 612). If the current CPU utilization level is not greater than the 20% utilization threshold, the CPU is operated in battery optimized mode (block 620) and clock throttling is disabled (block 618) such that power saving states such as the C2 and C3 states defined by the well known Advanced Configuration and Power Interface Specification, Revision 2.0, Jul. 27, 2000 (ACPI) can be entered more quickly following completion of the CPU workload. Lastly, for CPU utilizations falling in between the two utilization thresholds, the CPU is transitioned to and operated in maximum battery mode by entering battery optimized mode (block 614) and enabling clock throttling for the applied CPU clock (block 616). Consequently, the performance of CPU workloads having a consistent, intermediate demand intensity is reduced and the completion time is extended in order to reduce the total amount of power consumed. Following any transition to (or retention of) any of the above-described power management performance modes (maximum performance, battery optimized mode, and maximum battery) the process is terminated (block 622).
- Referring now to
FIG. 7 , a high-level logic flowchart of a method of determining the utilization of a central processing unit according to one embodiment of the present invention is illustrated.FIG. 7 depicts a technique by which a the utilization of a CPU may be determined independently of a data processing system's operating system. In one embodiment, this method is utilized to determine CPU utilization within the various method embodiments of the present invention such as atblocks FIGS. 4, 5 , and 6, respectively. The process illustrated byFIG. 7 begins atblock 700. Thereafter, a system-independent timer such as an ACPI chipset-compliant power management timer or Windows™ performance counter is read. (block 702). Next, a sampling time interval is defined using the independent timer's clock period, as well as currently and previously read system-independent timer values (block 704). A value is then read from a time stamp counter (block 706) which is incremented for each cycle or “clock” of a CPU clock signal which is applied to theprocessor core 200 ofcentral processing unit 120. Using a previously read time stamp counter value and the currently read value, the total number of CPU clock signal ticks or cycles applied to the CPU'sprocessor core 200 during the sampling time interval may be obtained (block 708). Thereafter, the total amount or “quantum” of time within the sampling time interval during which the CPU clock signal was active within the CPU'sprocessor core 200 can be derived using the accumulated number of CPU clock cycles and the CPU clock signal's period (block 710). CPU utilization may then be expressed as a ratio of this active CPU clock signal time to the sampling time interval (block 712). Thereafter, the process is terminated (block 714). - Although the present invention is described herein with reference to a specific preferred embodiment, many modifications and variations therein will readily occur to those with ordinary skill in the art. Accordingly, all such variations and modifications are included within the intended scope of the present invention as defined by the following claims.
Claims (18)
1. A method comprising:
determining a utilization of a central processing unit;
placing said central processing unit in a first processor performance mode in response to a determination that said utilization is greater than a first utilization threshold;
placing said central processing unit in a second processor performance mode in response to a determination that said utilization is less than or equal to said first utilization threshold, wherein said central processing unit operates at a higher frequency in said first processor performance mode than in said second processor performance mode.
2. The method as set forth in claim 1 , further comprising:
placing said central processing unit in a third processor performance mode in response to a determination that said utilization is greater than or equal to a second utilization threshold, wherein said second utilization threshold is greater than said first utilization threshold and said central processing unit operates at a higher frequency in said third processor performance mode than in said second processor performance mode.
3. The method as set forth in claim 1 , wherein placing said central processing unit in a first processor performance mode comprises:
receiving a user-specified power management profile; and
placing said central processing unit in said first processor performance mode in response to receiving said user-specified power management profile.
4. The method as set forth in claim 1 , wherein placing said central processing unit in a first processor performance mode in response to a determination that said utilization is greater than a first utilization threshold comprises placing said central processing unit in a first processor performance mode in response to a determination that said utilization is greater than 20%.
5. The method as set forth in claim 4 , wherein placing said central processing unit in a second processor performance mode in response to a determination that said utilization is less than or equal to said first utilization threshold comprises placing said central processing unit in a second processor performance mode in response to a determination that said utilization is less than or equal to 20%.
6. The method as set forth in claim 2 , wherein placing said central processing unit in a third processor performance mode in response to a determination that said utilization is greater than or equal to a second utilization threshold comprises placing said central processing unit in a third processor performance mode in response to a determination that said utilization is greater than or equal to 20%.
7. A data processing system-readable medium having a plurality of instructions executable by a data processing system embodied therein, wherein said instructions when executed cause said data processing system to perform a method comprising:
determining a utilization of a central processing unit;
placing said central processing unit in a first processor performance mode in response to a determination that said utilization is greater than a first utilization threshold;
placing said central processing unit in a second processor performance mode in response to a determination that said utilization is less than or equal to said first utilization threshold, wherein said central processing unit operates at a higher frequency in said first processor performance mode than in said second processor performance mode.
8. The data processing system-readable medium as set forth in claim 7 , wherein said method further comprises:
placing said central processing unit in a third processor performance mode in response to a determination that said utilization is greater than or equal to a second utilization threshold, wherein said second utilization threshold is greater than said first utilization threshold and said central processing unit operates at a higher frequency in said third processor performance mode than in said second processor performance mode.
9. The data processing system-readable medium as set forth in claim 7 , wherein placing said central processing unit in a first processor performance mode comprises:
receiving a user-specified power management profile; and
placing said central processing unit in said first processor performance mode in response to receiving said user-specified power management profile.
10. The data processing system-readable medium as set forth in claim 7 , wherein placing said central processing unit in a first processor performance mode in response to a determination that said utilization is greater than a first utilization threshold comprises placing said central processing unit in a first processor performance mode in response to a determination that said utilization is greater than 20%.
11. The data processing system-readable medium as set forth in claim 10 , wherein placing said central processing unit in a second processor performance mode in response to a determination that said utilization is less than or equal to said first utilization threshold comprises placing said central processing unit in a second processor performance mode in response to a determination that said utilization is less than or equal to 20%.
12. The data processing system-readable medium as set forth in claim 8 , wherein placing said central processing unit in a third processor performance mode in response to a determination that said utilization is greater than or equal to a second utilization threshold comprises placing said central processing unit in a third processor performance mode in response to a determination that said utilization is greater than or equal to 95%.
13. A plurality of instructions executable by a data processing system and embodied within a data processing system-readable medium, comprising:
a first code segment to determine a utilization of a central processing unit;
a second code segment to place said central processing unit in a first processor performance mode in response to a determination that said utilization is greater than a first utilization threshold;
a third code segment to place said central processing unit in a second processor performance mode in response to a determination that said utilization is less than or equal to said first utilization threshold, wherein said central processing unit operates at a higher frequency in said first processor performance mode than in said second processor performance mode.
14. The plurality of instructions as set forth in claim 13 , wherein said second code segment to place said central processing unit in a first processor performance mode comprises:
a fourth code segment to receive a user-specified power management profile; and
a fifth code segment to place said central processing unit in said first processor performance mode in response to receiving said user-specified power management profile.
15. The plurality of instructions as set forth in claim 13 , further comprising:
a sixth code segment to place said central processing unit in a third processor performance mode in response to a determination that said utilization is greater than or equal to a second utilization threshold, wherein said second utilization threshold is greater than said first utilization threshold and said central processing unit operates at a higher frequency in said third processor performance mode than in said second processor performance mode.
16. The plurality of instructions as set forth in claim 13 , wherein said second code segment to place said central processing unit in a first processor performance mode in response to a determination that said utilization is greater than a first utilization threshold comprises a code segment to place said central processing unit in said first processor performance mode in response to a determination that said utilization is greater than 20%.
17. The plurality of instructions as set forth in claim 16 , wherein said third code segment to place said central processing unit in a second processor performance mode in response to a determination that said utilization is less than or equal to said first utilization threshold comprises a code segment to place said central processing unit in a second processor performance mode in response to a determination that said utilization is less than or equal to 20%.
18. The plurality of instructions as set forth in claim 15 , wherein said sixth code segment to place said central processing unit in a third processor performance mode in response to a determination that said utilization is greater than or equal to a second utilization threshold comprises a code segment to place said central processing unit in said third processor performance mode in response to a determination that said utilization is greater than or equal to 20%.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/006,872 US20050108587A1 (en) | 2000-12-30 | 2004-12-07 | Demand-based method and system of CPU power management |
US11/478,119 US7596709B2 (en) | 2000-12-30 | 2006-06-28 | CPU power management based on utilization with lowest performance mode at the mid-utilization range |
US12/569,807 US20100023790A1 (en) | 2000-12-30 | 2009-09-29 | Cpu power management based on utilization with lowest performance mode at the mid-utilization range |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/751,759 US6829713B2 (en) | 2000-12-30 | 2000-12-30 | CPU power management based on utilization with lowest performance mode at the mid-utilization range |
US11/006,872 US20050108587A1 (en) | 2000-12-30 | 2004-12-07 | Demand-based method and system of CPU power management |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/751,759 Continuation US6829713B2 (en) | 2000-12-30 | 2000-12-30 | CPU power management based on utilization with lowest performance mode at the mid-utilization range |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/478,119 Continuation-In-Part US7596709B2 (en) | 2000-12-30 | 2006-06-28 | CPU power management based on utilization with lowest performance mode at the mid-utilization range |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050108587A1 true US20050108587A1 (en) | 2005-05-19 |
Family
ID=25023364
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/751,759 Expired - Lifetime US6829713B2 (en) | 2000-12-30 | 2000-12-30 | CPU power management based on utilization with lowest performance mode at the mid-utilization range |
US11/006,872 Abandoned US20050108587A1 (en) | 2000-12-30 | 2004-12-07 | Demand-based method and system of CPU power management |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/751,759 Expired - Lifetime US6829713B2 (en) | 2000-12-30 | 2000-12-30 | CPU power management based on utilization with lowest performance mode at the mid-utilization range |
Country Status (1)
Country | Link |
---|---|
US (2) | US6829713B2 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050249235A1 (en) * | 2004-05-07 | 2005-11-10 | Lian-Chun Lee | Method of accessing a mac address for a nic device |
US20060037024A1 (en) * | 2004-08-13 | 2006-02-16 | Intel Corporation | Managing processing system power and performance based on utilization trends |
US20090217070A1 (en) * | 2005-06-30 | 2009-08-27 | Intel Corporation | Dynamic Bus Parking |
US20090241122A1 (en) * | 2008-03-18 | 2009-09-24 | International Business Machines Corporation | Selecting a number of processing resources to run an application effectively while saving power |
US20100325454A1 (en) * | 2009-06-23 | 2010-12-23 | Hewlett-Packard Development Company, L.P. | Resource and Power Management Using Nested Heterogeneous Hypervisors |
US20100332856A1 (en) * | 2009-06-26 | 2010-12-30 | Song Justin J | System and method for processor utilization adjustment to improve deep C-state use |
CN103324270A (en) * | 2013-06-25 | 2013-09-25 | 东莞宇龙通信科技有限公司 | Mobile terminal and method for adjusting CPU (Central Processing Unit) frequency thereof |
US20230297154A1 (en) * | 2020-02-14 | 2023-09-21 | Telefonaktiebolaget Lm Ericsson (Publ) | Power resource management |
Families Citing this family (180)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6895520B1 (en) * | 2001-03-02 | 2005-05-17 | Advanced Micro Devices, Inc. | Performance and power optimization via block oriented performance measurement and control |
US7017060B2 (en) * | 2001-03-19 | 2006-03-21 | Intel Corporation | Power management system that changes processor level if processor utilization crosses threshold over a period that is different for switching up or down |
US7039575B2 (en) * | 2001-04-12 | 2006-05-02 | Ge Capital Services Structured Finance Group, Inc. | Methods and systems for the evaluation of power generating facilities |
US7254721B1 (en) * | 2001-05-01 | 2007-08-07 | Advanced Micro Devices, Inc. | System and method for controlling an intergrated circuit to enter a predetermined performance state by skipping all intermediate states based on the determined utilization of the intergrated circuit |
US7945600B1 (en) | 2001-05-18 | 2011-05-17 | Stratify, Inc. | Techniques for organizing data to support efficient review and analysis |
US7469246B1 (en) * | 2001-05-18 | 2008-12-23 | Stratify, Inc. | Method and system for classifying or clustering one item into multiple categories |
US7308451B1 (en) | 2001-09-04 | 2007-12-11 | Stratify, Inc. | Method and system for guided cluster based processing on prototypes |
US7058824B2 (en) * | 2001-06-15 | 2006-06-06 | Microsoft Corporation | Method and system for using idle threads to adaptively throttle a computer |
US7188260B1 (en) * | 2001-08-29 | 2007-03-06 | Cisco Technology, Inc. | Apparatus and method for centralized power management |
US6721672B2 (en) * | 2002-01-02 | 2004-04-13 | American Power Conversion | Method and apparatus for preventing overloads of power distribution networks |
US7698583B2 (en) * | 2002-10-03 | 2010-04-13 | Via Technologies, Inc. | Microprocessor capable of dynamically reducing its power consumption in response to varying operating temperature |
US20050044429A1 (en) * | 2003-08-22 | 2005-02-24 | Ip-First Llc | Resource utilization mechanism for microprocessor power management |
US7814350B2 (en) * | 2002-10-03 | 2010-10-12 | Via Technologies, Inc. | Microprocessor with improved thermal monitoring and protection mechanism |
US7770042B2 (en) * | 2002-10-03 | 2010-08-03 | Via Technologies, Inc. | Microprocessor with improved performance during P-state transitions |
US7774627B2 (en) * | 2002-10-03 | 2010-08-10 | Via Technologies, Inc. | Microprocessor capable of dynamically increasing its performance in response to varying operating temperature |
TW575803B (en) * | 2002-10-17 | 2004-02-11 | Uniwill Comp Corp | The method of managing portable computer power cord |
US7131015B2 (en) * | 2002-11-12 | 2006-10-31 | Arm Limited | Performance level selection in a data processing system using a plurality of performance request calculating algorithms |
US7321942B2 (en) * | 2002-11-12 | 2008-01-22 | Arm Limited | Performance counter for adding variable work increment value that is dependent upon clock frequency |
GB2395310A (en) * | 2002-11-12 | 2004-05-19 | Advanced Risc Mach Ltd | Data processing system performance counter |
US7152169B2 (en) * | 2002-11-29 | 2006-12-19 | Intel Corporation | Method for providing power management on multi-threaded processor by using SMM mode to place a physical processor into lower power state |
US7219241B2 (en) * | 2002-11-30 | 2007-05-15 | Intel Corporation | Method for managing virtual and actual performance states of logical processors in a multithreaded processor using system management mode |
US7275012B2 (en) * | 2002-12-30 | 2007-09-25 | Intel Corporation | Automated method and apparatus for processor thermal validation |
US6788155B2 (en) * | 2002-12-31 | 2004-09-07 | Intel Corporation | Low gain phase-locked loop circuit |
US7146514B2 (en) * | 2003-07-23 | 2006-12-05 | Intel Corporation | Determining target operating frequencies for a multiprocessor system |
US7269005B2 (en) * | 2003-11-21 | 2007-09-11 | Intel Corporation | Pumped loop cooling with remote heat exchanger and display cooling |
US7281149B2 (en) * | 2004-02-24 | 2007-10-09 | Hewlett-Packard Development Company, L.P. | Systems and methods for transitioning a CPU from idle to active |
US7698575B2 (en) * | 2004-03-30 | 2010-04-13 | Intel Corporation | Managing power consumption by requesting an adjustment to an operating point of a processor |
US7343502B2 (en) * | 2004-07-26 | 2008-03-11 | Intel Corporation | Method and apparatus for dynamic DLL powerdown and memory self-refresh |
US7890735B2 (en) * | 2004-08-30 | 2011-02-15 | Texas Instruments Incorporated | Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture |
US9063785B2 (en) * | 2004-11-03 | 2015-06-23 | Intel Corporation | Temperature-based thread scheduling |
US7526661B2 (en) * | 2004-12-02 | 2009-04-28 | Intel Corporation | Performance state-based thread management |
US7536567B2 (en) * | 2004-12-10 | 2009-05-19 | Hewlett-Packard Development Company, L.P. | BIOS-based systems and methods of processor power management |
DE102004059996B4 (en) * | 2004-12-13 | 2006-10-05 | Infineon Technologies Ag | Method and apparatus for adjusting the clock frequency of a processor |
US7502948B2 (en) * | 2004-12-30 | 2009-03-10 | Intel Corporation | Method, system, and apparatus for selecting a maximum operation point based on number of active cores and performance level of each of the active cores |
US8826288B2 (en) * | 2005-04-19 | 2014-09-02 | Hewlett-Packard Development Company, L.P. | Computing with both lock-step and free-step processor modes |
US7337339B1 (en) | 2005-09-15 | 2008-02-26 | Azul Systems, Inc. | Multi-level power monitoring, filtering and throttling at local blocks and globally |
TWI297237B (en) * | 2005-10-28 | 2008-05-21 | Hon Hai Prec Ind Co Ltd | Power switching circuit and power supply system using the same |
US8799687B2 (en) | 2005-12-30 | 2014-08-05 | Intel Corporation | Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates |
US7516342B2 (en) * | 2005-12-30 | 2009-04-07 | Intel Corporation | Method, apparatus and system to dynamically choose an optimum power state |
US20080011467A1 (en) * | 2006-06-23 | 2008-01-17 | Intel Corporation | Method, apparatus and system for thermal management using power density feedback |
KR101282139B1 (en) * | 2006-09-11 | 2013-07-04 | 삼성전자주식회사 | Computer system and control method thereof capable of changing performance mode using dedicated button |
US7925901B2 (en) * | 2007-03-15 | 2011-04-12 | International Business Machines Corporation | Method and system for estimating processor utilization from power measurements |
US7904287B2 (en) * | 2007-11-13 | 2011-03-08 | International Business Machines Corporation | Method and system for real-time prediction of power usage for a change to another performance state |
US8024590B2 (en) | 2007-12-10 | 2011-09-20 | Intel Corporation | Predicting future power level states for processor cores |
TW200928706A (en) * | 2007-12-31 | 2009-07-01 | Gigabyte United Inc | Method and system for power management of a motherboard |
TWI372330B (en) * | 2008-08-22 | 2012-09-11 | Asustek Comp Inc | Computer system capable of dynamically cahaging operation voltage and frequency of cpu |
TWI374355B (en) * | 2008-08-22 | 2012-10-11 | Asustek Comp Inc | Computer system capable of dynamically changing core voltage/frequency of cpu |
US8015423B1 (en) * | 2008-10-30 | 2011-09-06 | Hewlett-Packard Development Company, L.P. | Temporally normalized processor utilization |
US8527796B2 (en) | 2009-08-24 | 2013-09-03 | Intel Corporation | Providing adaptive frequency control for a processor using utilization information |
GB2473195B (en) * | 2009-09-02 | 2012-01-11 | 1E Ltd | Controlling the power state of a computer |
GB2473194A (en) * | 2009-09-02 | 2011-03-09 | 1E Ltd | Monitoring the performance of a computer based on the value of a net useful activity metric |
US8650426B2 (en) * | 2009-12-16 | 2014-02-11 | Qualcomm Incorporated | System and method for controlling central processing unit power in a virtualized system |
US9176572B2 (en) | 2009-12-16 | 2015-11-03 | Qualcomm Incorporated | System and method for controlling central processing unit power with guaranteed transient deadlines |
US8689037B2 (en) * | 2009-12-16 | 2014-04-01 | Qualcomm Incorporated | System and method for asynchronously and independently controlling core clocks in a multicore central processing unit |
US9128705B2 (en) * | 2009-12-16 | 2015-09-08 | Qualcomm Incorporated | System and method for controlling central processing unit power with reduced frequency oscillations |
US8775830B2 (en) * | 2009-12-16 | 2014-07-08 | Qualcomm Incorporated | System and method for dynamically controlling a plurality of cores in a multicore central processing unit based on temperature |
US20110145559A1 (en) * | 2009-12-16 | 2011-06-16 | Thomson Steven S | System and method for controlling central processing unit power with guaranteed steady state deadlines |
US9563250B2 (en) * | 2009-12-16 | 2017-02-07 | Qualcomm Incorporated | System and method for controlling central processing unit power based on inferred workload parallelism |
US8909962B2 (en) * | 2009-12-16 | 2014-12-09 | Qualcomm Incorporated | System and method for controlling central processing unit power with guaranteed transient deadlines |
US9104411B2 (en) | 2009-12-16 | 2015-08-11 | Qualcomm Incorporated | System and method for controlling central processing unit power with guaranteed transient deadlines |
US8566619B2 (en) | 2009-12-30 | 2013-10-22 | International Business Machines Corporation | Cooling appliance rating aware data placement |
US8612984B2 (en) | 2010-04-28 | 2013-12-17 | International Business Machines Corporation | Energy-aware job scheduling for cluster environments |
US8527801B2 (en) | 2010-06-30 | 2013-09-03 | International Business Machines Corporation | Performance control of frequency-adapting processors by voltage domain adjustment |
US8943334B2 (en) | 2010-09-23 | 2015-01-27 | Intel Corporation | Providing per core voltage and frequency control |
US8977677B2 (en) | 2010-12-01 | 2015-03-10 | Microsoft Technology Licensing, Llc | Throttling usage of resources |
US8812825B2 (en) * | 2011-01-10 | 2014-08-19 | Dell Products L.P. | Methods and systems for managing performance and power utilization of a processor employing a fully multithreaded load threshold |
US8533512B2 (en) * | 2011-02-10 | 2013-09-10 | International Business Machines Corporation | Dynamic power and performance calibration of data processing systems |
US9069555B2 (en) | 2011-03-21 | 2015-06-30 | Intel Corporation | Managing power consumption in a multi-core processor |
US8793515B2 (en) | 2011-06-27 | 2014-07-29 | Intel Corporation | Increasing power efficiency of turbo mode operation in a processor |
US8769316B2 (en) | 2011-09-06 | 2014-07-01 | Intel Corporation | Dynamically allocating a power budget over multiple domains of a processor |
US8688883B2 (en) | 2011-09-08 | 2014-04-01 | Intel Corporation | Increasing turbo mode residency of a processor |
US9074947B2 (en) | 2011-09-28 | 2015-07-07 | Intel Corporation | Estimating temperature of a processor core in a low power state without thermal sensor information |
US8914650B2 (en) | 2011-09-28 | 2014-12-16 | Intel Corporation | Dynamically adjusting power of non-core processor circuitry including buffer circuitry |
US8954770B2 (en) | 2011-09-28 | 2015-02-10 | Intel Corporation | Controlling temperature of multiple domains of a multi-domain processor using a cross domain margin |
US9026815B2 (en) | 2011-10-27 | 2015-05-05 | Intel Corporation | Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor |
US8832478B2 (en) | 2011-10-27 | 2014-09-09 | Intel Corporation | Enabling a non-core domain to control memory bandwidth in a processor |
US9158693B2 (en) | 2011-10-31 | 2015-10-13 | Intel Corporation | Dynamically controlling cache size to maximize energy efficiency |
US8943340B2 (en) | 2011-10-31 | 2015-01-27 | Intel Corporation | Controlling a turbo mode frequency of a processor |
US8972763B2 (en) | 2011-12-05 | 2015-03-03 | Intel Corporation | Method, apparatus, and system for energy efficiency and energy conservation including determining an optimal power state of the apparatus based on residency time of non-core domains in a power saving state |
US9239611B2 (en) | 2011-12-05 | 2016-01-19 | Intel Corporation | Method, apparatus, and system for energy efficiency and energy conservation including balancing power among multi-frequency domains of a processor based on efficiency rating scheme |
US9329901B2 (en) | 2011-12-09 | 2016-05-03 | Microsoft Technology Licensing, Llc | Resource health based scheduling of workload tasks |
US9052901B2 (en) | 2011-12-14 | 2015-06-09 | Intel Corporation | Method, apparatus, and system for energy efficiency and energy conservation including configurable maximum processor current |
US9098261B2 (en) | 2011-12-15 | 2015-08-04 | Intel Corporation | User level control of power management policies |
US9372524B2 (en) | 2011-12-15 | 2016-06-21 | Intel Corporation | Dynamically modifying a power/performance tradeoff based on processor utilization |
US9305274B2 (en) | 2012-01-16 | 2016-04-05 | Microsoft Technology Licensing, Llc | Traffic shaping based on request resource usage |
WO2013137860A1 (en) | 2012-03-13 | 2013-09-19 | Intel Corporation | Dynamically computing an electrical design point (edp) for a multicore processor |
US9323316B2 (en) | 2012-03-13 | 2016-04-26 | Intel Corporation | Dynamically controlling interconnect frequency in a processor |
US9354689B2 (en) | 2012-03-13 | 2016-05-31 | Intel Corporation | Providing energy efficient turbo operation of a processor |
US9547027B2 (en) | 2012-03-30 | 2017-01-17 | Intel Corporation | Dynamically measuring power consumption in a processor |
US8943341B2 (en) * | 2012-04-10 | 2015-01-27 | International Business Machines Corporation | Minimizing power consumption for fixed-frequency processing unit operation |
US10185566B2 (en) | 2012-04-27 | 2019-01-22 | Intel Corporation | Migrating tasks between asymmetric computing elements of a multi-core processor |
JP5755602B2 (en) * | 2012-06-12 | 2015-07-29 | 株式会社ソニー・コンピュータエンタテインメント | Information processing device |
US8984313B2 (en) | 2012-08-31 | 2015-03-17 | Intel Corporation | Configuring power management functionality in a processor including a plurality of cores by utilizing a register to store a power domain indicator |
US9063727B2 (en) | 2012-08-31 | 2015-06-23 | Intel Corporation | Performing cross-domain thermal control in a processor |
US9342122B2 (en) | 2012-09-17 | 2016-05-17 | Intel Corporation | Distributing power to heterogeneous compute elements of a processor |
US9423858B2 (en) | 2012-09-27 | 2016-08-23 | Intel Corporation | Sharing power between domains in a processor package using encoded power consumption information from a second domain to calculate an available power budget for a first domain |
US9575543B2 (en) | 2012-11-27 | 2017-02-21 | Intel Corporation | Providing an inter-arrival access timer in a processor |
US9183144B2 (en) | 2012-12-14 | 2015-11-10 | Intel Corporation | Power gating a portion of a cache memory |
US9292468B2 (en) | 2012-12-17 | 2016-03-22 | Intel Corporation | Performing frequency coordination in a multiprocessor system based on response timing optimization |
US9405351B2 (en) | 2012-12-17 | 2016-08-02 | Intel Corporation | Performing frequency coordination in a multiprocessor system |
US9075556B2 (en) | 2012-12-21 | 2015-07-07 | Intel Corporation | Controlling configurable peak performance limits of a processor |
US9235252B2 (en) | 2012-12-21 | 2016-01-12 | Intel Corporation | Dynamic balancing of power across a plurality of processor domains according to power policy control bias |
US9081577B2 (en) | 2012-12-28 | 2015-07-14 | Intel Corporation | Independent control of processor core retention states |
US9164565B2 (en) | 2012-12-28 | 2015-10-20 | Intel Corporation | Apparatus and method to manage energy usage of a processor |
US9424620B2 (en) * | 2012-12-29 | 2016-08-23 | Intel Corporation | Identification of GPU phase to determine GPU scalability during runtime |
US9122524B2 (en) * | 2013-01-08 | 2015-09-01 | Microsoft Technology Licensing, Llc | Identifying and throttling tasks based on task interactivity |
US9335803B2 (en) | 2013-02-15 | 2016-05-10 | Intel Corporation | Calculating a dynamically changeable maximum operating voltage value for a processor based on a different polynomial equation using a set of coefficient values and a number of current active cores |
US9367114B2 (en) | 2013-03-11 | 2016-06-14 | Intel Corporation | Controlling operating voltage of a processor |
US9395784B2 (en) | 2013-04-25 | 2016-07-19 | Intel Corporation | Independently controlling frequency of plurality of power domains in a processor system |
US9377841B2 (en) | 2013-05-08 | 2016-06-28 | Intel Corporation | Adaptively limiting a maximum operating frequency in a multicore processor |
US9823719B2 (en) | 2013-05-31 | 2017-11-21 | Intel Corporation | Controlling power delivery to a processor via a bypass |
US9348401B2 (en) | 2013-06-25 | 2016-05-24 | Intel Corporation | Mapping a performance request to an operating frequency in a processor |
US9471088B2 (en) | 2013-06-25 | 2016-10-18 | Intel Corporation | Restricting clock signal delivery in a processor |
US9348407B2 (en) | 2013-06-27 | 2016-05-24 | Intel Corporation | Method and apparatus for atomic frequency and voltage changes |
US9377836B2 (en) | 2013-07-26 | 2016-06-28 | Intel Corporation | Restricting clock signal delivery based on activity in a processor |
US9495001B2 (en) | 2013-08-21 | 2016-11-15 | Intel Corporation | Forcing core low power states in a processor |
US10386900B2 (en) | 2013-09-24 | 2019-08-20 | Intel Corporation | Thread aware power management |
US9405345B2 (en) | 2013-09-27 | 2016-08-02 | Intel Corporation | Constraining processor operation based on power envelope information |
US9594560B2 (en) | 2013-09-27 | 2017-03-14 | Intel Corporation | Estimating scalability value for a specific domain of a multicore processor based on active state residency of the domain, stall duration of the domain, memory bandwidth of the domain, and a plurality of coefficients based on a workload to execute on the domain |
US9436258B1 (en) * | 2013-11-21 | 2016-09-06 | Google Inc. | Dynamic service level objective power control in distributed process |
US9494998B2 (en) | 2013-12-17 | 2016-11-15 | Intel Corporation | Rescheduling workloads to enforce and maintain a duty cycle |
US9459689B2 (en) | 2013-12-23 | 2016-10-04 | Intel Corporation | Dyanamically adapting a voltage of a clock generation circuit |
US9323525B2 (en) | 2014-02-26 | 2016-04-26 | Intel Corporation | Monitoring vector lane duty cycle for dynamic optimization |
US9665153B2 (en) | 2014-03-21 | 2017-05-30 | Intel Corporation | Selecting a low power state based on cache flush latency determination |
US10108454B2 (en) | 2014-03-21 | 2018-10-23 | Intel Corporation | Managing dynamic capacitance using code scheduling |
JP2015231098A (en) | 2014-06-04 | 2015-12-21 | ソニー株式会社 | Vibration device and vibration method |
US9760158B2 (en) | 2014-06-06 | 2017-09-12 | Intel Corporation | Forcing a processor into a low power state |
US10417149B2 (en) | 2014-06-06 | 2019-09-17 | Intel Corporation | Self-aligning a processor duty cycle with interrupts |
US9513689B2 (en) | 2014-06-30 | 2016-12-06 | Intel Corporation | Controlling processor performance scaling based on context |
US9606602B2 (en) | 2014-06-30 | 2017-03-28 | Intel Corporation | Method and apparatus to prevent voltage droop in a computer |
US9575537B2 (en) | 2014-07-25 | 2017-02-21 | Intel Corporation | Adaptive algorithm for thermal throttling of multi-core processors with non-homogeneous performance states |
US9760136B2 (en) | 2014-08-15 | 2017-09-12 | Intel Corporation | Controlling temperature of a system memory |
US20160077571A1 (en) * | 2014-09-12 | 2016-03-17 | Microsoft Corporation | Heuristic Processor Power Management in Operating Systems |
US9671853B2 (en) | 2014-09-12 | 2017-06-06 | Intel Corporation | Processor operating by selecting smaller of requested frequency and an energy performance gain (EPG) frequency |
US10339023B2 (en) | 2014-09-25 | 2019-07-02 | Intel Corporation | Cache-aware adaptive thread scheduling and migration |
US9977477B2 (en) | 2014-09-26 | 2018-05-22 | Intel Corporation | Adapting operating parameters of an input/output (IO) interface circuit of a processor |
US9684360B2 (en) | 2014-10-30 | 2017-06-20 | Intel Corporation | Dynamically controlling power management of an on-die memory of a processor |
US9703358B2 (en) | 2014-11-24 | 2017-07-11 | Intel Corporation | Controlling turbo mode frequency operation in a processor |
US10048744B2 (en) | 2014-11-26 | 2018-08-14 | Intel Corporation | Apparatus and method for thermal management in a multi-chip package |
US9710043B2 (en) | 2014-11-26 | 2017-07-18 | Intel Corporation | Controlling a guaranteed frequency of a processor |
US20160147280A1 (en) | 2014-11-26 | 2016-05-26 | Tessil Thomas | Controlling average power limits of a processor |
US10877530B2 (en) | 2014-12-23 | 2020-12-29 | Intel Corporation | Apparatus and method to provide a thermal parameter report for a multi-chip package |
US20160224098A1 (en) | 2015-01-30 | 2016-08-04 | Alexander Gendler | Communicating via a mailbox interface of a processor |
US9639134B2 (en) | 2015-02-05 | 2017-05-02 | Intel Corporation | Method and apparatus to provide telemetry data to a power controller of a processor |
US9910481B2 (en) | 2015-02-13 | 2018-03-06 | Intel Corporation | Performing power management in a multicore processor |
US10234930B2 (en) | 2015-02-13 | 2019-03-19 | Intel Corporation | Performing power management in a multicore processor |
US9874922B2 (en) | 2015-02-17 | 2018-01-23 | Intel Corporation | Performing dynamic power control of platform devices |
US9842082B2 (en) | 2015-02-27 | 2017-12-12 | Intel Corporation | Dynamically updating logical identifiers of cores of a processor |
US9710054B2 (en) | 2015-02-28 | 2017-07-18 | Intel Corporation | Programmable power management agent |
US9760160B2 (en) | 2015-05-27 | 2017-09-12 | Intel Corporation | Controlling performance states of processing engines of a processor |
US9710041B2 (en) | 2015-07-29 | 2017-07-18 | Intel Corporation | Masking a power state of a core of a processor |
US10001822B2 (en) | 2015-09-22 | 2018-06-19 | Intel Corporation | Integrating a power arbiter in a processor |
US9983644B2 (en) | 2015-11-10 | 2018-05-29 | Intel Corporation | Dynamically updating at least one power management operational parameter pertaining to a turbo mode of a processor for increased performance |
US9910470B2 (en) | 2015-12-16 | 2018-03-06 | Intel Corporation | Controlling telemetry data communication in a processor |
US10146286B2 (en) | 2016-01-14 | 2018-12-04 | Intel Corporation | Dynamically updating a power management policy of a processor |
US10289188B2 (en) | 2016-06-21 | 2019-05-14 | Intel Corporation | Processor having concurrent core and fabric exit from a low power state |
US10281975B2 (en) | 2016-06-23 | 2019-05-07 | Intel Corporation | Processor having accelerated user responsiveness in constrained environment |
US10324519B2 (en) | 2016-06-23 | 2019-06-18 | Intel Corporation | Controlling forced idle state operation in a processor |
US10379596B2 (en) | 2016-08-03 | 2019-08-13 | Intel Corporation | Providing an interface for demotion control information in a processor |
US10423206B2 (en) | 2016-08-31 | 2019-09-24 | Intel Corporation | Processor to pre-empt voltage ramps for exit latency reductions |
US10234920B2 (en) | 2016-08-31 | 2019-03-19 | Intel Corporation | Controlling current consumption of a processor based at least in part on platform capacitance |
US10379904B2 (en) | 2016-08-31 | 2019-08-13 | Intel Corporation | Controlling a performance state of a processor using a combination of package and thread hint information |
US10168758B2 (en) | 2016-09-29 | 2019-01-01 | Intel Corporation | Techniques to enable communication between a processor and voltage regulator |
US10429919B2 (en) | 2017-06-28 | 2019-10-01 | Intel Corporation | System, apparatus and method for loose lock-step redundancy power management |
US10551901B2 (en) | 2017-07-01 | 2020-02-04 | Microsoft Technology Licensing, Llc | Core frequency management using effective utilization for power-efficient performance |
WO2019040054A1 (en) | 2017-08-23 | 2019-02-28 | Intel Corporation | System, apparatus and method for adaptive operating voltage in a field programmable gate array (fpga) |
US10620266B2 (en) | 2017-11-29 | 2020-04-14 | Intel Corporation | System, apparatus and method for in-field self testing in a diagnostic sleep state |
US10620682B2 (en) | 2017-12-21 | 2020-04-14 | Intel Corporation | System, apparatus and method for processor-external override of hardware performance state control of a processor |
US10620969B2 (en) | 2018-03-27 | 2020-04-14 | Intel Corporation | System, apparatus and method for providing hardware feedback information in a processor |
US10739844B2 (en) | 2018-05-02 | 2020-08-11 | Intel Corporation | System, apparatus and method for optimized throttling of a processor |
US10955899B2 (en) | 2018-06-20 | 2021-03-23 | Intel Corporation | System, apparatus and method for responsive autonomous hardware performance state control of a processor |
US10976801B2 (en) | 2018-09-20 | 2021-04-13 | Intel Corporation | System, apparatus and method for power budget distribution for a plurality of virtual machines to execute on a processor |
US10860083B2 (en) | 2018-09-26 | 2020-12-08 | Intel Corporation | System, apparatus and method for collective power control of multiple intellectual property agents and a shared power rail |
US11656676B2 (en) | 2018-12-12 | 2023-05-23 | Intel Corporation | System, apparatus and method for dynamic thermal distribution of a system on chip |
US11256657B2 (en) | 2019-03-26 | 2022-02-22 | Intel Corporation | System, apparatus and method for adaptive interconnect routing |
US11442529B2 (en) | 2019-05-15 | 2022-09-13 | Intel Corporation | System, apparatus and method for dynamically controlling current consumption of processing circuits of a processor |
US11698812B2 (en) | 2019-08-29 | 2023-07-11 | Intel Corporation | System, apparatus and method for providing hardware state feedback to an operating system in a heterogeneous processor |
US11366506B2 (en) | 2019-11-22 | 2022-06-21 | Intel Corporation | System, apparatus and method for globally aware reactive local power control in a processor |
US11132201B2 (en) | 2019-12-23 | 2021-09-28 | Intel Corporation | System, apparatus and method for dynamic pipeline stage control of data path dominant circuitry of an integrated circuit |
US11921564B2 (en) | 2022-02-28 | 2024-03-05 | Intel Corporation | Saving and restoring configuration and status information with reduced latency |
Citations (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4485440A (en) * | 1981-09-24 | 1984-11-27 | At&T Bell Laboratories | Central processor utilization monitor |
US5021679A (en) * | 1989-06-30 | 1991-06-04 | Poqet Computer Corporation | Power supply and oscillator for a computer system providing automatic selection of supply voltage and frequency |
US5072376A (en) * | 1988-06-10 | 1991-12-10 | Amdahl Corporation | Measuring utilization of processor shared by multiple system control programs |
US5153535A (en) * | 1989-06-30 | 1992-10-06 | Poget Computer Corporation | Power supply and oscillator for a computer system providing automatic selection of supply voltage and frequency |
US5349688A (en) * | 1989-11-13 | 1994-09-20 | Chips & Technologies, Inc. | Method for reducing power consumption includes comparing variance in number of times microprocessor tried to read input in predefined period to predefined variance |
US5564015A (en) * | 1994-05-12 | 1996-10-08 | Ast Research, Inc. | CPU activity monitoring through cache watching |
US5623647A (en) * | 1995-03-07 | 1997-04-22 | Intel Corporation | Application specific clock throttling |
US5627412A (en) * | 1994-11-07 | 1997-05-06 | Norand Corporation | Dynamically switchable power supply |
US5710929A (en) * | 1990-06-01 | 1998-01-20 | Vadem Corporation | Multi-state power management for computer systems |
US5719800A (en) * | 1995-06-30 | 1998-02-17 | Intel Corporation | Performance throttling to reduce IC power consumption |
US5745375A (en) * | 1995-09-29 | 1998-04-28 | Intel Corporation | Apparatus and method for controlling power usage |
US5752011A (en) * | 1994-06-20 | 1998-05-12 | Thomas; C. Douglas | Method and system for controlling a processor's clock frequency in accordance with the processor's temperature |
US5787294A (en) * | 1995-10-13 | 1998-07-28 | Vlsi Technology, Inc. | System for reducing the power consumption of a computer system and method therefor |
US5815693A (en) * | 1995-12-15 | 1998-09-29 | National Semiconductor Corporation | Processor having a frequency modulated core clock based on the criticality of program activity |
US5974567A (en) * | 1997-06-20 | 1999-10-26 | Compaq Computer Corporation | Ghost partition |
US5982814A (en) * | 1996-08-01 | 1999-11-09 | Pc-Tel, Inc. | Dynamic control of processor utilization by a host signal processing modem |
US6006336A (en) * | 1989-10-30 | 1999-12-21 | Texas Instruments Incorporated | Real-time power conservation for computers |
US6105142A (en) * | 1997-02-11 | 2000-08-15 | Vlsi Technology, Inc. | Intelligent power management interface for computer system hardware |
US6118306A (en) * | 1998-12-03 | 2000-09-12 | Intel Corporation | Changing clock frequency |
US6192479B1 (en) * | 1995-01-19 | 2001-02-20 | Texas Instruments Incorporated | Data processing with progressive, adaptive, CPU-driven power management |
US6212644B1 (en) * | 1998-09-10 | 2001-04-03 | Intel Corporation | Controlling temperatures in computers |
US6272642B2 (en) * | 1998-12-03 | 2001-08-07 | Intel Corporation | Managing a system's performance state |
US6470456B1 (en) * | 1998-07-24 | 2002-10-22 | Mitac Technology Corp. | Method and system for dynamically controlling the operation speed of a processor |
US6557108B1 (en) * | 1999-05-28 | 2003-04-29 | 3Com Corporation | System and method in a modem for providing a shortened reset pulse upon receipt of an external reset pulse |
US6574739B1 (en) * | 2000-04-14 | 2003-06-03 | Compal Electronics, Inc. | Dynamic power saving by monitoring CPU utilization |
-
2000
- 2000-12-30 US US09/751,759 patent/US6829713B2/en not_active Expired - Lifetime
-
2004
- 2004-12-07 US US11/006,872 patent/US20050108587A1/en not_active Abandoned
Patent Citations (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4485440A (en) * | 1981-09-24 | 1984-11-27 | At&T Bell Laboratories | Central processor utilization monitor |
US5072376A (en) * | 1988-06-10 | 1991-12-10 | Amdahl Corporation | Measuring utilization of processor shared by multiple system control programs |
US5021679A (en) * | 1989-06-30 | 1991-06-04 | Poqet Computer Corporation | Power supply and oscillator for a computer system providing automatic selection of supply voltage and frequency |
US5153535A (en) * | 1989-06-30 | 1992-10-06 | Poget Computer Corporation | Power supply and oscillator for a computer system providing automatic selection of supply voltage and frequency |
US5307003A (en) * | 1989-06-30 | 1994-04-26 | Poqet Computer Corporation | Varying the supply voltage in response to the current supplied to a computer system |
US6006336A (en) * | 1989-10-30 | 1999-12-21 | Texas Instruments Incorporated | Real-time power conservation for computers |
US5349688A (en) * | 1989-11-13 | 1994-09-20 | Chips & Technologies, Inc. | Method for reducing power consumption includes comparing variance in number of times microprocessor tried to read input in predefined period to predefined variance |
US5710929A (en) * | 1990-06-01 | 1998-01-20 | Vadem Corporation | Multi-state power management for computer systems |
US5564015A (en) * | 1994-05-12 | 1996-10-08 | Ast Research, Inc. | CPU activity monitoring through cache watching |
US5974557A (en) * | 1994-06-20 | 1999-10-26 | Thomas; C. Douglass | Method and system for performing thermal and power management for a computer |
US6487668B2 (en) * | 1994-06-20 | 2002-11-26 | C. Douglass Thomas | Thermal and power management to computer systems |
US6216235B1 (en) * | 1994-06-20 | 2001-04-10 | C. Douglass Thomas | Thermal and power management for computer systems |
US5752011A (en) * | 1994-06-20 | 1998-05-12 | Thomas; C. Douglas | Method and system for controlling a processor's clock frequency in accordance with the processor's temperature |
US5627412A (en) * | 1994-11-07 | 1997-05-06 | Norand Corporation | Dynamically switchable power supply |
US6192479B1 (en) * | 1995-01-19 | 2001-02-20 | Texas Instruments Incorporated | Data processing with progressive, adaptive, CPU-driven power management |
US5623647A (en) * | 1995-03-07 | 1997-04-22 | Intel Corporation | Application specific clock throttling |
US5719800A (en) * | 1995-06-30 | 1998-02-17 | Intel Corporation | Performance throttling to reduce IC power consumption |
US5745375A (en) * | 1995-09-29 | 1998-04-28 | Intel Corporation | Apparatus and method for controlling power usage |
US5787294A (en) * | 1995-10-13 | 1998-07-28 | Vlsi Technology, Inc. | System for reducing the power consumption of a computer system and method therefor |
US5815693A (en) * | 1995-12-15 | 1998-09-29 | National Semiconductor Corporation | Processor having a frequency modulated core clock based on the criticality of program activity |
US5982814A (en) * | 1996-08-01 | 1999-11-09 | Pc-Tel, Inc. | Dynamic control of processor utilization by a host signal processing modem |
US6105142A (en) * | 1997-02-11 | 2000-08-15 | Vlsi Technology, Inc. | Intelligent power management interface for computer system hardware |
US5974567A (en) * | 1997-06-20 | 1999-10-26 | Compaq Computer Corporation | Ghost partition |
US6470456B1 (en) * | 1998-07-24 | 2002-10-22 | Mitac Technology Corp. | Method and system for dynamically controlling the operation speed of a processor |
US6212644B1 (en) * | 1998-09-10 | 2001-04-03 | Intel Corporation | Controlling temperatures in computers |
US6272642B2 (en) * | 1998-12-03 | 2001-08-07 | Intel Corporation | Managing a system's performance state |
US6118306A (en) * | 1998-12-03 | 2000-09-12 | Intel Corporation | Changing clock frequency |
US6557108B1 (en) * | 1999-05-28 | 2003-04-29 | 3Com Corporation | System and method in a modem for providing a shortened reset pulse upon receipt of an external reset pulse |
US6574739B1 (en) * | 2000-04-14 | 2003-06-03 | Compal Electronics, Inc. | Dynamic power saving by monitoring CPU utilization |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050249235A1 (en) * | 2004-05-07 | 2005-11-10 | Lian-Chun Lee | Method of accessing a mac address for a nic device |
US20060037024A1 (en) * | 2004-08-13 | 2006-02-16 | Intel Corporation | Managing processing system power and performance based on utilization trends |
US7761874B2 (en) * | 2004-08-13 | 2010-07-20 | Intel Corporation | Managing processing system power and performance based on utilization trends |
US20090217070A1 (en) * | 2005-06-30 | 2009-08-27 | Intel Corporation | Dynamic Bus Parking |
US20090241122A1 (en) * | 2008-03-18 | 2009-09-24 | International Business Machines Corporation | Selecting a number of processing resources to run an application effectively while saving power |
US8205209B2 (en) * | 2008-03-18 | 2012-06-19 | International Business Machines Corporation | Selecting a number of processing resources to run an application effectively while saving power |
US20100325454A1 (en) * | 2009-06-23 | 2010-12-23 | Hewlett-Packard Development Company, L.P. | Resource and Power Management Using Nested Heterogeneous Hypervisors |
US9152200B2 (en) * | 2009-06-23 | 2015-10-06 | Hewlett-Packard Development Company, L.P. | Resource and power management using nested heterogeneous hypervisors |
US20100332856A1 (en) * | 2009-06-26 | 2010-12-30 | Song Justin J | System and method for processor utilization adjustment to improve deep C-state use |
US8347119B2 (en) * | 2009-06-26 | 2013-01-01 | Intel Corporation | System and method for processor utilization adjustment to improve deep C-state use |
CN103324270A (en) * | 2013-06-25 | 2013-09-25 | 东莞宇龙通信科技有限公司 | Mobile terminal and method for adjusting CPU (Central Processing Unit) frequency thereof |
US20230297154A1 (en) * | 2020-02-14 | 2023-09-21 | Telefonaktiebolaget Lm Ericsson (Publ) | Power resource management |
Also Published As
Publication number | Publication date |
---|---|
US6829713B2 (en) | 2004-12-07 |
US20020087901A1 (en) | 2002-07-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6829713B2 (en) | CPU power management based on utilization with lowest performance mode at the mid-utilization range | |
US7596709B2 (en) | CPU power management based on utilization with lowest performance mode at the mid-utilization range | |
US6711526B2 (en) | Operating system-independent method and system of determining CPU utilization | |
US7917787B2 (en) | Method, apparatus and system to dynamically choose an aoptimum power state | |
US6795927B1 (en) | Power state resynchronization | |
US7647513B2 (en) | Method and apparatus for improving responsiveness of a power management system in a computing device | |
US5564015A (en) | CPU activity monitoring through cache watching | |
US5991883A (en) | Power conservation method for a portable computer with LCD display | |
US5590342A (en) | Method and apparatus for reducing power consumption in a computer system using virtual device drivers | |
JP3406594B2 (en) | Computer power management system | |
US6845456B1 (en) | CPU utilization measurement techniques for use in power management | |
US7941683B2 (en) | Data processing device with low-power cache access mode | |
JP4422017B2 (en) | Method and apparatus for providing a separate power management state | |
US7694164B2 (en) | Operating system-independent method and system of determining CPU utilization | |
JP2008544736A (en) | Reducing computational system power through idle synchronization | |
JP2002526854A (en) | How to save power without sacrificing performance | |
KR20030041142A (en) | Method and apparatus to enhance processor power management | |
US7617488B2 (en) | Method and apparatus and determining processor utilization | |
US6112309A (en) | Computer system, device and operation frequency control method | |
US8452995B1 (en) | Universal serial bus low power idle mode | |
JP2000039937A (en) | Computer system and its power-saving control method | |
CA2527326C (en) | Method and apparatus for specifying factors that impede power savings of a processor | |
JP3007866B2 (en) | Computer system, device and operating frequency control method | |
JP2000305673A (en) | Method and device for managing power consumption |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |