US20050136619A1 - Semiconductor devices and methods of forming a trench in a semiconductor device - Google Patents
Semiconductor devices and methods of forming a trench in a semiconductor device Download PDFInfo
- Publication number
- US20050136619A1 US20050136619A1 US11/047,337 US4733705A US2005136619A1 US 20050136619 A1 US20050136619 A1 US 20050136619A1 US 4733705 A US4733705 A US 4733705A US 2005136619 A1 US2005136619 A1 US 2005136619A1
- Authority
- US
- United States
- Prior art keywords
- trench
- side wall
- layer
- forming
- hollow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Abstract
Description
- This patent arises from a divisional application claiming priority from U.S. application Ser. No. 10/745,028, filed Dec. 23, 2003.
- This disclosure relates generally to semiconductor devices, and more particularly to methods of forming a trench formed as a field region in a semiconductor device to isolate one active region from another with insulation material without any voids.
- STI (shallow trench isolation) structures have been widely used as isolation structures in semiconductor devices. These STI structures facilitate the miniaturization of semiconductor devices since the size of the field region is limited to a desired size of a trench by forming the trench in the semiconductor substrate and filling the trench with insulation material.
- Conventionally, in forming a trench isolation structure, a pad oxide film is deposited at a thickness of about 200 Å on a semiconductor substrate. A silicon nitride film is then deposited on the pad oxide film. Subsequently, a photosensitive film is applied and exposed on the silicon nitride film. The photosensitive film is then formed into a pattern by removing only the portion of the photosensitive film covering the region to be processed to define the trench.
- Next, the trench is formed in the semiconductor substrate by dry etching the exposed silicon nitride film, the pad oxide film, and the semiconductor substrate up to a predetermined depth while using the photosensitive film pattern as a mask. Subsequently, the photosensitive film pattern is removed. A cleaning process is then performed.
- Subsequently, a liner oxide film is formed on an entire surface of the silicon nitride film (including on an inner wall of the trench). A trench oxide film is then thickly deposited on the liner oxide film such that the trench is sufficiently filled.
- The trench oxide film is then planarized by a chemical mechanical polishing process until the silicon nitride film is exposed. Finally, the silicon nitride film is removed to complete the trench isolation process.
- In the conventional trench isolation structure, stress is concentrated on an edge of the trench. In addition, this edge of the trench is likely hollowed since the liner oxide film and a portion of the trench oxide film are etched together when the silicon nitride film is wet etched. This may make the edge of the trench fragile.
- Moreover, as semiconductor devices become more and more integrated, contacts become more susceptible to misalignment with the fragile edge of the trench. This misalignment may cause leakage current due to contact spiking, which may cause fatal defects in the semiconductor device.
- Conventional techniques for preventing this leakage current of the trench due to misalignment of the contacts are described in U.S. Pat. No. 6,420,770, U.S. Pat. No. 6,406,987, U.S. Pat. No. 6,403,445, and U.S. Pat. No. 6,350,661.
- Presently, using up to a 0.18 μm design rule, a contact pattern can be formed with a distance of 0.2-0.3 μm between the contact and the trench without misalignment. However, as the semiconductor device becomes more highly integrated, for example, by a 0.15 μm or 0.13 μm design rule and the like in the future, the distance between the contact and the trench becomes 0.1 μm, 0.0 μm, etc, (i.e., there is no margin for the contact alignment), and the current patterning processes cannot integrate the semiconductor device.
-
FIGS. 1 a to 1 e are cross-sectional views illustrating an example method of forming a trench in a semiconductor device in accordance with the teachings of the present disclosure. - In view of the foregoing, the present disclosure recognizes that there is a need for a new structured trench and a new formation process thereof in order to realize more highly integrated semiconductor devices. Hereinafter, an example method of fabricating a semiconductor device incorporating such a trench will be described in detail with reference to the accompanying drawings.
-
FIGS. 1 a to 1 e are cross-sectional views illustrating an example method of forming a trench in a semiconductor device. First, as shown inFIG. 1 a, apad oxide film 12 is thinly deposited on asemiconductor substrate 11. A firstsilicon nitride film 13 is deposited on thepad oxide film 12. A photosensitive film is applied and exposed on the firstsilicon nitride film 13. A pattern is then formed in thephotosensitive film 14 by removing only the portion (s) of the photosensitive film on the region(s) in which the trench(es) are to be formed. - The
pad oxide film 12 is optionally deposited in order to prevent or reduce stressing of the firstsilicon nitride film 13 from being transferred to thesemiconductor substrate 11. Thepad oxide film 12 is preferably deposited thinly, for example, at a thickness of about 100-300 Å. - Since the first
silicon nitride film 13 is made of a material having a high selectivity over thepad oxide film 12, the firstsilicon nitride film 13 functions as a termination layer in a subsequent chemical and mechanical polishing process for a trench oxide. The firstsilicon nitride film 13 is preferably deposited at a thickness of about 1500-3000 Å, for example, a thickness of about 2000 Å. - Although in the illustrated example, the
pad oxide film 12 and the firstsilicon nitride film 13 are formed, persons of ordinary skill in the art will appreciate that thepad oxide film 12 and the firstsilicon nitride film 13 are optional and may be not formed. - After the
photosensitive film 14 is patterned, a hollow 100 is formed by etching the exposed firstsilicon nitride film 13, thepad oxide film 12, and thesemiconductor substrate 11 up to a predetermined depth using thephotosensitive film pattern 14 as a mask. Subsequently, thephotosensitive film pattern 14 is removed, and then a cleaning process is performed. - The depth of the hollow 100 preferably corresponds to the thickness of a side wall layer to remain in a subsequent etch back process. In consideration of this, the hollow 100 is formed by etching the
semiconductor substrate 11 such that the depth of the hollow 100 is thinner than a desired depth of the trench. - Next, as shown in
FIG. 1 b, a secondsilicon nitride film 15 is deposited as a sacrificial layer on an entire surface of the firstsilicon nitride film 13 and an inner wall of the hollow 100. Next, the firstsilicon nitride film 13 and thesemiconductor substrate 11 on the bottom of the hollow 100 are exposed while leaving the secondsilicon nitride film 15 on a side wall of the hollow 100 to form aside wall layer 15′, as shown inFIG. 1 c. - The thickness of the
sacrificial layer 15 is preferably selected such that theside wall layer 15′ has a width of about 200-400 Å measured from the side wall of the hollow 100. When viewed from an entire sectional view, theside wall layer 15′ is formed on both side walls of the hollow. - Subsequently, a
trench 200 is formed by further etching thesemiconductor substrate 11 exposed on the bottom of the hollow 100 up to the desired depth of the trench (seeFIG. 1 c). - Next, as shown in
FIG. 1 d, aninsulation film 16 is thickly deposited on the entire top surface of the firstsilicon nitride film 13, theside wall film 15′ and the trench. - Then, as show in
FIG. 1 e, the trench isolation process is completed by chemically mechanically polishing theinsulation film 16 until the firstsilicon nitride film 13 is exposed. - The
insulation film 16 can be formed, for example, of an oxide film. - Before the
insulation film 16 is formed, a liner oxide layer can be formed on theside wall layer 15′ and the trench. In such a case, the trench is filled by forming the insulation film on the liner oxide layer. - As apparent from the above description, the hollow 100 is formed by etching the semiconductor substrate first. The
nitride film 15 is then deposited on the inner wall of the hollow 100. Theside wall layer 15′ is then formed by etching back thenitride film 15. Subsequently, the desired trench is formed by etching the semiconductor substrate. Because theside wall layer 15′ is formed on the side wall of the trench, contact spiking is prevented even in the case of misalignment of the contact pattern. Therefore, the impossibility of realizing a highly integrated semiconductor device due to contact spiking can be overcome. - From the foregoing, persons of ordinary skill in the art will appreciate that the above disclosed methods secure a process margin for misalignment of a contact pattern in order to facilitate the fabrication of more highly integrated semiconductor.
- The illustrated method of forming a trench in a semiconductor device comprises: forming a hollow 100 by etching a portion of a
semiconductor substrate 11; forming aside wall layer 15′ on an inner side wall of the hollow 100; forming a trench by further etching thesemiconductor substrate 11 exposed through the bottom of the hollow; and filling the trench by forming aninsulation film 16 on the side wall layer and the trench. - Preferably, forming the
side wall layer 15′ on the inner side wall of the hollow 100 includes forming asacrificial layer 15 on the hollow 100 and thesemiconductor substrate 11; and forming theside wall layer 15′ by etching back thesacrificial layer 15 such that thesacrificial layer 15 remains only on the inner side wall of the hollow 100. - Preferably, the
sacrificial layer 15 is a silicon nitride film. - Preferably, the
side wall layer 15′ has a width of approximately 200-400 Å measured from the inner side wall of the hollow 100. - Preferably, before forming the hollow 100, a
pad oxide film 12 and a polishingstop layer 13 is formed, wherein the hollow 100 is formed by etching the polishingstop layer 13, thepad oxide film 12 and thesemiconductor substrate 11. - Preferably, the polishing
stop layer 13 is a silicon nitride film formed at a thickness of approximately 1500-3000 Å. - Preferably, the
pad oxide film 12 is formed at a thickness of approximately 100-300 Å. - Preferably, in filling the trench by forming the
insulation film 16 on theside wall layer 15′ and the trench, theinsulation film 16 is formed to fill the trench on the entire surfaces of the polishingstop layer 13, theside wall layer 15′ and the trench, and theinsulation film 16 is then chemically mechanically polished until the polishingstop layer 13 is exposed. - Preferably, an oxide film is formed as the
insulation film 16. - Preferably, before the
insulation film 16 is formed, a liner oxide layer is formed on theside wall layer 15′ and the trench, and theinsulation film 16 is then formed on the liner oxide layer to fill the trench. - Although certain example methods and apparatus have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus and articles of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/047,337 US20050136619A1 (en) | 2002-12-24 | 2005-01-28 | Semiconductor devices and methods of forming a trench in a semiconductor device |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020083439A KR100888150B1 (en) | 2002-12-24 | 2002-12-24 | Formation method of trench in semiconductor device |
KR10-2002-0083439 | 2002-12-24 | ||
US10/745,028 US7030454B2 (en) | 2002-12-24 | 2003-12-23 | Semiconductor devices and methods of forming a trench in a semiconductor device |
US11/047,337 US20050136619A1 (en) | 2002-12-24 | 2005-01-28 | Semiconductor devices and methods of forming a trench in a semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/745,028 Division US7030454B2 (en) | 2002-12-24 | 2003-12-23 | Semiconductor devices and methods of forming a trench in a semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050136619A1 true US20050136619A1 (en) | 2005-06-23 |
Family
ID=32709709
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/745,028 Expired - Fee Related US7030454B2 (en) | 2002-12-24 | 2003-12-23 | Semiconductor devices and methods of forming a trench in a semiconductor device |
US11/047,337 Abandoned US20050136619A1 (en) | 2002-12-24 | 2005-01-28 | Semiconductor devices and methods of forming a trench in a semiconductor device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/745,028 Expired - Fee Related US7030454B2 (en) | 2002-12-24 | 2003-12-23 | Semiconductor devices and methods of forming a trench in a semiconductor device |
Country Status (2)
Country | Link |
---|---|
US (2) | US7030454B2 (en) |
KR (1) | KR100888150B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070145490A1 (en) * | 2005-12-26 | 2007-06-28 | Jong Bok Lee | Semiconductor device and method for manufacturing the same |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100469763B1 (en) * | 2003-02-03 | 2005-02-02 | 매그나칩 반도체 유한회사 | Method for forming isolation of semiconductor device |
KR101867755B1 (en) * | 2017-01-26 | 2018-06-15 | 매그나칩 반도체 유한회사 | Semiconductor and method for fabricating the same |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5128743A (en) * | 1980-09-17 | 1992-07-07 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
US6064104A (en) * | 1996-01-31 | 2000-05-16 | Advanced Micro Devices, Inc. | Trench isolation structures with oxidized silicon regions and method for making the same |
US6096612A (en) * | 1998-04-30 | 2000-08-01 | Texas Instruments Incorporated | Increased effective transistor width using double sidewall spacers |
US6165871A (en) * | 1999-07-16 | 2000-12-26 | Chartered Semiconductor Manufacturing Ltd. | Method of making low-leakage architecture for sub-0.18 μm salicided CMOS device |
US6204192B1 (en) * | 1999-03-29 | 2001-03-20 | Lsi Logic Corporation | Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures |
US6207532B1 (en) * | 1999-09-30 | 2001-03-27 | Taiwan Semiconductor Manufacturing Company | STI process for improving isolation for deep sub-micron application |
US6232202B1 (en) * | 1998-11-06 | 2001-05-15 | United Microelectronics Corp. | Method for manufacturing shallow trench isolation structure including a dual trench |
US6274457B1 (en) * | 1997-08-28 | 2001-08-14 | Mitsubishi Denki Kabushiki Kaisha | Method for manufacturing an isolation trench having plural profile angles |
US6323104B1 (en) * | 2000-03-01 | 2001-11-27 | Micron Technology, Inc. | Method of forming an integrated circuitry isolation trench, method of forming integrated circuitry, and integrated circuitry |
US6350661B2 (en) * | 1999-07-12 | 2002-02-26 | Chartered Semiconductor Manufacturing Ltd. | Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts |
US6350655B2 (en) * | 1997-08-01 | 2002-02-26 | Nippon Steel Corporation | Semiconductor device and a method of manufacturing the same |
US6403445B1 (en) * | 1999-04-06 | 2002-06-11 | Advanced Micro Devices, Inc. | Enhanced trench isolation structure |
US6406987B1 (en) * | 1998-09-08 | 2002-06-18 | Taiwan Semiconductor Manufacturing Company | Method for making borderless contacts to active device regions and overlaying shallow trench isolation regions |
US6420770B1 (en) * | 2000-02-23 | 2002-07-16 | Advanced Micro Devices, Inc. | STI (Shallow Trench Isolation) structures for minimizing leakage current through drain and source silicides |
US20030203580A1 (en) * | 2002-04-30 | 2003-10-30 | Chartered Semiconductor Manufacturing Ltd. | Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates |
US6723615B2 (en) * | 2002-01-31 | 2004-04-20 | Renesas Technology Corp. | Semiconductor device and method of fabricating the same |
US6727150B2 (en) * | 2002-07-26 | 2004-04-27 | Micron Technology, Inc. | Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR960002771B1 (en) * | 1992-12-31 | 1996-02-26 | 현대전자산업주식회사 | Manufacturing process of semiconductor integrated circuit isolation area |
-
2002
- 2002-12-24 KR KR1020020083439A patent/KR100888150B1/en not_active IP Right Cessation
-
2003
- 2003-12-23 US US10/745,028 patent/US7030454B2/en not_active Expired - Fee Related
-
2005
- 2005-01-28 US US11/047,337 patent/US20050136619A1/en not_active Abandoned
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5128743A (en) * | 1980-09-17 | 1992-07-07 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
US6064104A (en) * | 1996-01-31 | 2000-05-16 | Advanced Micro Devices, Inc. | Trench isolation structures with oxidized silicon regions and method for making the same |
US6350655B2 (en) * | 1997-08-01 | 2002-02-26 | Nippon Steel Corporation | Semiconductor device and a method of manufacturing the same |
US6274457B1 (en) * | 1997-08-28 | 2001-08-14 | Mitsubishi Denki Kabushiki Kaisha | Method for manufacturing an isolation trench having plural profile angles |
US6096612A (en) * | 1998-04-30 | 2000-08-01 | Texas Instruments Incorporated | Increased effective transistor width using double sidewall spacers |
US6406987B1 (en) * | 1998-09-08 | 2002-06-18 | Taiwan Semiconductor Manufacturing Company | Method for making borderless contacts to active device regions and overlaying shallow trench isolation regions |
US6232202B1 (en) * | 1998-11-06 | 2001-05-15 | United Microelectronics Corp. | Method for manufacturing shallow trench isolation structure including a dual trench |
US6204192B1 (en) * | 1999-03-29 | 2001-03-20 | Lsi Logic Corporation | Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures |
US6403445B1 (en) * | 1999-04-06 | 2002-06-11 | Advanced Micro Devices, Inc. | Enhanced trench isolation structure |
US6350661B2 (en) * | 1999-07-12 | 2002-02-26 | Chartered Semiconductor Manufacturing Ltd. | Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts |
US6165871A (en) * | 1999-07-16 | 2000-12-26 | Chartered Semiconductor Manufacturing Ltd. | Method of making low-leakage architecture for sub-0.18 μm salicided CMOS device |
US6207532B1 (en) * | 1999-09-30 | 2001-03-27 | Taiwan Semiconductor Manufacturing Company | STI process for improving isolation for deep sub-micron application |
US6420770B1 (en) * | 2000-02-23 | 2002-07-16 | Advanced Micro Devices, Inc. | STI (Shallow Trench Isolation) structures for minimizing leakage current through drain and source silicides |
US6323104B1 (en) * | 2000-03-01 | 2001-11-27 | Micron Technology, Inc. | Method of forming an integrated circuitry isolation trench, method of forming integrated circuitry, and integrated circuitry |
US6723615B2 (en) * | 2002-01-31 | 2004-04-20 | Renesas Technology Corp. | Semiconductor device and method of fabricating the same |
US20030203580A1 (en) * | 2002-04-30 | 2003-10-30 | Chartered Semiconductor Manufacturing Ltd. | Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates |
US6727150B2 (en) * | 2002-07-26 | 2004-04-27 | Micron Technology, Inc. | Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070145490A1 (en) * | 2005-12-26 | 2007-06-28 | Jong Bok Lee | Semiconductor device and method for manufacturing the same |
US7655524B2 (en) * | 2005-12-26 | 2010-02-02 | Dongbu Hitek Co., Ltd. | Method for manufacturing isolation layer having barrier layer formed thereon |
Also Published As
Publication number | Publication date |
---|---|
KR20040056856A (en) | 2004-07-01 |
US7030454B2 (en) | 2006-04-18 |
KR100888150B1 (en) | 2009-03-16 |
US20040135199A1 (en) | 2004-07-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100538810B1 (en) | Method of isolation in semiconductor device | |
US20050136619A1 (en) | Semiconductor devices and methods of forming a trench in a semiconductor device | |
US6828213B2 (en) | Method to improve STI nano gap fill and moat nitride pull back | |
US6391739B1 (en) | Process of eliminating a shallow trench isolation divot | |
US7323394B2 (en) | Method of producing element separation structure | |
US6344415B1 (en) | Method for forming a shallow trench isolation structure | |
US7339251B2 (en) | Shallow trench isolation structure and formation method thereof | |
US7199012B2 (en) | Method of forming a trench in a semiconductor device | |
KR100979230B1 (en) | The method for forming shall trench isolation in semiconductor device | |
US6613648B1 (en) | Shallow trench isolation using TEOS cap and polysilicon pullback | |
KR100829375B1 (en) | Formation method of trench in semiconductor device | |
KR100829368B1 (en) | Trench in semiconductor device and fabrication method of the trench | |
KR100826789B1 (en) | Trench of semiconductor device and formation method of the trench | |
KR100829366B1 (en) | Trench of semiconductor device and formation method of the trench | |
KR100515375B1 (en) | A method for forming a trench in semiconductor device | |
KR100567872B1 (en) | Method for forming isolation layer in a semiconductor manufacturing device | |
KR100539001B1 (en) | Method for fabricating shallow trench isolation of semiconductor device | |
KR100587084B1 (en) | method for fabricating semiconductor device | |
KR100826790B1 (en) | Method for fabricating trench of semiconductor device | |
KR20000051689A (en) | Shallow trench manufacturing method for isolating semiconductor devices | |
KR20000014372A (en) | Shallow trench manufacturing method for isolation | |
KR100561974B1 (en) | A Manufacturing Method of Semiconductor Element | |
KR20050119412A (en) | Shallow trench isolation layer preventable leakage current and method for forming the same | |
KR20020054664A (en) | A method for forming a field oxide of semiconductor device | |
KR20020054666A (en) | A method for forming a field oxide of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: DONGBUANAM SEMICONDUCTOR, INC., A KOREAN CORPORATI Free format text: MERGER;ASSIGNORS:ANAM SEMICONDUCTOR INC.;ANAM SEMICONDUCTOR INC.;REEL/FRAME:016593/0917 Effective date: 20041221 |
|
AS | Assignment |
Owner name: DONGBU ELECTRONICS CO., LTD.,KOREA, REPUBLIC OF Free format text: CHANGE OF NAME;ASSIGNOR:DONGANAM SEMICONDUCTOR INC.;REEL/FRAME:017749/0335 Effective date: 20060328 Owner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: CHANGE OF NAME;ASSIGNOR:DONGANAM SEMICONDUCTOR INC.;REEL/FRAME:017749/0335 Effective date: 20060328 |
|
AS | Assignment |
Owner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017749 FRAME 0335;ASSIGNOR:DONGBUANAM SEMICONDUCTOR INC.;REEL/FRAME:017821/0670 Effective date: 20060328 Owner name: DONGBU ELECTRONICS CO., LTD.,KOREA, REPUBLIC OF Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017749 FRAME 0335. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR SHOULD BE "DONGBUANAM SEMICONDUCTOR INC.";ASSIGNOR:DONGBUANAM SEMICONDUCTOR INC.;REEL/FRAME:017821/0670 Effective date: 20060328 Owner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017749 FRAME 0335. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR SHOULD BE "DONGBUANAM SEMICONDUCTOR INC.";ASSIGNOR:DONGBUANAM SEMICONDUCTOR INC.;REEL/FRAME:017821/0670 Effective date: 20060328 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |