US20050136674A1 - Method for forming contact hole - Google Patents

Method for forming contact hole Download PDF

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US20050136674A1
US20050136674A1 US10/740,680 US74068003A US2005136674A1 US 20050136674 A1 US20050136674 A1 US 20050136674A1 US 74068003 A US74068003 A US 74068003A US 2005136674 A1 US2005136674 A1 US 2005136674A1
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layer
forming
poly
contact hole
reflective layer
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US7005374B2 (en
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Tse-Yao Huang
Yi-Nan Chen
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Nanya Technology Corp
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Nanya Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present invention relates to a semiconductor integrated circuit device process, more specifically, to a method for forming contact holes in the semiconductor integrated circuit device, which can avoid the problem of the failure of the alignment marks due to light reflection.
  • contact holes In the process for semiconductor integrated circuits such as DRAM, formation of contact holes plays an important role in the process techniques.
  • the contact holes include bit line contact holes, substrate contact holes, gate contact holes and the like.
  • FIG. 1 a is a schematic diagram showing a prior art DRAM structure to where contact holes are to be formed.
  • CB bit line contact hole
  • CS substrate contact hole
  • CG gate contact hole
  • reference number 10 indicates a silicon substrate
  • 11 indicates a barrier nitride layer
  • 12 indicates a bit line region
  • 13 indicates a dielectric layer filled between the bit line regions 12 and 14 indicates an oxide layer on the dielectric layer 13 and the bit line regions 12 .
  • the material of the dielectric layer 13 comprises BPSC; and the material of the oxide layer 14 comprises TEOS, for example.
  • a thin conductive layer which can be a poly-silicon layer 15 , is formed.
  • a photoresist layer 16 is formed to define the position where the bit line contact hole CB is to be formed.
  • the barrier nitride layer 11 is formed on the substrate 10 .
  • the dielectric layer 13 , oxide layer 14 and thin poly-silicon layer 15 are formed.
  • the position where the substrate contact hole Cs is to be formed is defined by using the photoresist layer 16 .
  • a conductive layer such as a poly-silicon layer 17 , and a gate metal layer 18 , of which the material can be WSi, are formed.
  • a cap nitride layer 19 is formed on the gate metal layer 18 .
  • the oxide layer 14 and the thin poly-silicon layer 15 are formed on the cap nitride layer 19 .
  • the position where the gate contact hole CG is to be formed is defined by using the photoresist layer 16 .
  • FIG. 1 b After the structure of FIG. 1 a is etched and the photoresist layer 16 is removed, the resultant structure is shown in FIG. 1 b.
  • the cap nitride layer 19 acts as an etch stop layer. Accordingly, the depth of the etched contact hole fails to reach the gate metal layer 18 .
  • a poly hard mask 21 is formed on the partial structure where the gate contact hole CG is to be formed, as shown in FIG. 2 . Then, the predetermined portion of the cap nitride layer 19 is removed by etching, so that the gate contact hole CG can reach the gate metal layer 18 . Then, the poly hard mask 21 is removed, as shown in FIG. 3 .
  • the material of the poly hard mask has a large reflection to yellow light such that strong light reflection occurs in the processes of developing and imaging. Accordingly, aligning marks would fail, making it difficult to align the marks. Therefore, additional aligning marks are required for the steps of developing, etching and so on. As shown in the drawing, due to misalignment, the etching is difficult to be perfectly performed such that some residual is left in the contact hole. Accordingly, the profile of the contact hole is influenced.
  • An objective of the present invention is to provide an improved method for forming a contact hole, which can avoid the problem of alignment mark failure due to light reflection.
  • the improved method for forming a contact hole comprises steps of providing a substrate; forming a plurality of operation layers as required on the substrate; forming a conductive layer on the uppermost layer of the operation layers; forming an anti-reflective layer on the conductive layer; forming a photoresist layer on the anti-reflective layer to define a position where to a contact hole is be formed; removing a portion of the anti-reflective layer not covered by the photoresist layer; removing the photoresist layer; removing a portion of the conductive layer not cover by the residual anti-reflective layer; and forming a contact hole by etching with the residual conductive layer as a mask.
  • the step of removing the portion of the conductive layer includes sub-steps of partially removing the portion of the conductive layer not covered by the anti-reflective layer to form a recess; removing the anti-reflective layer; and opening the recess of the conductive layer to form an opening.
  • the material of the anti-reflective layer comprises nitride.
  • the material of the anti-reflective layer comprises SiON.
  • FIGS. 1 a and 1 b are schematic sectional diagrams illustrating steps of a conventional method for forming a contact hole
  • FIG. 2 is a schematic sectional diagram illustrating a step of using a poly hard mask in accordance with the conventional method for forming a gate contact hole
  • FIG. 3 is a schematic section diagram illustrating the gate contact hole formed from the structure of FIG. 2 ;
  • FIGS. 4 a to 4 h are schematic sectional diagrams illustrating steps of a method for forming contact holes in accordance with the present invention.
  • FIG. 4 a shows a step of a method for forming contact holes in accordance with an embodiment of the present invention.
  • a conductive layer which is preferably a poly-silicon layer 25
  • the oxide (dielectric) layer 14 is formed on the oxide (dielectric) layer 14 .
  • the difference between the present invention and the prior art is the thickness of the poly-silicon layer.
  • the thickness of the poly-silicon layer 15 is about hundreds of angstroms.
  • the thickness of the poly-silicon layer 25 is about 1200-1500 ⁇ .
  • an anti-reflective layer 30 which has a low reflectivity to yellow light, is formed on the poly-silicon layer 25 .
  • the etching selectivity ratio for the anti-reflective layer 30 to the poly-silicon layer 25 should be sufficiently large.
  • the material of the anti-reflective comprises nitride, such as SiON.
  • the selectivity ratio for SiON to poly-silicon can reach 100:1.
  • a photoresist layer 36 is formed on the anti-reflective layer 30 to define the positions of the bit line contact hole CB, substrate contact hole CS and gate contact hole CC; as shown in FIG. 4 c.
  • the portion of the anti-reflective layer 30 not covered by the photoresist 36 is then removed, as shown in FIG. 4 d.
  • the selectivity ratio for SiON to poly-silicon is about 100:1. Accordingly, the remaining anti-reflective layer 30 can act as a mask for defining positions to be etched in the subsequent step of etching the poly-silicon layer 25 .
  • the SiON (anti-reflective) layer 30 is removed by dilute HF etching.
  • dilute HF has a large etching selectivity for SiON in respect to poly-silicon. Therefore, the SiON can be easily removed.
  • the anti-reflective layer 30 is partially removed, as shown in FIG. 4 f, the recesses of the poly-silicon are opened to form openings, as shown in FIG. 4 g.
  • the remaining poly-silicon layer 25 is used as a mask for the subsequent etching step for forming contact holes.
  • the openings in the poly-silicon layer 25 are opened by two steps. That is, the recesses are formed in the poly-silicon layer 25 by partially etching, then the recesses in the poly-silicon layer 25 are opened as openings after the anti-reflective layer 30 is removed.
  • the portions of the dielectric layer 13 , oxide layer 14 , cap nitride layer 19 and the like, corresponding to the positions defined by the openings of the poly-silicon layer 25 are removed by etching to form a bit line contact hole CB, a substrate contact hole CS, and a gate contact hole CG and portions of the poly-silicon layer 25 are also removed to thin its thickness, as shown in FIG. 4 h.
  • bit line contact hole CB, substrate contact hole CS and gate contact hole CG can be formed at the same time.

Abstract

Disclosed is an improved method for forming contact holes. The method of the present invention comprises the steps of providing a substrate; forming a plurality of operation layers on the substrate as necessary; forming a poly-silicon layer on the uppermost one of the operation layers; forming an anti-reflective layer on the poly-silicon layer; forming a photoresist layer on the anti-reflective layer to define the positions where the contact holes are to be formed; removing portions of the anti-reflective layer not covered with the photoresist layer; removing the photoresist layer; removing portions of the poly-silicon layer not covered with the anti-reflective layer; and using the residual poly-silicon layer as a mask to etch and form the contact holes. In the step of removing portions of the poly-silicon layer comprises partially removing portions of the poly-silicon not covered with the anti-reflective layer to form recesses, removing the anti-reflective layer, and opening the recesses of the poly-silicon to form openings

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor integrated circuit device process, more specifically, to a method for forming contact holes in the semiconductor integrated circuit device, which can avoid the problem of the failure of the alignment marks due to light reflection.
  • 2. Description of the Prior Art
  • In the process for semiconductor integrated circuits such as DRAM, formation of contact holes plays an important role in the process techniques. Take DRAM as an example, the contact holes include bit line contact holes, substrate contact holes, gate contact holes and the like.
  • FIG. 1 a is a schematic diagram showing a prior art DRAM structure to where contact holes are to be formed. In this drawing, positions where a bit line contact hole (CB), a substrate contact hole (CS), and a gate contact hole (CG) are to be respectively formed are shown. At the portion where the bit line contact hole CB is to be formed, reference number 10 indicates a silicon substrate, 11 indicates a barrier nitride layer, 12 indicates a bit line region, 13 indicates a dielectric layer filled between the bit line regions 12 and 14 indicates an oxide layer on the dielectric layer 13 and the bit line regions 12. The material of the dielectric layer 13 comprises BPSC; and the material of the oxide layer 14 comprises TEOS, for example. On the oxide layer 14, a thin conductive layer, which can be a poly-silicon layer 15, is formed. Finally, a photoresist layer 16 is formed to define the position where the bit line contact hole CB is to be formed. At the portion where the substrate contact hole CS is to be formed, the barrier nitride layer 11 is formed on the substrate 10. On the barrier nitride layer 11, the dielectric layer 13, oxide layer 14 and thin poly-silicon layer 15 are formed. Finally, the position where the substrate contact hole Cs is to be formed is defined by using the photoresist layer 16. At the portion where the gate contact hole CG is to be formed, on the substrate 10, a conductive layer such as a poly-silicon layer 17, and a gate metal layer 18, of which the material can be WSi, are formed. On the gate metal layer 18, a cap nitride layer 19 is formed. Then, the oxide layer 14 and the thin poly-silicon layer 15 are formed on the cap nitride layer 19. Finally, the position where the gate contact hole CG is to be formed is defined by using the photoresist layer 16.
  • After the structure of FIG. 1 a is etched and the photoresist layer 16 is removed, the resultant structure is shown in FIG. 1 b. As can be seen from this drawing, at the portion of the gate contact hole CC; the cap nitride layer 19 acts as an etch stop layer. Accordingly, the depth of the etched contact hole fails to reach the gate metal layer 18.
  • In order to remove the unnecessary portion of the cap nitride layer 19, a poly hard mask 21 is formed on the partial structure where the gate contact hole CG is to be formed, as shown in FIG. 2. Then, the predetermined portion of the cap nitride layer 19 is removed by etching, so that the gate contact hole CG can reach the gate metal layer 18. Then, the poly hard mask 21 is removed, as shown in FIG. 3.
  • However, the material of the poly hard mask has a large reflection to yellow light such that strong light reflection occurs in the processes of developing and imaging. Accordingly, aligning marks would fail, making it difficult to align the marks. Therefore, additional aligning marks are required for the steps of developing, etching and so on. As shown in the drawing, due to misalignment, the etching is difficult to be perfectly performed such that some residual is left in the contact hole. Accordingly, the profile of the contact hole is influenced.
  • Therefore, there is a need for a solution to overcome the problems stated above. The present invention satisfies such a need.
    • SUMMARY OF THE INVENTION
  • An objective of the present invention is to provide an improved method for forming a contact hole, which can avoid the problem of alignment mark failure due to light reflection.
  • According to an aspect of the present invention, the improved method for forming a contact hole comprises steps of providing a substrate; forming a plurality of operation layers as required on the substrate; forming a conductive layer on the uppermost layer of the operation layers; forming an anti-reflective layer on the conductive layer; forming a photoresist layer on the anti-reflective layer to define a position where to a contact hole is be formed; removing a portion of the anti-reflective layer not covered by the photoresist layer; removing the photoresist layer; removing a portion of the conductive layer not cover by the residual anti-reflective layer; and forming a contact hole by etching with the residual conductive layer as a mask.
  • According to another aspect of the present invention, in the improved method for forming a contact hole, the step of removing the portion of the conductive layer includes sub-steps of partially removing the portion of the conductive layer not covered by the anti-reflective layer to form a recess; removing the anti-reflective layer; and opening the recess of the conductive layer to form an opening.
  • According to a further aspect of the present invention, in the improved method for forming a contact hole, the material of the anti-reflective layer comprises nitride.
  • According to still another aspect of the present invention, in the improved method for forming a contact hole, the material of the anti-reflective layer comprises SiON.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The following drawings are only for illustrating the mutual relationships between the respective portions and are not drawn according to practical dimensions and ratios. In addition, the like reference numbers indicate the similar elements.
  • FIGS. 1 a and 1 b are schematic sectional diagrams illustrating steps of a conventional method for forming a contact hole;
  • FIG. 2 is a schematic sectional diagram illustrating a step of using a poly hard mask in accordance with the conventional method for forming a gate contact hole;
  • FIG. 3 is a schematic section diagram illustrating the gate contact hole formed from the structure of FIG. 2; and
  • FIGS. 4 a to 4 h are schematic sectional diagrams illustrating steps of a method for forming contact holes in accordance with the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • An embodiment of the present invention will be described in detail with reference to the accompanying drawings.
  • FIG. 4 a shows a step of a method for forming contact holes in accordance with an embodiment of the present invention. In this drawing, the same reference numbers as those in FIG. 1 a indicate the similar parts, and therefore the relevant descriptions are omitted herein. As shown, in accordance with the present invention, a conductive layer, which is preferably a poly-silicon layer 25, is formed on the oxide (dielectric) layer 14. The difference between the present invention and the prior art is the thickness of the poly-silicon layer. In the prior art, the thickness of the poly-silicon layer 15 is about hundreds of angstroms. In this embodiment of the present invention, the thickness of the poly-silicon layer 25 is about 1200-1500 Å.
  • Then, as shown in FIG. 4 b, an anti-reflective layer 30, which has a low reflectivity to yellow light, is formed on the poly-silicon layer 25. The etching selectivity ratio for the anti-reflective layer 30 to the poly-silicon layer 25 should be sufficiently large. Preferably, the material of the anti-reflective comprises nitride, such as SiON. For dilute HF etching, the selectivity ratio for SiON to poly-silicon can reach 100:1.
  • Subsequently, a photoresist layer 36 is formed on the anti-reflective layer 30 to define the positions of the bit line contact hole CB, substrate contact hole CS and gate contact hole CC; as shown in FIG. 4 c.
  • The portion of the anti-reflective layer 30 not covered by the photoresist 36 is then removed, as shown in FIG. 4 d. As mentioned above, for dilute HF etching, the selectivity ratio for SiON to poly-silicon is about 100:1. Accordingly, the remaining anti-reflective layer 30 can act as a mask for defining positions to be etched in the subsequent step of etching the poly-silicon layer 25.
  • As shown in FIG. 4 e, partially removing the portion of the poly-silicon layer 25 not covered by the anti-reflective layer 30 by dry etching, for example, to form recesses corresponding to the respective contact hole positions in the poly-silicon layer 25. For example, the thickness of each recess is less than that of other portions of the poly-silicon layer 25 by about 800 Å. Then, the SiON (anti-reflective) layer 30 is removed by dilute HF etching. As stated above, dilute HF has a large etching selectivity for SiON in respect to poly-silicon. Therefore, the SiON can be easily removed. After the anti-reflective layer 30 is partially removed, as shown in FIG. 4 f, the recesses of the poly-silicon are opened to form openings, as shown in FIG. 4 g. The remaining poly-silicon layer 25 is used as a mask for the subsequent etching step for forming contact holes.
  • In the step shown in FIG. 4 e, if the openings in poly-silicon 25 are opened by only one operation, due to the characteristics of the etchant and the material of the poly-silicon, the profiles of the openings will be degraded. It is difficult to obtain perfect opening profile. Accordingly, in the present embodiment, the openings in the poly-silicon layer 25 are opened by two steps. That is, the recesses are formed in the poly-silicon layer 25 by partially etching, then the recesses in the poly-silicon layer 25 are opened as openings after the anti-reflective layer 30 is removed.
  • Finally, using the remaining poly-silicon layer 25 as the mask, the portions of the dielectric layer 13, oxide layer 14, cap nitride layer 19 and the like, corresponding to the positions defined by the openings of the poly-silicon layer 25, are removed by etching to form a bit line contact hole CB, a substrate contact hole CS, and a gate contact hole CG and portions of the poly-silicon layer 25 are also removed to thin its thickness, as shown in FIG. 4 h.
  • In accordance with the present invention, the bit line contact hole CB, substrate contact hole CS and gate contact hole CG can be formed at the same time. In addition, it is not necessary to use the poly hard mask to form the contact holes in two stages. The steps of applying and removing the poly hard mask are omitted.
  • While the embodiment of the present invention is illustrated and described, various modifications and alterations can be made by persons skilled in this art. The embodiment of the present invention is therefore described in an illustrative but not restrictive sense. It is intended that the present invention may not be limited to the particular forms as illustrated, and that all modifications and alterations which maintain the spirit and realm of the present invention are within the scope as defined in the appended claims.

Claims (11)

1. A method for forming a contact hole, said method comprising steps of:
providing a substrate;
forming a plurality of operation layers on said substrate as required;
forming a conductive layer on the uppermost one of said operation layers;
forming an anti-reflective layer on said conductive layer;
forming a photoresist layer on said anti-reflective layer to define a position where said contact hole is to be formed;
removing a portion of said anti-reflective layer not covered by said photoresist layer;
removing said photoresist layer;
partially removing a portion of said conductive layer not covered by said anti-reflective layer to form a recess;
removing said anti-reflective layer;
opening said recess of said conductive layer to form an opening; and
using the remaining conductive layer as a mask to form said contact hole by etching.
2. (canceled)
3. The method as claimed in claim 1, wherein said etching selectivity ratio for said anti-reflective layer in respect to said conductive layer is large.
4. The method as claimed in claim 1, wherein said anti-reflective layer comprises nitride.
5. The method as claimed in claim 4, wherein said anti-reflective layer comprises SiON.
6. The method as claimed in claim 1, wherein said conductive layer comprises poly-silicon.
7. A method for forming a contact hole, said method consisting essentially of:
providing a substrate;
forming a plurality of operation layers on said substrate as required;
forming a conductive layer on the uppermost one of said operation layers;
forming an anti-reflective layer on said conductive layer;
forming a photoresist layer on said anti-reflective layer to define a position where said contact hole is to be formed;
removing a portion of said anti-reflective layer not covered by said photoresist layer;
removing said photoresist layer;
partially removing a portion of said conductive layer not covered by said anti-reflective layer to form a recess;
removing said anti-reflective layer;
opening said recess of said conductive layer to form an opening; and
using the remaining conductive layer as a mask to form said contact hole by etching.
8. The method as claimed in claim 7, wherein said etching selectivity ratio for said anti-reflective layer in respect to said conductive layer is large.
9. The method as claimed in claim 7, wherein said anti-reflective layer comprises nitride.
10. The method as claimed in claim 9, wherein said anti-reflective layer comprises SiON.
11. The method as claimed in claim 7, wherein said conductive layer comprises poly-silicon.
US10/740,680 2003-12-22 2003-12-22 Method for forming contact hole Expired - Lifetime US7005374B2 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008123A (en) * 1997-11-04 1999-12-28 Lucent Technologies Inc. Method for using a hardmask to form an opening in a semiconductor substrate
US6027861A (en) * 1998-03-20 2000-02-22 Taiwan Semiconductor Manufacturing Company VLSIC patterning process
US6287951B1 (en) * 1998-12-07 2001-09-11 Motorola Inc. Process for forming a combination hardmask and antireflective layer
US20030129840A1 (en) * 2002-01-07 2003-07-10 Ajay Kumar Process for in-situ etching a hardmask stack

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008123A (en) * 1997-11-04 1999-12-28 Lucent Technologies Inc. Method for using a hardmask to form an opening in a semiconductor substrate
US6027861A (en) * 1998-03-20 2000-02-22 Taiwan Semiconductor Manufacturing Company VLSIC patterning process
US6287951B1 (en) * 1998-12-07 2001-09-11 Motorola Inc. Process for forming a combination hardmask and antireflective layer
US20030129840A1 (en) * 2002-01-07 2003-07-10 Ajay Kumar Process for in-situ etching a hardmask stack

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