US20050139932A1 - Transistors of semiconductor devices and methods of fabricating the same - Google Patents

Transistors of semiconductor devices and methods of fabricating the same Download PDF

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US20050139932A1
US20050139932A1 US11/027,518 US2751804A US2005139932A1 US 20050139932 A1 US20050139932 A1 US 20050139932A1 US 2751804 A US2751804 A US 2751804A US 2005139932 A1 US2005139932 A1 US 2005139932A1
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gate electrode
epitaxial layer
source
spacers
forming
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Yong Cho
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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DongbuAnam Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66606—Lateral single gate silicon transistors with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

  • the present disclosure relates generally to semiconductor devices and, more particularly, to transistors of semiconductor devices and methods of fabricating the same.
  • MOS metal-oxide-semiconductor
  • MOSFET MOS field-effect-transistor
  • the surface region through which the electric current flows is known as a channel.
  • the characteristics of a MOSFET are determined by a dopant concentration in the channel. More specifically, it is very important to precisely dope impurities into the channel region because device characteristics such as the threshold voltage of the transistor and the drain current are subject to the dopant concentration.
  • Retrograde channels are widely used for high performance microprocessors requiring a channel length less than 0.2 ⁇ m.
  • the retrograde channel is generally formed by heavy ion implantation using indium (In), arsenic (As), or antimony (Sb).
  • the retrograde channel is suitable for high performance MOSFET devices with high driving current characteristics because a low dopant concentration in its surface increases the surface mobility of an electric current.
  • the channel length is shortened, and a very thin channel is required.
  • conventional ion implantation technology cannot achieve a retrograde channel less than 50 nm in depth.
  • an epitaxial channel has been suggested.
  • the epitaxial channel has not achieved an improvement in the current on-off characteristics because it is difficult to control the loss and diffusion of the channel dopants due to an epitaxial layer formation process and a later thermal treatment process.
  • the most ideal channel doping method may embody a ⁇ -doped epitaxial channel.
  • both doped and undoped epitaxial layers cannot be made into a ⁇ -doped epitaxial channel less than 30 nm in depth because of later dopant diffusion.
  • a method for preventing diffusion of dopants in a ⁇ -doped layer has been suggested in Lee and Lee, Laser Thermal Annealed SSR Well Prior to Epi - Channel Growth (LASPE ) for 70 nm nFET , IEDM 2000.
  • the suggested method performs channel doping by using an ultra-low energy ion implantation and an instant laser annealing.
  • the instant laser annealing controls the diffusion and loss of dopants during a selective epitaxial growth.
  • the laser power for the laser annealing may cause partial melting of the silicon substrate surface, thereby deteriorating the surface roughness and causing crystal defects. Therefore, the laser annealing method is not applicable to practical semiconductor device manufacturing processes.
  • FIG. 1 is a cross-sectional view of a conventional transistor having a super steep retrograde (SSR) epitaxial channel.
  • SSR super steep retrograde
  • FIG. 1 is a cross-sectional view of a conventional transistor having an SSR epitaxial channel.
  • FIGS. 2 a through 2 e are cross-sectional views illustrating an example process of fabricating a transistor of a semiconductor device having an SSR epitaxial channel and reverse spacers performed in accordance with the teachings of the present invention.
  • FIGS. 2 a through 2 e are cross-sectional views illustrating an example process of fabricating a transistor of a semiconductor device having an SSR epitaxial channel and reverse spacers.
  • an inversion epitaxial layer 11 is formed over a silicon substrate 10 .
  • the inversion epitaxial layer 11 is used as an SSR epitaxial channel.
  • a hard mask 12 is formed on the inversion epitaxial layer 11 .
  • the hard mask 12 covers an area for reverse spacers to be formed by a later unit process.
  • a silicon epitaxial layer 14 is formed over the inversion epitaxial layer 11 , but not on the area covered by the hard mask.
  • the hard mask is then removed to form a trench through the silicon epitaxial layer 14 .
  • the trench is filled with an insulating layer.
  • the insulating layer is then dry-etched to form reverse spacers 13 on the sidewalls of the trench.
  • the width of the trench is smaller than the width of a gate electrode to be formed by a later unit process.
  • the insulating layer is preferably a single layer of tetra ethyl ortho silicate (TEOS) or a multi-layer of TEOS-SiN-TEOS.
  • an oxide layer and a polysilicon layer are sequentially deposited over the structure of FIG. 2 c . Some portion(s) of the oxide layer and the polysilicon layer are removed by using a dry etching process to complete a gate oxide 15 and a gate electrode 16 .
  • the gate electrode 16 is positioned above the inversion epitaxial layer between the reverse spacers. In the illustrated example process, the width of the gate electrode 16 is smaller than the width of the trench, but larger than the space between the reverse spacers 13 .
  • the length of a channel under the gate electrode 16 is defined as the length of the SSR epitaxial channel 11 between the reverse spacers 13 .
  • the illustrated example process can considerably reduce the length of the channel compared to a conventional process which forms a channel having the same length as the gate electrode. Therefore, the illustrated example process is applicable to a fabrication process for a less than 90 nm transistor.
  • pocket-well regions (not shown) and lightly doped drain (LDD) regions 17 are formed in the silicon substrate 10 by performing a first ion implantation process.
  • conventional technology must implant low energy ions in order to form a shallow junction to prevent a leakage current of the junction area.
  • the illustrated example process can form a shallow junction even when high energy ions are implanted because the silicon epitaxial layer 14 and the reverse spacers 13 on the inversion epitaxial layer 11 function as a buffer layer during the first ion implantation.
  • an insulating layer is deposited over the structure of FIG. 2 d .
  • An etching process is performed to form gate spacers 18 on the sidewalls of the gate electrode 16 .
  • a second ion implantation process is then performed using the gate electrode 16 and the gate spacers 18 as a mask to form deep source and drain regions 19 in the silicon substrate 10 .
  • the illustrated example process may form elevated source and drain regions because the second ion implantation process may implant ions into the silicon epitaxial layer 14 on the source and drain regions 19 .
  • the described example process achieves the shallow junction necessary for a nanometer scale transistor design, thereby obviating the problem of parasitic capacitance due to the formation of the shallow junction.
  • a silicide layer 20 is respectively formed on the gate electrode 16 and on the source drain regions 19 by using a known unit process.
  • MOS transistor comprising an inversion epitaxial layer as an SSR epitaxial channel and elevated source and drain regions is completed.
  • a trench is placed over the inversion epitaxial layer and reverse spacers are positioned on the sidewalls of the trench.
  • gate spacers are placed on the sidewalls of the gate electrode.
  • Pocket-well regions are formed under opposite sides of the gate electrode in the silicon substrate, and LDD regions are positioned adjacent the upper part of the pocket-well regions and the inversion epitaxial layer over the pocket-well regions.
  • Source and drain regions (which have a larger thickness than the LDD regions), are positioned adjacent the LDD regions in the silicon substrate.
  • a silicide layer is positioned on the gate electrode and through the silicon epitaxial layer on the source and drain regions, respectively.
  • the disclosed methods of fabricating a transistor of a semiconductor device simplify the manufacturing process and reduce production costs because they use an existing gate fabrication process.
  • the disclosed methods simplify the manufacturing process in comparison with a conventional selective epitaxial growth process requiring an additional ion implantation process.

Abstract

Transistors and methods of fabricating transistors are disclosed. A disclosed method comprises forming an inversion epitaxial layer on a silicon substrate; forming a hard mask on the inversion epitaxial layer; depositing a silicon epitaxial layer over the inversion epitaxial layer; forming a trench through the silicon epitaxial layer by removing the hard mask; forming reverse spacers on the sidewalls of the trench by filling the trench with an insulating layer and etching the insulating layer; forming a gate electrode over the reverse spacers; forming pocket-well regions and LDD regions in the silicon substrate by performing ion implantations; forming spacers on the sidewalls of the gate electrode; forming source and drain regions in the silicon substrate by performing an ion implantation; and forming a silicide layer on the gate electrode and the source and drain regions.

Description

    FIELD OF THE DISCLOSURE
  • The present disclosure relates generally to semiconductor devices and, more particularly, to transistors of semiconductor devices and methods of fabricating the same.
    • BACKGROUND
  • In a metal-oxide-semiconductor (MOS) transistor such as a MOS field-effect-transistor (MOSFET), electric current flows through a surface region under a gate electrode and a gate oxide when an electric field is applied to the source and drain junction regions while a gate charge is applied. The surface region through which the electric current flows is known as a channel. The characteristics of a MOSFET are determined by a dopant concentration in the channel. More specifically, it is very important to precisely dope impurities into the channel region because device characteristics such as the threshold voltage of the transistor and the drain current are subject to the dopant concentration.
  • Conventional channel doping is achieved by performing well ion implantation, channel ion implantation, or threshold ion implantation. Channel structures formed by such ion implantation include a flat channel in which a dopant concentration is uniform through the whole region of the channel, a buried channel which is formed at a predetermined distance from the top surface of a semiconductor substrate, and a retrograde channel which has a vertically increasing doping profile from the top surface of the channel. Retrograde channels are widely used for high performance microprocessors requiring a channel length less than 0.2 μm. In such a context, the retrograde channel is generally formed by heavy ion implantation using indium (In), arsenic (As), or antimony (Sb). The retrograde channel is suitable for high performance MOSFET devices with high driving current characteristics because a low dopant concentration in its surface increases the surface mobility of an electric current.
  • As the degree of integration of a semiconductor device increase, the channel length is shortened, and a very thin channel is required. However, conventional ion implantation technology cannot achieve a retrograde channel less than 50 nm in depth. To solve such a problem, an epitaxial channel has been suggested. However, the epitaxial channel has not achieved an improvement in the current on-off characteristics because it is difficult to control the loss and diffusion of the channel dopants due to an epitaxial layer formation process and a later thermal treatment process.
  • The most ideal channel doping method may embody a δ-doped epitaxial channel. However, according to the reported findings, both doped and undoped epitaxial layers cannot be made into a δ-doped epitaxial channel less than 30 nm in depth because of later dopant diffusion.
  • To solve such a problem, a method for preventing diffusion of dopants in a δ-doped layer has been suggested in Lee and Lee, Laser Thermal Annealed SSR Well Prior to Epi-Channel Growth (LASPE) for 70 nm nFET, IEDM 2000. The suggested method performs channel doping by using an ultra-low energy ion implantation and an instant laser annealing. According to the suggested method, the instant laser annealing controls the diffusion and loss of dopants during a selective epitaxial growth.
  • However, the laser power for the laser annealing may cause partial melting of the silicon substrate surface, thereby deteriorating the surface roughness and causing crystal defects. Therefore, the laser annealing method is not applicable to practical semiconductor device manufacturing processes.
  • FIG. 1 is a cross-sectional view of a conventional transistor having a super steep retrograde (SSR) epitaxial channel. Although conventional transistor fabrication technology has reduced the depth of the channel by forming a retrograde channel 17 as shown in FIG. 1, it has failed to substantially reduce the length of the channel.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view of a conventional transistor having an SSR epitaxial channel.
  • FIGS. 2 a through 2 e are cross-sectional views illustrating an example process of fabricating a transistor of a semiconductor device having an SSR epitaxial channel and reverse spacers performed in accordance with the teachings of the present invention.
    • DETAILED DESCRIPTION
  • FIGS. 2 a through 2 e are cross-sectional views illustrating an example process of fabricating a transistor of a semiconductor device having an SSR epitaxial channel and reverse spacers. Referring to FIG. 2 a, an inversion epitaxial layer 11 is formed over a silicon substrate 10. The inversion epitaxial layer 11 is used as an SSR epitaxial channel.
  • Referring to FIG. 2 b, a hard mask 12 is formed on the inversion epitaxial layer 11. The hard mask 12 covers an area for reverse spacers to be formed by a later unit process.
  • Referring to FIG. 2 c, a silicon epitaxial layer 14 is formed over the inversion epitaxial layer 11, but not on the area covered by the hard mask. The hard mask is then removed to form a trench through the silicon epitaxial layer 14. The trench is filled with an insulating layer. The insulating layer is then dry-etched to form reverse spacers 13 on the sidewalls of the trench. In the illustrated example process, the width of the trench is smaller than the width of a gate electrode to be formed by a later unit process. The insulating layer is preferably a single layer of tetra ethyl ortho silicate (TEOS) or a multi-layer of TEOS-SiN-TEOS.
  • Referring to FIG. 2 d, an oxide layer and a polysilicon layer are sequentially deposited over the structure of FIG. 2 c. Some portion(s) of the oxide layer and the polysilicon layer are removed by using a dry etching process to complete a gate oxide 15 and a gate electrode 16. The gate electrode 16 is positioned above the inversion epitaxial layer between the reverse spacers. In the illustrated example process, the width of the gate electrode 16 is smaller than the width of the trench, but larger than the space between the reverse spacers 13. The length of a channel under the gate electrode 16 is defined as the length of the SSR epitaxial channel 11 between the reverse spacers 13. By forming the reverse spacers 13 on the area for the gate electrode 16, the illustrated example process can considerably reduce the length of the channel compared to a conventional process which forms a channel having the same length as the gate electrode. Therefore, the illustrated example process is applicable to a fabrication process for a less than 90 nm transistor.
  • Next, pocket-well regions (not shown) and lightly doped drain (LDD) regions 17 are formed in the silicon substrate 10 by performing a first ion implantation process. Generally, conventional technology must implant low energy ions in order to form a shallow junction to prevent a leakage current of the junction area. However, the illustrated example process can form a shallow junction even when high energy ions are implanted because the silicon epitaxial layer 14 and the reverse spacers 13 on the inversion epitaxial layer 11 function as a buffer layer during the first ion implantation.
  • Referring to FIG. 2 e, an insulating layer is deposited over the structure of FIG. 2 d. An etching process is performed to form gate spacers 18 on the sidewalls of the gate electrode 16. A second ion implantation process is then performed using the gate electrode 16 and the gate spacers 18 as a mask to form deep source and drain regions 19 in the silicon substrate 10. Particularly, the illustrated example process may form elevated source and drain regions because the second ion implantation process may implant ions into the silicon epitaxial layer 14 on the source and drain regions 19. Moreover, because the silicon epitaxial layer 14 functions as a buffer layer during the second ion implantation process, the described example process achieves the shallow junction necessary for a nanometer scale transistor design, thereby obviating the problem of parasitic capacitance due to the formation of the shallow junction. Subsequently, a silicide layer 20 is respectively formed on the gate electrode 16 and on the source drain regions 19 by using a known unit process.
  • Consequently, a MOS transistor comprising an inversion epitaxial layer as an SSR epitaxial channel and elevated source and drain regions is completed. In detail, as shown in FIG. 2 e, after an inversion epitaxial layer is formed on a semiconductor substrate, a trench is placed over the inversion epitaxial layer and reverse spacers are positioned on the sidewalls of the trench. After a gate electrode is positioned above the inversion epitaxial layer between the reverse spacers, gate spacers are placed on the sidewalls of the gate electrode. Pocket-well regions are formed under opposite sides of the gate electrode in the silicon substrate, and LDD regions are positioned adjacent the upper part of the pocket-well regions and the inversion epitaxial layer over the pocket-well regions. Source and drain regions, (which have a larger thickness than the LDD regions), are positioned adjacent the LDD regions in the silicon substrate. A silicide layer is positioned on the gate electrode and through the silicon epitaxial layer on the source and drain regions, respectively.
  • From the foregoing, persons of ordinary skill in the art will appreciate that the disclosed methods of fabricating a transistor of a semiconductor device simplify the manufacturing process and reduce production costs because they use an existing gate fabrication process. In other words, by depositing a silicon epitaxial layer before source and drain regions are formed in a silicon substrate and performing ion implantation processes, the disclosed methods simplify the manufacturing process in comparison with a conventional selective epitaxial growth process requiring an additional ion implantation process.
  • From the foregoing, persons of ordinary skill in the art will further appreciate that, by forming an SSR epitaxial channel, a silicon epitaxial layer, and reverse spacers, the disclosed methods of fabricating a transistor of a semiconductor device reduce parasitic capacitance and a junction leakage current of a nanometer scale MOS transistors.
  • It is noted that this patent claims priority from Korean Patent Application Serial Number 10-2003-0102038, which was filed on Dec. 31, 2003, and is hereby incorporated by reference in its entirety.
  • Although certain example methods, apparatus and articles of manufacture have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus and articles of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.

Claims (10)

1. A transistor comprising:
an inversion epitaxial layer on a silicon substrate;
a trench over the inversion epitaxial layer;
reverse spacers on sidewalls of the trench;
a gate electrode above the inversion epitaxial layer between the reverse spacers;
spacers on the sidewalls of the gate electrode;
pocket-well regions under opposite sides of the gate electrode;
LDD regions positioned adjacent respective ones of the pocket-well regions;
source and drain regions positioned adjacent the LDD regions, the source and drain regions having a larger thickness than the LDD regions; and
a silicide layer positioned on the gate electrode and the source and drain regions.
2. A transistor as defined by claim 1, wherein the inversion epitaxial layer is used as an SSR epitaxial channel.
3. A transistor as defined by claim 1, wherein a gate channel is located under the gate electrode, the gate channel having a length defined by a length of the inversion epitaxial layer exposed between the reverse spacers.
4. A transistor as defined by claim 1, wherein the gate electrode has a width smaller than the trench and larger than a space between the reverse spacers.
5. A transistor as defined by claim 1, wherein the source and drain regions are elevated source and drain regions.
6. A method of fabricating a transistor comprising:
forming an inversion epitaxial layer on a silicon substrate;
forming a hard mask on the inversion epitaxial layer;
forming a silicon epitaxial layer over the inversion epitaxial layer;
removing the hard mask to form a trench through the silicon epitaxial layer;
filling the trench with an insulating layer;
etching the insulating layer to form reverse spacers on sidewalls of the trench;
forming a gate electrode over the reverse spacers, the gate electrode being positioned above the inversion epitaxial layer between the reverse spacers;
performing ion implantation using the gate electrode as a mask to form pocket-well regions and LDD regions;
forming spacers on sidewalls of the gate electrode;
performing ion implantation using the gate electrode and the spacers as a mask to form source/drain regions; and
forming a silicide layer on the gate electrode and the source and drain regions.
7. A method as defined by claim 6, wherein the reverse spacers are formed by a dry etching process.
8. A method as defined by claim 6, wherein the reverse spacers are formed of a single layer of TEOS or a multi-layer of TEOS-SiN-TEOS.
9. A method as defined by claim 6, wherein the source and drain regions are elevated source and drain regions.
10. A method as defined by claim 6, wherein the silicide layer on the source and drain regions is formed through the silicon epitaxial layer on the source and drain regions
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060138569A1 (en) * 2004-12-29 2006-06-29 Dongbuanam Semiconductor Inc. Semiconductor device and manufacturing method thereof
CN100356528C (en) * 2005-08-31 2007-12-19 北京大学 Method for making MOS transistor with source-drain on insulating layer
CN100356527C (en) * 2005-08-31 2007-12-19 北京大学 Method for making MOS transistor with source-drain on insulating layer
US20180040735A1 (en) * 2014-09-05 2018-02-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and fabricating method thereof

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100647457B1 (en) * 2005-12-09 2006-11-23 한국전자통신연구원 A semiconductor device and a method for manufacturing the same
JP2007184420A (en) * 2006-01-06 2007-07-19 Nec Electronics Corp Manufacturing method of semiconductor device
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8377783B2 (en) 2010-09-30 2013-02-19 Suvolta, Inc. Method for reducing punch-through in a transistor device
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
WO2013022753A2 (en) 2011-08-05 2013-02-14 Suvolta, Inc. Semiconductor devices having fin structures and fabrication methods thereof
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
WO2014071049A2 (en) 2012-10-31 2014-05-08 Suvolta, Inc. Dram-type device with low variation transistor peripheral circuits, and related methods
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US8994415B1 (en) 2013-03-01 2015-03-31 Suvolta, Inc. Multiple VDD clock buffer
US8988153B1 (en) 2013-03-09 2015-03-24 Suvolta, Inc. Ring oscillator with NMOS or PMOS variation insensitivity
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9449967B1 (en) 2013-03-15 2016-09-20 Fujitsu Semiconductor Limited Transistor array structure
US9112495B1 (en) 2013-03-15 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US8976575B1 (en) 2013-08-29 2015-03-10 Suvolta, Inc. SRAM performance monitor
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
CN113410307B (en) * 2021-04-16 2022-10-04 深圳真茂佳半导体有限公司 Field effect transistor structure, manufacturing method thereof and chip device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5736435A (en) * 1995-07-03 1998-04-07 Motorola, Inc. Process for fabricating a fully self-aligned soi mosfet
US5879998A (en) * 1997-07-09 1999-03-09 Advanced Micro Devices, Inc. Adaptively controlled, self-aligned, short channel device and method for manufacturing same
US6528847B2 (en) * 1998-06-29 2003-03-04 Advanced Micro Devices, Inc. Metal oxide semiconductor device having contoured channel region and elevated source and drain regions
US6753230B2 (en) * 2002-05-18 2004-06-22 Hynix Semiconductor Inc. Method for fabricating semiconductor device with ultra-shallow super-steep-retrograde epi-channel by decaborane doping

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5231038A (en) * 1989-04-04 1993-07-27 Mitsubishi Denki Kabushiki Kaisha Method of producing field effect transistor
US5166084A (en) * 1991-09-03 1992-11-24 Motorola, Inc. Process for fabricating a silicon on insulator field effect transistor
JP2856603B2 (en) * 1992-07-09 1999-02-10 シャープ株式会社 Method for manufacturing semiconductor device
JP3963023B2 (en) * 1996-04-26 2007-08-22 ソニー株式会社 Manufacturing method of semiconductor integrated device
JPH09321287A (en) * 1996-05-28 1997-12-12 Sony Corp Fabrication of semiconductor device
US6127232A (en) * 1997-12-30 2000-10-03 Texas Instruments Incorporated Disposable gate/replacement gate MOSFETS for sub-0.1 micron gate length and ultra-shallow junctions
JP2000156502A (en) * 1998-09-21 2000-06-06 Texas Instr Inc <Ti> Integrated circuit and method
JP2000106431A (en) * 1998-09-28 2000-04-11 Sanyo Electric Co Ltd Manufacture of semiconductor device
JP2002124665A (en) * 2000-10-12 2002-04-26 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
TW487976B (en) * 2001-06-05 2002-05-21 United Microelectronics Corp Method of fabricating a transistor
KR100414736B1 (en) * 2002-05-20 2004-01-13 주식회사 하이닉스반도체 A method for forming a transistor of a semiconductor device
US7138320B2 (en) * 2003-10-31 2006-11-21 Advanced Micro Devices, Inc. Advanced technique for forming a transistor having raised drain and source regions

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5736435A (en) * 1995-07-03 1998-04-07 Motorola, Inc. Process for fabricating a fully self-aligned soi mosfet
US5879998A (en) * 1997-07-09 1999-03-09 Advanced Micro Devices, Inc. Adaptively controlled, self-aligned, short channel device and method for manufacturing same
US6528847B2 (en) * 1998-06-29 2003-03-04 Advanced Micro Devices, Inc. Metal oxide semiconductor device having contoured channel region and elevated source and drain regions
US6753230B2 (en) * 2002-05-18 2004-06-22 Hynix Semiconductor Inc. Method for fabricating semiconductor device with ultra-shallow super-steep-retrograde epi-channel by decaborane doping

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060138569A1 (en) * 2004-12-29 2006-06-29 Dongbuanam Semiconductor Inc. Semiconductor device and manufacturing method thereof
US7211859B2 (en) * 2004-12-29 2007-05-01 Dongbu Electronics Co., Ltd. Semiconductor device and manufacturing method thereof
CN100356528C (en) * 2005-08-31 2007-12-19 北京大学 Method for making MOS transistor with source-drain on insulating layer
CN100356527C (en) * 2005-08-31 2007-12-19 北京大学 Method for making MOS transistor with source-drain on insulating layer
US20180040735A1 (en) * 2014-09-05 2018-02-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and fabricating method thereof
US10355135B2 (en) * 2014-09-05 2019-07-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and fabricating method thereof
US10818794B2 (en) 2014-09-05 2020-10-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and fabricating method thereof
US11342458B2 (en) 2014-09-05 2022-05-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and fabricating method thereof

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