US20050145893A1 - Methods for fabricating metal gate structures - Google Patents
Methods for fabricating metal gate structures Download PDFInfo
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- US20050145893A1 US20050145893A1 US10/748,345 US74834503A US2005145893A1 US 20050145893 A1 US20050145893 A1 US 20050145893A1 US 74834503 A US74834503 A US 74834503A US 2005145893 A1 US2005145893 A1 US 2005145893A1
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 86
- 239000002184 metal Substances 0.000 title claims abstract description 86
- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000005224 laser annealing Methods 0.000 claims abstract description 25
- 238000004377 microelectronic Methods 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 9
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 230000003213 activating effect Effects 0.000 claims description 4
- 150000001247 metal acetylides Chemical class 0.000 claims description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 229910000765 intermetallic Inorganic materials 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 3
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 2
- 229910045601 alloy Inorganic materials 0.000 claims 2
- 239000000956 alloy Substances 0.000 claims 2
- 229910052750 molybdenum Inorganic materials 0.000 claims 2
- 239000011733 molybdenum Substances 0.000 claims 2
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- 239000010955 niobium Substances 0.000 claims 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims 2
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 2
- 229910052721 tungsten Inorganic materials 0.000 claims 2
- 239000010937 tungsten Substances 0.000 claims 2
- 230000008569 process Effects 0.000 description 24
- 238000000137 annealing Methods 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 4
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- 230000002411 adverse Effects 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
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- 125000006850 spacer group Chemical group 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- -1 but not limited to Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
- H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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Abstract
Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the substrate.
Description
- The present invention relates to the field of microelectronic devices, and more particularly to methods of fabricating metal gate transistors.
- Microelectronic devices are often manufactured in and on silicon wafers and on other types other substrates. Such integrated circuits may include millions of transistors, such as metal oxide semiconductor (MOS) field effect transistors, as are well known in the art. In the fabrication of MOS transistors, it is common to form doped junctions by ion implantation. For example, using a gate structure as a mask, an ion implantation may form implanted regions, such as source/drain regions, as are known in the art. As a result of the ion implantation of a dopant species, damage may occur to a semiconductor substrate. In addition, many of the implanted species may not find substitutional sites i.e., they may remain unactivated within the crystal lattice of the substrate.
- In order to repair the damage and to activate the species into substitutional sites, it is common to use an annealing or heating step. For example, rapid thermal annealing (RTA) and diffusion furnace annealing are two conventional processes that may be utilized to anneal semiconductor devices.
- While conventional annealing techniques may commonly be used when a gate structure comprises a polysilicon material, problems may occur when the gate structure comprises a metal material. For example, one problem that may occur is that a metal gate material may undergo undesired phase changes when using a conventional annealing process. Such phase changes may change the work function of a metal gate structure, which may adversely affect the performance of a transistor.
- Another problem that may occur when using conventional annealing techniques with a metal gate structure is that the metal gate material may diffuse into an underlying gate dielectric layer, for example. Referring to
FIG. 2 a, agate structure 202 may comprise a gatedielectric layer 204, a metal layer 206 (such as a work function metal layer, as is known in the art), apolysilicon fill layer 208, and aspacer 210. - The
gate structure 202 may also comprise source/drain regions 212 that are implanted with a plurality of implantedspecies 216. Thepolysilicon fill layer 208 may also be implanted with the plurality of implantedspecies 216. Apre-anneal depth 220 of themetal layer 206 may be bounded by thetop 205 of the underlying gatedielectric layer 204 and thebottom 207 of thepolysilicon fill layer 208. Thegate structure 202 may be disposed on asubstrate 203, such as a silicon substrate. Aconventional annealing process 218, such as an RTA or diffusion process, may be performed on thegate structure 202. - After the
conventional annealing process 218 has been performed, the plurality of implantedspecies 216 may be activated within the crystal lattice of thegate structure 202, such as within the source/drain regions 212. Unfortunately, the conventional annealing process may be of such a time duration that themetal layer 206 may undergo a phase change, or may diffuse into the underlying gatedielectric layer 204 and/or may diffuse into the upper polysilicon fill layer 208 (seeFIG. 2 b). Consequently, apost-anneal depth 226 of themetal layer 206 may be larger than thepre-anneal depth 220 of themetal layer 206. This is due to the diffused polysiliconfill layer portion 222 of themetal layer 206 and the diffused gatedielectric layer portion 224 of themetal layer 206. - The phase change or the diffusion of the
metal layer 206 into the gatedielectric layer 204 and/or into the upperpolysilicon fill layer 208 may cause undesirable changes in the work function of themetal layer 206, as well as shorting etc. that may adversely affect the performance of the device. In addition, a source/drain junction depth 228 may be larger than is desired for a particular application, due to the amount of time required to anneal thegate structure 202 using theconventional annealing process 218. - For example, the ratio of the source/
drain junction depth 228 to a source/drain junction length 230 may be greater than about 1:2, which may be undesirable for a particular application since shallower source/drain regions 212 typically result in faster device performance, as is known in the art. Thus, there is a need for better methods of annealing implanted regions in the manufacture of integrated circuits that comprise metal gates. The methods and structures of the present invention provide such methods. - While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
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FIGS. 1 a-1 b represent structures according to an embodiment of the present invention. -
FIGS. 2 a-2 b represent structures from the Prior Art. - In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
- Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the substrate. Laser annealing the substrate enables the fabrication of metal gate transistors that do not substantially diffuse into adjacent layers, and also enables the fabrication of transistors comprising shallow source/drain regions.
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FIGS. 1 a-1 b illustrate an embodiment of a method and associated structures of laser annealing a substrate comprising metal gates to form shallow source/drain regions.FIG. 1 a illustrates a cross-section of a portion of asubstrate 100 that may preferably comprise asilicon substrate 100. Thesilicon substrate 100 may be comprised of materials such as, but not limited to, silicon, silicon-on-insulator, germanium, indium, antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, or combinations thereof. - The
silicon substrate 100 may comprise agate structure 102, that may comprise a gatedielectric layer 104. The gatedielectric layer 104 may preferably comprises a high-k gatedielectric layer 104. Some of the materials that may be used to make high-k gate dielectric layer may include: hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide. Although a few examples of materials that may be used to form thedielectric layer 104 are described here, that layer may be made from other materials that serve to reduce gate leakage. - A
metal layer 106 may be disposed on the gatedielectric layer 104. Themetal layer 106 may comprise any conductive material from which a metal gate electrode may be derived, such as hafnium, zirconium, titanium, tantalum, aluminum, platinum, palladium, nickel, cobalt, and ruthenium or combinations thereof, for example. Themetal layer 106 may be formed using PVD (“Physical vapor deposition”), CVD (“Chemical vapor deposition”), or ALD (“Atomic Layer deposition”) as are known in the art. A pre-laseranneal depth 120 of themetal layer 106 may be bounded by thetop 105 of the underlying gatedielectric layer 104 and by thebottom 107 of thepolysilicon fill layer 108. - The
metal layer 106 may preferably comprise a workfunction metal layer 106, that is, themetal layer 106 may comprise a suitable work function value for operation in a microelectronic device fabricated according to the methods of the present embodiment. For example, themetal layer 106 may preferably comprise a work function value that is compatible with either a PMOS gate electrode (which typically comprises a work function value of about 5.1±3 electron volts) or an NMOS gate electrode (which typically comprises a work function value of about 4.1±3 electron volts). - The
gate structure 102 may comprise apolysilicon fill layer 108, that may be disposed on themetal layer 106. Thepolysilicon fill layer 108 may act as a masking layer for theunderlying metal layer 106 during a subsequentlaser annealing process 118. Thelaser anneal process 118 may be performed to activate (i.e., incorporate an implanted species into the crystal lattice) a plurality of implantedspecies 116, that may comprise p and/or n type dopants, as are known in the art. The plurality of implantedspecies 116 may be located within the source/drain regions 112 and within thepolysilicon fill layer 108, and may have been implanted during a subsequent process step using conventional ion implant techniques as are well known in the art. Thegate structure 102 may further comprise aspacer 110, as is known in the art. - The
laser annealing process 118, may be performed on thesubstrate 100, and consequently may be performed on thegate structure 102. Thelaser annealing process 118 may comprise utilizing a laser beam, such as an excimer laser beam for example, but may comprise any type of laser beam and/or process that provides sufficient energy to activate the source/drain regions 112, as well as activating the polysilicon fill layer 108 (FIG. 1 b) while at the same time may preferably be of a shorter duration than more conventional annealing processes. In one embodiment, thelaser annealing process 118 may comprise a pulsed laser beam that is pulsed at a time interval of about 20 nanoseconds or less. The laser annealing process 1 18 allows for the rapid dissipation of heat into thesubstrate 100, i.e., the substrate acts as a thermal sink for the laser annealing process. - The duration and temperature of the
laser annealing process 118 may vary depending upon the particular application, but will be chosen so that for aparticular metal layer 106, themetal layer 106 will not substantially melt, or diffuse into either thegate dielectric layer 104 nor thepolysilicon fill layer 108, as may occur in prior art annealing processes (seeFIG. 2 b). In other words, in the current embodiment, a postlaser anneal depth 122 of themetal layer 106 may be bounded by the top 105 of the underlyinggate dielectric layer 104 and by thebottom 107 of thepolysilicon fill layer 108, and is substantially the same depth as thepre-laser anneal depth 120. - In addition, the
laser annealing process 118 of the current embodiment does not result in deleterious phase changes and/or inter-metallic formation in themetal layer 106. This is because thelaser annealing process 118 is optimized (for such parameters as time and temperature) to apply a sufficient amount of energy to the source/drain region 1 12 to activate the plurality of implantedspecies 116, but does not cause substantial diffusion, formation of inter-metallics or phase changes of the metal layer. - The laser annealing process 1 18 thus allows a more precise control over such anneal process parameters as time and temperature than more conventional annealing processes, such as an RTA or diffusion annealing process. Due to the greater degree of process control when using the
laser annealing process 118 of the present invention, themetal layer 106 may comprise metal materials that may not otherwise be available (due to temperature and/or diffusion limitations, for example) for use in the fabrication of metal gates, such as metal carbides, for example. - Another advantage of the present invention is that after the
laser annealing process 118 has been performed and the implantedspecies 116 of the source/drain regions 112 have been activated, a source/drain junction depth 128 may be formed that is significantly more shallow than a source/drain junction depth that may be formed when using more conventional anneal processes. For example, the ratio of the source/drain junction depth 128 to a source/drain junction length 130 may be less than about 1:2, which may be preferable for a particular application since shallower source/drain regions 112 typically result in faster device performance, as is known in the art. - Thus, the method of the present invention enables the formation of shallow source/drain regions with devices comprising metal gates, wherein the metal gates do not exhibit substantial diffusion, shorting or phase changes, for example.
- As described above, the present invention describes methods of forming a microelectronic structure comprising providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and laser annealing the substrate.
- Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims. In addition, it is appreciated that a microelectronic device, such as a transistor is well known in the art. Therefore, it is appreciated that the Figures provided herein illustrate only portions of an exemplary microelectronic device that pertains to the practice of the present invention. Thus the present invention is not limited to the structures described herein.
Claims (24)
1. A method of forming a microelectronic structure comprising:
providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and
laser annealing the substrate.
2. The method of claim 1 wherein providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer comprises providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer comprising a work function from about 3.9 electron volts to about 5.2 electron volts that is disposed on the gate dielectric layer.
3. The method of claim 1 wherein providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer further comprises wherein the metal layer does not substantially diffuse into the gate dielectric layer.
4. The method of claim 1 wherein providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer further comprises wherein the metal layer does not substantially diffuse into a polysilicon layer disposed on the metal layer.
5. The method of claim 1 wherein laser annealing the substrate. comprises exposing the substrate to a laser beam for a time sufficient to activate an implanted species.
6. The method of claim 1 wherein laser annealing the substrate comprises exposing the substrate to a laser beam pulsed at about 20 nanosecond intervals or less.
7. The method of claim 1 wherein laser annealing the substrate comprises activating an implanted species in the source/drain regions by laser annealing.
8. The method of claim 7 wherein activating an implanted species in the source/drain regions by laser annealing comprises activating an implanted species in the source/drain regions, wherein the ratio of the depth of the source/drain regions to the length of the source/drain regions is less than about 1:2 by laser annealing.
9. The method of claim 1 wherein providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer comprises providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a high k dielectric layer.
10. The method of claim 1 wherein providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer comprises providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer selected from the group consisting of tungsten, platinum, ruthenium, palladium, molybdenum and niobium, and their alloys, metal carbides, metal nitrides, metal carbides and conductive metal oxides.
11. A method of forming a microelectronic structure comprising;
providing a substrate comprising doped source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a high k dielectric layer, and wherein the metal layer comprises a work function approximately equal to a work function of n doped polysilicon; and
forming shallow source/drain regions by laser annealing the substrate.
12. The method of claim 11 wherein forming shallow source/drain regions comprises forming source/drain regions wherein the ratio of the depth of the source/drain regions to the length of the source/drain regions is less than about 1:2.
13. The method of claim 11 wherein providing a substrate comprising doped source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a high k dielectric layer, and wherein the metal layer comprises a work function approximately equal to a work function of n doped polysilicon comprises providing a substrate comprising doped source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a high k dielectric layer, and wherein the metal layer comprises a work function from about 3.9 to about 4.2 electron volts.
14. The method of claim 11 wherein providing a substrate comprising doped source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a high k dielectric layer, and wherein the metal layer comprises a work function approximately equal to a work function of n doped polysilicon comprises providing a substrate comprising doped source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a high k dielectric layer, and wherein the metal layer comprises a work function approximately equal to a work function of p doped polysilicon.
15. The method of claim 11 wherein providing a substrate comprising doped source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a high k dielectric layer, and wherein the metal layer comprises a work function approximately equal to a work function of p doped polysilicon comprises providing a substrate comprising doped source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a high k dielectric layer, and wherein the metal layer comprises a work function comprises a work function from about 4.8 to about 5.1 electron volts.
16. The method of claim 11 wherein providing a substrate comprising doped source/drain-and gate regions, wherein the gate region comprises a metal layer disposed on a high k dielectric layer comprises providing a substrate comprising doped source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a high k dielectric layer selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide and /or combinations thereof.
17. A structure comprising:
a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, wherein the ratio of the depth of the source/drain regions to the length of the source/drain regions is less than about 1:2, and wherein the metal layer is not substantially diffused into the gate dielectric layer.
18. The structure of claim 17 further comprising wherein the metal layer is not substantially diffused into a polysilicon layer disposed on the metal layer.
19. The structure of claim 17 wherein the metal layer comprises a work function between about 3.9 and about 4.2 electron volts.
20. The structure of claim 17 wherein the metal layer comprises a work function between about 4.8 and about 5.2 electron volts.
21. The structure of claim 17 wherein the high k dielectric layer is selected from the group consisting of hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide and /or combinations thereof.
22. The structure of claim 17 wherein the metal layer does not comprise an inter-metallic layer.
23. The structure of claim 17 wherein the metal layer comprises a material selected from the group consisting of tungsten, platinum, ruthenium, palladium, molybdenum and niobium, and their alloys, metal carbides, metal nitrides, and conductive metal oxides.
24. The structure of claim 17 wherein the metal layer does not comprise a phase changed metal layer.
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US11/120,353 US7439571B2 (en) | 2003-12-29 | 2005-05-02 | Method for fabricating metal gate structures |
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