US20050184788A1 - Logic level voltage translator - Google Patents
Logic level voltage translator Download PDFInfo
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- US20050184788A1 US20050184788A1 US10/786,357 US78635704A US2005184788A1 US 20050184788 A1 US20050184788 A1 US 20050184788A1 US 78635704 A US78635704 A US 78635704A US 2005184788 A1 US2005184788 A1 US 2005184788A1
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- signal
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- transistor
- voltage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/10—Modifications for increasing the maximum permissible switched voltage
- H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
Abstract
A voltage level translator provides an output signal having an external voltage in response to an input signal having an internal voltage. The voltage level translator includes first and second input signal transistors, first and second output signal transistors, and includes a signal stabilization circuit and/or an enable circuit. A ready-signal generation circuit provides a ready signal indicating that a voltage supply is at an operating voltage. The ready-signal generation circuit can include unbalanced transistors.
Description
- 1. Field of Invention
- The invention relates to operating voltage levels of integrated circuits. In particular, the invention relates to apparatus and methods for translating voltage levels of signals traveling between integrated circuits that operate at different voltage levels.
- 2. Discussion of Related Art
- Electronic systems often include circuits that operate at relatively low voltages, at times including core logic circuits and memory circuits, and other circuits that operate at higher voltages. Such mixed-mode voltage systems typically require voltage translation and voltage clamping capabilities. Voltage translation components allow proper communication of the I/O signals traveling between circuits operating at different voltage levels.
- Circuits that employ transistors having smaller gate dimensions typically require an associated decrease in supply voltage level. Microprocessors and memory circuits, for example, often are fabricated with transistors having the smallest possible gate sizes. Thus, electronic systems, such as a cellular telephones and personal computers, will typically have components, such as processors, that operate at a low internal voltage, and additional components that operate at a relatively high external voltage. While an internal voltage supply may provide, for example, 2.5V, 1.5V or 0.9V, external voltage supplies may provide, for example, 5V, 3.3V or 2.5V.
- Voltage translation circuits can provide uni- or bidirectional conversion of the low- and high-voltage signals produced by the circuits using the different supply voltage levels. Often, for example, a level-shifting circuit is used to increase the upper voltage-level swing of the low-voltage signals produced by high-performance complimentary metal-oxide-semiconductor (CMOS) logic devices. Unfortunately, a level-shifting circuit may fail to function properly when an internal voltage supply is producing less than its full operating voltage. Moreover, level-shifting circuits can introduce distortions and/or delays in the low-voltage signals that they convert to high-voltage signals.
- The invention arises, in part, from the realization that a voltage level shifting circuit can include an enabling circuit to prevent incorrect operation and unnecessary power use when an internal voltage supply is not ready for normal operation. The invention also arises, in part, from the realization that a voltage level shifting circuit can include a signal stabilizing circuit to improve, for example, the shape and delay characteristics of a shifted signal.
- Accordingly, in a first aspect, the invention features a voltage level translator that provides an output signal having an external voltage in response to an input signal having an internal voltage. The voltage level translator includes first and second input signal transistors, first and second output signal transistors, and includes a signal stabilization circuit and/or an enable circuit.
- The gate of the first input signal transistor receives the input signal, and the gate of the second input signal transistor receives an input complementary signal. The drain of the first output signal transistor is connected to the gate of the second output signal transistor, to the drain of the first input signal transistor, and to an output complementary signal node. The drain of the second output signal transistor is connected to the gate of the first output signal transistor, to the drain of the second input signal transistor, and to an output signal node. The signal stabilization circuit is connected to the drains of the first and second input signal transistors to modify a pulse parameter of the output signal at the output signal node.
- The first and second output signal transistors can be high voltage transistors. The external voltage can have a value in a range of, for example, about 2.0 volts to about 10.0 volts, and the internal voltage can have a value in a range of, for example, about 0.5 volt to about 2.0 volts. The first and second input signal transistors can be n-channel MOS (NMOS) transistors. The first and second input signal transistors can be low voltage transistors.
- The translator can further include first and second high voltage transistors that each have essentially zero threshold voltage and mediate the connection between the first and second input signal transistors and the first and second output signal transistors. The translator can further include a cascode circuit. The zero-threshold transistors and the cascode circuit can protect the drains of the first and second input signal transistors from the external voltage.
- The signal-stabilization circuit can include first and second signal stabilization transistors. The drain of the first signal-stabilization transistor can be connected to the drain of the first input signal transistor, and the drain of the second signal-stabilization transistor can be connected to the drain of the second input signal transistor. The sources of the first and second signal-stabilization transistors can be connected to an internal voltage supply. The gate of the first signal-stabilization transistor can receive the input signal, and the gate of the second signal-stabilization transistor can receive the input complementary signal. The first and second signal-stabilization transistors can be low-voltage p-channel MOS (PMOS) transistors, and the first and second output signal transistors can be PMOS transistors.
- The enable circuit has a first state that connects an external voltage supply to the sources of the first and second output signal transistors, and a second state that isolates the external voltage supply from the sources of the first and second output signal transistors in response to a signal that indicates the readiness of an internal voltage supply. The enable circuit can include first and second high voltage PMOS transistors having gates that receive the signal indicating that the internal voltage supply is ready.
- The voltage level translator can further include a ready-signal generation circuit that delivers an external high voltage signal to the enable circuit to indicate that the internal voltage supply is ready for safe operation.
- In a second aspect, the invention features a ready-signal generation circuit for providing a ready signal indicating that a voltage supply is at an operating voltage. The circuit includes a pair of input transistors. The gate of first input transistor receives the input signal, and the gate of the second input transistor receives an input complementary signal.
- The ready-signal generation circuit also includes a pair of output transistors. The drain of the first output transistor is connected to the gate of the second output transistor, to the drain of the first input transistor, and to an output complementary signal node. The drain of the second output transistor is connected to the gate of the first output transistor, to the drain of the second input transistor, and to an output signal node. At least one of the pairs of input transistors and output transistors are unbalanced. An unbalanced pair can be unbalanced by, for example, connecting a resistive element in parallel with one of the transistors of the pair. Alone or in combination with the resistive element, the unbalanced pair can be unbalanced by, for example, having different parameters, such as different gate dimensions.
- The ready-signal generation circuit can further include first and second high voltage transistors that each have essentially zero threshold voltage, and that mediate the connections between the pair of input signal transistors and the pair of output signal transistors.
- The accompanying drawings, are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. In the drawings:
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FIG. 1 is a schematic diagram of an example of a conventional voltage level translator that converts an internal signal to an external signal; -
FIG. 2 is a schematic diagram of an embodiment of a voltage level translator, according to principles of the invention; -
FIG. 3 is schematic diagram of an embodiment of an enable circuit, according to principles of the invention; -
FIG. 4 is schematic diagram of an embodiment of a signal-stabilization circuit, according to principles of the invention; -
FIG. 5 is schematic diagram of a embodiment of a supply-ready signal generator, according to principles of the invention; -
FIG. 6 is schematic diagram of an embodiment of a signal-stabilization circuit, according to principles of the invention; -
FIG. 7 is schematic diagram of an embodiment of a signal-stabilization circuit, according to principles of the invention; and -
FIG. 8 is schematic diagram of an embodiment of a signal-stabilization circuit, according to principles of the invention. - This invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways. Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having,” “containing”, “involving”, and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
- The term “connected” is herein used to refer to components that are either in direct or indirect electrical communication. A direct connection is an uninterrupted interconnect pathway having an essentially non-variable resistance. An indirect connection includes additional components, such as transistors. Thus, an indirect connection can be variable. For example, the connection can have a variable resistance and/or can have a conductive state and an open state. For example, as generally used herein, two connected components may be connected via a transistor that provides a conductive path or an open circuit, depending on the state of the transistor.
- The terms “core,” “internal,” and “low,” depending on context, herein refer to components configured to operate with a voltage supply provides a relatively low voltage. These terms also may refer to such a supply, for example, a supply providing a voltage selected from a range of about 0.70 V to about 1.25 V (“VddL”). The terms “I/O,” “external,” and “high,” depending on context, herein refer to components that are configured to operate with a voltage supply that provides a relatively high voltage. These terms also may refer to such a supply, for example, a supply providing a voltage selected from a range of about 2.25 V to about 3.75 V (“VddH”). A ground voltage (“Vss”) is typically at zero volt.
- For convenience, transistors that operate at a high voltage are in some instances herein referred to as “3V” transistors, and transistors that operate at a low voltage are in some instances herein referred to as “1V” transistors. This terminology is not, however, intended to limit the scope of the invention to the use of transistors operating at 1V and 3V.
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FIG. 1 is a schematic diagram of an example of a conventionalvoltage level translator 100 that converts an internal signal to an external signal. Thetranslator 100 includes a differential transistor pair of four high-voltage transistors transistors transistors transistors transistors output signal node 191 and an outputcomplementary signal node 192. As would be understood by one having ordinary skill in the microprocessor circuit arts, thetranslator 100, in cooperation with other circuit components, can convert, for example, core logic signals of a low-voltage level to I/O signals of a high-voltage level. - Now referring to
FIG. 2 , various embodiments of the invention can provide voltage level translation with circuit-protection features and/or output-signal stabilization features.FIG. 2 is a schematic diagram of an embodiment of avoltage level translator 200, according to principles of the invention. Thetranslator 200 includes a pair of input-signal transistors signal transistors signal transistors signal transistors signal node 291 and an outputcomplementary signal node 292. - The
translator 200 also includes an enablecircuit 270 and/or asignal stabilization circuit 230. The enablecircuit 270 may receive an internal supply-ready signal from an internal supply-ready signal generator 500. The internal supply-ready signal generator 500 will be described in more detail with reference toFIG. 5 . Thetranslator 200 may also include acascode circuit 220, which can help to protect the input-signal transistors - The
voltage level translator 200 can be included in, for example, a microprocessor to convert low-voltage signals output by the processor core into input signals for, for example, I/O circuitry. For example, each output-signal pad of a processor can have an associatedtranslator 200 to shift the low-voltage signal produced by the processor to a high-voltage signal that can properly interact with high-voltage external circuitry. In this example, if the processor has 128 output pads, the processor can include, for example, 128translators 200. - The
translator 200 circuitry can be located in the periphery of the processor circuitry. Alternatively, thetranslator 200 circuitry can be located internally to the processor circuitry. Moreover, core logic and I/O circuitry can be located on a single integrated circuit chip, or can be on separate chips. - The input-
signal transistors translator 200 preferably includes a native-transistor circuit 250 to, in part, protect the input-signal transistors transistor circuit 250 shown inFIG. 2 includes two3V NMOS transistors transistors - The
transistors transistors transistors native transistors input signal transistors translator 200. - Due to their low threshold voltages, the
native transistors native transistors native transistors - The
native transistors signal transistors translator 200, low-voltage transistors can be used to provide better switching behavior. Since thetranslator 200 can utilize low-voltage transistors, which can be small in area relative to high voltage transistors, the low-voltageinput signal transistors - The
output signal transistors output signal transistors input signal transistors native transistors signal node 291 in correspondence with the input signal received by the input-signal transistor 211. - The
cascode circuit 220 can include two1V NMOS transistors transistors transistors native transistors transistors signal transistors transistors signal transistors native transistors cascode circuit 220 can shield the drains of the input-signal transistors -
FIG. 3 is schematic diagram of an embodiment of an enablecircuit 270 a, which can serve as thecircuit 270 shown inFIG. 2 . The enablecircuit 270 a includes two3V PMOS transistors transistors signal transistors transistors ready signal generator 500. When the ready signal is received, as, for example, a 3V signal, thetransistors circuit 270 a thus can prevent erroneous functioning of thetranslator 200 and circuits supported by thetranslator 200, when an internal power supply has not achieved normal operating conditions. - The enable circuit 70 helps to assure that the output-
signal transistors signal transistors voltage level translator 200. The internal supply can cause this problem when its voltage level is below the level required for proper transistor operation. The enablecircuit 270 can thus disable the translator and avoid the occurrence of a DC path through thetranslator 200. - A device, such as a processor, can include, for example, a
second translator 200 to provide an output enable signal in addition to thefirst translator 200 that provides the output signal. An output enable signal can be delivered to external circuit components for their use in determining when, for example, interaction with the processor is possible. -
FIG. 4 is a schematic diagram of an embodiment of a signal-stabilization circuit 230 a, which can serve as thecircuit 230 shown inFIG. 2 . Thestabilization circuit 230 a includes two1V PMOS transistors transistors input signal transistors transistors cascode circuit 220 can mediate the connections of theinput signal transistors stabilization circuit 230 a. - The
stabilization circuit 230 a can provide, for example, a more consistent and accurate signal pulse width, and a balanced rise and fall time. That is, the output signal of thetranslator 200 can then better match the input signal. Thecircuit 230 a can also provide a speed improvement for thetranslator 200. Further, thecircuit 230 a can act as a voltage clamp to protect the input-signal transistors - Thus, the
stabilization circuit 230 a can help to ensure that the pulse width of output logic signals remain close to that of incoming logic signals. Signal integrity can be desirable, for example, when an electronic system utilizes a precise internal time reference that should be preserved externally. - Now referring to
FIG. 5 , various embodiments of thevoltage level translator 200 are well suited for use as the supply-ready signal generator 500. Thus, each pad of a microprocessor can have, for example, atranslator 200 to provide an output voltage signal, and agenerator 500 to provide a ready signal to thetranslator 200. -
FIG. 5 is schematic diagram of a more detailed embodiment of a supply-ready signal generator 500 a, which can advantageously serve as thegenerator 500 shown inFIG. 2 . The supply-ready signal generator 500 a includes a pair of input-signal transistors signal transistors signal transistors signal transistors signal node 591 and an outputcomplementary signal node 592. The generator 500 a also includes two low threshold voltage3V NMOS transistors transistors signal transistors 561. - The parameters of the
transistors signal transistor 561 is less than W/L for the other output-signal transistor 562. Similarly, gate dimensions can be chosen so that W/L for one input-signal transistor 512 is less than W/L for the other output-signal transistor 511. - Thus, the conductance of one input-
signal transistor 511 is weaker than the other input-signal transistor 512. Similarly, the conductance of one output-signal transistor 562 is weaker than the other output-signal transistor 561. The resistive component 573 can pull up the outputcomplementary signal node 592, which must be pulled down by a weak input-signal transistor 511 and a lowthreshold voltage transistor 551. - The pair of
output transistors - Functionally, the generator 500 a produces a ready signal at an external (high) voltage in response to reception of an inner voltage that exceeds a preset safe voltage level for an internal voltage supply. Thus, the supply-ready signal generator 500 a detects a ready condition of an internal voltage supply, and responsively produces an internal-supply ready signal. The ready signal can be delivered to, for example, the enable
circuit 270. In turn, the enablecircuit 270 can permit operation of thevoltage translator 200. - Because the transistors of a device as-fabricated are typically well matched, the intentionally unbalanced transistors of the supply-ready signal generator 500 a can provide a good test of a safe internal operating voltage. The out-of-balance nature of the supply-ready signal generator 500 a can assure that a signal will not be generated by the unbalanced circuit of the supply-ready signal generator 500 a unless the supply voltage is also sufficient to properly operate other low-voltage transistors in the device. So, for example, by the time the supply-ready signal generator 500 a is capable of providing a high-voltage internal-supply ready signal, the
translation circuit 200, which is preferably balanced, will typically function correctly. - Now referring to
FIGS. 6, 7 and 8, some alternative embodiments of signal-stabilization circuits are described.FIG. 6 is schematic diagram of an embodiment of a signal-stabilization circuit 230 b, which can serve as thecircuit 230 shown inFIG. 2 . Thestabilization circuit 230 b includes four1V PMOS transistors 231 b. Thetransistors 231 b have their drains connected in series to one of the drains of the input-signal transistors transistors cascode circuit 220 can mediate the connections of the input-signal transistors stabilization circuit 230 a. -
FIG. 7 is schematic diagram of another embodiment of a signal-stabilization circuit 230 c, which can serve as thecircuit 230 shown inFIG. 2 . Thestabilization circuit 230 c includes two1V PMOS transistors transistors signal transistors FIG. 8 is schematic diagram of still another embodiment of a signal-stabilization circuit 230 d, which can serve as thecircuit 230 shown inFIG. 2 . Thestabilization circuit 230 d includes two1V PMOS transistors transistors signal transistors - Having thus described several aspects of at least one embodiment of this invention, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description and drawings are by way of example only.
Claims (20)
1. A voltage level translator for providing an output signal having an external voltage in response to an input signal having an internal voltage, the voltage level translator comprising:
first and second input signal transistors, the gate of the first input signal transistor receiving the input signal, and the gate of the second input signal transistor receiving an input complementary signal;
first and second output signal transistors,
the drain of the first output signal transistor connected to the gate of the second output signal transistor, the drain of the first input signal transistor, and to an output complementary signal node,
the drain of the second output signal transistor connected to the gate of the first output signal transistor, the drain of the second input signal transistor, and to an output signal node; and
a signal stabilization circuit connected to the drains of the first and second input signal transistors to modify a pulse parameter of the output signal at the output signal node.
2. The voltage level translator of claim 1 , wherein the signal stabilization circuit comprises first and second signal stabilization transistors, the drain of the first signal stabilization transistor connected to the drain of the first input signal transistor, and the drain of the second signal stabilization transistor connected to the drain of the second input signal transistor.
3. The voltage level translator of claim 2 , wherein the sources of the first and second signal stabilization transistors are connected to an internal voltage supply.
4. The voltage level translator of claim 3 , wherein the gate of the first signal stabilization transistor receives the input signal, and the gate of the second signal stabilization transistor receives the input complementary signal.
5. The voltage level translator of claim 3 , wherein the first and second signal stabilization transistors are low voltage PMOS transistors.
6. The voltage level translator of claim 1 , wherein the first and second output signal transistors are PMOS transistors.
7. The voltage level translator of claim 6 , wherein the first and second output signal transistors are high voltage transistors.
8. The voltage level translator of claim 1 , wherein the first and second input signal transistors are NMOS transistors.
9. The voltage level translator of claim 8 , wherein the first and second input signal transistors are low voltage transistors.
10. The voltage level translator of claim 9 , further comprising first and second high voltage transistors that each have essentially zero threshold voltage and mediate the connections between the first and second input signal transistors and the first and second output signal transistors.
11. The voltage level translator of claim 9 , further comprising a cascode circuit that protects the drains of the first and second input signal transistors from the external voltage.
12. A voltage level translator for providing an output signal having an external voltage in response to an input signal having an internal voltage, the voltage level translator comprising:
first and second input signal transistors, the gate of the first input signal transistor receiving the input signal, and the gate of the second input signal transistor receiving an input complementary signal;
first and second output signal transistors,
the drain of the first output signal transistor connected to the gate of the second output signal transistor, to the drain of the first input signal transistor, and to an output complementary signal node,
the drain of the second output signal transistor connected to the gate of the first output signal transistor, to the drain of the second input signal transistor, and to an output signal node; and
an enable circuit having a first state that connects an external voltage supply to the sources of the first and second output signal transistors, and a second state that isolates the external voltage supply from the sources of the first and second output signal transistors in response to a signal that indicates the readiness of an internal voltage supply.
13. The voltage level translator of claim 12 , wherein the enable circuit comprises first and second high voltage PMOS transistors having gates that receive the signal indicating that the internal voltage supply is ready.
14. The voltage level translator of claim 12 , further comprising a ready-signal generation circuit that delivers an external high voltage signal to the enable circuit to indicate that the internal voltage supply is ready.
15. The voltage level translator of claim 12 , further comprising first and second high voltage transistors that each have essentially zero threshold voltage, and that mediate the connection between the first and second input signal transistors and the first and second output signal transistors.
16. The voltage level translator of claim 12 , further comprising a signal stabilization circuit connected to the drains of the first and second input signal transistors to modify a pulse parameter of the output signal at the output signal node.
17. A ready-signal generation circuit for providing a ready-signal indicating that a voltage supply is at an operating voltage, the circuit comprising:
a pair of input transistors, the gate of a first input transistor of the pair of input transistors receiving the input signal, and the gate of a second input transistor of the pair of input transistors receiving an input complementary signal; and
a pair of output transistors,
the drain of a first output transistor of the pair of output transistors connected to the gate of a second output transistor of the pair of output transistors, to the drain of the first input transistor, and to an output complementary signal node,
the drain of the second output transistor connected to the gate of the first output transistor, to the drain of the second input transistor, and to an output signal node,
wherein at least one of the pairs of input transistors and output transistors are unbalanced.
18. The ready-signal generation circuit of claim 17 , wherein a resistive element connected in parallel with one transistor of the input and output transistors at least in part causes the at least one unbalanced pair to be unbalanced.
19. The ready-signal generation circuit of claim 17 , wherein the at least one unbalanced pair has a parameter selected to at least in part cause the at least one unbalanced pair to be unbalanced.
20. The ready-signal generation circuit of claim 17 , further comprising first and second high voltage transistors that each have essentially zero threshold voltage, and that mediate the connections between the pair of input signal transistors and the pair of output signal transistors.
Priority Applications (2)
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US10/786,357 US20050184788A1 (en) | 2004-02-25 | 2004-02-25 | Logic level voltage translator |
US11/205,475 US7573313B2 (en) | 2004-02-25 | 2005-08-17 | Logic level voltage translator |
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US10/786,357 US20050184788A1 (en) | 2004-02-25 | 2004-02-25 | Logic level voltage translator |
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US11/205,475 Division US7573313B2 (en) | 2004-02-25 | 2005-08-17 | Logic level voltage translator |
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US11/205,475 Expired - Lifetime US7573313B2 (en) | 2004-02-25 | 2005-08-17 | Logic level voltage translator |
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US6650168B1 (en) * | 2002-09-30 | 2003-11-18 | Taiwan Semiconductor Manufacturing Company | High-speed level shifter using zero-threshold MOSFETS |
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US7642600B1 (en) | 2006-12-07 | 2010-01-05 | National Semiconductor Corporation | System and method for providing a low voltage thin gate input/output structure with thick gate overvoltage/backdrive protection |
US20090027104A1 (en) * | 2007-07-06 | 2009-01-29 | Analog Devices, Inc. | Methods and apparatus for predictable level shifter power-up state |
US8063662B2 (en) | 2007-07-06 | 2011-11-22 | Analog Devices, Inc. | Methods and apparatus for predictable level shifter power-up state |
US20090058773A1 (en) * | 2007-09-04 | 2009-03-05 | Yu-Jui Chang | Display driver and related display |
US8159481B2 (en) * | 2007-09-04 | 2012-04-17 | Himax Technologies Limited | Display driver and related display |
US20090295439A1 (en) * | 2008-05-27 | 2009-12-03 | Tsung-Hsien Tsai | Phase Lock Loop (PLL) with Gain Control |
US7786771B2 (en) * | 2008-05-27 | 2010-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Phase lock loop (PLL) with gain control |
US8929171B2 (en) | 2011-11-09 | 2015-01-06 | Samsung Electronics Co., Ltd. | Voltage supply controller, nonvolatile memory device and memory system |
US20150229302A1 (en) * | 2014-02-07 | 2015-08-13 | Samsung Electronics Co., Ltd. | Sense amplifier and method of operating the same |
JP2017121052A (en) * | 2015-12-28 | 2017-07-06 | 株式会社半導体エネルギー研究所 | Level shift circuit, driver ic, and electronic equipment |
CN111682870A (en) * | 2020-07-08 | 2020-09-18 | 湖南国科微电子股份有限公司 | Receiver architecture and receiver integrated chip |
Also Published As
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US20050275445A1 (en) | 2005-12-15 |
US7573313B2 (en) | 2009-08-11 |
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