US20050189646A1 - Packaged die on PCB with heat sink encapsulant and methods - Google Patents

Packaged die on PCB with heat sink encapsulant and methods Download PDF

Info

Publication number
US20050189646A1
US20050189646A1 US11/053,082 US5308205A US2005189646A1 US 20050189646 A1 US20050189646 A1 US 20050189646A1 US 5308205 A US5308205 A US 5308205A US 2005189646 A1 US2005189646 A1 US 2005189646A1
Authority
US
United States
Prior art keywords
semiconductor chip
substrate
barrier material
contact point
thermal conductivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/053,082
Inventor
Salman Akram
James Wark
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/053,082 priority Critical patent/US20050189646A1/en
Publication of US20050189646A1 publication Critical patent/US20050189646A1/en
Priority to US11/603,581 priority patent/US20070069372A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909Post-treatment of the layer connector or bonding area
    • H01L2224/83951Forming additional members, e.g. for reinforcing, fillet sealant
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85203Thermocompression bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • H01L2224/85207Thermosonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01031Gallium [Ga]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01032Germanium [Ge]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Definitions

  • the present invention relates to an apparatus and a method for providing a heat sink on a semiconductor chip. More particularly, the present invention relates to forming a heat sink on an upper surface of a semiconductor chip by placing a heat conductive material thereon which forms a portion of a glob top.
  • COB Chip On Board
  • TAB tape automated bonding
  • a flip chip attachment consists of attaching a flip chip to a printed circuit board or other substrate.
  • a flip chip is a semiconductor chip that has a pattern or array of terminations spaced around an active surface of the flip chip for face-down mounting of the flip chip to a substrate.
  • the flip chip active surface has one of the following electrical connectors: Ball Grid Array (“BGA”), wherein an array of minute solder balls is disposed on the surface of a flip chip which attaches to the substrate (“the attachment surface”); Slightly Larger than Integrated Circuit Carrier (“SLICC”), which is similar to a BGA but has a smaller solder ball pitch and diameter than a BGA; or a Pin Grid Array (“PGA”), wherein an array of small pins extends substantially perpendicularly from the attachment surface of a flip chip wherein the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto.
  • BGA Ball Grid Array
  • SLICC Slightly Larger than Integrated Circuit Carrier
  • PGA Pin Grid Array
  • the solder or other conductive ball arrangement on the flip chip must be a mirror image of the connecting bond pads on the printed circuit board such that precise connection is made.
  • the flip chip is bonded to the printed circuit board by reflowing the solder balls.
  • the solder balls may also be replaced with a conductive polymer.
  • the pin arrangement of the flip chip must be a mirror image of the pin recesses on the printed circuit board. After insertion, the flip chip is generally bonded by soldering the pins into place.
  • An underfill encapsulant is generally disposed between the flip chip and the printed circuit board for environmental protection and to enhance the attachment of the flip chip to the printed circuit board.
  • a variation of the pin-in-recess PGA is a J-lead PGA wherein the loops of the J's are soldered to pads on the surface of the circuit board.
  • Wire bonding and TAB attachment generally begin with attaching a semiconductor chip to the surface of a printed circuit board with an appropriate adhesive such as an epoxy.
  • wire bonding a plurality of bond wires is attached one at a time to each bond pad on the semiconductor chip and extends to a corresponding lead or trace end on the printed circuit board.
  • the bond wires are generally attached through one of three industry-standard wire bonding techniques: ultrasonic bonding, using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding, using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding, using a combination of pressure, elevated temperature and ultrasonic vibration bursts.
  • the semiconductor chip may be oriented either face up or face down (with its active surface and bond pads either up or down with respect to the circuit board) for wire bonding, although face up orientation is more common.
  • TAB ends of metal leads carried on an insulating tape such as a polyamide are respectively attached to the bond pads on the semiconductor chip and to the lead or trace ends on the printed circuit board.
  • An encapsulant is generally used to cover the bond wires and metal tape leads to prevent contamination.
  • a glob of encapsulant material 102 (usually epoxy or silicone or a combination thereof) is generally applied to a COB assembly 100 to surround a semiconductor chip or flip chip 104 which is attached to a substrate 106 via a plurality of electrical connections 108 which extends between a plurality of semiconductor chip bond pads 110 and a corresponding plurality of substrate bond pads 112 .
  • An underfill encapsulant 114 is dispensed between the semiconductor chip 104 and the substrate 106 .
  • the glob top materials 202 are often used to hermetically seal bare dice 204 (shown in shadow) on a printed circuit board 206 such as SIMM modules to form a COB assembly 200 .
  • the organic resins generally used in the glob top encapsulation are usually selected for low moisture permeability and low thermal coefficient of expansion to avoid exposure of the encapsulated chip to moisture or mechanical stress respectively.
  • the thermal and electrical properties are often not optimal for removing heat efficiently away from the semiconductor dice or for use in high temperature areas.
  • Every semiconductor chip in a COB assembly generates some heat during operation. Some glob tops and package encapsulation materials serve to draw the heat away from most semiconductor chips. Indeed, one factor in choosing a package encapsulation material is its thermal dissipation properties. If the temperature of the semiconductor chip is not controlled or accommodated, system reliability problems may occur due to excess temperature rise during operation. The device/semiconductor junction temperature (the location of the heat source due to power dissipation) must be maintained below a limiting value such as 85° C. The primary reason to control this temperature is that switching voltage is a sensitive function of device temperature. In addition, various failure mechanisms are thermally activated and failure rates become excessive above the desired temperature limit.
  • FIG. 3 illustrates a finned COB assembly 300 .
  • the finned COB assembly 300 comprises a semiconductor chip or flip chip 302 which is attached to a substrate 304 via a plurality of electrical connections 306 which extends between a plurality of semiconductor chip bond pads 308 and a corresponding plurality of substrate bond pads 310 .
  • An underfill encapsulant 312 is dispensed between the semiconductor chip 302 and the substrate 304 .
  • a cap 314 having a plurality of heat-dissipating fins 316 is attached to an upper surface 318 of the semiconductor chip 302 with a layer of thermally conductive adhesive 320 .
  • the addition of heat-dissipating fins, blocks or the like substantially increases the cost of production for COB assemblies.
  • U.S. Pat. No. 5,379,186 issued Jan. 3, 1995, to Gold et al. (“Gold”) relates to a heat-producing semiconductor chip attached to a substrate which uses multiple encapsulants to dissipate heat. “Gold” teaches placing a layer of encapsulant material over the semiconductor chip with a layer of thermally conductive material applied over the encapsulant material layer. “Gold” specifically teaches that the encapsulant material layer used for covering the semiconductor is a relatively poor conductor of heat (i.e., an insulative material) which is assumedly chosen for its adherence and protective properties. The thermally conductive material is applied over the encapsulant material to aid in the removal of heat from the semiconductor device through the insulating encapsulant material. However, this invention is inherently inefficient since the heat must be drawn from an insulative material.
  • the present invention relates to an apparatus and a method for providing a heat sink on a semiconductor chip.
  • the apparatus is constructed with a two-step process for forming a dual material glob top.
  • the process comprises providing a semiconductor chip attached to and in electrical communication with a substrate by any known industry technique such as flip chip attachment, TAB attachment, wire bonding and the like.
  • a barrier glob top material is applied to the edges of the semiconductor chip on the surface (“opposing surface”) opposite the surface (“attachment surface”) attached to the substrate to form a wall around a periphery of the opposing surface of the semiconductor chip and extends to contact and adhere to the substrate.
  • the barrier glob top performs the function of sealing and protecting the semiconductor chip.
  • the barrier glob top material is selected for low moisture permeability, low thermal coefficient of expansion, and good adhesion and sealing properties.
  • Preferred barrier glob top materials include epoxy, polyamide, urethane silicone, acrylic or the like.
  • the wall formed around the periphery of the opposing surface preferably covers and encapsulates the bond wires or TAB. If the semiconductor chip is a flip chip, an underfill encapsulant may be disposed between the semiconductor chip and the substrate.
  • the wall around the periphery of the opposing surface of the semiconductor chip forms a recess.
  • a heat-dissipating glob top material is disposed within the recess to contact the opposing surface of the semiconductor chip.
  • the heat-dissipating glob top material is chosen for its ability to transfer heat away from the semiconductor chip (i.e., high thermal conductivity material).
  • the heat-dissipating glob top material has a higher thermal conductivity than the barrier glob top material.
  • the heat-dissipating glob top may also extend over the barrier glob top wall to contact the substrate.
  • heat-dissipating glob top materials include: standard, high purity barrier glob top materials containing arsenic, boron, gallium, germanium, phosphorus, silicon or other such suitable highly conductive materials.
  • the apparatus of the present invention has all of the adherence and sealing benefits of a low thermal conductivity glob top material while at the same time enjoying the benefits of heat-dissipation provided by a high thermal conductivity glob top material.
  • FIG. 1 is a side cross-sectional view of a prior art glob top encapsulated semiconductor chip attached to a substrate;
  • FIG. 2 is an oblique plan view of a prior art substrate with a plurality of semiconductors attached to a substrate with a glob top encapsulation;
  • FIG. 3 is a side cross-sectional view of a prior art semiconductor assembly with heat-dissipating fins attached to a substrate;
  • FIG. 4 is a side cross-sectional view of a first encapsulated semiconductor assembly of the present invention.
  • FIG. 5 is an oblique plan view of the first encapsulated semiconductor assembly of FIG. 4 ;
  • FIG. 6 is a side cross-sectional view of a second encapsulated semiconductor assembly of the present invention.
  • FIG. 7 is a side cross-sectional view of a third encapsulated semiconductor assembly of the present invention.
  • FIG. 8 is a side cross-sectional view of a fourth encapsulated semiconductor assembly of the present invention.
  • FIG. 9 is a side cross-sectional view of a multiple encapsulated semiconductor dice assembly of the present invention.
  • FIG. 4 illustrates a first encapsulated semiconductor assembly 400 of the present invention.
  • the first encapsulated semiconductor assembly 400 comprises a flip chip or semiconductor chip 402 having a plurality of bond pads 404 on an active surface 406 of the semiconductor chip 402 .
  • a facing surface 408 of each bond pad 404 has a conductive pad 410 in electrical communication therewith.
  • the conductive pads 410 are in electrical communication with a plurality of respective bond pads 412 on an upper surface 414 of a substrate 416 .
  • Each substrate bond pad 412 is connected on a lower bond pad surface 418 to a trace lead 420 (shown by a dashed line).
  • An underfill encapsulant 422 may be disposed between the semiconductor chip 402 and the substrate 416 .
  • a barrier glob top 424 is applied to surround a periphery of the semiconductor chip 402 which seals and protects the semiconductor chip 402 and forms a recess or cavity 426 .
  • a heat-dissipating glob top 428 is disposed within the recess 426 as shown in FIG. 4 .
  • FIG. 6 illustrates a second encapsulated semiconductor assembly 600 of the present invention.
  • the encapsulated semiconductor assembly 600 comprises a semiconductor chip 602 attached by a back side 604 to a facing surface 606 of a substrate 608 .
  • the semiconductor chip 602 has a plurality of bond pads 610 on an active surface 612 of the semiconductor chip 602 .
  • a facing surface 614 of each bond pad 610 has a bond wire 616 in electrical communication therewith.
  • Each bond wire 616 is in electrical communication with a respective bond pad 620 on the substrate facing surface 606 .
  • Each substrate bond pad 620 is connected on a lower bond pad surface 622 to a trace lead 624 (shown by a dashed line).
  • a barrier glob top 626 is applied to surround a periphery of the semiconductor chip 602 , forming a recess or cavity 628 .
  • a heat-dissipating glob top 630 is disposed within the recess 628 .
  • FIG. 7 illustrates a third encapsulated semiconductor assembly 700 of the present invention.
  • the third encapsulated semiconductor assembly 700 is similar to the second encapsulated semiconductor assembly 600 ; therefore, components common to FIGS. 6 and 7 retain the same numeric designation.
  • the difference between the third encapsulated semiconductor assembly 700 and the second encapsulated semiconductor assembly 600 is that the third encapsulated semiconductor assembly 700 has a plurality of TAB attachments 702 forming an electrical communication between the facing surface 614 of the semiconductor chip bond pad 610 and the substrate bond pads 620 rather than the bond wires 616 of the second encapsulated semiconductor assembly 600 .
  • FIG. 8 illustrates a fourth encapsulated semiconductor assembly 800 of the present invention.
  • the fourth encapsulated semiconductor assembly 800 is similar to the second encapsulated semiconductor assembly 600 ; therefore, components common to FIGS. 6 and 8 retain the same numeric designation.
  • the difference between the fourth encapsulated semiconductor assembly 800 and the second encapsulated semiconductor assembly 600 is that the fourth encapsulated semiconductor assembly 800 has a heat-dissipating glob top 802 which is disposed within the recess 628 and extends over the barrier glob top 626 to contact and adhere to the substrate 608 .
  • FIG. 9 illustrates a multiple encapsulated semiconductor dice assembly 900 of the present invention.
  • the multiple encapsulated semiconductor dice assembly 900 is similar to the fourth encapsulated semiconductor assembly 800 ; therefore, components common to FIGS. 8 and 9 retain the same numeric designation.
  • the difference between the multiple encapsulated semiconductor dice assembly 900 and the fourth encapsulated semiconductor assembly 800 is that the multiple encapsulated semiconductor dice assembly 900 has multiple semiconductor dice 902 and 904 with a heat-dissipating glob top 802 which extends over the semiconductor dice 902 and 904 to contact and adhere to the substrate 608 .

Abstract

An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob top material is applied to the edges of the semiconductor chip on the surface (“opposing surface”) opposite the surface attached to the substrate to form a wall around a periphery of the opposing surface of the semiconductor chip wherein the barrier glob top material also extends to contact and adhere to the substrate. The wall around the periphery of the opposing surface of the semiconductor chip forms a recess. A heat-dissipating glob top material is disposed within the recess to contact the opposing surface of the semiconductor chip.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of application Ser. No. 10/639,349, filed Aug. 12, 2003, now U.S. Pat. No. 6,853,069, issued Feb. 8, 2005, which is a continuation of application Ser. No. 10/232,782, filed Aug. 28, 2002, now U.S. Pat. No. 6,617,684, issued Sep. 9, 2003, which is a continuation of application Ser. No. 09/835,541, filed Apr. 16, 2001, now U.S. Pat. No. 6,534,858, issued Mar. 18, 2003, which is a continuation of application Ser. No. 09/189,102, filed Nov. 9, 1998, now U.S. Pat. No. 6,252,308, issued Jun. 26, 2001, which is a continuation of application Ser. No. 08/653,030, filed May 24, 1996, now U.S. Pat. No. 5,866,953, issued on Feb. 2, 1999.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to an apparatus and a method for providing a heat sink on a semiconductor chip. More particularly, the present invention relates to forming a heat sink on an upper surface of a semiconductor chip by placing a heat conductive material thereon which forms a portion of a glob top.
  • 2. State of the Art
  • Chip On Board (“COB”) techniques are used to attach semiconductor dice to a printed circuit board including flip chip attachment, wire bonding and tape automated bonding (“TAB”).
  • Flip chip attachment consists of attaching a flip chip to a printed circuit board or other substrate. A flip chip is a semiconductor chip that has a pattern or array of terminations spaced around an active surface of the flip chip for face-down mounting of the flip chip to a substrate. Generally the flip chip active surface has one of the following electrical connectors: Ball Grid Array (“BGA”), wherein an array of minute solder balls is disposed on the surface of a flip chip which attaches to the substrate (“the attachment surface”); Slightly Larger than Integrated Circuit Carrier (“SLICC”), which is similar to a BGA but has a smaller solder ball pitch and diameter than a BGA; or a Pin Grid Array (“PGA”), wherein an array of small pins extends substantially perpendicularly from the attachment surface of a flip chip wherein the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto. With the BGA or SLICC, the solder or other conductive ball arrangement on the flip chip must be a mirror image of the connecting bond pads on the printed circuit board such that precise connection is made. The flip chip is bonded to the printed circuit board by reflowing the solder balls. The solder balls may also be replaced with a conductive polymer. With the PGA, the pin arrangement of the flip chip must be a mirror image of the pin recesses on the printed circuit board. After insertion, the flip chip is generally bonded by soldering the pins into place. An underfill encapsulant is generally disposed between the flip chip and the printed circuit board for environmental protection and to enhance the attachment of the flip chip to the printed circuit board. A variation of the pin-in-recess PGA is a J-lead PGA wherein the loops of the J's are soldered to pads on the surface of the circuit board.
  • Wire bonding and TAB attachment generally begin with attaching a semiconductor chip to the surface of a printed circuit board with an appropriate adhesive such as an epoxy. In wire bonding, a plurality of bond wires is attached one at a time to each bond pad on the semiconductor chip and extends to a corresponding lead or trace end on the printed circuit board. The bond wires are generally attached through one of three industry-standard wire bonding techniques: ultrasonic bonding, using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding, using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding, using a combination of pressure, elevated temperature and ultrasonic vibration bursts. The semiconductor chip may be oriented either face up or face down (with its active surface and bond pads either up or down with respect to the circuit board) for wire bonding, although face up orientation is more common. With TAB, ends of metal leads carried on an insulating tape such as a polyamide are respectively attached to the bond pads on the semiconductor chip and to the lead or trace ends on the printed circuit board. An encapsulant is generally used to cover the bond wires and metal tape leads to prevent contamination.
  • After assembly as shown in FIG. 1, a glob of encapsulant material 102 (usually epoxy or silicone or a combination thereof) is generally applied to a COB assembly 100 to surround a semiconductor chip or flip chip 104 which is attached to a substrate 106 via a plurality of electrical connections 108 which extends between a plurality of semiconductor chip bond pads 110 and a corresponding plurality of substrate bond pads 112. An underfill encapsulant 114 is dispensed between the semiconductor chip 104 and the substrate 106. As shown in FIG. 2, the glob top materials 202 are often used to hermetically seal bare dice 204 (shown in shadow) on a printed circuit board 206 such as SIMM modules to form a COB assembly 200. The organic resins generally used in the glob top encapsulation are usually selected for low moisture permeability and low thermal coefficient of expansion to avoid exposure of the encapsulated chip to moisture or mechanical stress respectively. However, even though the chemical properties of these glob top materials have desirable properties for encapsulation, the thermal and electrical properties are often not optimal for removing heat efficiently away from the semiconductor dice or for use in high temperature areas.
  • Every semiconductor chip in a COB assembly generates some heat during operation. Some glob tops and package encapsulation materials serve to draw the heat away from most semiconductor chips. Indeed, one factor in choosing a package encapsulation material is its thermal dissipation properties. If the temperature of the semiconductor chip is not controlled or accommodated, system reliability problems may occur due to excess temperature rise during operation. The device/semiconductor junction temperature (the location of the heat source due to power dissipation) must be maintained below a limiting value such as 85° C. The primary reason to control this temperature is that switching voltage is a sensitive function of device temperature. In addition, various failure mechanisms are thermally activated and failure rates become excessive above the desired temperature limit. Furthermore, it is important to control the variation in device operating temperature across all the devices in the system. This is also due to the temperature sensitivity of switching voltage since too large a variation from device to device would increase the voltage range over which switching occurs, leading to switching errors due to noise and power-supply fluctuations. Moreover, the fluctuations in temperature cause differential thermal expansions which give rise to a fatigue process that can lead to cracks occurring in the COB assembly during burn-in or general operation.
  • Thus high heat-producing semiconductor dice such as microprocessors may require adjustments in the size of the COB assembly and will often require the addition of metal heat-dissipating fins, blocks or the like on the package. FIG. 3 illustrates a finned COB assembly 300. The finned COB assembly 300 comprises a semiconductor chip or flip chip 302 which is attached to a substrate 304 via a plurality of electrical connections 306 which extends between a plurality of semiconductor chip bond pads 308 and a corresponding plurality of substrate bond pads 310. An underfill encapsulant 312 is dispensed between the semiconductor chip 302 and the substrate 304. A cap 314 having a plurality of heat-dissipating fins 316 is attached to an upper surface 318 of the semiconductor chip 302 with a layer of thermally conductive adhesive 320. The addition of heat-dissipating fins, blocks or the like substantially increases the cost of production for COB assemblies.
  • Other means for heat dissipation have also been attempted. U.S. Pat. No. 5,434,105 issued Jul. 18, 1995, to Liou relates to the use of heat spreaders attached to a semiconductor device by a glob top to strengthen the heat coupling from an integrated circuit die to the lead frame wherein heat can then pass through the leads of the lead frame to the circuit board. However, the heat is not dissipated away from the circuit. Rather, the heat is conducted into the circuit board, which can still cause heat related problems. U.S. Pat. No. 5,488,254 issued Jan. 30, 1996, to Nishimura et al. and U.S. Pat. No. 5,489,801 issued Feb. 6, 1996, to Blish relate to encasing a heat slug (a piece of heat conducting material) in the encapsulation material. Although each of these patents attempts to address the problems of potential differences in the thermal coefficient of expansion between the heat slug and the encapsulation material, these attempts are never entirely successful and the adhesion interfaces between the heat slug and the encapsulation material may become separated, allowing moisture to reach and destroy the encased chip.
  • Changes in encapsulation materials have also been attempted to achieve high thermal conductivity, low coefficient of thermal expansion and low moisture permeability. U.S. Pat. No. 4,358,552 issued Nov. 9, 1982, to Shinohara et al. and U.S. Pat. No. 4,931,852 issued Jun. 5, 1990, to Brown et al. are examples of such attempts. However, no attempt has been entirely successful in balancing all of these desired factors or are simply too expensive.
  • U.S. Pat. No. 5,379,186 issued Jan. 3, 1995, to Gold et al. (“Gold”) relates to a heat-producing semiconductor chip attached to a substrate which uses multiple encapsulants to dissipate heat. “Gold” teaches placing a layer of encapsulant material over the semiconductor chip with a layer of thermally conductive material applied over the encapsulant material layer. “Gold” specifically teaches that the encapsulant material layer used for covering the semiconductor is a relatively poor conductor of heat (i.e., an insulative material) which is assumedly chosen for its adherence and protective properties. The thermally conductive material is applied over the encapsulant material to aid in the removal of heat from the semiconductor device through the insulating encapsulant material. However, this invention is inherently inefficient since the heat must be drawn from an insulative material.
  • Therefore, it would be advantageous to develop a technique and assembly for inexpensively forming a heat-dissipating mechanism on a semiconductor chip in combination with commercially available, widely practiced semiconductor device fabrication techniques.
  • BRIEF SUMMARY OF THE INVENTION
  • The present invention relates to an apparatus and a method for providing a heat sink on a semiconductor chip. The apparatus is constructed with a two-step process for forming a dual material glob top. The process comprises providing a semiconductor chip attached to and in electrical communication with a substrate by any known industry technique such as flip chip attachment, TAB attachment, wire bonding and the like. A barrier glob top material is applied to the edges of the semiconductor chip on the surface (“opposing surface”) opposite the surface (“attachment surface”) attached to the substrate to form a wall around a periphery of the opposing surface of the semiconductor chip and extends to contact and adhere to the substrate. The barrier glob top performs the function of sealing and protecting the semiconductor chip. Thus the barrier glob top material is selected for low moisture permeability, low thermal coefficient of expansion, and good adhesion and sealing properties. Preferred barrier glob top materials include epoxy, polyamide, urethane silicone, acrylic or the like.
  • If the semiconductor chip makes electrical contact between the opposing side and the substrate with bond wires or TAB, the wall formed around the periphery of the opposing surface preferably covers and encapsulates the bond wires or TAB. If the semiconductor chip is a flip chip, an underfill encapsulant may be disposed between the semiconductor chip and the substrate.
  • The wall around the periphery of the opposing surface of the semiconductor chip forms a recess. A heat-dissipating glob top material is disposed within the recess to contact the opposing surface of the semiconductor chip. The heat-dissipating glob top material is chosen for its ability to transfer heat away from the semiconductor chip (i.e., high thermal conductivity material). As a general matter, the heat-dissipating glob top material has a higher thermal conductivity than the barrier glob top material. The heat-dissipating glob top may also extend over the barrier glob top wall to contact the substrate. It is also understood that a plurality of semiconductor chips with barrier glob tops could be attached to a substrate with a continuous heat-dissipating glob top filling each semiconductor chip barrier glob top recess and covering each of the plurality of semiconductor chips. Preferred heat-dissipating glob top materials include: standard, high purity barrier glob top materials containing arsenic, boron, gallium, germanium, phosphorus, silicon or other such suitable highly conductive materials.
  • Differences in the thermal coefficient of expansion between the barrier glob top and the heat-dissipating glob top and the potential of separation of the interface between the barrier glob top and the heat-dissipating glob top are less an issue with the present invention since the barrier glob top completely seals the semiconductor chip from moisture or external contamination.
  • Thus, the apparatus of the present invention has all of the adherence and sealing benefits of a low thermal conductivity glob top material while at the same time enjoying the benefits of heat-dissipation provided by a high thermal conductivity glob top material.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
  • FIG. 1 is a side cross-sectional view of a prior art glob top encapsulated semiconductor chip attached to a substrate;
  • FIG. 2 is an oblique plan view of a prior art substrate with a plurality of semiconductors attached to a substrate with a glob top encapsulation;
  • FIG. 3 is a side cross-sectional view of a prior art semiconductor assembly with heat-dissipating fins attached to a substrate;
  • FIG. 4 is a side cross-sectional view of a first encapsulated semiconductor assembly of the present invention;
  • FIG. 5 is an oblique plan view of the first encapsulated semiconductor assembly of FIG. 4;
  • FIG. 6 is a side cross-sectional view of a second encapsulated semiconductor assembly of the present invention;
  • FIG. 7 is a side cross-sectional view of a third encapsulated semiconductor assembly of the present invention;
  • FIG. 8 is a side cross-sectional view of a fourth encapsulated semiconductor assembly of the present invention; and
  • FIG. 9 is a side cross-sectional view of a multiple encapsulated semiconductor dice assembly of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 4 illustrates a first encapsulated semiconductor assembly 400 of the present invention. The first encapsulated semiconductor assembly 400 comprises a flip chip or semiconductor chip 402 having a plurality of bond pads 404 on an active surface 406 of the semiconductor chip 402. A facing surface 408 of each bond pad 404 has a conductive pad 410 in electrical communication therewith. The conductive pads 410 are in electrical communication with a plurality of respective bond pads 412 on an upper surface 414 of a substrate 416. Each substrate bond pad 412 is connected on a lower bond pad surface 418 to a trace lead 420 (shown by a dashed line). An underfill encapsulant 422 may be disposed between the semiconductor chip 402 and the substrate 416.
  • As seen in FIGS. 4 and 5, a barrier glob top 424 is applied to surround a periphery of the semiconductor chip 402 which seals and protects the semiconductor chip 402 and forms a recess or cavity 426. A heat-dissipating glob top 428 is disposed within the recess 426 as shown in FIG. 4.
  • FIG. 6 illustrates a second encapsulated semiconductor assembly 600 of the present invention. The encapsulated semiconductor assembly 600 comprises a semiconductor chip 602 attached by a back side 604 to a facing surface 606 of a substrate 608. The semiconductor chip 602 has a plurality of bond pads 610 on an active surface 612 of the semiconductor chip 602. A facing surface 614 of each bond pad 610 has a bond wire 616 in electrical communication therewith. Each bond wire 616 is in electrical communication with a respective bond pad 620 on the substrate facing surface 606. Each substrate bond pad 620 is connected on a lower bond pad surface 622 to a trace lead 624 (shown by a dashed line). A barrier glob top 626 is applied to surround a periphery of the semiconductor chip 602, forming a recess or cavity 628. A heat-dissipating glob top 630 is disposed within the recess 628.
  • FIG. 7 illustrates a third encapsulated semiconductor assembly 700 of the present invention. The third encapsulated semiconductor assembly 700 is similar to the second encapsulated semiconductor assembly 600; therefore, components common to FIGS. 6 and 7 retain the same numeric designation. The difference between the third encapsulated semiconductor assembly 700 and the second encapsulated semiconductor assembly 600 is that the third encapsulated semiconductor assembly 700 has a plurality of TAB attachments 702 forming an electrical communication between the facing surface 614 of the semiconductor chip bond pad 610 and the substrate bond pads 620 rather than the bond wires 616 of the second encapsulated semiconductor assembly 600.
  • FIG. 8 illustrates a fourth encapsulated semiconductor assembly 800 of the present invention. The fourth encapsulated semiconductor assembly 800 is similar to the second encapsulated semiconductor assembly 600; therefore, components common to FIGS. 6 and 8 retain the same numeric designation. The difference between the fourth encapsulated semiconductor assembly 800 and the second encapsulated semiconductor assembly 600 is that the fourth encapsulated semiconductor assembly 800 has a heat-dissipating glob top 802 which is disposed within the recess 628 and extends over the barrier glob top 626 to contact and adhere to the substrate 608.
  • FIG. 9 illustrates a multiple encapsulated semiconductor dice assembly 900 of the present invention. The multiple encapsulated semiconductor dice assembly 900 is similar to the fourth encapsulated semiconductor assembly 800; therefore, components common to FIGS. 8 and 9 retain the same numeric designation. The difference between the multiple encapsulated semiconductor dice assembly 900 and the fourth encapsulated semiconductor assembly 800 is that the multiple encapsulated semiconductor dice assembly 900 has multiple semiconductor dice 902 and 904 with a heat-dissipating glob top 802 which extends over the semiconductor dice 902 and 904 to contact and adhere to the substrate 608.
  • Having thus described in detail preferred embodiments of the present invention, it is to be understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description as many apparent variations thereof are possible without departing from the spirit or scope thereof.

Claims (38)

1. A semiconductor assembly having a substrate and a semiconductor chip having a first surface connected to the substrate and a second surface, the assembly comprising:
a barrier material located round the periphery of the second surface of the semiconductor chip substantially forming a wall having a portion contacting the substrate;
a recess formed by the wall about the periphery of the second surface of the semiconductor chip; and
a heat-dissipating material disposed within the recess having a second thermal conductivity different than the barrier material.
2. A semiconductor assembly of claim 1 wherein the barrier material adheres to a periphery of the second surface of the semiconductor chip substantially forming a wall, the barrier material substantially contacting a portion of the substrate, the barrier material having a first thermal conductivity and wherein the heat-dissipating material is disposed within the recess, the heat-dissipating material having a second thermal conductivity different than the first thermal conductivity of the barrier material.
3. The semiconductor assembly of claim 2, wherein the second thermal conductivity of the heat-dissipating material is greater than the first thermal conductivity of the barrier material.
4. The semiconductor assembly of claim 1, wherein the barrier material substantially encapsulates at least one bond wire forming a connection between the semiconductor chip and the substrate.
5. The semiconductor assembly of claim 2, wherein an electrical connection between the semiconductor chip and the substrate comprises at least one tape automated bond between at least one electrical contact point on the second surface of the semiconductor chip and a respective electrical contact point on the substrate.
6. The semiconductor assembly of claim 5, wherein the barrier material substantially encapsulates the at least one tape automated bond.
7. The semiconductor assembly of claim 2, wherein an electrical connection between the semiconductor chip and the substrate comprises at least one conductive bond between at least one electrical contact point on the second surface of the semiconductor chip and a respective electrical contact point on the substrate.
8. The semiconductor assembly of claim 7, further comprising an underfill encapsulant disposed between the semiconductor chip and the substrate.
9. An assembly method for a semiconductor assembly having a substrate and a semiconductor chip having a first surface and a second surface comprising:
attaching at least a portion of the first surface of the semiconductor chip to at least a portion of the substrate;
forming an electrical connection between the semiconductor chip and the substrate;
forming a wall substantially around a periphery of the second surface of the semiconductor chip using a barrier material, the wall around the periphery of the second surface of the semiconductor chip defining a recess, the barrier material having a first thermal conductivity;
extending the barrier material to contact the substrate; and
disposing a heat-dissipating material substantially within the recess, the heat-dissipating material having a second thermal conductivity different than the first thermal conductivity of the barrier material.
10. The method of claim 9, wherein the second thermal conductivity of the heat-dissipating material is greater than the first thermal conductivity of the barrier material.
11. The method of claim 9, wherein the electrical connection between the semiconductor chip and the substrate comprises attaching at least one bond wire between at least one electrical contact point on the second surface of the semiconductor chip and a respective electrical contact point on the substrate.
12. The method of claim 9, wherein the barrier material substantially encapsulates the at least one bond wire.
13. The method of claim 9, wherein the electrical connection between the semiconductor chip and the substrate comprises attaching at least one tape automated bond between at least one electrical contact point on the second surface of the semiconductor chip and a respective electrical contact point on the substrate.
14. The method of claim 13, wherein the barrier material substantially encapsulates the at least one tape automated bond.
15. The method of claim 9, wherein the electrical connection between the semiconductor chip and the substrate comprises attaching at least one conductive bond between at least one electrical contact point on the second surface of the semiconductor chip and a respective electrical contact point on the substrate.
16. The method of claim 15, further comprising disposing an underfill encapsulant substantially between the semiconductor chip and the substrate.
17. A semiconductor assembly having a semiconductor chip having a first surface and a second surface, the first surface attached to at least a portion of a substrate and electrically connected to a portion of the substrate comprising:
a barrier material adhered to a periphery of the second surface of the semiconductor chip substantially forming a wall, a portion of the wall extending beyond the semiconductor chip forming a recess located above the second surface of the semiconductor chip, the barrier material substantially extending to and contacting portions of the substrate, the barrier material having a first thermal conductivity; and
a heat-dissipating material disposed within the recess, the heat-dissipating material having a second thermal conductivity different than the first thermal conductivity of the barrier material.
18. The semiconductor assembly of claim 17, wherein the second thermal conductivity of the heat-dissipating material is greater than the first thermal conductivity of the barrier material.
19. The semiconductor assembly of claim 17, wherein the electrical connection between the semiconductor chip and the substrate comprises at least one bond wire between at least one electrical contact point on the second surface of the semiconductor chip and a respective electrical contact point on the substrate.
20. The semiconductor assembly of claim 17, wherein the barrier material substantially encapsulates the at least one bond wire.
21. The semiconductor assembly of claim 17, wherein the electrical connection between the semiconductor chip and the substrate comprises at least one tape automated bond between at least one electrical contact point on the second surface of the semiconductor chip and a respective electrical contact point on the substrate.
22. The semiconductor assembly of claim 21, wherein the barrier material substantially encapsulates the at least one tape automated bond.
23. The semiconductor assembly of claim 17, wherein the electrical connection between the semiconductor chip and the substrate comprises at least one conductive bond between at least one electrical contact point on the second surface of the semiconductor chip and a respective electrical contact point on the substrate.
24. The semiconductor assembly of claim 23, further comprising an underfill encapsulant substantially disposed between the semiconductor chip and the substrate.
25. A method of making a semiconductor assembly having a substrate and a plurality of semiconductor chips, each semiconductor chip of the plurality having a first surface and a second surface, comprising:
attaching a portion of the first surface of each semiconductor chip to a portion of the substrate;
disposing an underfill material substantially between the substrate and each semiconductor chip;
forming an electrical connection between each semiconductor chip and the substrate;
forming a wall substantially around a periphery of the second surface of each semiconductor chip using a barrier material, the wall and the second surface of each semiconductor chip defining a recess, the barrier material having a first thermal conductivity;
extending the barrier material to contact and adhere to the substrate; and
disposing a heat-dissipating material substantially within the recess, the heat-dissipating material having a second thermal conductivity different than the first thermal conductivity of the barrier material.
26. The method of claim 25, wherein the second thermal conductivity of the heat-dissipating material is greater than the first thermal conductivity of the barrier material.
27. The method of claim 25, wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one bond wire between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.
28. The method of claim 27, wherein the barrier material substantially encapsulates the at least one bond wire.
29. The method of claim 27, wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one tape automated bond between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.
30. The method of claim 29, wherein the barrier material substantially encapsulates the at least one tape automated bond.
31. The method of claim 25, wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one conductive bond between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.
32. A heat transfer method for a semiconductor assembly having a substrate and a plurality of semiconductor chips, each semiconductor chip of the plurality having a first surface and a second surface, comprising:
attaching a portion of the first surface of each semiconductor chip to a portion of the substrate;
disposing an underfill material substantially between the substrate and each semiconductor chip;
forming an electrical connection between each semiconductor chip and the substrate;
forming a wall substantially around a periphery of the second surface of each semiconductor chip using a barrier material, the wall and the second surface of each semiconductor chip defining a recess, the barrier material having a first thermal conductivity;
extending the barrier material to contact and adhere to the substrate; and
disposing a heat-dissipating material substantially within the recess, the heat-dissipating material having a second thermal conductivity different than the first thermal conductivity of the barrier material.
33. The method of claim 32, wherein the second thermal conductivity of the heat-dissipating material is greater than the first thermal conductivity of the barrier material.
34. The method of claim 32, wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one bond wire between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.
35. The method of claim 34, wherein the barrier material substantially encapsulates the at least one bond wire.
36. The method of claim 34, wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one tape automated bond between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.
37. The method of claim 36, wherein the barrier material substantially encapsulates the at least one tape automated bond.
38. The method of claim 32, wherein the electrical connection between each semiconductor chip and the substrate comprises attaching at least one conductive bond between at least one electrical contact point on the second surface of each semiconductor chip and a respective electrical contact point on the substrate.
US11/053,082 1996-05-24 2005-02-07 Packaged die on PCB with heat sink encapsulant and methods Abandoned US20050189646A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11/053,082 US20050189646A1 (en) 1996-05-24 2005-02-07 Packaged die on PCB with heat sink encapsulant and methods
US11/603,581 US20070069372A1 (en) 1996-05-24 2006-11-22 Packaged die on PCB with heat sink encapsulant and methods

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US08/653,030 US5866953A (en) 1996-05-24 1996-05-24 Packaged die on PCB with heat sink encapsulant
US09/189,102 US6252308B1 (en) 1996-05-24 1998-11-09 Packaged die PCB with heat sink encapsulant
US09/835,541 US6534858B2 (en) 1996-05-24 2001-04-16 Assembly and methods for packaged die on pcb with heat sink encapsulant
US10/232,782 US6617684B2 (en) 1996-05-24 2002-08-28 Packaged die on PCB with heat sink encapsulant
US10/639,349 US6853069B2 (en) 1996-05-24 2003-08-12 Packaged die on PCB with heat sink encapsulant and methods
US11/053,082 US20050189646A1 (en) 1996-05-24 2005-02-07 Packaged die on PCB with heat sink encapsulant and methods

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/639,349 Continuation US6853069B2 (en) 1996-05-24 2003-08-12 Packaged die on PCB with heat sink encapsulant and methods

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/603,581 Division US20070069372A1 (en) 1996-05-24 2006-11-22 Packaged die on PCB with heat sink encapsulant and methods

Publications (1)

Publication Number Publication Date
US20050189646A1 true US20050189646A1 (en) 2005-09-01

Family

ID=24619213

Family Applications (7)

Application Number Title Priority Date Filing Date
US08/653,030 Expired - Lifetime US5866953A (en) 1996-05-24 1996-05-24 Packaged die on PCB with heat sink encapsulant
US09/189,102 Expired - Lifetime US6252308B1 (en) 1996-05-24 1998-11-09 Packaged die PCB with heat sink encapsulant
US09/835,541 Expired - Lifetime US6534858B2 (en) 1996-05-24 2001-04-16 Assembly and methods for packaged die on pcb with heat sink encapsulant
US10/232,782 Expired - Lifetime US6617684B2 (en) 1996-05-24 2002-08-28 Packaged die on PCB with heat sink encapsulant
US10/639,349 Expired - Fee Related US6853069B2 (en) 1996-05-24 2003-08-12 Packaged die on PCB with heat sink encapsulant and methods
US11/053,082 Abandoned US20050189646A1 (en) 1996-05-24 2005-02-07 Packaged die on PCB with heat sink encapsulant and methods
US11/603,581 Abandoned US20070069372A1 (en) 1996-05-24 2006-11-22 Packaged die on PCB with heat sink encapsulant and methods

Family Applications Before (5)

Application Number Title Priority Date Filing Date
US08/653,030 Expired - Lifetime US5866953A (en) 1996-05-24 1996-05-24 Packaged die on PCB with heat sink encapsulant
US09/189,102 Expired - Lifetime US6252308B1 (en) 1996-05-24 1998-11-09 Packaged die PCB with heat sink encapsulant
US09/835,541 Expired - Lifetime US6534858B2 (en) 1996-05-24 2001-04-16 Assembly and methods for packaged die on pcb with heat sink encapsulant
US10/232,782 Expired - Lifetime US6617684B2 (en) 1996-05-24 2002-08-28 Packaged die on PCB with heat sink encapsulant
US10/639,349 Expired - Fee Related US6853069B2 (en) 1996-05-24 2003-08-12 Packaged die on PCB with heat sink encapsulant and methods

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/603,581 Abandoned US20070069372A1 (en) 1996-05-24 2006-11-22 Packaged die on PCB with heat sink encapsulant and methods

Country Status (1)

Country Link
US (7) US5866953A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050026414A1 (en) * 2000-02-24 2005-02-03 Williams Vernon M. Methods for consolidating previously unconsolidated conductive material to form conductive structures or contact pads or secure conductive structures to contact pads
US20100118482A1 (en) * 2008-11-13 2010-05-13 Mosaid Technologies Incorporated System including a plurality of encapsulated semiconductor chips
EP2466655A1 (en) * 2010-12-14 2012-06-20 Liang Meng Plastic Share Co. Ltd. LED package structure and manufacturing method for the same
US9933577B2 (en) 2016-03-11 2018-04-03 Globalfoundries Inc. Photonics chip
US20180358238A1 (en) * 2017-06-09 2018-12-13 Advanced Semiconductor Engineering, Inc. Semiconductor device package having an underfill barrier

Families Citing this family (176)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6097089A (en) * 1998-01-28 2000-08-01 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package
US6821821B2 (en) * 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
US5866953A (en) * 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
JP3834335B2 (en) * 1996-08-08 2006-10-18 セイコーエプソン株式会社 Resin coating method for semiconductor element and liquid crystal display device
US6962829B2 (en) * 1996-10-31 2005-11-08 Amkor Technology, Inc. Method of making near chip size integrated circuit package
KR100246333B1 (en) * 1997-03-14 2000-03-15 김영환 Ball grid array package and method for manufacturing thereof
JPH10335383A (en) 1997-05-28 1998-12-18 Matsushita Electric Ind Co Ltd Producing method for semiconductor device
US5962810A (en) * 1997-09-09 1999-10-05 Amkor Technology, Inc. Integrated circuit package employing a transparent encapsulant
US6204564B1 (en) * 1997-11-21 2001-03-20 Rohm Co., Ltd. Semiconductor device and method for making the same
US7233056B1 (en) * 1998-02-23 2007-06-19 Micron Technology, Inc. Chip scale package with heat spreader
US6297960B1 (en) 1998-06-30 2001-10-02 Micron Technology, Inc. Heat sink with alignment and retaining features
US6297548B1 (en) 1998-06-30 2001-10-02 Micron Technology, Inc. Stackable ceramic FBGA for high thermal applications
US6092281A (en) 1998-08-28 2000-07-25 Amkor Technology, Inc. Electromagnetic interference shield driver and method
US6117797A (en) * 1998-09-03 2000-09-12 Micron Technology, Inc. Attachment method for heat sinks and devices involving removal of misplaced encapsulant
US6184465B1 (en) * 1998-11-12 2001-02-06 Micron Technology, Inc. Semiconductor package
US6507101B1 (en) * 1999-03-26 2003-01-14 Hewlett-Packard Company Lossy RF shield for integrated circuits
US6211574B1 (en) * 1999-04-16 2001-04-03 Advanced Semiconductor Engineering Inc. Semiconductor package with wire protection and method therefor
JP2000306948A (en) * 1999-04-21 2000-11-02 Rohm Co Ltd Semiconductor device and manufacture thereof
SE514076C2 (en) 1999-04-23 2000-12-18 Ericsson Telefon Ab L M Method and apparatus related to microwave lens
US6048656A (en) * 1999-05-11 2000-04-11 Micron Technology, Inc. Void-free underfill of surface mounted chips
US6274927B1 (en) 1999-06-03 2001-08-14 Amkor Technology, Inc. Plastic package for an optical integrated circuit device and method of making
US6359334B1 (en) 1999-06-08 2002-03-19 Micron Technology, Inc. Thermally conductive adhesive tape for semiconductor devices and method using the same
ATE315886T1 (en) * 1999-07-08 2006-02-15 Sunstar Engineering Inc BACKING MATERIAL FOR SEMICONDUCTOR HOUSINGS
US6122171A (en) 1999-07-30 2000-09-19 Micron Technology, Inc. Heat sink chip package and method of making
US6709968B1 (en) 2000-08-16 2004-03-23 Micron Technology, Inc. Microelectronic device with package with conductive elements and associated method of manufacture
US6670719B2 (en) 1999-08-25 2003-12-30 Micron Technology, Inc. Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture
US6448635B1 (en) 1999-08-30 2002-09-10 Amkor Technology, Inc. Surface acoustical wave flip chip
KR20010054743A (en) * 1999-12-08 2001-07-02 윤종용 Semiconductor package comprising double underfill area
US6700209B1 (en) * 1999-12-29 2004-03-02 Intel Corporation Partial underfill for flip-chip electronic packages
US6949822B2 (en) * 2000-03-17 2005-09-27 International Rectifier Corporation Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance
CN1211723C (en) * 2000-04-04 2005-07-20 胜开科技股份有限公司 Computer card and its making method
US6558600B1 (en) 2000-05-04 2003-05-06 Micron Technology, Inc. Method for packaging microelectronic substrates
US6611053B2 (en) * 2000-06-08 2003-08-26 Micron Technology, Inc. Protective structure for bond wires
US6589820B1 (en) 2000-06-16 2003-07-08 Micron Technology, Inc. Method and apparatus for packaging a microelectronic die
US6576494B1 (en) 2000-06-28 2003-06-10 Micron Technology, Inc. Recessed encapsulated microelectronic devices and methods for formation
US7273769B1 (en) * 2000-08-16 2007-09-25 Micron Technology, Inc. Method and apparatus for removing encapsulating material from a packaged microelectronic device
US6483044B1 (en) * 2000-08-23 2002-11-19 Micron Technology, Inc. Interconnecting substrates for electrical coupling of microelectronic components
US6979595B1 (en) * 2000-08-24 2005-12-27 Micron Technology, Inc. Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices
US6838760B1 (en) * 2000-08-28 2005-01-04 Micron Technology, Inc. Packaged microelectronic devices with interconnecting units
US6576495B1 (en) 2000-08-30 2003-06-10 Micron Technology, Inc. Microelectronic assembly with pre-disposed fill material and associated method of manufacture
US6787388B1 (en) * 2000-09-07 2004-09-07 Stmicroelectronics, Inc. Surface mount package with integral electro-static charge dissipating ring using lead frame as ESD device
TW469609B (en) * 2000-10-11 2001-12-21 Ultratera Corp Chipless package semiconductor device and its manufacturing method
US6564447B1 (en) * 2000-11-15 2003-05-20 National Semiconductor Corporation Non lead frame clamping for matrix leadless leadframe package molding
US6545869B2 (en) 2001-01-17 2003-04-08 International Business Machines Corporation Adjusting fillet geometry to couple a heat spreader to a chip carrier
JP4626919B2 (en) * 2001-03-27 2011-02-09 ルネサスエレクトロニクス株式会社 Semiconductor device
US7115986B2 (en) * 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US6444501B1 (en) * 2001-06-12 2002-09-03 Micron Technology, Inc. Two stage transfer molding method to encapsulate MMC module
DE10137666A1 (en) * 2001-08-01 2003-02-27 Infineon Technologies Ag Protection device for assemblies and process for their manufacture
SG122743A1 (en) * 2001-08-21 2006-06-29 Micron Technology Inc Microelectronic devices and methods of manufacture
SG111919A1 (en) * 2001-08-29 2005-06-29 Micron Technology Inc Packaged microelectronic devices and methods of forming same
US6861720B1 (en) 2001-08-29 2005-03-01 Amkor Technology, Inc. Placement template and method for placing optical dies
SG104293A1 (en) * 2002-01-09 2004-06-21 Micron Technology Inc Elimination of rdl using tape base flip chip on flex for die stacking
US6784534B1 (en) 2002-02-06 2004-08-31 Amkor Technology, Inc. Thin integrated circuit package having an optically transparent window
US6622380B1 (en) 2002-02-12 2003-09-23 Micron Technology, Inc. Methods for manufacturing microelectronic devices and methods for mounting microelectronic packages to circuit boards
US7238550B2 (en) * 2002-02-26 2007-07-03 Tandon Group Ltd. Methods and apparatus for fabricating Chip-on-Board modules
SG111935A1 (en) * 2002-03-04 2005-06-29 Micron Technology Inc Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods
SG115455A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Methods for assembly and packaging of flip chip configured dice with interposer
SG115456A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
SG115459A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Flip chip packaging using recessed interposer terminals
US6975035B2 (en) * 2002-03-04 2005-12-13 Micron Technology, Inc. Method and apparatus for dielectric filling of flip chip on interposer assembly
SG121707A1 (en) * 2002-03-04 2006-05-26 Micron Technology Inc Method and apparatus for flip-chip packaging providing testing capability
US6745462B2 (en) 2002-03-07 2004-06-08 Kulicke & Soffa Industries, Inc. Method and apparatus for reducing deformation of encapsulant in semiconductor device encapsulation by stencil printing
US6844618B2 (en) * 2002-04-04 2005-01-18 Micron Technology, Inc. Microelectronic package with reduced underfill and methods for forming such packages
US7109588B2 (en) * 2002-04-04 2006-09-19 Micron Technology, Inc. Method and apparatus for attaching microelectronic substrates and support members
US6534859B1 (en) * 2002-04-05 2003-03-18 St. Assembly Test Services Ltd. Semiconductor package having heat sink attached to pre-molded cavities and method for creating the package
EP1365450A1 (en) * 2002-05-24 2003-11-26 Ultratera Corporation An improved wire-bonded chip on board package
US6673649B1 (en) * 2002-07-05 2004-01-06 Micron Technology, Inc. Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages
US6987032B1 (en) 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
US6979594B1 (en) 2002-07-19 2005-12-27 Asat Ltd. Process for manufacturing ball grid array package
US6800948B1 (en) * 2002-07-19 2004-10-05 Asat Ltd. Ball grid array package
SG120879A1 (en) * 2002-08-08 2006-04-26 Micron Technology Inc Packaged microelectronic components
SG127684A1 (en) * 2002-08-19 2006-12-29 Micron Technology Inc Packaged microelectronic component assemblies
US20040036170A1 (en) * 2002-08-20 2004-02-26 Lee Teck Kheng Double bumping of flexible substrate for first and second level interconnects
SG114585A1 (en) * 2002-11-22 2005-09-28 Micron Technology Inc Packaged microelectronic component assemblies
JP3793143B2 (en) * 2002-11-28 2006-07-05 株式会社シマノ Bicycle electronic control device
US7199459B2 (en) * 2003-01-22 2007-04-03 Siliconware Precision Industries Co., Ltd. Semiconductor package without bonding wires and fabrication method thereof
JP4390541B2 (en) * 2003-02-03 2009-12-24 Necエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US6768209B1 (en) * 2003-02-03 2004-07-27 Micron Technology, Inc. Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of underfilling microelectronic devices
US6879050B2 (en) * 2003-02-11 2005-04-12 Micron Technology, Inc. Packaged microelectronic devices and methods for packaging microelectronic devices
SG143931A1 (en) 2003-03-04 2008-07-29 Micron Technology Inc Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths
US6921860B2 (en) 2003-03-18 2005-07-26 Micron Technology, Inc. Microelectronic component assemblies having exposed contacts
JP3947525B2 (en) * 2003-04-16 2007-07-25 沖電気工業株式会社 Semiconductor device heat dissipation structure
US7332797B2 (en) * 2003-06-30 2008-02-19 Intel Corporation Wire-bonded package with electrically insulating wire encapsulant and thermally conductive overmold
US7180169B2 (en) * 2003-08-28 2007-02-20 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for manufacturing the same
US7368810B2 (en) 2003-08-29 2008-05-06 Micron Technology, Inc. Invertible microfeature device packages
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US6888719B1 (en) * 2003-10-16 2005-05-03 Micron Technology, Inc. Methods and apparatuses for transferring heat from microelectronic device modules
TWI228304B (en) * 2003-10-29 2005-02-21 Advanced Semiconductor Eng Method for manufacturing ball grid package
SG153627A1 (en) 2003-10-31 2009-07-29 Micron Technology Inc Reduced footprint packaged microelectronic components and methods for manufacturing such microelectronic components
TWI238499B (en) * 2003-11-03 2005-08-21 Siliconware Precision Industries Co Ltd Semiconductor package
US7154185B2 (en) * 2003-11-20 2006-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Encapsulation method for SBGA
US20050110168A1 (en) * 2003-11-20 2005-05-26 Texas Instruments Incorporated Low coefficient of thermal expansion (CTE) semiconductor packaging materials
US7081669B2 (en) * 2003-12-04 2006-07-25 Intel Corporation Device and system for heat spreader with controlled thermal expansion
US7153725B2 (en) * 2004-01-27 2006-12-26 St Assembly Test Services Ltd. Strip-fabricated flip chip in package and flip chip in system heat spreader assemblies and fabrication methods therefor
JP2005311321A (en) * 2004-03-22 2005-11-04 Sharp Corp Semiconductor device and its manufacturing method, and liquid crystal module/semiconductor module provided with the semiconductor device
US20050247039A1 (en) * 2004-05-04 2005-11-10 Textron Inc. Disposable magnetic bedknife
DE102004027074B4 (en) * 2004-06-02 2009-06-04 Infineon Technologies Ag Method for producing a BGA (Ball Grid Array) component with a thin metallic cooling foil
US7411289B1 (en) 2004-06-14 2008-08-12 Asat Ltd. Integrated circuit package with partially exposed contact pads and process for fabricating the same
US7091581B1 (en) 2004-06-14 2006-08-15 Asat Limited Integrated circuit package and process for fabricating the same
SG145547A1 (en) * 2004-07-23 2008-09-29 Micron Technology Inc Microelectronic component assemblies with recessed wire bonds and methods of making same
US7602618B2 (en) 2004-08-25 2009-10-13 Micron Technology, Inc. Methods and apparatuses for transferring heat from stacked microfeature devices
US7157310B2 (en) * 2004-09-01 2007-01-02 Micron Technology, Inc. Methods for packaging microfeature devices and microfeature devices formed by such methods
US20060103008A1 (en) * 2004-11-15 2006-05-18 Stats Chippac Ltd. Hyper thermally enhanced semiconductor package system
US8164182B2 (en) * 2004-11-15 2012-04-24 Stats Chippac Ltd. Hyper thermally enhanced semiconductor package system comprising heat slugs on opposite surfaces of a semiconductor chip
US20060162850A1 (en) * 2005-01-24 2006-07-27 Micron Technology, Inc. Methods and apparatus for releasably attaching microfeature workpieces to support members
US7968371B2 (en) * 2005-02-01 2011-06-28 Stats Chippac Ltd. Semiconductor package system with cavity substrate
US8278751B2 (en) * 2005-02-08 2012-10-02 Micron Technology, Inc. Methods of adhering microfeature workpieces, including a chip, to a support member
TWI254422B (en) * 2005-02-17 2006-05-01 Advanced Semiconductor Eng Chip package and producing method thereof
US8610262B1 (en) 2005-02-18 2013-12-17 Utac Hong Kong Limited Ball grid array package with improved thermal characteristics
DE102005014674B4 (en) * 2005-03-29 2010-02-11 Infineon Technologies Ag Semiconductor module with semiconductor chips in a plastic housing in separate areas and method for producing the same
US20060261498A1 (en) * 2005-05-17 2006-11-23 Micron Technology, Inc. Methods and apparatuses for encapsulating microelectronic devices
DE102005023949B4 (en) * 2005-05-20 2019-07-18 Infineon Technologies Ag A method of manufacturing a composite panel with semiconductor chips and a plastic package and a method of manufacturing semiconductor components by means of a benefit
US7573125B2 (en) * 2005-06-14 2009-08-11 Micron Technology, Inc. Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods
US7169248B1 (en) * 2005-07-19 2007-01-30 Micron Technology, Inc. Methods for releasably attaching support members to microfeature workpieces and microfeature assemblies formed using such methods
WO2007012992A1 (en) * 2005-07-28 2007-02-01 Nxp B.V. A package and manufacturing method for a microelectronic component
US7807505B2 (en) * 2005-08-30 2010-10-05 Micron Technology, Inc. Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods
US7745944B2 (en) * 2005-08-31 2010-06-29 Micron Technology, Inc. Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts
US20070148820A1 (en) * 2005-12-22 2007-06-28 Micron Technology, Inc. Microelectronic devices and methods for manufacturing microelectronic devices
SG133445A1 (en) 2005-12-29 2007-07-30 Micron Technology Inc Methods for packaging microelectronic devices and microelectronic devices formed using such methods
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
DE102006007303A1 (en) * 2006-02-16 2007-08-30 Infineon Technologies Ag Printed circuit board, has grouting cover element, in which multiple chips connected electrically with printed circuit board, are embedded
US7749349B2 (en) 2006-03-14 2010-07-06 Micron Technology, Inc. Methods and systems for releasably attaching support members to microfeature workpieces
SG172743A1 (en) * 2006-03-29 2011-07-28 Micron Technology Inc Packaged microelectronic devices recessed in support member cavities, and associated methods
US7985623B2 (en) 2006-04-14 2011-07-26 Stats Chippac Ltd. Integrated circuit package system with contoured encapsulation
US7910385B2 (en) * 2006-05-12 2011-03-22 Micron Technology, Inc. Method of fabricating microelectronic devices
JP5481769B2 (en) * 2006-11-22 2014-04-23 日亜化学工業株式会社 Semiconductor device and manufacturing method thereof
US7833456B2 (en) * 2007-02-23 2010-11-16 Micron Technology, Inc. Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece
US7750449B2 (en) 2007-03-13 2010-07-06 Micron Technology, Inc. Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components
US7955898B2 (en) 2007-03-13 2011-06-07 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
JP5075463B2 (en) * 2007-04-19 2012-11-21 ルネサスエレクトロニクス株式会社 Semiconductor device
US7687895B2 (en) * 2007-04-30 2010-03-30 Infineon Technologies Ag Workpiece with semiconductor chips and molding, semiconductor device and method for producing a workpiece with semiconductors chips
DE102007020656B4 (en) 2007-04-30 2009-05-07 Infineon Technologies Ag Semiconductor chip workpiece, semiconductor device, and method of manufacturing a semiconductor chip workpiece
US7714426B1 (en) 2007-07-07 2010-05-11 Keith Gann Ball grid array package format layers and structure
US20090079097A1 (en) * 2007-09-25 2009-03-26 Silverbrook Research Pty Ltd Electronic component with wire bonds in low modulus fill encapsulant
US20090127700A1 (en) * 2007-11-20 2009-05-21 Matthew Romig Thermal conductor lids for area array packaged multi-chip modules and methods to dissipate heat from multi-chip modules
US8084849B2 (en) * 2007-12-12 2011-12-27 Stats Chippac Ltd. Integrated circuit package system with offset stacking
US7985628B2 (en) * 2007-12-12 2011-07-26 Stats Chippac Ltd. Integrated circuit package system with interconnect lock
US7781261B2 (en) * 2007-12-12 2010-08-24 Stats Chippac Ltd. Integrated circuit package system with offset stacking and anti-flash structure
US8536692B2 (en) * 2007-12-12 2013-09-17 Stats Chippac Ltd. Mountable integrated circuit package system with mountable integrated circuit die
US8659154B2 (en) 2008-03-14 2014-02-25 Infineon Technologies Ag Semiconductor device including adhesive covered element
US20090243069A1 (en) * 2008-03-26 2009-10-01 Zigmund Ramirez Camacho Integrated circuit package system with redistribution
SG142321A1 (en) 2008-04-24 2009-11-26 Micron Technology Inc Pre-encapsulated cavity interposer
US9293385B2 (en) * 2008-07-30 2016-03-22 Stats Chippac Ltd. RDL patterning with package on package system
JP4560113B2 (en) * 2008-09-30 2010-10-13 株式会社東芝 Printed circuit board and electronic device provided with printed circuit board
CN102105971B (en) 2009-04-24 2013-05-22 松下电器产业株式会社 Method for mounting semiconductor package component, and structure having semiconductor package component mounted therein
JP5062283B2 (en) 2009-04-30 2012-10-31 日亜化学工業株式会社 Semiconductor device and manufacturing method thereof
JP4676012B2 (en) * 2009-06-03 2011-04-27 株式会社東芝 Electronics
US9230874B1 (en) * 2009-07-13 2016-01-05 Altera Corporation Integrated circuit package with a heat conductor
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
JP2012009713A (en) * 2010-06-25 2012-01-12 Shinko Electric Ind Co Ltd Semiconductor package and method of manufacturing the same
JP2012015225A (en) * 2010-06-30 2012-01-19 Hitachi Ltd Semiconductor device
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
KR20130026062A (en) * 2011-09-05 2013-03-13 삼성전자주식회사 Printed circuit board assembly manufacturing method for the same
US9093416B2 (en) * 2011-11-28 2015-07-28 Infineon Technologies Ag Chip-package and a method for forming a chip-package
US20130242538A1 (en) * 2012-03-13 2013-09-19 Shenzhen China Star Optoelectronics Technology Co Ltd. Led light bar and backlight module
US9257368B2 (en) 2012-05-14 2016-02-09 Intel Corporation Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias
DE112012006469B4 (en) 2012-06-08 2022-05-05 Intel Corporation Microelectronic package with non-coplanar encapsulated microelectronic devices and a bumpless build-up layer
JP2014013836A (en) * 2012-07-04 2014-01-23 Ps4 Luxco S A R L Semiconductor device
KR101506130B1 (en) * 2012-09-06 2015-03-26 시그네틱스 주식회사 PBGA package having a reinforcement resin
WO2014037978A1 (en) * 2012-09-06 2014-03-13 パナソニック株式会社 Mounting structure and method for supplying reinforcing resin material
US9847317B2 (en) * 2014-07-08 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and packaged semiconductor devices
US9165794B1 (en) * 2014-07-31 2015-10-20 Himax Display, Inc. Partial glob-top encapsulation technique
TWI594341B (en) * 2015-01-19 2017-08-01 神盾股份有限公司 Fingerprint sensor package and method for fabricating the same
DE102015120109B4 (en) * 2015-11-19 2018-03-01 Danfoss Silicon Power Gmbh Power semiconductor module with a power semiconductor covering Glob-top potting compound
JP2018098487A (en) * 2016-12-14 2018-06-21 株式会社村田製作所 Semiconductor module
US10279610B2 (en) 2016-12-20 2019-05-07 Xerox Corporation Cooling insert
EP3340293A1 (en) * 2016-12-20 2018-06-27 Siemens Aktiengesellschaft Semiconductor module with support structure on the bottom
KR102639555B1 (en) * 2017-01-13 2024-02-23 삼성전자주식회사 EMI shielding structure having heat dissipation unit and manufacturing method the same
US10211072B2 (en) * 2017-06-23 2019-02-19 Applied Materials, Inc. Method of reconstituted substrate formation for advanced packaging applications
US11152274B2 (en) * 2017-09-11 2021-10-19 Advanced Semiconductor Engineering, Inc. Multi-moldings fan-out package and process
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10879195B2 (en) * 2018-02-15 2020-12-29 Micron Technology, Inc. Method for substrate moisture NCF voiding elimination
KR102633142B1 (en) 2019-08-26 2024-02-02 삼성전자주식회사 Semiconductor package
KR20220003342A (en) * 2020-07-01 2022-01-10 삼성전기주식회사 Electronic component pagkage and manufacturing method thereof
KR20220018645A (en) * 2020-08-07 2022-02-15 삼성전기주식회사 Electronic device module

Citations (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4143456A (en) * 1976-06-28 1979-03-13 Citizen Watch Commpany Ltd. Semiconductor device insulation method
US4264917A (en) * 1978-10-19 1981-04-28 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull Flat package for integrated circuit devices
US4300153A (en) * 1977-09-22 1981-11-10 Sharp Kabushiki Kaisha Flat shaped semiconductor encapsulation
US4323914A (en) * 1979-02-01 1982-04-06 International Business Machines Corporation Heat transfer structure for integrated circuit package
US4358552A (en) * 1981-09-10 1982-11-09 Morton-Norwich Products, Inc. Epoxy resinous molding compositions having low coefficient of thermal expansion and high thermal conductivity
US4507675A (en) * 1981-03-05 1985-03-26 Matsushita Electronics Corporation Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor
US4642671A (en) * 1982-07-29 1987-02-10 Lucas Industries Public Limited Company Semi-conductor assembly
US4801998A (en) * 1984-08-20 1989-01-31 Oki Electric Industry Co., Ltd. EPROM device
US4931852A (en) * 1986-06-13 1990-06-05 Advanced Micro Devices, Inc. High thermal conductivity/low alpha emission molding compound containing high purity semiconductor filler and integrated circuit package
US4961107A (en) * 1989-04-03 1990-10-02 Motorola Inc. Electrically isolated heatsink for single-in-line package
US5051275A (en) * 1989-11-09 1991-09-24 At&T Bell Laboratories Silicone resin electronic device encapsulant
US5101465A (en) * 1990-08-07 1992-03-31 At&T Bell Laboratories Leadframe-based optical assembly
US5144747A (en) * 1991-03-27 1992-09-08 Integrated System Assemblies Corporation Apparatus and method for positioning an integrated circuit chip within a multichip module
US5173764A (en) * 1991-04-08 1992-12-22 Motorola, Inc. Semiconductor device having a particular lid means and encapsulant to reduce die stress
US5194930A (en) * 1991-09-16 1993-03-16 International Business Machines Dielectric composition and solder interconnection structure for its use
US5216278A (en) * 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
US5300459A (en) * 1989-12-28 1994-04-05 Sanken Electric Co., Ltd. Method for reducing thermal stress in an encapsulated integrated circuit package
US5311060A (en) * 1989-12-19 1994-05-10 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5371404A (en) * 1993-02-04 1994-12-06 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
US5379186A (en) * 1993-07-06 1995-01-03 Motorola, Inc. Encapsulated electronic component having a heat diffusing layer
US5394303A (en) * 1992-09-11 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor device
US5434105A (en) * 1994-03-04 1995-07-18 National Semiconductor Corporation Process for attaching a lead frame to a heat sink using a glob-top encapsulation
US5436203A (en) * 1994-07-05 1995-07-25 Motorola, Inc. Shielded liquid encapsulated semiconductor device and method for making the same
US5438216A (en) * 1992-08-31 1995-08-01 Motorola, Inc. Light erasable multichip module
US5450283A (en) * 1992-11-03 1995-09-12 Motorola, Inc. Thermally enhanced semiconductor device having exposed backside and method for making the same
US5488254A (en) * 1991-08-05 1996-01-30 Hitachi, Ltd. Plastic-molded-type semiconductor device
US5489801A (en) * 1993-11-03 1996-02-06 Intel Corporation Quad flat package heat slug composition
US5489538A (en) * 1992-08-21 1996-02-06 Lsi Logic Corporation Method of die burn-in
US5552635A (en) * 1994-01-11 1996-09-03 Samsung Electronics Co., Ltd. High thermal emissive semiconductor device package
US5610442A (en) * 1995-03-27 1997-03-11 Lsi Logic Corporation Semiconductor device package fabrication method and apparatus
US5641997A (en) * 1993-09-14 1997-06-24 Kabushiki Kaisha Toshiba Plastic-encapsulated semiconductor device
US5656857A (en) * 1994-05-12 1997-08-12 Kabushiki Kaisha Toshiba Semiconductor device with insulating resin layer and substrate having low sheet resistance
US5659952A (en) * 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5726079A (en) * 1996-06-19 1998-03-10 International Business Machines Corporation Thermally enhanced flip chip package and method of forming
US5744863A (en) * 1994-07-11 1998-04-28 International Business Machines Corporation Chip carrier modules with heat sinks attached by flexible-epoxy
US5863810A (en) * 1994-05-09 1999-01-26 Euratec B.V. Method for encapsulating an integrated circuit having a window
US5866953A (en) * 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1143456A (en) * 1912-10-05 1915-06-15 Harry E Sheldon Cast-metal railroad cross-tie.
JPS5277684A (en) * 1975-12-24 1977-06-30 Seiko Epson Corp Exeternal wiring of integrated circuit
JPS6094744A (en) * 1983-10-27 1985-05-27 Nippon Denso Co Ltd Hybrid ic device
JPS60178651A (en) * 1984-02-24 1985-09-12 Nec Corp Semiconductor device
JPH04157758A (en) * 1990-10-19 1992-05-29 Mitsubishi Electric Corp Printed circuit board

Patent Citations (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4143456A (en) * 1976-06-28 1979-03-13 Citizen Watch Commpany Ltd. Semiconductor device insulation method
US4300153A (en) * 1977-09-22 1981-11-10 Sharp Kabushiki Kaisha Flat shaped semiconductor encapsulation
US4264917A (en) * 1978-10-19 1981-04-28 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull Flat package for integrated circuit devices
US4323914A (en) * 1979-02-01 1982-04-06 International Business Machines Corporation Heat transfer structure for integrated circuit package
US4507675A (en) * 1981-03-05 1985-03-26 Matsushita Electronics Corporation Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor
US4358552A (en) * 1981-09-10 1982-11-09 Morton-Norwich Products, Inc. Epoxy resinous molding compositions having low coefficient of thermal expansion and high thermal conductivity
US4642671A (en) * 1982-07-29 1987-02-10 Lucas Industries Public Limited Company Semi-conductor assembly
US4801998A (en) * 1984-08-20 1989-01-31 Oki Electric Industry Co., Ltd. EPROM device
US4931852A (en) * 1986-06-13 1990-06-05 Advanced Micro Devices, Inc. High thermal conductivity/low alpha emission molding compound containing high purity semiconductor filler and integrated circuit package
US4961107A (en) * 1989-04-03 1990-10-02 Motorola Inc. Electrically isolated heatsink for single-in-line package
US5051275A (en) * 1989-11-09 1991-09-24 At&T Bell Laboratories Silicone resin electronic device encapsulant
US5311060A (en) * 1989-12-19 1994-05-10 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5300459A (en) * 1989-12-28 1994-04-05 Sanken Electric Co., Ltd. Method for reducing thermal stress in an encapsulated integrated circuit package
US5101465A (en) * 1990-08-07 1992-03-31 At&T Bell Laboratories Leadframe-based optical assembly
US5216278A (en) * 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
US5144747A (en) * 1991-03-27 1992-09-08 Integrated System Assemblies Corporation Apparatus and method for positioning an integrated circuit chip within a multichip module
US5173764A (en) * 1991-04-08 1992-12-22 Motorola, Inc. Semiconductor device having a particular lid means and encapsulant to reduce die stress
US5488254A (en) * 1991-08-05 1996-01-30 Hitachi, Ltd. Plastic-molded-type semiconductor device
US5194930A (en) * 1991-09-16 1993-03-16 International Business Machines Dielectric composition and solder interconnection structure for its use
US5489538A (en) * 1992-08-21 1996-02-06 Lsi Logic Corporation Method of die burn-in
US5438216A (en) * 1992-08-31 1995-08-01 Motorola, Inc. Light erasable multichip module
US5394303A (en) * 1992-09-11 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor device
US5450283A (en) * 1992-11-03 1995-09-12 Motorola, Inc. Thermally enhanced semiconductor device having exposed backside and method for making the same
US5371404A (en) * 1993-02-04 1994-12-06 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
US5379186A (en) * 1993-07-06 1995-01-03 Motorola, Inc. Encapsulated electronic component having a heat diffusing layer
US5641997A (en) * 1993-09-14 1997-06-24 Kabushiki Kaisha Toshiba Plastic-encapsulated semiconductor device
US5489801A (en) * 1993-11-03 1996-02-06 Intel Corporation Quad flat package heat slug composition
US5552635A (en) * 1994-01-11 1996-09-03 Samsung Electronics Co., Ltd. High thermal emissive semiconductor device package
US5434105A (en) * 1994-03-04 1995-07-18 National Semiconductor Corporation Process for attaching a lead frame to a heat sink using a glob-top encapsulation
US5863810A (en) * 1994-05-09 1999-01-26 Euratec B.V. Method for encapsulating an integrated circuit having a window
US5656857A (en) * 1994-05-12 1997-08-12 Kabushiki Kaisha Toshiba Semiconductor device with insulating resin layer and substrate having low sheet resistance
US5436203A (en) * 1994-07-05 1995-07-25 Motorola, Inc. Shielded liquid encapsulated semiconductor device and method for making the same
US5744863A (en) * 1994-07-11 1998-04-28 International Business Machines Corporation Chip carrier modules with heat sinks attached by flexible-epoxy
US5659952A (en) * 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5610442A (en) * 1995-03-27 1997-03-11 Lsi Logic Corporation Semiconductor device package fabrication method and apparatus
US5866953A (en) * 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
US6252308B1 (en) * 1996-05-24 2001-06-26 Micron Technology, Inc. Packaged die PCB with heat sink encapsulant
US6534858B2 (en) * 1996-05-24 2003-03-18 Micron Technology, Inc. Assembly and methods for packaged die on pcb with heat sink encapsulant
US6853069B2 (en) * 1996-05-24 2005-02-08 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant and methods
US5726079A (en) * 1996-06-19 1998-03-10 International Business Machines Corporation Thermally enhanced flip chip package and method of forming

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050026414A1 (en) * 2000-02-24 2005-02-03 Williams Vernon M. Methods for consolidating previously unconsolidated conductive material to form conductive structures or contact pads or secure conductive structures to contact pads
US20050221531A1 (en) * 2000-02-24 2005-10-06 Williams Vernon M Carrier substrates and conductive elements thereof
US20050230806A1 (en) * 2000-02-24 2005-10-20 Williams Vernon M Conductive elements with adjacent, mutually adhered regions and semiconductor device assemblies including such conductive elements
US20050230843A1 (en) * 2000-02-24 2005-10-20 Williams Vernon M Flip-chip type semiconductor devices and conductive elements thereof
US7273802B2 (en) 2000-02-24 2007-09-25 Micron Technology, Inc. Methods for consolidating previously unconsolidated conductive material to form conductive structures or contact pads or secure conductive structures to contact pads
US8908378B2 (en) * 2008-11-13 2014-12-09 Conversant Intellectual Property Management Inc. System including a plurality of encapsulated semiconductor chips
US8472199B2 (en) * 2008-11-13 2013-06-25 Mosaid Technologies Incorporated System including a plurality of encapsulated semiconductor chips
US20130271910A1 (en) * 2008-11-13 2013-10-17 Mosaid Technologies Incorporated System including a plurality of encapsulated semiconductor chips
US20100118482A1 (en) * 2008-11-13 2010-05-13 Mosaid Technologies Incorporated System including a plurality of encapsulated semiconductor chips
EP2466655A1 (en) * 2010-12-14 2012-06-20 Liang Meng Plastic Share Co. Ltd. LED package structure and manufacturing method for the same
US9933577B2 (en) 2016-03-11 2018-04-03 Globalfoundries Inc. Photonics chip
US10409006B2 (en) 2016-03-11 2019-09-10 Globalfoundries Inc. Photonics chip
US20180358238A1 (en) * 2017-06-09 2018-12-13 Advanced Semiconductor Engineering, Inc. Semiconductor device package having an underfill barrier
US10217649B2 (en) * 2017-06-09 2019-02-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package having an underfill barrier

Also Published As

Publication number Publication date
US6853069B2 (en) 2005-02-08
US6617684B2 (en) 2003-09-09
US20010015492A1 (en) 2001-08-23
US6252308B1 (en) 2001-06-26
US5866953A (en) 1999-02-02
US20020195699A1 (en) 2002-12-26
US20070069372A1 (en) 2007-03-29
US6534858B2 (en) 2003-03-18
US20040036160A1 (en) 2004-02-26

Similar Documents

Publication Publication Date Title
US6853069B2 (en) Packaged die on PCB with heat sink encapsulant and methods
US6661103B2 (en) Apparatus for packaging flip chip bare die on printed circuit boards
US5734201A (en) Low profile semiconductor device with like-sized chip and mounting substrate
US6507107B2 (en) Semiconductor/printed circuit board assembly
US6239366B1 (en) Face-to-face multi-chip package
US5710459A (en) Integrated circuit package provided with multiple heat-conducting paths for enhancing heat dissipation and wrapping around cap for improving integrity and reliability
US5693572A (en) Ball grid array integrated circuit package with high thermal conductivity
US6667556B2 (en) Flip chip adaptor package for bare die
US6404049B1 (en) Semiconductor device, manufacturing method thereof and mounting board
US5598031A (en) Electrically and thermally enhanced package using a separate silicon substrate
US6411507B1 (en) Removing heat from integrated circuit devices mounted on a support structure
US6743658B2 (en) Methods of packaging an integrated circuit
US20030067750A1 (en) Wirebonded microelectronic packages including heat dissipation devices for heat removal from active surfaces thereof
US20050189623A1 (en) Multiple die package
US7344916B2 (en) Package for a semiconductor device
JPH0964247A (en) Package of chip scale with circuit base board of metal
US20070166882A1 (en) Methods for fabricating chip-scale packages having carrier bonds
US6600651B1 (en) Package with high heat dissipation
US6265769B1 (en) Double-sided chip mount package
CN218957731U (en) Package for integrated circuit
US20030064542A1 (en) Methods of packaging an integrated circuit
KR20000001487A (en) Ball grid array package having super-heat emission characteristic

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION