US20050194683A1 - Bonding structure and fabrication thereof - Google Patents
Bonding structure and fabrication thereof Download PDFInfo
- Publication number
- US20050194683A1 US20050194683A1 US10/795,736 US79573604A US2005194683A1 US 20050194683 A1 US20050194683 A1 US 20050194683A1 US 79573604 A US79573604 A US 79573604A US 2005194683 A1 US2005194683 A1 US 2005194683A1
- Authority
- US
- United States
- Prior art keywords
- bonding structure
- copper
- protection layer
- layer
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05681—Tantalum [Ta] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05684—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48647—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48663—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/48684—Tungsten (W) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48747—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48763—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/48784—Tungsten (W) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01025—Manganese [Mn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- the present invention relates to a semiconductor structure and in particular to a copper-based bonding structure with a surface protection layer.
- Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed inter-layer dielectrics and interconnected metallization layers defining conductive patterns.
- An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines.
- the conductive patterns on different metallization layers are electrically connected by a conductive plug filling with a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region.
- Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor chips comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
- Copper (Cu) and copper alloys have received considerable attention as a replacement material for aluminum (Al) in ultra large scale interconnection metalizations. Copper is relatively inexpensive, easy to process, has lower resistance than aluminum, and has improved electrical properties over tungsten (W), making copper a desirable metal for use as a conductive plug as well as conductive wiring.
- Al aluminum
- W tungsten
- the bonding pad area is located on the top surface of the integrated circuit structure formed on the semiconductor substrate.
- the bonding pad area is the region where wires make contact with bonding pads to form electrical connection with the Cu interconnects.
- the copper can be designed to act as an interconnect as well as a bonding pad.
- an object of the invention is to provide a reliable bonding structure adopting copper pad, suitable for wire bonding technology or flip-chip bonding technology, with a protection layer to prevent the surface thereof from oxidizing.
- the present invention provides a bonding structure, comprising a copper-based pad formed in an insulator layer and a protection layer substantially covering a top surface of the copper-based pad.
- a conductive bonding is further formed over the protection layer connected to connect the copper-based pad.
- Another object of the invention is to provide a method of fabricating a copper bonding structure suitable for wire bonding technology or flip-chip bonding technology.
- the present invention provides a method of fabricating a bonding structure, comprising the steps of forming an insulating layer over a substrate and forming a copper-based pad in the insulating layer. A protection layer is then formed substantially covering the top surface of the copper-based pad. A passivation layer is forming over the copper-based pad and the insulating layer and the passivation layer is then patterned to expose a portion of the protection layer.
- a conductive bonding is further formed over the exposed protection layer to connect the copper-based pad.
- the protection layer comprises a conductive material selected from a group consisting of metal nitride, copper alloy, copper compounds, and combinations thereof.
- the protection layer comprises refractory metal.
- the conductive bonding is a conductive bump or a conductive wire.
- FIGS. 1 to 4 are cross sections showing a process for forming a bonding structure of the invention.
- FIGS. 1 to 4 show cross sections of a process for fabricating a copper bonding structure of the invention.
- an integrated circuit (IC) structure 100 having copper structures 108 formed therein is provided.
- the integrated circuit structure 100 may comprise a semiconductor substrate having integrated circuit devices and multilayer interconnection structures formed thereon.
- the integrated circuit devices can be active devices or passive devices formed on the semiconductor substrate and the multilayer interconnection structures can be multi metallization layers supported and spaced by inter-layer dielectric.
- the formed integrated circuit devices and multilayer interconnection structures are not shown here in the integrated circuit structure 100 , for simplicity.
- the integrated circuit (IC) structure 100 having copper structures 108 can be fabricated by the following steps. First, a first and a second insulating layer 102 and 104 are sequentially formed on the structure 100 .
- the material of insulating layers 102 and 104 can be oxide, nitride, polymers, spin-on glass, low-k dielectric or a combination thereof.
- the low-k dielectric can be either organic dielectric such as benzocyclobutene (BCB), SiLK, available from Dow Chemical, and Flare, available from AlliedSignal of Morristown or inorganic dielectric such as hydrogen silsesquioxane (HSQ), fluorocarbon silsesquioxane (FSQ), methylsilsesquioxane (MSQ), nanoglass, or the like.
- the dielectric constant of the insulating layers 102 and 104 are preferably less than 3.6.
- the insulating layers 102 and 104 are preferably formed using chemical vapor deposition (CVD) or spin-on coating, although other deposition techniques can be employed as well.
- each of the openings includes a narrow via opening in the lower portion for forming interconnects therein and a device opening in the upper portion for forming a conductive line or bonding pad.
- a copper layer 108 is then formed in the openings 106 a and 106 b .
- the copper layer 108 can be formed by blanketing a copper-based material over the second insulating layer 104 and filling the openings 106 a and 106 b .
- the copper-based material over the top surface of the second insulating layer 104 is then planarized through a proper etch-back step or a chemical mechanical polishing (CMP) step.
- CMP chemical mechanical polishing
- the copper layer 108 is thus respectively left in these openings 106 a , 106 b and the top surfaces thereof are also exposed.
- the copper-based material of the copper layer 108 can be, for example, high purity elemental copper or copper-based alloys containing minor amounts of zinc (Zn), manganese (Mn), titanium (Ti), aluminum (Al) and germanium (Ge).
- a protection layer 120 for preventing oxidation of the top surface of each copper layer 108 is formed on top surface of each copper layer 108 .
- the thickness thereof is about 100 ⁇ to 1000 ⁇ .
- the protection layer 120 in the present invention is preferably formed by a self-aligned process 122 such as selective chemical vapor deposition (CVD) while additional protective material such as tungsten (W) is formed.
- CVD selective chemical vapor deposition
- W tungsten
- Conventional silicidation or nitridation processes can also be adopted to form copper compounds such as copper silicde or copper nitride on the top surface of each copper layer 108 .
- the copper compound can be formed by first depositing a metal layer (not shown) on the exposed surface of the copper layer 108 followed by a thermal treatment step.
- the copper compounds can be also formed by exposing a copper surface to silane (SiH 4 ) plasma to selectively form the copper silicide.
- an electrochemical plating (ECP) process (not shown) can be also used to form copper alloys containing minor amounts of refractory metal such as zinc (Zn), manganese (Mn), titanium (Ti), aluminum (Al) germanium (Ge) on the top surface of each copper layer 108 .
- the material of the protection layer 120 can be conductive material such as tantalum, tantalum nitride, tungsten, tungsten nitride, metal nitride, copper alloys, copper compounds or a combination thereof.
- the copper-based material of the copper layer 108 can be further recessed with a depth d beneath the surface of adjacent second insulating layer 104 .
- the depth d is about 100 ⁇ to 1000 ⁇ and can be achieved by an additional over-etch step of the etching back process or an is over polishing step of the CMP process during the planarizing of the copper layer 108 .
- the protection layer 120 can be formed by the described self-aligned process 122 and can be thus left in each recess above each copper layer 108 and shows a substantially planar surface, as shown in FIG. 3 .
- a passivation layer 124 is then formed over each second insulating layer 104 and covers the protection layers 120 to prevent the copper layers 108 from mechanical scratches and surrounding moisture.
- the material of the passivation layer 124 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, spin-on glass (SOG) or a combination thereof.
- the passivation layer 124 is patterned to form an opening therein, exposing a portion of the protection layer 120 as a bonding pad region 126 for the use of sequential wire bonding or flip-chip bonding.
- a conductive bump 128 such as solder bump or gold bump, can be then formed therein without oxidizing the copper layer 108 thereunder, thus ensuring the reliability of the copper-based bonding pad.
- conductive wires such as gold wires or aluminum wires used in conventional wire bonding technology can be also formed therein.
- a copper bonding pad with a protection layer formed thereon is illustrated.
- the protection layer 120 can be self-aligned formed on the underlying copper bonding pad (referring to one copper layer 108 ) without an additional photolithography process and can be thus easily fabricated.
- the copper-based material of the bonding pad costs less than conventional aluminum bonding pad and the thickness of the copper bonding pad can be also reduced due to better conductivity of the copper-based material.
- conductive bumps for flip-chip bonding technique or conductive wires for conventional wire bonding technique can be formed on the copper bonding pad of the invention without oxidizing the copper layer therein and the reliability thereof can thus be ensured.
Abstract
A bonding structure and the method of fabricating the same are disclosed. The bonding structure of the invention includes a copper-based pad formed in an insulator layer and a protection layer substantially covering top surface of the copper-based pad. The protection layer is self-aligned formed and the material thereof is selected from a group consisting of metal nitride, copper alloy, copper compounds, and a combination thereof.
Description
- The present invention relates to a semiconductor structure and in particular to a copper-based bonding structure with a surface protection layer.
- Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed inter-layer dielectrics and interconnected metallization layers defining conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different metallization layers are electrically connected by a conductive plug filling with a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor chips comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
- Copper (Cu) and copper alloys have received considerable attention as a replacement material for aluminum (Al) in ultra large scale interconnection metalizations. Copper is relatively inexpensive, easy to process, has lower resistance than aluminum, and has improved electrical properties over tungsten (W), making copper a desirable metal for use as a conductive plug as well as conductive wiring.
- In the formation of copper interconnects using a damascene metallization process, copper is exposed in a bonding pad area. The bonding pad area is located on the top surface of the integrated circuit structure formed on the semiconductor substrate. The bonding pad area is the region where wires make contact with bonding pads to form electrical connection with the Cu interconnects. In this case, where the copper interconnects are exposed in the bonding pad area, the copper can be designed to act as an interconnect as well as a bonding pad.
- Conventional techniques for wire bonding, however, are not compatible with bonding pads comprising Cu. Existing bonding techniques such as wedge bonding and ultrasonic bonding require thermal agitation, that is, rubbing the wire against the bonding pad to form a bond therebetween. The existing technology works for the bonding of either gold wires or aluminum wires to aluminum pads. However, such technologies do not work for the bonding of gold wires or aluminum wires to copper pads, since copper is easily oxidized, forming copper oxide which is an insulator.
- In U.S. Pat. No. 5,785,236 issued to Cheung et. al., methodology is disclosed for electrically connecting wires to a Cu interconnect by forming an intermediate Al pad on the Cu interconnect. In U.S. Pat. No. 6,239,494 issued to Besser et. al. another methodology is disclosed for electrically connecting wires to a Cu interconnect by forming an Al pad and an intermediate diffusion barrier on the Cu interconnect. In both described patents, uses the Al pad is used, however, disadvantageously, as it increases the resistance of the interconnection system.
- A need therefore exists to form a reliable copper pad so that conventional wire bonding technology can be employed.
- Accordingly, an object of the invention is to provide a reliable bonding structure adopting copper pad, suitable for wire bonding technology or flip-chip bonding technology, with a protection layer to prevent the surface thereof from oxidizing.
- In order to achieve the above object, the present invention provides a bonding structure, comprising a copper-based pad formed in an insulator layer and a protection layer substantially covering a top surface of the copper-based pad.
- In one embodiment of the invention, a conductive bonding is further formed over the protection layer connected to connect the copper-based pad.
- Another object of the invention is to provide a method of fabricating a copper bonding structure suitable for wire bonding technology or flip-chip bonding technology.
- In order to achieve the above object, the present invention provides a method of fabricating a bonding structure, comprising the steps of forming an insulating layer over a substrate and forming a copper-based pad in the insulating layer. A protection layer is then formed substantially covering the top surface of the copper-based pad. A passivation layer is forming over the copper-based pad and the insulating layer and the passivation layer is then patterned to expose a portion of the protection layer.
- In one embodiment of the invention, a conductive bonding is further formed over the exposed protection layer to connect the copper-based pad.
- In another embodiment of the invention, the protection layer comprises a conductive material selected from a group consisting of metal nitride, copper alloy, copper compounds, and combinations thereof.
- In another embodiment of the invention, the protection layer comprises refractory metal.
- In another embodiment of the invention, the conductive bonding is a conductive bump or a conductive wire.
- A detailed description is given in the following embodiments with reference to the accompanying drawings.
- The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
- FIGS. 1 to 4 are cross sections showing a process for forming a bonding structure of the invention.
- FIGS. 1 to 4 show cross sections of a process for fabricating a copper bonding structure of the invention.
- In
FIG. 1 , an integrated circuit (IC)structure 100 havingcopper structures 108 formed therein is provided. Theintegrated circuit structure 100 may comprise a semiconductor substrate having integrated circuit devices and multilayer interconnection structures formed thereon. The integrated circuit devices can be active devices or passive devices formed on the semiconductor substrate and the multilayer interconnection structures can be multi metallization layers supported and spaced by inter-layer dielectric. The formed integrated circuit devices and multilayer interconnection structures, however, are not shown here in theintegrated circuit structure 100, for simplicity. - The integrated circuit (IC)
structure 100 havingcopper structures 108 can be fabricated by the following steps. First, a first and a secondinsulating layer structure 100. The material ofinsulating layers insulating layers insulating layers - Next, two
separate openings insulating layers copper layer 108 is then formed in theopenings copper layer 108 can be formed by blanketing a copper-based material over the secondinsulating layer 104 and filling theopenings insulating layer 104 is then planarized through a proper etch-back step or a chemical mechanical polishing (CMP) step. Thecopper layer 108 is thus respectively left in theseopenings copper layer 108 can be, for example, high purity elemental copper or copper-based alloys containing minor amounts of zinc (Zn), manganese (Mn), titanium (Ti), aluminum (Al) and germanium (Ge). - In
FIG. 2 , aprotection layer 120 for preventing oxidation of the top surface of eachcopper layer 108 is formed on top surface of eachcopper layer 108. The thickness thereof is about 100 Å to 1000 Å. Here, theprotection layer 120 in the present invention is preferably formed by a self-alignedprocess 122 such as selective chemical vapor deposition (CVD) while additional protective material such as tungsten (W) is formed. Conventional silicidation or nitridation processes (not shown) can also be adopted to form copper compounds such as copper silicde or copper nitride on the top surface of eachcopper layer 108. The copper compound can be formed by first depositing a metal layer (not shown) on the exposed surface of thecopper layer 108 followed by a thermal treatment step. Finally, the un-reacted metal is selectively removed by proper an appropriate etching process to leave the copper compound on the exposed copper surface. The copper compounds can be also formed by exposing a copper surface to silane (SiH4) plasma to selectively form the copper silicide. Further, an electrochemical plating (ECP) process (not shown) can be also used to form copper alloys containing minor amounts of refractory metal such as zinc (Zn), manganese (Mn), titanium (Ti), aluminum (Al) germanium (Ge) on the top surface of eachcopper layer 108. Thus, the material of theprotection layer 120 can be conductive material such as tantalum, tantalum nitride, tungsten, tungsten nitride, metal nitride, copper alloys, copper compounds or a combination thereof. - In addition, the copper-based material of the
copper layer 108 can be further recessed with a depth d beneath the surface of adjacent second insulatinglayer 104. The depth d is about 100 Å to 1000 Å and can be achieved by an additional over-etch step of the etching back process or an is over polishing step of the CMP process during the planarizing of thecopper layer 108. Next, theprotection layer 120 can be formed by the described self-alignedprocess 122 and can be thus left in each recess above eachcopper layer 108 and shows a substantially planar surface, as shown inFIG. 3 . - In
FIG. 4 , apassivation layer 124 is then formed over each second insulatinglayer 104 and covers the protection layers 120 to prevent the copper layers 108 from mechanical scratches and surrounding moisture. The material of thepassivation layer 124 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, spin-on glass (SOG) or a combination thereof. Next, thepassivation layer 124 is patterned to form an opening therein, exposing a portion of theprotection layer 120 as abonding pad region 126 for the use of sequential wire bonding or flip-chip bonding. Due to the anti-oxidation protection provided to thebonding region 126 by the exposedprotection layer 120, aconductive bump 128 such as solder bump or gold bump, can be then formed therein without oxidizing thecopper layer 108 thereunder, thus ensuring the reliability of the copper-based bonding pad. Further, conductive wires such as gold wires or aluminum wires used in conventional wire bonding technology can be also formed therein. - As shown in
FIG. 4 , a copper bonding pad with a protection layer formed thereon is illustrated. In the invention, theprotection layer 120 can be self-aligned formed on the underlying copper bonding pad (referring to one copper layer 108) without an additional photolithography process and can be thus easily fabricated. Moreover, the copper-based material of the bonding pad costs less than conventional aluminum bonding pad and the thickness of the copper bonding pad can be also reduced due to better conductivity of the copper-based material. Due to the anti-oxidation protection provided to the copper bonding pad by the protection layer, either conductive bumps for flip-chip bonding technique or conductive wires for conventional wire bonding technique can be formed on the copper bonding pad of the invention without oxidizing the copper layer therein and the reliability thereof can thus be ensured. - While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (27)
1. A bonding structure, comprising:
a copper-based pad formed in an insulator layer;
a protection layer substantially covering a top surface of the copper-based pad; and
a conductive bonding directly connecting the protection layer.
2. (canceled)
3. The bonding structure as claimed in claim 1 , wherein the protection layer is a self-aligned protection layer.
4. The bonding structure as claimed in claim 1 , wherein the insulating layer comprises organic low-k material and inorganic low-k material.
5. The bonding structure as claimed in claim 1 , wherein the protection layer is a tungsten layer.
6. The bonding structure as claimed in claim 1 , wherein the thickness of the protection layer is 100 Å to 1000 Å.
7. The bonding structure as claimed in claim 1 , wherein the protection layer comprises a conductive material selected form a group consisting of metal nitride, copper alloy, copper compounds, and a combination thereof.
8. The bonding structure as claimed in claim 1 , wherein the protection layer comprises refractory metal.
9. The bonding structure as claimed in claim 1 , wherein the dielectric constant of the insulating layer is less than 3.6.
10-21. (canceled)
22. A bonding structure, comprising:
a copper-based pad over an interconnect thereunder formed in an insulator layer;
a protection layer substantially covering a top surface of the copper-based pad; and
a conductive bonding directly connecting the protection layer.
23. (canceled)
24. The bonding structure as claimed in claim 22 , wherein the protection layer is a self-aligned protection layer.
25. The bonding structure as claimed in claim 22 , wherein the insulating layer comprises organic low-k material.
26. The bonding structure as claimed in claim 22 , wherein the insulating layer comprises inorganic low-k material.
27. The bonding structure as claimed in claim 22 , wherein the thickness of the protection layer is 100 Å to 1000 Å.
28. The bonding structure as claimed in claim 22 , wherein the protection layer comprises a conductive material selected from a group consisting of metal nitride, copper alloy, copper compounds, and a combination thereof.
29. The bonding structure as claimed in claim 22 , wherein the protection layer comprises refractory metal.
30. The bonding structure as claimed in claim 22 , wherein the dielectric constant of the insulating layer is less than 3.6.
31. A bonding structure, comprising:
a copper-based pad formed in an insulator layer, having a recession below a top surface of the insulator layer; and
a protection layer substantially filling the recession and leveling to a top surface of the insulator layer.
32. The bonding structure as claimed in claim 31 , wherein the recession has a depth about 100-1000 Å.
33. The bonding structure as claimed in claim 31 , wherein the protection layer is a self-aligned protection layer.
34. The bonding structure as claimed in claim 31 , wherein the insulating layer comprises organic low-k material and inorganic low-k material.
35. The bonding structure as claimed in claim 31 , wherein the protection layer is a tungsten layer.
36. The bonding structure as claimed in claim 31 , wherein the protection layer comprises a conductive material selected form a group consisting of metal nitride, copper alloy, copper compounds, and a combination thereof.
37. The bonding structure as claimed in claim 31 , wherein the protection layer comprises refractory metal.
38. The bonding structure as claimed in claim 31 , wherein the dielectric constant of the insulating layer is less than 3.6.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/795,736 US20050194683A1 (en) | 2004-03-08 | 2004-03-08 | Bonding structure and fabrication thereof |
TW093123077A TWI271808B (en) | 2004-03-08 | 2004-08-02 | Bonding structure and fabrication thereof |
US11/964,195 US8034711B2 (en) | 2004-03-08 | 2007-12-26 | Bonding structure and fabrication thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/795,736 US20050194683A1 (en) | 2004-03-08 | 2004-03-08 | Bonding structure and fabrication thereof |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/964,195 Division US8034711B2 (en) | 2004-03-08 | 2007-12-26 | Bonding structure and fabrication thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050194683A1 true US20050194683A1 (en) | 2005-09-08 |
Family
ID=34912514
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/795,736 Abandoned US20050194683A1 (en) | 2004-03-08 | 2004-03-08 | Bonding structure and fabrication thereof |
US11/964,195 Expired - Fee Related US8034711B2 (en) | 2004-03-08 | 2007-12-26 | Bonding structure and fabrication thereof |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/964,195 Expired - Fee Related US8034711B2 (en) | 2004-03-08 | 2007-12-26 | Bonding structure and fabrication thereof |
Country Status (2)
Country | Link |
---|---|
US (2) | US20050194683A1 (en) |
TW (1) | TWI271808B (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070197023A1 (en) * | 2006-02-22 | 2007-08-23 | Chartered Semiconductor Manufacturing, Ltd | Entire encapsulation of Cu interconnects using self-aligned CuSiN film |
US20090275195A1 (en) * | 2006-04-04 | 2009-11-05 | Chen-Hua Yu | Interconnect Structure Having a Silicide/Germanide Cap Layer |
US20090283913A1 (en) * | 2008-05-16 | 2009-11-19 | Kabushiki Kaisha Toshiba | Semiconductor device and method for fabricating semiconductor device |
US20100065964A1 (en) * | 2008-09-15 | 2010-03-18 | Abdalla Aly Naem | Copper-topped interconnect structure that has thin and thick copper traces and method of forming the copper-topped interconnect structure |
US7964934B1 (en) | 2007-05-22 | 2011-06-21 | National Semiconductor Corporation | Fuse target and method of forming the fuse target in a copper process flow |
US8030733B1 (en) | 2007-05-22 | 2011-10-04 | National Semiconductor Corporation | Copper-compatible fuse target |
US20130069231A1 (en) * | 2011-09-16 | 2013-03-21 | Chipmos Technologies Inc. | Solder cap bump in semiconductor package and method of manufacturing the same |
US20130112462A1 (en) * | 2011-11-07 | 2013-05-09 | International Business Machines Corporation | Metal Alloy Cap Integration |
US20170053879A1 (en) * | 2015-08-21 | 2017-02-23 | Infineon Technologies Ag | Method, a semiconductor device and a layer arrangement |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8969197B2 (en) * | 2012-05-18 | 2015-03-03 | International Business Machines Corporation | Copper interconnect structure and its formation |
US8765602B2 (en) | 2012-08-30 | 2014-07-01 | International Business Machines Corporation | Doping of copper wiring structures in back end of line processing |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5436412A (en) * | 1992-10-30 | 1995-07-25 | International Business Machines Corporation | Interconnect structure having improved metallization |
US5785236A (en) * | 1995-11-29 | 1998-07-28 | Advanced Micro Devices, Inc. | Advanced copper interconnect system that is compatible with existing IC wire bonding technology |
US6114243A (en) * | 1999-11-15 | 2000-09-05 | Chartered Semiconductor Manufacturing Ltd | Method to avoid copper contamination on the sidewall of a via or a dual damascene structure |
US6239494B1 (en) * | 1999-04-21 | 2001-05-29 | Advanced Micro Devices, Inc. | Wire bonding CU interconnects |
US6265300B1 (en) * | 1993-03-31 | 2001-07-24 | Intel Corporation | Wire bonding surface and bonding method |
US6274933B1 (en) * | 1999-01-26 | 2001-08-14 | Agere Systems Guardian Corp. | Integrated circuit device having a planar interlevel dielectric layer |
US6378759B1 (en) * | 2000-07-18 | 2002-04-30 | Chartered Semiconductor Manufacturing Ltd. | Method of application of conductive cap-layer in flip-chip, COB, and micro metal bonding |
US6451681B1 (en) * | 1999-10-04 | 2002-09-17 | Motorola, Inc. | Method of forming copper interconnection utilizing aluminum capping film |
US6457234B1 (en) * | 1999-05-14 | 2002-10-01 | International Business Machines Corporation | Process for manufacturing self-aligned corrosion stop for copper C4 and wirebond |
US6635497B2 (en) * | 2001-12-21 | 2003-10-21 | Texas Instruments Incorporated | Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing |
US20040084780A1 (en) * | 1998-07-07 | 2004-05-06 | Tri-Rung Yew | Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit |
US6835643B2 (en) * | 1999-06-14 | 2004-12-28 | Micron Technology, Inc. | Method of improving copper interconnects of semiconductor devices for bonding |
US6844631B2 (en) * | 2002-03-13 | 2005-01-18 | Freescale Semiconductor, Inc. | Semiconductor device having a bond pad and method therefor |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5223455A (en) * | 1987-07-10 | 1993-06-29 | Kabushiki Kaisha Toshiba | Method of forming refractory metal film |
US5243222A (en) * | 1991-04-05 | 1993-09-07 | International Business Machines Corporation | Copper alloy metallurgies for VLSI interconnection structures |
JPH05243402A (en) * | 1992-03-03 | 1993-09-21 | Nec Corp | Manufacture of semiconductor device |
US6166444A (en) * | 1999-06-21 | 2000-12-26 | United Microelectronics Corp. | Cascade-type chip module |
US7655555B2 (en) * | 1999-08-27 | 2010-02-02 | Texas Instruments Incorporated | In-situ co-deposition of Si in diffusion barrier material depositions with improved wettability, barrier efficiency, and device reliability |
TW420854B (en) | 1999-08-30 | 2001-02-01 | Taiwan Semiconductor Mfg | Method for improving the bonding property between the gold (Au) connection wire and the copper (Cu) bonding-pad |
TW526555B (en) | 1999-09-17 | 2003-04-01 | United Microelectronics Corp | Etching method of inorganic low dielectric constant material layer |
SG125881A1 (en) * | 1999-12-03 | 2006-10-30 | Lytle Steven Alan | Define via in dual damascene process |
DE10022061A1 (en) * | 2000-05-06 | 2001-11-08 | Leybold Vakuum Gmbh | Magnetic bearing arrangement with damping device especially for turbo-compressor, has two bearings each including stator annular magnet stack and rotor annular magnet stack |
JP2002110679A (en) * | 2000-09-29 | 2002-04-12 | Hitachi Ltd | Method for manufacturing semiconductor integrated circuit device |
JP4340040B2 (en) | 2002-03-28 | 2009-10-07 | 富士通マイクロエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US6740392B1 (en) * | 2003-04-15 | 2004-05-25 | Micron Technology, Inc. | Surface barriers for copper and silver interconnects produced by a damascene process |
-
2004
- 2004-03-08 US US10/795,736 patent/US20050194683A1/en not_active Abandoned
- 2004-08-02 TW TW093123077A patent/TWI271808B/en not_active IP Right Cessation
-
2007
- 2007-12-26 US US11/964,195 patent/US8034711B2/en not_active Expired - Fee Related
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5436412A (en) * | 1992-10-30 | 1995-07-25 | International Business Machines Corporation | Interconnect structure having improved metallization |
US6265300B1 (en) * | 1993-03-31 | 2001-07-24 | Intel Corporation | Wire bonding surface and bonding method |
US5785236A (en) * | 1995-11-29 | 1998-07-28 | Advanced Micro Devices, Inc. | Advanced copper interconnect system that is compatible with existing IC wire bonding technology |
US20040084780A1 (en) * | 1998-07-07 | 2004-05-06 | Tri-Rung Yew | Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit |
US6274933B1 (en) * | 1999-01-26 | 2001-08-14 | Agere Systems Guardian Corp. | Integrated circuit device having a planar interlevel dielectric layer |
US6239494B1 (en) * | 1999-04-21 | 2001-05-29 | Advanced Micro Devices, Inc. | Wire bonding CU interconnects |
US20030072928A1 (en) * | 1999-05-14 | 2003-04-17 | Edelstein Daniel C. | Self-aligned corrosion stop for copper C4 and wirebond |
US6457234B1 (en) * | 1999-05-14 | 2002-10-01 | International Business Machines Corporation | Process for manufacturing self-aligned corrosion stop for copper C4 and wirebond |
US6835643B2 (en) * | 1999-06-14 | 2004-12-28 | Micron Technology, Inc. | Method of improving copper interconnects of semiconductor devices for bonding |
US6451681B1 (en) * | 1999-10-04 | 2002-09-17 | Motorola, Inc. | Method of forming copper interconnection utilizing aluminum capping film |
US6114243A (en) * | 1999-11-15 | 2000-09-05 | Chartered Semiconductor Manufacturing Ltd | Method to avoid copper contamination on the sidewall of a via or a dual damascene structure |
US6378759B1 (en) * | 2000-07-18 | 2002-04-30 | Chartered Semiconductor Manufacturing Ltd. | Method of application of conductive cap-layer in flip-chip, COB, and micro metal bonding |
US6635497B2 (en) * | 2001-12-21 | 2003-10-21 | Texas Instruments Incorporated | Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing |
US6844631B2 (en) * | 2002-03-13 | 2005-01-18 | Freescale Semiconductor, Inc. | Semiconductor device having a bond pad and method therefor |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7524755B2 (en) | 2006-02-22 | 2009-04-28 | Chartered Semiconductor Manufacturing, Ltd. | Entire encapsulation of Cu interconnects using self-aligned CuSiN film |
US20070197023A1 (en) * | 2006-02-22 | 2007-08-23 | Chartered Semiconductor Manufacturing, Ltd | Entire encapsulation of Cu interconnects using self-aligned CuSiN film |
US20090275195A1 (en) * | 2006-04-04 | 2009-11-05 | Chen-Hua Yu | Interconnect Structure Having a Silicide/Germanide Cap Layer |
US8143162B2 (en) * | 2006-04-04 | 2012-03-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure having a silicide/germanide cap layer |
US7964934B1 (en) | 2007-05-22 | 2011-06-21 | National Semiconductor Corporation | Fuse target and method of forming the fuse target in a copper process flow |
US8030733B1 (en) | 2007-05-22 | 2011-10-04 | National Semiconductor Corporation | Copper-compatible fuse target |
US20090283913A1 (en) * | 2008-05-16 | 2009-11-19 | Kabushiki Kaisha Toshiba | Semiconductor device and method for fabricating semiconductor device |
US7936070B2 (en) * | 2008-05-16 | 2011-05-03 | Kabushiki Kaisha Toshiba | Semiconductor device and method for fabricating semiconductor device |
US20100065964A1 (en) * | 2008-09-15 | 2010-03-18 | Abdalla Aly Naem | Copper-topped interconnect structure that has thin and thick copper traces and method of forming the copper-topped interconnect structure |
US20100190332A1 (en) * | 2008-09-15 | 2010-07-29 | Abdalla Aly Naem | Method of Forming a Copper Topped Interconnect Structure that has Thin and Thick Copper Traces |
US7709956B2 (en) | 2008-09-15 | 2010-05-04 | National Semiconductor Corporation | Copper-topped interconnect structure that has thin and thick copper traces and method of forming the copper-topped interconnect structure |
US8324097B2 (en) * | 2008-09-15 | 2012-12-04 | National Semiconductor Corporation | Method of forming a copper topped interconnect structure that has thin and thick copper traces |
US20130069231A1 (en) * | 2011-09-16 | 2013-03-21 | Chipmos Technologies Inc. | Solder cap bump in semiconductor package and method of manufacturing the same |
US8431478B2 (en) * | 2011-09-16 | 2013-04-30 | Chipmos Technologies, Inc. | Solder cap bump in semiconductor package and method of manufacturing the same |
US20130112462A1 (en) * | 2011-11-07 | 2013-05-09 | International Business Machines Corporation | Metal Alloy Cap Integration |
US20170053879A1 (en) * | 2015-08-21 | 2017-02-23 | Infineon Technologies Ag | Method, a semiconductor device and a layer arrangement |
CN106469710A (en) * | 2015-08-21 | 2017-03-01 | 英飞凌科技股份有限公司 | A kind of method, a kind of semiconductor device and a kind of layer arrangement |
KR20170022918A (en) * | 2015-08-21 | 2017-03-02 | 인피니언 테크놀로지스 아게 | A method, a semiconductor device and a layer arrangement |
KR101890987B1 (en) | 2015-08-21 | 2018-08-22 | 인피니언 테크놀로지스 아게 | A method, a semiconductor device and a layer arrangement |
Also Published As
Publication number | Publication date |
---|---|
TWI271808B (en) | 2007-01-21 |
TW200531193A (en) | 2005-09-16 |
US8034711B2 (en) | 2011-10-11 |
US20080102198A1 (en) | 2008-05-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8034711B2 (en) | Bonding structure and fabrication thereof | |
US7538434B2 (en) | Copper interconnection with conductive polymer layer and method of forming the same | |
US7514354B2 (en) | Methods for forming damascene wiring structures having line and plug conductors formed from different materials | |
CN101924096B (en) | Through-silicon via structure and a process for forming the same | |
US20220359274A1 (en) | Method and Apparatus for Back End of Line Semiconductor Device Processing | |
US6239494B1 (en) | Wire bonding CU interconnects | |
US6468906B1 (en) | Passivation of copper interconnect surfaces with a passivating metal layer | |
US7494912B2 (en) | Terminal pad structures and methods of fabricating same | |
US6893959B2 (en) | Method to form selective cap layers on metal features with narrow spaces | |
US20060205204A1 (en) | Method of making a semiconductor interconnect with a metal cap | |
US20060145347A1 (en) | Semiconductor device and method for fabricating the same | |
US9257389B2 (en) | Semiconductor device having metal interconnections | |
CN101958311B (en) | Semiconductor structure and forming method | |
US8102051B2 (en) | Semiconductor device having an electrode and method for manufacturing the same | |
US20100155949A1 (en) | Low cost process flow for fabrication of metal capping layer over copper interconnects | |
US8324731B2 (en) | Integrated circuit device | |
US20030228749A1 (en) | Plating metal caps on conductive interconnect for wirebonding | |
US6777318B2 (en) | Aluminum/copper clad interconnect layer for VLSI applications | |
US6638849B2 (en) | Method for manufacturing semiconductor devices having copper interconnect and low-K dielectric layer | |
US20060121717A1 (en) | Bonding structure and fabrication thereof | |
US20050064629A1 (en) | Tungsten-copper interconnect and method for fabricating the same | |
US6590288B1 (en) | Selective deposition in integrated circuit interconnects | |
JP3488146B2 (en) | Semiconductor device and manufacturing method thereof | |
KR100718451B1 (en) | Metal line in semiconductor device and manufacturing method thereof | |
KR20090048820A (en) | Semiconductor device and method for fabricating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIW Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YU, CHEN-YUA;TSENG, HORNG-HUEI;REEL/FRAME:015068/0250 Effective date: 20040225 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |