US20050200027A1

US20050200027A1 - Conductive through wafer vias

Info

Publication number: US20050200027A1
Application number: US11/052,181
Authority: US
Inventors: Nishant Sinha; Warren Farnworth
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2003-03-05
Filing date: 2005-02-07
Publication date: 2005-09-15
Also published as: US20040173909A1; US6852627B2

Abstract

Methods for fabricating a conductive contact (through-via) through a full thickness of a substrate such as a semiconductor wafer or interposer substrate, and semiconductor devices and systems incorporating the conductive through-via are provided. The conductive contact is fabricated by applying a metal layer onto a backside of a substrate, forming a through-hole through the substrate and the metal layer, sealing the hole in the metal layer by an electroless plating process, and filling the hole by an electroplating or an electroless plating process.

Description

CROSS REFERENCE TO RELATED APPLICATION

This application is a division of U.S. Ser. No. 10/379,890, filed Mar. 5, 2003, pending.

FIELD OF THE INVENTION

The invention relates generally to semiconductor fabrication, and more particularly to methods for providing interconnects from one surface to the opposite surface of a substrate for making electrical connections with semiconductor components, and more particularly to methods for filling a through-via in a wafer, interposer or other substrate with a conductive material.

BACKGROUND OF THE INVENTION

Interposers are utilized for interfacing two electrical components, for example, a semiconductor device and a printed circuit board, or a semiconductor wafer and a probe card for testing of the dies on the wafer. These interposers may comprise silicon or ceramic substrate that include metal-filled vias that extend through the interposer from one side to the opposite side. The metal-filled via provide electrical communication between conductive structures disposed on the opposing surfaces of the interposer, which align with contact pads or other structures of the electrical components to establish electrical connection between the two components.
Continued miniaturization of integrated circuits results in contact vias having increasingly higher aspect ratios (defined as the ratio of height to width of the via).
Conventional methods of filling a through-via using a plasma chemical vapor deposition (PCVD) process to form a seed layer followed by a conformal metal electroplating process are limited to low aspect ratio openings. As is known in the art, high aspect ratio vias are difficult to fill conformally, that is, without forming voids or keyholes that can adversely affect conductivity of the contacts.

SUMMARY OF THE INVENTION

The present invention provides methods for fabricating a conductive contact (through-via) through the full thickness of a semiconductor wafer, interposer, or other substrate, and semiconductor devices and systems incorporating the conductive through-via.
One embodiment of a method of forming a conductive contact according to the invention comprises applying a layer of metal onto a first surface of a substrate, forming an opening through the substrate and the metal layer, electroless plating a metal to fill the opening through the metal layer, and plating a metal to fill the opening in the substrate. The metal layer can be applied to the backside surface of the substrate by various processes including deposition processes, adhering a metal sheet, among others. The gap formed in the metal layer is sealed by an electroless plating process, and the opening in the substrate is filled with metal deposited by an electroplating or electroless plating process. In embodiments in which the substrate is a semiconductive material (e.g., silicon), an isolation layer can be formed onto sidewalls of the substrate within the opening prior to the metal plating steps. The process of the invention results in a conductive contact that is without voids or keyholes.
In another aspect, the invention provides a semiconductor device. In various embodiments, the device comprises a conductive through-via according to the invention disposed through a substrate.
In one embodiment, the device comprises the conductive through-via in process, which comprises a layer of metal disposed on a surface of a substrate and an opening through the substrate and the metal layer. In another embodiment, the device comprises a metal layer disposed on a surface of a substrate, an opening through the substrate and the metal layer, and a plated metal disposed in the opening of the metal layer. In yet another embodiment, the device comprises a metal layer disposed on a surface of a substrate, an opening through the substrate and the metal layer, an electrolessly plated metal sealing in the opening (gap) in the metal layer, and a plated metal fill disposed in the opening in the substrate to form a conductive contact.
The device can comprise a semiconductor wafer, an interposer, or other substrate comprising the conductive through-via, or the conductive through-via in process.
Another aspect of the invention is a system comprising a microprocessor in communication with a memory device comprising the conductive through-via of the invention.
The invention advantageously provides a simplified method of forming through-wafer vias that are void-free. The present method involves fewer process steps than prior art methods, provides a cost savings in the production. Additionally, the process achieves a solid fill contact by depositing metal upward from the base of the opening rather than by conformal plating or deposition by vapor.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below with reference to the following accompanying drawings, which are for illustrative purposes only. Throughout the following views, the reference numerals will be used in the drawings, and the same reference numerals will be used throughout the several views and in the description to indicate same or like parts.
FIGS. 1-8 are diagrammatic cross-sectional views of a fragment of a semiconductor substrate at sequential processing steps showing fabrication of a conductive contact according to an embodiment of the method of the invention.
FIG. 1 illustrates a processing step forming a metal layer on a surface of the substrate.
FIG. 2 shows formation of openings through the substrate and the metal layer.
FIG. 3 shows formation of an isolation layer on the sidewalls of the openings and the surface of the substrate.
FIGS. 4-6 depict sequential processing steps to electroless plate a conductive metal in the gap in the metal layer.
FIGS. 7-8 illustrate sequential electroplating process steps to deposit metal in the opening to form the conductive contact.
FIG. 9 illustrates in another embodiment of an electroplating process step to fill multiple openings in the substrate according to the invention.
FIG. 10 illustrates another embodiment of a process step to fill the via opening according to the invention, using an electroless plating technique to form the conductive contacts.
FIG. 11 is a cross-sectional view of the wafer fragment after formation of conductive contacts and processing steps to remove excess metal and form circuit traces on the substrate.
FIG. 12 is a block diagram of an embodiment of a system in which the conductive through-vias of the invention can be used.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will be described generally with reference to the drawings for the purpose of illustrating the present preferred embodiments only and not for purposes of limiting the same. The figures illustrate processing steps for use in fabricating a conductive through-via in accordance with the present invention. It should be readily apparent that the processing steps are only a portion of the entire fabrication process.
In the current application, the terms “semiconductive wafer fragment” or “wafer fragment” or “wafer” will be understood to mean any construction comprising semiconductor material, including but not limited to bulk semiconductive materials such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure including, but not limited to, the semiconductive wafer fragments or wafers described above, and interposer substrates, among others.
The invention provides methods for filling a through-via that is formed through the thickness of a wafer or other substrate with a conductive metal. The conductive via is disposed in a substrate comprising an opening extending from the first surface to the second surface and at least partially filled with a conductive material. The conductive vias can be used for interconnecting contacts on a component, for example, a contact pad on one side of a substrate (e.g., interposer) to a conductive element such as a contact pad on the opposing side of the substrate, among other uses.
Steps in an embodiment of a method for fabricating a conductive through-via in a semiconductor device 10 according to the invention are illustrated in FIGS. 1-8. Initially, as shown in FIG. 1, a substrate 12 comprising opposing first and second surfaces 14, 16, and a thickness t₁is provided. The substrate 12 can comprise an unprocessed semiconductor wafer or other substrate, the wafer with various process layers formed thereon including one or more semiconductor layers or other formations and active or operable portions of semiconductor devices fabricated through etching, deposition, or other well known techniques, an interposer substrate for use between a test substrate and a semiconductor device to be tested or between a memory device and system in a package to provide routing, among other substrates. An exemplary thickness t₁of the substrate is about 28 mil, which can be about 8 to about 32 mil.
In the illustrated example, the substrate 12 comprises a semiconductive material such as monocrystalline silicon, polycrystalline silicon, germanium, silicon-on-glass, or silicon-on-sapphire, for example, but can also comprises a non-conductive (electrically insulating) material such as a ceramic, a plastic or polymer material such as bismaleimide triazine (BT) resin, a glass filled epoxy resin material such as such as FR-4 or FR-5 laminates, and an aramid-filled resin, for example, among other materials that are used as substrates in fabricating semiconductor devices and carrier substrates.
As shown in FIG. 1, a layer 18 of conductive metal is applied onto the second surface 16 of the substrate 12. The conductive metal layer 18 can comprise nickel, copper, aluminum, palladium, platinum, or silver, for example. The metal layer 18 can be fabricated by known metallization techniques, such as by chemical vapor deposition (CVD), physical vapor deposition (PVD) (e.g., sputtering), evaporation using a conventional metal evaporator, electroless plating, and electroplating, for example, to deposit a blanket layer of metal over the substrate. A pre-fabricated metal sheet or foil can also be adhered or laminated to the substrate using an adhesive material. As depicted, the metal layer includes an exposed (bottom) surface 20 and sidewalls 22.
The thickness t₂of the metal layer 18 can range from a thin seed layer of about 0.2 to about 0.5 μm to a thicker layer of up to about 2 μm. Preferably, the thickness t₂of the metal layer 18 is about one-tenth of the radius (r₁) of the gap 26 that is subsequently formed in the metal layer 18 (FIG. 2).
Next, as shown in FIG. 2, one or more contact openings or via holes 24 are formed through the entire thickness t₁, t₂of the substrate 12 and the metal layer 18, creating an opening or gap 26 in the metal layer. The openings 24 can be formed using a variety of fabrication techniques known in the art and appropriate to the substrate, including, for example, a dry etch utilizing photolithographic processing, or photochemical processing. The openings can also be formed using a laser machining (drilling) process, as described, for example, in U.S. Pat. No. 6,400,172 (Akram et al.). The openings 24 include sidewalls 28, and generally have a diameter (d) of about 0.17 to about 0.90 μm, typically less than about 0.40 μm, with substrates ranging in thickness from about 10 μm to about 725 μm, typically about 250 μm, resulting in an aspect ratio of about 42 to about 1 down to about 0.11 to 1, typically greater than about 6.25.
Following formation of the openings 18, a clean step can be performed to remove residual materials from the openings. Such a clean step can be performed, for example, by wet etching or stripping a sacrificial layer.
As shown in FIG. 3, an isolation layer 30 can be formed on the sidewalls 28 within the openings 24 and on the first surface 12 of the substrate 12 by known techniques in the art. The isolation layer 30 can comprise a dielectric or insulative material such as an oxide (e.g., silicon dioxide (SiO₂)), nitride (e.g., silicon nitride (Si₃N₄)), or an oxynitride, for example, or a glass such as borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or borosilicate glass (BSG). The isolation layer can be formed to a desired thickness using chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), rapid thermal nitridation (RTN), spin-on-glass (SOG) process, flow coating, or other process. The isolation layer 30 can also comprise an insulating polymer, such as BT resin, polyimide, benzocyclobutene (BCB), and/or polybenzoxazole (PBO), for example, deposited using an injection or capillary process or vacuum draw. A representative thickness of the isolation layer is about 1-5 μm. If the substrate 12 is formed of an electrically insulating material (e.g., ceramic), the isolation layer can be eliminated.
As shown in FIGS. 4-6, a conductive metal is then deposited to fill and seal the gap 26 in the metal layer 18 and short the metal layer together. According to the invention, a metal fill or plug layer 32 is fabricated by plating a conductive metal onto the sidewalls 22 of the metal layer 18 within the gap 26 using an electroless deposition (i.e., electroless plating, electrochemical deposition) process. The process of electroless plating of a metal generally comprises dipping the semiconductor element with the exposed metal layer into a solution including at least one inorganic metal salt and at least one agent that reduces the metal salt (reducing agent), wherein the metal selectively bonds or plates on the metal layer to a desired thickness.
Using an electroless deposition process, metal is deposited onto the sidewalls (edge, rim) 22 of the metal layer 18 within the gap 26, and on the exposed surface 20 of the metal layer 18 on the backside 33 of the substrate 12, by dipping at least the metal layer 18 into an electroless plating solution 34. Referring to FIGS. 4-5, as the plating progresses, there is a uniform build-up of metal 36 from the plating solution 34 onto the sidewalls 22 of the metal layer 18 resulting in the inward growth (arrows 38) of the metal layer 18 to fill the gap 26 and the formation of the plug layer 32, which effectively seals the gap 26. There is a corresponding build-up of metal 36 onto the exposed (bottom) surface 20 of the metal layer 18 on the backside 33 of the substrate 12.
For example, a metal layer 18 having a thickness t₂of about 2 μm can be applied onto the surface 16 of the substrate 12, and a contact opening 24 can be formed in the substrate through the metal layer 18 forming a gap 26 having a diameter d₁of about 50 μm (or radius r₁of about 25 μm). Plating can then be performed, whereby a buildup of metal 36 to a thickness of about 25 μm on the exposed surfaces 20 (including the sidewalls 22) of the metal layer 18 will form a plug 32 to fill the gap 26 (FIG. 6), and increase the thickness t₂of the metal layer 18 on the backside 33 of the substrate 12 to about 27 μm (about the radius r₁).
A conventional electroless plating process can be used. Exemplary metals include copper, nickel, cobalt, palladium, platinum, and silver. Electroless plating tools and solutions for electrolessly plating these metals are known in the art. For example, for electroless depositing nickel, the metal solution can comprise nickel chloride and a chemical reducing agent such as sodium hydroxyacetate and sodium hypophosphate at a temperature of about 85° C. to about 90° C. For depositing palladium, the metal solution can comprise palladium chloride and a chemical reducing agent such as sodium hypophosphate at a temperature of about 50° C. to about 60° C. For depositing silver, the solution can comprise a silver salt such as AgNO₃or KAg(CN)₂, and a chemical reducing agent such as potassium hypophosphite, among others.
The thickness of the plug layer 32 within the gap 26 is controlled by the concentration of the metal plating solution 34 and the length of time that the metal layer 18, 36 is immersed in the aqueous solution 34. To terminate the electroless deposition, the metal layer is removed and rinsed.
Next, a conventional electroplating or electroless plating process is used to deposit a conductive metal into the openings 24 onto the plug layer 32 to fill the opening 24 and form a conductive contact 40. Electroplating and electroless plating tools and plating solutions are known in the art and commercially available.
Generally, in an electroplating process, a substrate is submerged in a plating bath comprising metal ions. A current is applied to reduce the metal ions within the plating solution and metal deposits onto exposed metal surfaces on the substrate. The substrate remains submerged in the solution bath and the current is applied until a desired thickness of metal is deposited. The current is then terminated and the substrate is placed into a rinse bath to remove residual bath liquid and particles from the surface.
In an electroplating process according to the invention, the exposed surface 42 of the metal layer 36 on the backside 33 of the substrate 12 is sealed or covered to prevent further metal deposition thereon, and the openings 24 are uncovered. For example, as depicted in FIG. 7, the substrate 12 can be housed within a container 44 with sealing members 46 (e.g., rubber seals) disposed on the insulating layer 30 over the first (front side) surface 14 of the substrate 12, with the openings 24 exposed. As shown, a volume of gas 48 such as air or nitrogen (N₂) is disposed within the container 44 about metal layer 36 on the backside 33 of the substrate 12. According to the method, an electrode 50 is placed into contact with the surface 42 of the metal layer 36, and the front side 52 of the substrate 10 is immersed into an electroplating solution 54. A current from an energy source 56, for example, a battery, is applied through the electrode 50 to the metal layer 36, and metal deposits from solution onto the metal plug layer 32 within the opening 24 to form a metal layer 58. The metal plates upward from the plug layer 32 in the direction of arrow 60 to fill the opening 24, resulting in the conductive metal contact 40 shown in FIG. 8. The current to the electrode 50 is then terminated.
FIG. 9 illustrates another embodiment of an electroplating process to fill multiple openings in the substrate. As shown, a blanket electrode 50′ (metal sheet, bus bar) can be positioned over the surface 42′ of the metal layer 36′. A current from the electrode 50′ to the plug layer 32′ causes metal from the plating solution 54′ to deposit onto the plug layers 32′ in each of the openings 24′ to form the conductive contacts 40′.
Electroplating solutions are known and commercially available. The solution can comprise a conventional electroplating solution, including a metal sulfate solution and acids, commercially available, for example, from Shipley Company, LLC of Marlborough, Mass., Pac Tech USA, Inc. of Santa Clara, Calif., or Enthone OMI (Ethone, Inc., West Haven, Conn.). For example, in a copper electroplating process, the solution can comprise copper sulfate. In an example of a silver electroplating process, the substrate is immersed in a bath comprising a commercially available silver plating bath, for example, a cyanide-free silver plating solution comprising silver succinimide (C₄H₅O₂NAg), commercially under the trade name Techni-Silver CY-LESS® L2 from Technic, Inc., Cranston, R.I.
In another embodiment, the metal fill 40 within the openings 24 can be deposited by an electroless plating process, as described hereinabove. For example, the backside of the substrate and metal layer 36 can be sealed within a container 44 as described with reference to FIG. 7, without an electrode contact 50 against the metal layer 36. The sealed container-substrate unit 62 (without electrode 50) can then be submersed into an electroless plating solution for a time period effective to plate a metal layer 58 onto the plug layer 32 and fill the opening 24 to form the contact 40. Plating can be readily conducted in batch by immersing multiple units 62 (without electrode) into the plating solution.
In another example of an electroless plating process shown in FIG. 10, a flexible tape or other cover material 64″ can be applied to seal the surface 42″ of the metal layer 36″ from contact with the electroless plating solution 34″. The taped substrate can be submerged in the plating bath 34″ whereupon metal 58″ from the solution will plate onto exposed surfaces 42″ of the metal layer, including the plug layer 32″ to fill the opening 24″ and form the conductive contacts 40″.
Referring now to FIG. 11, after formation of the contacts 40, the device 10 is removed from the bath, and excess of the metal fill can be removed according to known methods in the art. Unwanted surface metal can be removed to expose the isolation layer 30 while leaving the desired metal within the opening 24 as depicted. Exemplary methods of removing metal material include a conventional dry etch or chemical mechanical polishing (CMP). The finished construction includes a conductive contact 40 formed within the opening 24.
Optionally, as also depicted, circuit traces 66 or other interconnects and contact structures can be fabricated on the isolation layer 30 to couple the via contact 40 to contact pads 68 or other conductive structures, and/or to circuit devices such as a internal circuitry and/or a microprocessor, for example. In addition, the metal layers 18, 36 on the backside of the substrate 12 can be removed by CMP, etching or other process, or patterned as shown to define circuit traces 70 leading from the via contact 40 to contact pads 72, as shown. The conductive contacts 40 can thus connect contact pads 68 on the top surface 14 of the substrate 12 to a conductive element shown as a contact pad 72 on the bottom surface 16 of the substrate.
The substrate 12 can be designed as an interposer for connecting semiconductor devices, including flip-chips, chip scale packages and ball grid array packages to a substrate, such as a test substrate or a higher level carrier substrate. The contact pads 68, 72 on the interposer substrate can be arranged in a pattern that corresponds to that of contact pads on a test or carrier substrate to be connected, or arranged in a different pattern than the bond pads and, therefore, reroute the bond pads of the test or carrier substrate.
Subsequent processing may then be conducted on semiconductor device structure 10, as known in the art.
FIG. 12 illustrates an embodiment of a system 74 in which the present invention can be incorporated. The system includes a memory device 76 (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), etc.) comprising a conductive contact according to the invention. The memory device 76 is coupled to a microprocessor 78, which may be programmed to carry out particular functions as is known in the art.
In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A semiconductor device, comprising: a substrate comprising first and second surfaces, a layer of a metal over the first surface of the substrate, and an opening extending through the substrate and the metal layer, the opening in the metal layer having a radius, and the metal layer having a thickness of about one-tenth of said radius of the opening.

2. The device of claim 1, wherein the thickness of the metal layer is about 0.2 μm to about 2 μm.

3. The device of claim 1, wherein the metal layer over the first surface of the substrate comprises a plated metal layer.

4. The device of claim 1, wherein the metal layer comprises a metal foil adhered to the first surface of the substrate.

5. The device of claim 1, wherein the substrate comprises a semiconductive material selected from the group consisting of monocrystalline silicon, polycrystalline silicon, germanium, silicon-on-glass, and silicon-on-sapphire.

6. The device of claim 1, wherein the substrate comprises a semiconductor wafer.

7. The device of claim 1, wherein the substrate comprises a non-conductive material selected from the group consisting of ceramic, polymer resin, glass-filled epoxy resin, and aramid-filled resin.

8. A semiconductor device, comprising: a substrate comprising first and second surfaces, a layer of a metal over the first surface of the substrate, and an opening extending through the substrate and the metal layer, the opening having sidewalls defined by the substrate and an isolation layer on said sidewalls, the opening through the metal layer having a radius and sidewalls defined by the substrate, and the metal layer having a thickness of about one-tenth of said radius of the opening.

9. The device of claim 8, wherein the isolation layer comprises a material selected from the group consisting of oxide, nitride, oxynitride, and glass.

10. The device of claim 8, wherein the isolation layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.

11. The device of claim 8, wherein the isolation layer comprises a glass selected from the group consisting of borophosphosilicate glass, phosphosilicate glass, and borosilicate glass.

12. The device of claim 8, wherein the isolation layer comprises an insulating polymeric material.

13. The device of claim 12, wherein the polymeric material is selected from the group consisting of bismaleimide triazine (BT) resin, benzocyclobutene, polybenzoxazole, and polyimide.

14. A semiconductor device, comprising: a nonconductive substrate comprising first and second surfaces, a layer of a metal over the first surface of the substrate, and an opening extending through the substrate and the metal layer, the opening in the metal layer having a radius, and the metal layer having a thickness of about one-tenth of said radius of the opening.

15. The device of claim 14, wherein the substrate comprises a material selected from the group consisting of ceramic, polymer resin, glass-filled epoxy resin, and aramid-filled resin.

16. A semiconductor device, comprising: a substrate comprising first and second surfaces, a layer of a metal over the first surface of the substrate, an opening extending through the substrate and the metal layer, and a plated metal plug sealing the opening of the metal layer.

17. A semiconductor device, comprising: a substrate comprising first and second surfaces, a layer of a metal over the first surface of the substrate, an opening extending through the substrate and the metal layer, the opening having sidewalls defined by the substrate and an isolation layer on said sidewalls, and a plated metal plug sealing the opening of the metal layer.

18. A semiconductor device, comprising: a substrate comprising first and second surfaces, a layer of a metal over the first surface of the substrate, an opening extending through the substrate and the metal layer, a plated metal plug sealing the opening of the metal layer, and a plated metal fill overlying the plated metal plug within the opening in the substrate.

19. A semiconductor device, comprising: a substrate comprising first and second surfaces, a layer of a metal over the first surface of the substrate, an opening extending through the substrate and the metal layer, the opening having sidewalls defined by the substrate and an isolation layer on said sidewalls, a plated metal plug sealing the opening of the metal layer, and a plated metal fill overlying the plated metal plug within the opening in the substrate.

20. A semiconductor wafer, comprising first and second surfaces, and a thickness, a layer of a metal over the first surface of the wafer, and an opening extending through the thickness of the wafer and the metal layer, the opening in the metal layer having a radius, and the metal layer having a thickness of about one-tenth of said radius of the opening.

21. A semiconductor wafer, comprising first and second surfaces, and a thickness, a layer of a metal over the first surface of the wafer, and an opening extending through the thickness of the wafer and the metal layer, the opening having sidewalls defined by the substrate and an isolation layer on said sidewalls, the opening in the metal layer having a radius, and the metal layer having a thickness of about one-tenth of said radius of the opening.

22. A semiconductor wafer, comprising first and second surfaces, and a thickness, a layer of a metal over the first surface of the wafer, and an opening extending through the thickness of the wafer and the metal layer, and a plated metal plug sealing the opening of the metal layer.

23. A semiconductor wafer, comprising: first and second surfaces, a layer of a metal on the first surface of the wafer, an opening extending through the wafer and the metal layer, the opening defined by sidewalls of the wafer, an isolation layer over said sidewalls within the opening, a conductive contact within the opening comprising a plated metal plug sealing the opening through the metal layer and a plated metal filling the opening through the wafer.

24. A semiconductor wafer, comprising: first and second surfaces, a layer of a metal on the first surface of the wafer, an opening extending through the wafer and the metal layer, the opening defined by sidewalls of the wafer, an isolation layer over said sidewalls within the opening, a conductive contact within the opening comprising an electrolessly plated metal plug sealing the opening through the metal layer and an electroplated metal filling the opening through the wafer.

25. A semiconductor wafer, comprising: first and second surfaces, a layer of a metal on the first surface of the wafer, an opening extending through the wafer and the metal layer, the opening defined by sidewalls of the wafer, an isolation layer over said sidewalls within the opening, a conductive contact within the opening comprising a plated metal plug sealing the opening through the metal layer and a plated metal filling the opening through the wafer. the metal layer patterned to define a circuit trace extending from the conductive contact to a contact pad on the first surface of the wafer.

26. An interposer for a semiconductor device, comprising: a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, a plated metal plug sealing the opening through the metal layer and a plated metal filling the opening through the substrate.

27. The interposer of claim 26, wherein the plated metal filling the via within the wafer comprises an electrolessly plated metal.

28. The interposer of claim 26, wherein the plated metal filling the via within the wafer comprises an electroplated metal.

29. The interposer of claim 26, wherein the substrate comprises a semiconductive material.

30. The interposer of claim 26, wherein the substrate comprises an electrically insulating material.

31. An interposer for a semiconductor device, comprising: a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, an isolation layer over sidewalls of the substrate within the opening, a plated metal plug sealing the opening through the metal layer, and a plated metal over the isolation layer and filling the opening through the substrate.

32. An interposer for a semiconductor device, comprising: a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, an isolation layer over sidewalls of the substrate within the opening, an electrolessly plated metal plug sealing the opening through the metal layer, and a plated metal over the isolation layer and filling the opening through the substrate.

33. An interposer for a semiconductor device, comprising: a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, an isolation layer over sidewalls of the substrate within the opening, a plated metal plug sealing the opening through the metal layer, a plated metal over the isolation layer and filling the opening through the substrate, and the metal layer patterned to define a circuit trace extending from the plated metal plug to a contact pad on the first surface of the wafer.

34. A semiconductor device comprising the interposer of claim 33.

35. An interposer for an electrical component, comprising: a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, a conductive contact filling the opening and comprising a plated metal plug sealing the opening through the metal layer and a plated metal fill within the opening through the substrate, the conductive contact in electrical communication with a contact pad on each of the first and second surfaces of the substrate.

36. The interposer of claim 35, wherein at least one of the first and second surfaces of the substrate of the interposer comprise a plurality of contact pads arranged in a pattern corresponding to contact pads on the electrical component to be connected thereto.

37. The interposer of claim 35, wherein at least one of the first and second surfaces of the substrate of the interposer comprise a plurality of contact pads arranged in a pattern different than a pattern of bond pads on the electrical component to be connected thereto to provide rerouting of said bond pads.

38. An interposer for an electrical component, comprising: a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, a conductive contact filling the opening and comprising a plated metal plug sealing the opening through the metal layer and a plated metal fill within the opening through the substrate, a contact pad on each of the first and second surfaces of the substrate, the conductive contact in electrical communication with the contact pads wherein the metal layer is patterned to define a circuit trace extending from the conductive contact to the contact pad on the first surface of the substrate.

39. An assembly comprising an electrical component mounted on an interposer, the interposer comprising:

a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, a conductive contact filling the opening and comprising a plated metal plug sealing the opening through the metal layer and a plated metal fill within the opening through the substrate, the conductive contact in electrical communication with a contact pad on each of the first and second surfaces of the substrate.

40. An assembly comprising an electrical component mounted on an interposer, the interposer comprising:

a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, a conductive contact filling the opening and comprising a plated metal plug sealing the opening through the metal layer and a plated metal fill within the opening through the substrate, a plurality of contact pads on each of the first and second surfaces of the substrate, the conductive contact in electrical communication with at least one of said contact pads on each of the first and second surfaces of the substrate.

41. The assembly of claim 40, wherein the plurality of contact pads on the surface of the substrate of the interposer which the electrical component is mounted thereon are arranged in a pattern corresponding to contact pads of the electrical component.

42. The assembly of claim 40, wherein the plurality of contact pads on the surface of the substrate of the interposer which the electrical component is mounted thereon are arranged in a pattern different than a pattern of bond pads of the electrical component to provide rerouting of said bond pads.

43. The assembly of claim 40, wherein the electrical component is selected from the group consisting of a flip chip and a die package.

44. The assembly of claim 40, wherein the electrical component is selected from the group consisting of a test substrate, a higher level carrier substrate, a memory device, and a circuit board.

45. The assembly of claim 44, wherein the electrical component comprises a probe card for testing a semiconductor die.

46. An assembly comprising a semiconductor die mounted on an interposer, the interposer comprising:

a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, a conductive contact filling the opening and comprising an electrolessly plated metal plug sealing the opening through the metal layer and an electroplated plated metal fill within the opening through the substrate, and a plurality of contact pads on each of the first and second surfaces of the substrate, the conductive contact in electrical connection with at least one of said contact pads situated on the surface of the interposer substrate onto which the semiconductor die is mounted, and said contact pad on the interposer substrate in electrical communication with a contact pad of the semiconductor die.

47. An assembly comprising first and second electrical components mounted on an interposer, the interposer comprising:

a substrate having first and second surfaces, a layer of a metal on the first surface of the substrate, an opening extending through the substrate and the metal layer, a conductive contact filling the opening and comprising an electrolessly plated metal plug sealing the opening through the metal layer and an electroplated plated metal fill within the opening through the substrate, and a plurality of contact pads on each of the first and second surfaces of the interposer substrate, the conductive contact in electrical connection with at least one contact pad situated on each of the first and second surfaces of the interposer substrate, wherein the first and second electrical components are mounted, respectively, on the first and second surfaces of the interposer substrate, and each of the first and second electrical components have a contact pad in electrical connection to said contact pad situated, respectively, on the first surface and on the second surface of the interposer substrate.

48. The assembly of claim 47, wherein one of the electrical components is selected from the group consisting of a flip chip and a die package, and another of the electrical components is selected from the group consisting of a test substrate, a higher level carrier substrate, a memory device, and a circuit board.

49. A system, comprising:

a microprocessor; and

a memory device in communication with the microprocessor, the memory device comprising a device according to claim 1.

50. A system, comprising:

a microprocessor; and

a memory device in communication with the microprocessor, the memory device comprising an interposer according to claim 27.

51. A system, comprising:

a microprocessor; and

a memory device in communication with the microprocessor, the memory device comprising an interposer according to claim 35.