US20050227438A1 - Semiconductor device and method of manufacturing same - Google Patents
Semiconductor device and method of manufacturing same Download PDFInfo
- Publication number
- US20050227438A1 US20050227438A1 US11/140,756 US14075605A US2005227438A1 US 20050227438 A1 US20050227438 A1 US 20050227438A1 US 14075605 A US14075605 A US 14075605A US 2005227438 A1 US2005227438 A1 US 2005227438A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor
- electrode
- substrate
- semiconductor substrate
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 4
- 238000000227 grinding Methods 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 43
- 229910052710 silicon Inorganic materials 0.000 description 43
- 239000010703 silicon Substances 0.000 description 43
- 238000000034 method Methods 0.000 description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 239000000243 solution Substances 0.000 description 9
- 230000006378 damage Effects 0.000 description 6
- 239000007772 electrode material Substances 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 230000003746 surface roughness Effects 0.000 description 6
- 239000006227 byproduct Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 239000003082 abrasive agent Substances 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000003292 diminished effect Effects 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000010008 shearing Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000012188 paraffin wax Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/135—Removal of substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/928—Front and rear surface processing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/938—Lattice strain control or utilization
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/964—Roughened surface
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Definitions
- This invention relates to a semiconductor device which has a low ON-resistance, and further, to a method of manufacturing such a semiconductor device.
- Japanese Unexamined Patent Publication 1-169970 discloses a method which an N-type impurity layer is formed in a back surface of a drain substrate so as to reduce a contact resistance between the drain substrate and a drain electrode.
- Japanese Examined Patent Publication 58-45814 discloses a method of manufacturing the semiconductor device which has a good ohmic contact between the drain substrate and the drain electrode.
- the device has a multilayer metal electrode on a back surface of a drain substrate.
- the multilayer metal electrode consists of layers having a gold layer as a main layer.
- R ON R 1 +R 2 +R 3+ R 4+ R 5+ R 6+ R 7+ R 8+ R 9+ R 10
- R 1 denotes a contact resistance of a drain electrode 50
- R 2 denotes a contact resistance between the drain electrode 50 and an N-Type impurity layer 52
- R 3 denotes a resistance of N drain substrate 54
- R 4 , R 5 and R 6 denote resistances of N drain region 56 respectively
- R 7 denotes a resistance of P-Type diffusion region 58 for forming a channel
- R 8 denotes a resistance of N-type source 60
- R 9 denotes a contact resistance between the N-Type source 60 and a source electrode 62
- R 10 denotes a resistance of the source electrode 62 .
- the method by which the N-Type impurity layer is formed is complex because an oxide film adhered to the back surface of the N drain substrate 54 and a diffusion layer having an opposite conductive type (P) to that of the N drain substrate 54 must be removed before the N-type impurity layer 52 is formed.
- a semiconductor device for household use is demanded with a withstanding voltage more than 100V, normally more than 200V. It is a necessary to make a resistance of a epitaxial layer (the N drain region 56 ) formed on the N drain substrate 54 high to get the withstanding voltage. Therefore, the ratio of the resistance of the N drain substrate 54 to the resistance of the epitaxial layer becomes small.
- a semiconductor device for a motor vehicle is demanded with a withstanding voltage of at most 50-60V.
- the resistance of the epitaxial layer is relatively low, and the ratio of the resistance of N drain substrate 54 to the resistance of the epitaxial layer becomes large. Therefore, in the semiconductor device for a motor vehicle, it is effective to reduce the resistance of the N drain substrate 54 for reducing the ON-resistance.
- the N drain substrate 54 is warped by heat generated in a step that the N-Type impurity layer 52 is formed when the thickness t n of the N drain substrate 54 is too thin.
- the thickness t n needs to be thick to keep the strength thereof. Therefore, the resistance R 3 of the N drain substrate 54 becomes high, and thus the ON-resistance also becomes high.
- the technique by which the concentration of antimony (Sb) as a impurity in the N drain substrate 54 is heightened and the resistivity is diminished, may be adopted so as to reduce the resistance R 3 of the N drain substrate 54 .
- the barrier height of the gold for an P-type silicon substrate is 0.2 eV, and therefore so a good ohmic contact between those can be obtained.
- the barrier height of the gold for an N-type silicon substrate is relatively high, 0.8 eV, the contact between those becomes a schottky contact and may have undesirable diode character.
- An object of this invention is to reduce the ON-resistance of a semiconductor device.
- Another object of this invention is to get a good ohmic contact.
- a still further object of this invention is to provide a thin semiconductor device having the advantage of small stress from a package and easy wire bonding.
- a semiconductor device includes an N-type semi-conductor substrate including arsenic as an impurity and having a ground surface formed on one surface thereof, said ground surface having concavo-convex irregularities, a first electrode formed on another surface other than said one surface of said N-type semiconductor substrate, a second electrode formed on said ground surface and ohmically contacted with said N-type semiconductor substrate through said ground surface, and a semiconductor element formed in said N-type semiconductor substrate and in which an electric current flows between said first electrode and said second electrode during an ON-state thereof.
- FIG. 1 is a sectional view of a semiconductor device of this invention
- FIG. 2A-2C are sectional views showing the sequence of processes of the semiconductor device of this of this invention.
- FIG. 3 is a side view for explaining a surface grinding proceeding
- FIG. 4 is a side view for explaining a lapping grinding proceeding
- FIG. 5 shows a relationship between the thickness t and destructive strength
- FIG. 6 is a sectional view for explaining a load test
- FIG. 7 shows a relationship between the granularity of a grindstone and warp of the silicon substrate
- FIG. 8 shows a relationship between the impurity concentration and the contact resistance
- FIG. 9 shows a relationship between V DS and I DS of power MOS FET
- FIG. 10 shows a relationship between V F and the concentration of As in the silicon substrate
- FIG. 11 shows a relationship between the concentration of As and the value of the leak current
- FIG. 12 shows a relationship between the thickness t and shearing stress
- FIG. 13 is a sectional view of a semiconductor device of the prior art
- FIG. 14 shows a relationship between the granularity and surface roughness
- FIG. 15 shows a relationship between the granularity and an ON-resistance.
- FIG. 1 shows an N-type drain region 2 formed on a silicon substrate 1 which is doped with As (arsenic) formed by crystallizing melted silicon that has As therein.
- a P-type region 4 is formed in the N-type drain region 2 for forming a channel.
- An N-type source region 6 is formed in the P-type region 4 .
- a polycrystalline silicon gate 10 is formed on the N-type drain region 2 and the P-type region 4 through an oxide film (SiO 2 ) 8 .
- a source electrode 12 is formed on the oxide film 8 and electrically connected with the P-type region 4 and the N-type source region 6 .
- An ohmic electrode 26 is formed on a ground surface 22 which is formed on a back surface of the silicon substrate 1 .
- the prior art used Sb (antimony) as an N-type impurity.
- Sb antimony
- the concentration of Sb could not be more than 5 ⁇ 10 18 cm ⁇ 3 owing to its limitation of solution.
- the inventors have solved this problem by including As in the silicon substrate 1 as the N-type impurity. As has a higher limitation of solution than Sb and therefore solves this problem.
- the concentration of As is set within a range between 7 ⁇ 10 18 cm ⁇ 3 ⁇ 1 ⁇ 10 21 cm ⁇ 3 Therefore, the contact resistance between the silicon substrate 1 and the ohmic electrode 26 can be reduced sufficient to avoid a schottky contact and get an ohmic contact.
- the ground surface 22 has been ground to have a concavo-convex surface which has many coarse surface irregularities. Therefore, the ohmic electrode 26 can be firmly adhered to the ground surface 22 because the ground surface 22 has a suitable concavo-convex surface.
- FIG. 2A-2C show the sequence of the process.
- a silicon crystal is formed by a CZ (Czochralski) method, where As is added as a dopant in a melted silicon.
- the silicon substrate 1 is formed by slicing the silicon crystal. Therefore the silicon substrate 1 has As a solid solution, the concentration of As being 7 ⁇ 10 18 ⁇ 1 ⁇ 10 21 cm ⁇ 3 , and resistivity of the silicon wafer is less than 0.008 ⁇ cm.
- FIG. 2A shows the N-type drain region 2 having P (phosphorus) as an impurity and being grown on a main surface of the silicon substrate 1 by an epitaxial growth method.
- the oxide film (SiO 2 ) 8 is formed on a surface of the N-type drain region 2 .
- the polycrystalline silicon is deposited on the oxide film 8 by an LPCVD (low pressure chemical vapor deposition) technique.
- P (phosphorus) is introduced in the polycrystalline silicon, and the polycrystalline silicon is locally etched to form the polycrystalline silicon gate 10 .
- the polycrystalline silicon gate 10 is oxidized, and P-type impurities such as B (boron), Al (aluminium), Ga (gallium) or the like are diffused into the N-type drain region 2 by using this polycrystalline silicon gate 10 as a mask for forming the P-type region 4 .
- a portion of the P-type region 4 becomes a channel region.
- the N-type source region 6 is formed by locally diffusing N-type impurities such as As, P (phosphorus) or the like into the P-type region 4 .
- Windows are then opened in the oxide film 8 and Al—Si is deposited by a sputtering method for forming the source electrode 12 , so that the source electrode 12 is connected to both the P-type region 4 and the N-type source region 6 .
- a device layer 14 consists of the P-type region 4 , the N-type source region 6 , the oxide film 8 , the polycrystalline silicon gate 10 , and the source electrode 12 .
- a passivation film such as a plasma-SiN or the like may be formed on the source electrode 12 for stabilizing a surface of the device layer 14 .
- a by-product layer 16 such as a polycrystalline silicon, a silicon oxide (SiO 2 ) or the like, is spontaneously formed on another (back) surface of the silicon substrate 1 while the aforementioned device is being manufactured.
- the another surface of the silicon substrate 1 on which the by-product layer 16 is formed thereon is ground by a surface grinding (SG) proceeding for removing the by-product layer 16 .
- the surface grinding is carried out by using a grindstone 18 as shown in FIG. 3 .
- the granularity of the grindstone 18 is between No. 300-No. 500.
- a surface of the device layer 14 is covered with a adhesive film (not shown) and the device layer 14 is fixed by a vacuum chuck 20 .
- FIG. 2B shows the by-product layer 16 removed by the grinding, and a ground surface 22 being formed.
- the thickness t from one surface of the device layer 14 to the another surface of the silicon substrate 1 is 200-450 ⁇ m. After grinding, the whole device is washed by super pure water.
- the silicon crystal of the another surface of the silicon substrate 1 is damaged by the grinding. This damage destroys some part of the crystalline structure of the silicon substrate, and should therefore be avoided. It also decreases the destruction strength.
- the depth of this damaged layer is only 1-2 ⁇ m if the surface grinding device of FIG. 3 is used.
- FIG. 5 shows a graph of depth of the damaged layer. Because the depth of the damaged layer is shallow, the destruction strength of this device is still between 1.0-1.6 kg.
- FIG. 6 shows a load test where the destruction strength is defined as a maximum load when a chip destroyed. The load test is carried out in such a way that the center of the chip is supported at its both ends and has a load applied thereon by a load piece 24 .
- FIG. 4 shows the lapping grinding is carried out in the condition which the device is fixed on upper surface plate 30 by paraffin glue and abrasives (a mix of abrasives No. 800 and No. 1200 of SiC) are supplied between the device and a lower surface plate 32 .
- abrasives a mix of abrasives No. 800 and No. 1200 of SiC
- FIG. 7 shows that when the granularity of the grindstone 18 is No. 300-No. 500, the warping of the silicon substrate 1 can be reduced. If the granularity is finer than No. 500, however the warp becomes larger. If the granularity is coarser than No. 300, the possibility which of breaking of the silicon substrate 1 is increased.
- the reason why the warping is reduce is that the coarser the granularity is, the more stress in the silicon substrate is dispersed.
- FIG. 14 shows a relationship between the granularity of the grindstone 18 and surface roughness Ra.
- the surface roughness Ra is in a range between 0.3-0.6 ⁇ m.
- the surface roughness Ra is almost 0,2 ⁇ m.
- the surface roughness Ra becomes almost 0 ⁇ m. It is to be noted that surface roughness Ra of the silicon substrate 1 which is polished up is also almost 0 ⁇ m.
- FIG. 15 shows a relationship between the granularity of the grindstone 18 and an ON-resistance.
- the ON-resistance becomes low.
- barrier height of the ohmic electrode 26 for the silicon substrate 1 becomes high, and the contact resistance between the ohmic electrode 26 and the silicon substrate 1 .
- the granularity is a range between No. 320-No. 600 to reduce the ON-resistance.
- FIG. 2C snows that after the spontaneously formed by product layer 16 (not shown) has been removed by a wet etching or an RF etching, and an ohmic electrode 26 is formed on the ground surface 22 by a sputtering method.
- the ohmic electrode 26 acts as a drain electrode.
- the ohmic electrode 26 is a multilayer electrode consisting of Ti—Ni—Au layers.
- electrode material such as Ti (titanium), V (vanadium), Cr (chromium), Ni (nickel) or the like
- impurity concentration in the silicon substrate 1 more than 5 ⁇ 10 18 cm ⁇ 3 , preferably, more than 7 ⁇ 10 18 cm ⁇ 3 so as to make an ohmic contact with the electrode material.
- the barrier height ⁇ B of the electrode material for silicon is 0.4-0.6 eV. As shown in FIG.
- the contact resistance between the electrode material and the silicon substrate 1 begins to rapidly be reduced, and if the impurity concentration is more than 7 ⁇ 10 18 cm ⁇ 3 , the contact resistance becomes less than 10 ⁇ 3 ⁇ cm 2 .
- FIG. 9 shows a relationship between V DS (voltage between the source and the drain) and I DS (current between the source and drain) of this power MOS FET.
- Voltage of the gate V G is a parameter shown in Figure as being used as an index so as to judge whether the contact is a schottky contact.
- FIG. 10 shows a relationship between this calculated V F and a concentration of As in the silicon substrate 1 .
- V F becomes substantially 0(zero) and the contact is an ohmic contact.
- the upper limitation of the concentration of As which is included in the silicon substrate 1 is its limitation of solution. This limitation is found by measuring the value of leakage current through the P-N junction.
- FIG. 11 shows a relationship between the concentration of As and the value of the leakage current through the P-N junction.
- a P-type impurity such as B(boron) or the like is diffused in an N-type silicon substrate including As as an impurity.
- the concentration of As is higher than its limitation of solution, the crystallinity of silicon is disordered and leakage current flows through the P-N junction. Therefore, the concentration when the leakage current begins to flow is defined as the value of its limitation of solution. As shown in FIG. 11 , the limitation of solution is 1 ⁇ 10 21 cm ⁇ 3 .
- the chip which was manufactured by abovementioned manufacturing steps is molded by silicone resin, and an IC package is formed.
- this molding step because a thickness of the chip is thin, as shown in FIG. 12 , the shearing stress becomes low. Consequently, the stress of the IC package is relaxed.
- a lead frame (not shown) is bonded to the source electrode 12 with a wire, the wire-bonding work becomes easy because the height of the lead frame and the source electrode 12 are similar and therefore these makes a low step.
- the present invention has been described with reference to the abovementioned embodiment, but the present invention is not limited to this embodiment and can be modified without departing from the spirit or concept of the present invention.
- the present invention may be applied to an IGBT (Insulated Gate Bipolar Transistor), SIT (Static Induction Transistor), SI (State Induction) thyristor or the like other than the power MOSFET.
- IGBT Insulated Gate Bipolar Transistor
- SIT Static Induction Transistor
- SI State Induction
Abstract
A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.
Description
- This application is a divisional of U.S. Ser. No. 10/880,048 filed Jun. 29, 2004, which is a divisional of U.S. Ser. No. 10/880,044 filed Jun. 29, 2004, which is a divisional of U.S. Ser. No. 10/651,277 filed Aug. 28, 2003, which is a divisional of Ser. No. 10/283,981 filed Oct. 30, 2002, now U.S. Pat. No. 6,649,478 which is a divisional of Ser. No. 08/962,322 filed Oct. 31, 1997, now U.S. Pat. No. 6,498,366 which is a divisional of Ser. No. 08/409,900 filed Mar. 22, 1995 now U.S. Pat. No. 5,689,130 which is a continuation of Ser. No. 07/953,766 filed Sep. 30, 1992, ABD, which is a divisional of Ser. No. 07/652,920 filed Feb. 8, 1991 now U.S. Pat. No. 5,242,862. This application claims the benefit of JPSN P2-33367, filed Feb. 14, 1990. The disclosure of the above applications are incorporated herein by reference.
- 1. Field of the Invention
- This invention relates to a semiconductor device which has a low ON-resistance, and further, to a method of manufacturing such a semiconductor device.
- 2. Description of the Related Art
- Many kinds of methods of manufacturing for reducing an ON-resistance of a semiconductor device have been known. For example, Japanese Unexamined Patent Publication 1-169970 discloses a method which an N-type impurity layer is formed in a back surface of a drain substrate so as to reduce a contact resistance between the drain substrate and a drain electrode. Japanese Examined Patent Publication 58-45814 discloses a method of manufacturing the semiconductor device which has a good ohmic contact between the drain substrate and the drain electrode. The device has a multilayer metal electrode on a back surface of a drain substrate. The multilayer metal electrode consists of layers having a gold layer as a main layer.
- As shown in
FIG. 13 , the ON-resistance of a field effect transistor (FET) is represented by the following equation:
R ON =R1+R2+R3+R4+R5+R6+R7+R8+R9+R10
wherein, R1 denotes a contact resistance of adrain electrode 50; R2 denotes a contact resistance between thedrain electrode 50 and an N-Type impurity layer 52; R3 denotes a resistance ofN drain substrate 54; R4, R5 and R6 denote resistances ofN drain region 56 respectively; R7 denotes a resistance of P-Type diffusion region 58 for forming a channel; R8 denotes a resistance of N-type source 60; R9 denotes a contact resistance between the N-Type source 60 and asource electrode 62; and R10 denotes a resistance of thesource electrode 62. - However, such a conventional method of manufacturing the semiconductor device has many problems. For example, the method by which the N-Type impurity layer is formed is complex because an oxide film adhered to the back surface of the
N drain substrate 54 and a diffusion layer having an opposite conductive type (P) to that of theN drain substrate 54 must be removed before the N-type impurity layer 52 is formed. - A semiconductor device for household use is demanded with a withstanding voltage more than 100V, normally more than 200V. It is a necessary to make a resistance of a epitaxial layer (the N drain region 56) formed on the
N drain substrate 54 high to get the withstanding voltage. Therefore, the ratio of the resistance of theN drain substrate 54 to the resistance of the epitaxial layer becomes small. On the contrary, a semiconductor device for a motor vehicle is demanded with a withstanding voltage of at most 50-60V. The resistance of the epitaxial layer is relatively low, and the ratio of the resistance ofN drain substrate 54 to the resistance of the epitaxial layer becomes large. Therefore, in the semiconductor device for a motor vehicle, it is effective to reduce the resistance of theN drain substrate 54 for reducing the ON-resistance. - The resistance R3 of the
N drain substrate 54 is represented by the following equation:
R3=ρN ×t n /S
wherein, ρN denotes resistivity of theN drain substrate 54; tn denotes a thickness of theN drain substrate 54; and S denotes a cross section of theN drain substrate 54. It is necessary to reduce the thickness tn of theN drain substrate 54 so as to reduce this resistance R3. However, the thickness tn of theN drain substrate 54 for forming the N-Type impurity layer 52 is determined in accordance with a thickness of a silicon wafer. The reason is that theN drain substrate 54 is warped by heat generated in a step that the N-Type impurity layer 52 is formed when the thickness tn of theN drain substrate 54 is too thin. To get a wafer of large diameter, the thickness tn needs to be thick to keep the strength thereof. Therefore, the resistance R3 of theN drain substrate 54 becomes high, and thus the ON-resistance also becomes high. - The technique by which the concentration of antimony (Sb) as a impurity in the
N drain substrate 54 is heightened and the resistivity is diminished, may be adopted so as to reduce the resistance R3 of theN drain substrate 54. However, it is impossible to make the resistance R3 less than 0.01Ω·cm because of the limitation of the amount solution of Sb which can be in the solution. - Moreover, since it is impossible to make the impurity concentration in the substrate high because of the limitation of solution, it is difficult to get a good ohmic contact between an N-type substrate and an electrode.
- On the other hand, in the method which utilizes gold as an electrode material, the barrier height of the gold for an P-type silicon substrate is 0.2 eV, and therefore so a good ohmic contact between those can be obtained. However, since the barrier height of the gold for an N-type silicon substrate is relatively high, 0.8 eV, the contact between those becomes a schottky contact and may have undesirable diode character.
- Moreover, when an overall thickness is thick, stress from a package and a step between a lead frame and the
source electrode 62 becomes higher. Therefore, the wire bonding work becomes very difficult. Also, the cost of gold is very high. - Techniques other than the aforementioned techniques have also been known. The technique which is disclosed in Japanese Unexamined Patent Publication 57-15420 suggests that a back surface of a silicon substrate is ground to improve adherence between the back surface and a collector electrode formed on the back surface. The technique which is disclosed in “IEEE ELECTRON DEVICE LETTERS, VOL. 10, NO. 3 MARCH 1989, P101-103” suggests that a 0.004Ω·cm arsenic-doped silicon substrate is used.
- An object of this invention is to reduce the ON-resistance of a semiconductor device.
- Another object of this invention is to get a good ohmic contact.
- A still further object of this invention is to provide a thin semiconductor device having the advantage of small stress from a package and easy wire bonding.
- To accomplish the above objects, a semiconductor device according to this invention includes an N-type semi-conductor substrate including arsenic as an impurity and having a ground surface formed on one surface thereof, said ground surface having concavo-convex irregularities, a first electrode formed on another surface other than said one surface of said N-type semiconductor substrate, a second electrode formed on said ground surface and ohmically contacted with said N-type semiconductor substrate through said ground surface, and a semiconductor element formed in said N-type semiconductor substrate and in which an electric current flows between said first electrode and said second electrode during an ON-state thereof.
-
FIG. 1 is a sectional view of a semiconductor device of this invention; -
FIG. 2A-2C are sectional views showing the sequence of processes of the semiconductor device of this of this invention; -
FIG. 3 is a side view for explaining a surface grinding proceeding; -
FIG. 4 is a side view for explaining a lapping grinding proceeding; -
FIG. 5 shows a relationship between the thickness t and destructive strength; -
FIG. 6 is a sectional view for explaining a load test; -
FIG. 7 shows a relationship between the granularity of a grindstone and warp of the silicon substrate; -
FIG. 8 shows a relationship between the impurity concentration and the contact resistance; -
FIG. 9 shows a relationship between V DS and IDS of power MOS FET; -
FIG. 10 shows a relationship between V F and the concentration of As in the silicon substrate; -
FIG. 11 shows a relationship between the concentration of As and the value of the leak current; -
FIG. 12 shows a relationship between the thickness t and shearing stress; -
FIG. 13 is a sectional view of a semiconductor device of the prior art; -
FIG. 14 shows a relationship between the granularity and surface roughness; and -
FIG. 15 shows a relationship between the granularity and an ON-resistance. - The preferred embodiments of this invention will be described with reference to the drawings. The embodiments are suitable for a semiconductor device for a motor vehicle.
-
FIG. 1 shows an N-type drain region 2 formed on asilicon substrate 1 which is doped with As (arsenic) formed by crystallizing melted silicon that has As therein. A P-type region 4 is formed in the N-type drain region 2 for forming a channel. An N-type source region 6 is formed in the P-type region 4. Apolycrystalline silicon gate 10 is formed on the N-type drain region 2 and the P-type region 4 through an oxide film (SiO2) 8. Asource electrode 12 is formed on theoxide film 8 and electrically connected with the P-type region 4 and the N-type source region 6. Anohmic electrode 26 is formed on aground surface 22 which is formed on a back surface of thesilicon substrate 1. - Here, the prior art used Sb (antimony) as an N-type impurity. However, the concentration of Sb could not be more than 5×1018cm−3 owing to its limitation of solution. The inventors have solved this problem by including As in the
silicon substrate 1 as the N-type impurity. As has a higher limitation of solution than Sb and therefore solves this problem. The concentration of As is set within a range between 7×1018 cm−3−1×1021 cm−3 Therefore, the contact resistance between thesilicon substrate 1 and theohmic electrode 26 can be reduced sufficient to avoid a schottky contact and get an ohmic contact. Since the concentration of As is more than 7×1018 cm−3, a good ohmic contact can be obtained for almost all electrode materials. Moreover, the resistivity of thesilicon substrate 1 is also diminished because of the higher concentration of As included in thesilicon substrate 1 as an impurity. Consequently, the resistance R3 of thesilicon substrate 1 is also reduced. Theground surface 22 has been ground to have a concavo-convex surface which has many coarse surface irregularities. Therefore, theohmic electrode 26 can be firmly adhered to theground surface 22 because theground surface 22 has a suitable concavo-convex surface. - The process of forming the aforementioned semiconductor device of the embodiment of this invention will now be described with reference to
FIG. 2A-2C .FIG. 2A-2C show the sequence of the process. A silicon crystal is formed by a CZ (Czochralski) method, where As is added as a dopant in a melted silicon. Thesilicon substrate 1 is formed by slicing the silicon crystal. Therefore thesilicon substrate 1 has As a solid solution, the concentration of As being 7×1018−1×1021 cm−3, and resistivity of the silicon wafer is less than 0.008Ω·cm.FIG. 2A shows the N-type drain region 2 having P (phosphorus) as an impurity and being grown on a main surface of thesilicon substrate 1 by an epitaxial growth method. The oxide film (SiO2) 8 is formed on a surface of the N-type drain region 2. The polycrystalline silicon is deposited on theoxide film 8 by an LPCVD (low pressure chemical vapor deposition) technique. P (phosphorus) is introduced in the polycrystalline silicon, and the polycrystalline silicon is locally etched to form thepolycrystalline silicon gate 10. Thepolycrystalline silicon gate 10 is oxidized, and P-type impurities such as B (boron), Al (aluminium), Ga (gallium) or the like are diffused into the N-type drain region 2 by using thispolycrystalline silicon gate 10 as a mask for forming the P-type region 4. A portion of the P-type region 4 becomes a channel region. The N-type source region 6 is formed by locally diffusing N-type impurities such as As, P (phosphorus) or the like into the P-type region 4. Windows are then opened in theoxide film 8 and Al—Si is deposited by a sputtering method for forming thesource electrode 12, so that thesource electrode 12 is connected to both the P-type region 4 and the N-type source region 6. Here, adevice layer 14 consists of the P-type region 4, the N-type source region 6, theoxide film 8, thepolycrystalline silicon gate 10, and thesource electrode 12. Moreover, a passivation film such as a plasma-SiN or the like may be formed on thesource electrode 12 for stabilizing a surface of thedevice layer 14. - During this process, a by-
product layer 16, such as a polycrystalline silicon, a silicon oxide (SiO2) or the like, is spontaneously formed on another (back) surface of thesilicon substrate 1 while the aforementioned device is being manufactured. The another surface of thesilicon substrate 1 on which the by-product layer 16 is formed thereon is ground by a surface grinding (SG) proceeding for removing the by-product layer 16. The surface grinding is carried out by using a grindstone 18 as shown inFIG. 3 . The granularity of the grindstone 18 is between No. 300-No. 500. In this embodiment, a surface of thedevice layer 14 is covered with a adhesive film (not shown) and thedevice layer 14 is fixed by avacuum chuck 20. -
FIG. 2B shows the by-product layer 16 removed by the grinding, and aground surface 22 being formed. In this condition, the thickness t from one surface of thedevice layer 14 to the another surface of thesilicon substrate 1 is 200-450 μm. After grinding, the whole device is washed by super pure water. - The silicon crystal of the another surface of the
silicon substrate 1 is damaged by the grinding. This damage destroys some part of the crystalline structure of the silicon substrate, and should therefore be avoided. It also decreases the destruction strength. However, the depth of this damaged layer is only 1-2 μm if the surface grinding device ofFIG. 3 is used.FIG. 5 shows a graph of depth of the damaged layer. Because the depth of the damaged layer is shallow, the destruction strength of this device is still between 1.0-1.6 kg.FIG. 6 shows a load test where the destruction strength is defined as a maximum load when a chip destroyed. The load test is carried out in such a way that the center of the chip is supported at its both ends and has a load applied thereon by aload piece 24. - If the another surface of the
silicon substrate 1 is ground by lapping grinding instead of surface grinding, the depth of the damaged layer is 6-7 μm, and the destruction strength of this device becomes 0.3-0.6 kg (shown inFIG. 5 ).FIG. 4 shows the lapping grinding is carried out in the condition which the device is fixed onupper surface plate 30 by paraffin glue and abrasives (a mix of abrasives No. 800 and No. 1200 of SiC) are supplied between the device and alower surface plate 32. As understood by comparing the two lines inFIG. 5 , surface grinding will make the destruction strength stronger than lapping grinding. -
FIG. 7 shows that when the granularity of the grindstone 18 is No. 300-No. 500, the warping of thesilicon substrate 1 can be reduced. If the granularity is finer than No. 500, however the warp becomes larger. If the granularity is coarser than No. 300, the possibility which of breaking of thesilicon substrate 1 is increased. - The reason why the warping is reduce is that the coarser the granularity is, the more stress in the silicon substrate is dispersed.
-
FIG. 14 shows a relationship between the granularity of the grindstone 18 and surface roughness Ra. When the granularity is No. 320, the surface roughness Ra is in a range between 0.3-0.6 μm. When the granularity is No. 600, the surface roughness Ra is almost 0,2 μm. When the granularity is No. 4000, the surface roughness Ra becomes almost 0 μm. It is to be noted that surface roughness Ra of thesilicon substrate 1 which is polished up is also almost 0 μm. -
FIG. 15 shows a relationship between the granularity of the grindstone 18 and an ON-resistance. As shown inFIG. 15 , when the granularity is coarser, the ON-resistance becomes low. The reason is that when the granularity is coarser, barrier height of theohmic electrode 26 for thesilicon substrate 1 becomes high, and the contact resistance between theohmic electrode 26 and thesilicon substrate 1. It is desirable that the granularity is a range between No. 320-No. 600 to reduce the ON-resistance. -
FIG. 2C snows that after the spontaneously formed by product layer 16 (not shown) has been removed by a wet etching or an RF etching, and anohmic electrode 26 is formed on theground surface 22 by a sputtering method. Theohmic electrode 26 acts as a drain electrode. In this embodiment, theohmic electrode 26 is a multilayer electrode consisting of Ti—Ni—Au layers. When electrode material, such as Ti (titanium), V (vanadium), Cr (chromium), Ni (nickel) or the like, is adopted, it is necessary to make an impurity concentration in thesilicon substrate 1 more than 5×1018 cm−3, preferably, more than 7×1018 cm−3 so as to make an ohmic contact with the electrode material. The barrier height ΦB of the electrode material for silicon is 0.4-0.6 eV. As shown inFIG. 8 , if the impurity concentration is more than 5×1018cm−3, the contact resistance between the electrode material and thesilicon substrate 1 begins to rapidly be reduced, and if the impurity concentration is more than 7×1018cm−3, the contact resistance becomes less than 10−3Ω·cm2. -
FIG. 9 shows a relationship between V DS (voltage between the source and the drain) and I DS (current between the source and drain) of this power MOS FET. Voltage of the gate V G is a parameter shown in Figure as being used as an index so as to judge whether the contact is a schottky contact. -
FIG. 10 shows a relationship between this calculated V F and a concentration of As in thesilicon substrate 1. As shown inFIG. 10 , when the concentration of As is more than 7×1018 cm−3, V F becomes substantially 0(zero) and the contact is an ohmic contact. - The upper limitation of the concentration of As which is included in the
silicon substrate 1 is its limitation of solution. This limitation is found by measuring the value of leakage current through the P-N junction. -
FIG. 11 shows a relationship between the concentration of As and the value of the leakage current through the P-N junction. Before the value of the leakage current is measured, to form P-N junction, a P-type impurity such as B(boron) or the like is diffused in an N-type silicon substrate including As as an impurity. When the concentration of As is higher than its limitation of solution, the crystallinity of silicon is disordered and leakage current flows through the P-N junction. Therefore, the concentration when the leakage current begins to flow is defined as the value of its limitation of solution. As shown inFIG. 11 , the limitation of solution is 1×1021 cm−3. - The chip which was manufactured by abovementioned manufacturing steps is molded by silicone resin, and an IC package is formed. In this molding step, because a thickness of the chip is thin, as shown in
FIG. 12 , the shearing stress becomes low. Consequently, the stress of the IC package is relaxed. Moreover, when a lead frame (not shown) is bonded to thesource electrode 12 with a wire, the wire-bonding work becomes easy because the height of the lead frame and thesource electrode 12 are similar and therefore these makes a low step. - The present invention has been described with reference to the abovementioned embodiment, but the present invention is not limited to this embodiment and can be modified without departing from the spirit or concept of the present invention. For example, the present invention may be applied to an IGBT (Insulated Gate Bipolar Transistor), SIT (Static Induction Transistor), SI (State Induction) thyristor or the like other than the power MOSFET. These semiconductor elements flow current in a vertical direction (a direction of a thickness of a substrate) and an electrode formed on N-type silicon substrate.
Claims (4)
1. A method of manufacturing a vertical type semiconductor device comprising:
preparing a semiconductor wafer which has a heavily doped semiconductor substrate doped with arsenic as an impurity and a lightly doped semiconductor layer disposed over said semiconductor substrate;
forming a semiconductor element at a surface portion of said semiconductor layer;
forming a first metal layer for a first electrode of said semiconductor element over said surface portion of said semiconductor layer;
grinding a back of said semiconductor substrate to thin said semiconductor substrate and roughen a back surface of said semiconductor substrate, said grinding being performed until a thickness from a surface of said first metal layer to said back surface is 200-450 microns;
performing a RF etching upon said back surface; and
forming on said back surface a second metal layer for a second electrode of said semiconductor element.
2. A method of manufacturing a vertical type semiconductor device according to claim 1 , wherein said forming of said second metal layer includes forming by a sputtering method.
3. A method of manufacturing a vertical type semiconductor device comprising:
preparing a semiconductor wafer which has a heavily doped semiconductor substrate and a lightly doped semiconductor layer disposed over said semiconductor substrate;
forming a semiconductor element at a surface portion of said semiconductor layer;
forming a first metal layer for a first electrode of said semiconductor element over said surface portion of said semiconductor layer;
grinding a back of said semiconductor substrate to thin said semiconductor substrate and roughen a back surface of said semiconductor substrate;
performing a RF etching upon said back surface; and
forming on said back surface a second metal layer for a second electrode of said semiconductor element.
4. A method of manufacturing a vertical type semiconductor device according to claim 3 , wherein said forming of said second metal layer includes forming by a sputtering method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/140,756 US20050227438A1 (en) | 1990-02-14 | 2005-05-31 | Semiconductor device and method of manufacturing same |
Applications Claiming Priority (11)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JPP2-33367 | 1990-02-14 | ||
JP2033367A JP2513055B2 (en) | 1990-02-14 | 1990-02-14 | Method for manufacturing semiconductor device |
US07/652,920 US5242862A (en) | 1990-02-14 | 1991-02-08 | Semiconductor device and method of manufacturing same |
US95376692A | 1992-09-30 | 1992-09-30 | |
US08/409,900 US5689130A (en) | 1990-02-14 | 1995-03-22 | Vertical semiconductor device with ground surface providing a reduced ON resistance |
US08/962,322 US6498366B1 (en) | 1990-02-14 | 1997-10-31 | Semiconductor device that exhibits decreased contact resistance between substrate and drain electrode |
US10/283,981 US6649478B2 (en) | 1990-02-14 | 2002-10-30 | Semiconductor device and method of manufacturing same |
US10/651,277 US6903417B2 (en) | 1990-02-14 | 2003-08-28 | Power semiconductor device |
US10/880,044 US7064033B2 (en) | 1990-02-14 | 2004-06-29 | Semiconductor device and method of manufacturing same |
US10/880,048 US6949434B2 (en) | 1990-02-14 | 2004-06-29 | Method of manufacturing a vertical semiconductor device |
US11/140,756 US20050227438A1 (en) | 1990-02-14 | 2005-05-31 | Semiconductor device and method of manufacturing same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/880,048 Division US6949434B2 (en) | 1990-02-14 | 2004-06-29 | Method of manufacturing a vertical semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050227438A1 true US20050227438A1 (en) | 2005-10-13 |
Family
ID=12384616
Family Applications (10)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/652,920 Expired - Lifetime US5242862A (en) | 1990-02-14 | 1991-02-08 | Semiconductor device and method of manufacturing same |
US08/409,900 Expired - Lifetime US5689130A (en) | 1990-02-14 | 1995-03-22 | Vertical semiconductor device with ground surface providing a reduced ON resistance |
US08/473,775 Expired - Lifetime US5663096A (en) | 1990-02-14 | 1995-06-06 | Method of manufacturing a vertical semiconductor device with ground surface providing a reduced ON resistance |
US08/962,322 Expired - Fee Related US6498366B1 (en) | 1990-02-14 | 1997-10-31 | Semiconductor device that exhibits decreased contact resistance between substrate and drain electrode |
US08/962,278 Expired - Fee Related US5994187A (en) | 1990-02-14 | 1997-10-31 | Method of manufacturing a vertical semiconductor device |
US10/283,981 Expired - Fee Related US6649478B2 (en) | 1990-02-14 | 2002-10-30 | Semiconductor device and method of manufacturing same |
US10/651,277 Expired - Fee Related US6903417B2 (en) | 1990-02-14 | 2003-08-28 | Power semiconductor device |
US10/880,048 Expired - Fee Related US6949434B2 (en) | 1990-02-14 | 2004-06-29 | Method of manufacturing a vertical semiconductor device |
US10/880,044 Expired - Fee Related US7064033B2 (en) | 1990-02-14 | 2004-06-29 | Semiconductor device and method of manufacturing same |
US11/140,756 Abandoned US20050227438A1 (en) | 1990-02-14 | 2005-05-31 | Semiconductor device and method of manufacturing same |
Family Applications Before (9)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/652,920 Expired - Lifetime US5242862A (en) | 1990-02-14 | 1991-02-08 | Semiconductor device and method of manufacturing same |
US08/409,900 Expired - Lifetime US5689130A (en) | 1990-02-14 | 1995-03-22 | Vertical semiconductor device with ground surface providing a reduced ON resistance |
US08/473,775 Expired - Lifetime US5663096A (en) | 1990-02-14 | 1995-06-06 | Method of manufacturing a vertical semiconductor device with ground surface providing a reduced ON resistance |
US08/962,322 Expired - Fee Related US6498366B1 (en) | 1990-02-14 | 1997-10-31 | Semiconductor device that exhibits decreased contact resistance between substrate and drain electrode |
US08/962,278 Expired - Fee Related US5994187A (en) | 1990-02-14 | 1997-10-31 | Method of manufacturing a vertical semiconductor device |
US10/283,981 Expired - Fee Related US6649478B2 (en) | 1990-02-14 | 2002-10-30 | Semiconductor device and method of manufacturing same |
US10/651,277 Expired - Fee Related US6903417B2 (en) | 1990-02-14 | 2003-08-28 | Power semiconductor device |
US10/880,048 Expired - Fee Related US6949434B2 (en) | 1990-02-14 | 2004-06-29 | Method of manufacturing a vertical semiconductor device |
US10/880,044 Expired - Fee Related US7064033B2 (en) | 1990-02-14 | 2004-06-29 | Semiconductor device and method of manufacturing same |
Country Status (2)
Country | Link |
---|---|
US (10) | US5242862A (en) |
JP (1) | JP2513055B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070111480A1 (en) * | 2005-11-16 | 2007-05-17 | Denso Corporation | Wafer product and processing method therefor |
US20080006856A1 (en) * | 2006-06-22 | 2008-01-10 | Fuji Electric Device Technology Co., Ltd | Semiconductor device with back surface electrode including a stress relaxation film |
US20110039382A1 (en) * | 2006-12-07 | 2011-02-17 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20130256964A1 (en) * | 2012-03-27 | 2013-10-03 | Mitsubishi Electric Corporation | Wafer suction method, wafer suction stage, and wafer suction system |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2513055B2 (en) | 1990-02-14 | 1996-07-03 | 日本電装株式会社 | Method for manufacturing semiconductor device |
JP3412332B2 (en) * | 1995-04-26 | 2003-06-03 | 株式会社デンソー | Semiconductor device |
JP3498431B2 (en) * | 1995-07-04 | 2004-02-16 | 株式会社デンソー | Method for manufacturing semiconductor device |
US6478977B1 (en) * | 1995-09-13 | 2002-11-12 | Hitachi, Ltd. | Polishing method and apparatus |
US5698474A (en) * | 1996-02-26 | 1997-12-16 | Hypervision, Inc. | High speed diamond-based machining of silicon semiconductor die in wafer and packaged form for backside emission microscope detection |
US6613674B1 (en) * | 1997-11-12 | 2003-09-02 | Micron Technology, Inc. | Semiconductor processing methods of forming integrated circuitry, and methods of forming dynamic random access memory circuitry |
US5963406A (en) | 1997-12-19 | 1999-10-05 | Leviton Manufacturing Co., Inc. | Arc fault detector with circuit interrupter |
US6104062A (en) * | 1998-06-30 | 2000-08-15 | Intersil Corporation | Semiconductor device having reduced effective substrate resistivity and associated methods |
JP3339838B2 (en) * | 1999-06-07 | 2002-10-28 | ローム株式会社 | Semiconductor device and method of manufacturing the same |
US6184064B1 (en) * | 2000-01-12 | 2001-02-06 | Micron Technology, Inc. | Semiconductor die back side surface and method of fabrication |
US20070042549A1 (en) * | 2000-04-17 | 2007-02-22 | Fairchild Semiconductor Corporation | Semiconductor device having reduced effective substrate resistivity and associated methods |
FR2818443B1 (en) * | 2000-12-20 | 2003-10-31 | Sagem | METHOD FOR MANUFACTURING INFRARED MATRIX DETECTOR WITH LIGHTING FROM THE REAR PANEL |
DE10205323B4 (en) * | 2001-02-09 | 2011-03-24 | Fuji Electric Systems Co., Ltd. | Method for producing a semiconductor component |
US6630369B2 (en) * | 2001-07-17 | 2003-10-07 | Ultra Tec Manufacturing, Inc. | Sample preparation apparatus and method |
JP3580293B2 (en) * | 2002-03-26 | 2004-10-20 | 株式会社デンソー | Method for manufacturing semiconductor device |
US7145254B2 (en) * | 2001-07-26 | 2006-12-05 | Denso Corporation | Transfer-molded power device and method for manufacturing transfer-molded power device |
US7148125B2 (en) * | 2001-12-12 | 2006-12-12 | Denso Corporation | Method for manufacturing semiconductor power device |
US7169685B2 (en) | 2002-02-25 | 2007-01-30 | Micron Technology, Inc. | Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive |
DK174717B1 (en) * | 2002-05-22 | 2003-10-06 | Danfoss Drives As | Engine control containing an electronic circuit for protection against inrush currents |
US7084423B2 (en) | 2002-08-12 | 2006-08-01 | Acorn Technologies, Inc. | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
US6833556B2 (en) * | 2002-08-12 | 2004-12-21 | Acorn Technologies, Inc. | Insulated gate field effect transistor having passivated schottky barriers to the channel |
JP3870896B2 (en) * | 2002-12-11 | 2007-01-24 | 株式会社デンソー | Semiconductor device manufacturing method and semiconductor device manufactured thereby |
US6879050B2 (en) * | 2003-02-11 | 2005-04-12 | Micron Technology, Inc. | Packaged microelectronic devices and methods for packaging microelectronic devices |
US7529847B2 (en) * | 2003-03-20 | 2009-05-05 | Microsoft Corporation | Access to audio output via capture service |
DE10338078B4 (en) * | 2003-08-19 | 2008-10-16 | Infineon Technologies Ag | Semiconductor element with improved adhesion properties of the non-metallic surfaces and method for its production |
DE10345494B4 (en) * | 2003-09-30 | 2016-04-07 | Infineon Technologies Ag | Method for processing a thin semiconductor substrate |
JP4878738B2 (en) * | 2004-04-30 | 2012-02-15 | 株式会社ディスコ | Semiconductor device processing method |
US7384826B2 (en) * | 2004-06-29 | 2008-06-10 | International Rectifier Corporation | Method of forming ohmic contact to a semiconductor body |
US8901699B2 (en) | 2005-05-11 | 2014-12-02 | Cree, Inc. | Silicon carbide junction barrier Schottky diodes with suppressed minority carrier injection |
JP4221012B2 (en) * | 2006-06-12 | 2009-02-12 | トヨタ自動車株式会社 | Semiconductor device and manufacturing method thereof |
DE112007001701B4 (en) * | 2006-07-20 | 2018-03-15 | Sumco Techxiv Corp. | Method for injection of dopant, doping device and pulling device |
FR2914488B1 (en) * | 2007-03-30 | 2010-08-27 | Soitec Silicon On Insulator | DOPE HEATING SUBSTRATE |
JPWO2010109572A1 (en) | 2009-03-23 | 2012-09-20 | トヨタ自動車株式会社 | Semiconductor device |
JP5726434B2 (en) * | 2010-04-14 | 2015-06-03 | 浜松ホトニクス株式会社 | Semiconductor photo detector |
US9159825B2 (en) | 2010-10-12 | 2015-10-13 | Silanna Semiconductor U.S.A., Inc. | Double-sided vertical semiconductor device with thinned substrate |
CN105448998B (en) | 2010-10-12 | 2019-09-03 | 高通股份有限公司 | IC chip and vertical power device |
CN102522326B (en) * | 2011-12-14 | 2014-09-24 | 杭州立昂微电子股份有限公司 | Production method of semiconductor discrete device back side metal suitable for screen printing |
US8778735B1 (en) * | 2013-06-29 | 2014-07-15 | Alpha & Omega Semiconductor, Inc. | Packaging method of molded wafer level chip scale package (WLCSP) |
JP2014157957A (en) * | 2013-02-18 | 2014-08-28 | Mitsubishi Electric Corp | Semiconductor device |
JP2014207382A (en) | 2013-04-15 | 2014-10-30 | ラピスセミコンダクタ株式会社 | Semiconductor device manufacturing method and semiconductor device |
US20150118810A1 (en) * | 2013-10-24 | 2015-04-30 | Madhur Bobde | Buried field ring field effect transistor (buf-fet) integrated with cells implanted with hole supply path |
US9620611B1 (en) | 2016-06-17 | 2017-04-11 | Acorn Technology, Inc. | MIS contact structure with metal oxide conductor |
US10170627B2 (en) | 2016-11-18 | 2019-01-01 | Acorn Technologies, Inc. | Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height |
US11398434B2 (en) * | 2017-09-20 | 2022-07-26 | Mitsubishi Electric Corporation | Semiconductor device, and method for manufacturing semiconductor device |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4213818A (en) * | 1979-01-04 | 1980-07-22 | Signetics Corporation | Selective plasma vapor etching process |
US4782028A (en) * | 1987-08-27 | 1988-11-01 | Santa Barbara Research Center | Process methodology for two-sided fabrication of devices on thinned silicon |
US4859626A (en) * | 1988-06-03 | 1989-08-22 | Texas Instruments Incorporated | Method of forming thin epitaxial layers using multistep growth for autodoping control |
US4879250A (en) * | 1988-09-29 | 1989-11-07 | The Boeing Company | Method of making a monolithic interleaved LED/PIN photodetector array |
US4902641A (en) * | 1987-07-31 | 1990-02-20 | Motorola, Inc. | Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure |
US4985740A (en) * | 1989-06-01 | 1991-01-15 | General Electric Company | Power field effect devices having low gate sheet resistance and low ohmic contact resistance |
Family Cites Families (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US1053694A (en) | 1910-04-29 | 1913-02-18 | Union Paper Company | Feeding mechanism for blanking and forming machines. |
US1469757A (en) | 1921-09-30 | 1923-10-02 | Edward L Sibley Mfg Company In | Blanking-out eyelets |
US3083926A (en) | 1959-06-17 | 1963-04-02 | Herr Equipment Corp | Strip handling |
US3278813A (en) * | 1964-04-22 | 1966-10-11 | Gen Electric | Transistor housing containing packed, earthy, nonmetallic, electrically insulating material |
US3858238A (en) * | 1970-02-07 | 1974-12-31 | Tokyo Shibaura Electric Co | Semiconductor devices containing as impurities as and p or b and the mehtod of manufacturing the same |
US3879230A (en) * | 1970-02-07 | 1975-04-22 | Tokyo Shibaura Electric Co | Semiconductor device diffusion source containing as impurities AS and P or B |
SE367138B (en) | 1972-10-05 | 1974-05-20 | Asea Ab | |
US4027383A (en) * | 1974-01-24 | 1977-06-07 | Massachusetts Institute Of Technology | Integrated circuit packaging |
JPS52111080A (en) | 1976-03-15 | 1977-09-17 | Kazutoshi Yamazaki | Method of obtaining blanks from material of specified length |
JPS5553462A (en) * | 1978-10-13 | 1980-04-18 | Int Rectifier Corp | Mosfet element |
JPS5715420A (en) * | 1980-06-30 | 1982-01-26 | Nec Home Electronics Ltd | Manufacture of semiconductor device |
JPS5790763A (en) | 1980-11-28 | 1982-06-05 | Fujitsu Ltd | Priority process system |
JPS5797630A (en) | 1980-12-10 | 1982-06-17 | Hitachi Ltd | Manufacture of semiconductor device |
JPS5845814A (en) * | 1981-09-11 | 1983-03-17 | Tatsuji Yamamura | Method of manufacturing saw |
JPS59113629A (en) * | 1982-12-20 | 1984-06-30 | Fujitsu Ltd | Semiconductor device |
JPS59189625A (en) * | 1983-04-13 | 1984-10-27 | Nec Corp | Manufacture of semiconductor device |
JPS59213140A (en) * | 1983-05-18 | 1984-12-03 | Toshiba Corp | Manufacture of semiconductor device |
JPS59220937A (en) * | 1983-05-31 | 1984-12-12 | Toshiba Corp | Manufacture of semiconductor device |
US4602541A (en) | 1984-12-06 | 1986-07-29 | Trumpf Gmbh & Co. | Punch press with means for rotating the workpiece and method of using same and tooling therefor |
DE3446807A1 (en) * | 1984-12-21 | 1986-07-03 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Thin-film solar cell having an n-i-p structure |
JPS61230404A (en) | 1985-04-03 | 1986-10-14 | Murata Mfg Co Ltd | Dielectric coaxial resonator |
JPS61234041A (en) * | 1985-04-09 | 1986-10-18 | Tdk Corp | Semiconductor device and manufacture thereof |
JPS61296769A (en) * | 1985-06-25 | 1986-12-27 | Yokogawa Electric Corp | Production of high withstand voltage mosfet |
JPS6223170A (en) * | 1985-07-23 | 1987-01-31 | Nec Corp | Manufacture of vertical type field-effect transistor for power |
JPS6224332A (en) * | 1985-07-24 | 1987-02-02 | Usac Electronics Ind Co Ltd | Initial diagnosis control system |
JPS6243123A (en) * | 1985-08-21 | 1987-02-25 | Rohm Co Ltd | Formation of ohmic contact in individual semiconductor device |
JPS62243332A (en) * | 1986-04-15 | 1987-10-23 | Toshiba Corp | Processing of semiconductor wafer |
US4859629A (en) * | 1986-04-18 | 1989-08-22 | M/A-Com, Inc. | Method of fabricating a semiconductor beam lead device |
JPS62253633A (en) | 1986-04-26 | 1987-11-05 | Mazda Motor Corp | Electrode structure for corona discharge of surface of pi molded article and production thereof |
JP2710249B2 (en) * | 1986-06-12 | 1998-02-10 | 富士電機株式会社 | Switching semiconductor device |
SE460147B (en) | 1987-03-03 | 1989-09-11 | Asea Stal Ab | POWER PLANT WITH FLUIDIZED BATH AND A COOLING DEVICE FOR BEDDING MATERIAL |
JPS63253633A (en) * | 1987-04-09 | 1988-10-20 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
US4927784A (en) * | 1987-05-01 | 1990-05-22 | Raytheon Company | Simultaneous formation of via hole and tube structures for GaAs monolithic microwave integrated circuits |
GB8711373D0 (en) * | 1987-05-14 | 1987-06-17 | Secr Defence | Electroluminescent silicon device |
US4751191A (en) * | 1987-07-08 | 1988-06-14 | Mobil Solar Energy Corporation | Method of fabricating solar cells with silicon nitride coating |
JPH01169970A (en) * | 1987-12-25 | 1989-07-05 | Hitachi Ltd | Semiconductor device |
JPH0233367A (en) | 1988-07-21 | 1990-02-02 | Daiyu Shoji:Kk | Textile or knit having collagen fiber layer of natural leather |
US4853345A (en) * | 1988-08-22 | 1989-08-01 | Delco Electronics Corporation | Process for manufacture of a vertical DMOS transistor |
JPH02210860A (en) * | 1989-02-09 | 1990-08-22 | Fujitsu Ltd | Semiconductor integrated circuit device |
JP2854907B2 (en) | 1990-01-11 | 1999-02-10 | シチズン時計株式会社 | Progressive press die |
JP2513055B2 (en) * | 1990-02-14 | 1996-07-03 | 日本電装株式会社 | Method for manufacturing semiconductor device |
US5241862A (en) * | 1990-12-24 | 1993-09-07 | Litton Systems, Inc. | Integrated accelerometer with single hardstop geometry |
US5333961A (en) | 1992-08-05 | 1994-08-02 | Rockwell International Corporation | Keyboard with top mountable key cap assemblies and method |
JPH07233367A (en) * | 1993-12-28 | 1995-09-05 | Toshiba Corp | Fluorescent material, slurry fluorescent material and production of fluorescent lump |
JP2962396B2 (en) | 1994-06-27 | 1999-10-12 | 株式会社ユニシアジェックス | Inclined hole drilling device |
CH688306A5 (en) | 1994-09-07 | 1997-07-31 | Eugen Haenggi | Method and apparatus for punching Loechernin a flat workpiece. |
US5744213A (en) | 1995-08-25 | 1998-04-28 | Soltech. Inc. | Enclosure panel with herringbone aperture pattern |
JPH0973760A (en) | 1995-09-07 | 1997-03-18 | Sony Corp | Method for blanking plate stock and base plate of tape cassette |
US6114193A (en) * | 1998-05-05 | 2000-09-05 | Vishay Lite-On Power Semicon Corp. | Method for preventing the snap down effect in power rectifier with higher breakdown voltage |
-
1990
- 1990-02-14 JP JP2033367A patent/JP2513055B2/en not_active Expired - Lifetime
-
1991
- 1991-02-08 US US07/652,920 patent/US5242862A/en not_active Expired - Lifetime
-
1995
- 1995-03-22 US US08/409,900 patent/US5689130A/en not_active Expired - Lifetime
- 1995-06-06 US US08/473,775 patent/US5663096A/en not_active Expired - Lifetime
-
1997
- 1997-10-31 US US08/962,322 patent/US6498366B1/en not_active Expired - Fee Related
- 1997-10-31 US US08/962,278 patent/US5994187A/en not_active Expired - Fee Related
-
2002
- 2002-10-30 US US10/283,981 patent/US6649478B2/en not_active Expired - Fee Related
-
2003
- 2003-08-28 US US10/651,277 patent/US6903417B2/en not_active Expired - Fee Related
-
2004
- 2004-06-29 US US10/880,048 patent/US6949434B2/en not_active Expired - Fee Related
- 2004-06-29 US US10/880,044 patent/US7064033B2/en not_active Expired - Fee Related
-
2005
- 2005-05-31 US US11/140,756 patent/US20050227438A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4213818A (en) * | 1979-01-04 | 1980-07-22 | Signetics Corporation | Selective plasma vapor etching process |
US4902641A (en) * | 1987-07-31 | 1990-02-20 | Motorola, Inc. | Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure |
US4782028A (en) * | 1987-08-27 | 1988-11-01 | Santa Barbara Research Center | Process methodology for two-sided fabrication of devices on thinned silicon |
US4859626A (en) * | 1988-06-03 | 1989-08-22 | Texas Instruments Incorporated | Method of forming thin epitaxial layers using multistep growth for autodoping control |
US4879250A (en) * | 1988-09-29 | 1989-11-07 | The Boeing Company | Method of making a monolithic interleaved LED/PIN photodetector array |
US4985740A (en) * | 1989-06-01 | 1991-01-15 | General Electric Company | Power field effect devices having low gate sheet resistance and low ohmic contact resistance |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070111480A1 (en) * | 2005-11-16 | 2007-05-17 | Denso Corporation | Wafer product and processing method therefor |
US20080006856A1 (en) * | 2006-06-22 | 2008-01-10 | Fuji Electric Device Technology Co., Ltd | Semiconductor device with back surface electrode including a stress relaxation film |
US7521757B2 (en) * | 2006-06-22 | 2009-04-21 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device with back surface electrode including a stress relaxation film |
US20110039382A1 (en) * | 2006-12-07 | 2011-02-17 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device and method for manufacturing the same |
US8343833B2 (en) * | 2006-12-07 | 2013-01-01 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20130256964A1 (en) * | 2012-03-27 | 2013-10-03 | Mitsubishi Electric Corporation | Wafer suction method, wafer suction stage, and wafer suction system |
US9312160B2 (en) * | 2012-03-27 | 2016-04-12 | Mitsubishi Electric Corporation | Wafer suction method, wafer suction stage, and wafer suction system |
Also Published As
Publication number | Publication date |
---|---|
US5689130A (en) | 1997-11-18 |
US20040036140A1 (en) | 2004-02-26 |
US5994187A (en) | 1999-11-30 |
US20040241930A1 (en) | 2004-12-02 |
US20040237327A1 (en) | 2004-12-02 |
US6949434B2 (en) | 2005-09-27 |
US7064033B2 (en) | 2006-06-20 |
JP2513055B2 (en) | 1996-07-03 |
US6903417B2 (en) | 2005-06-07 |
US6498366B1 (en) | 2002-12-24 |
US5242862A (en) | 1993-09-07 |
US20030052366A1 (en) | 2003-03-20 |
US5663096A (en) | 1997-09-02 |
JPH03236225A (en) | 1991-10-22 |
US6649478B2 (en) | 2003-11-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6903417B2 (en) | Power semiconductor device | |
JP2995723B2 (en) | Vertical current semiconductor device using wafer bonding and method of manufacturing the same | |
US5859465A (en) | High voltage power schottky with aluminum barrier metal spaced from first diffused ring | |
EP1016142B1 (en) | SiC SEMICONDUCTOR DEVICE COMPRISING A PN JUNCTION | |
US20090035925A1 (en) | Gallium Nitride Semiconductor Device | |
US5278443A (en) | Composite semiconductor device with Schottky and pn junctions | |
CA1189634A (en) | Low-loss and high-speed diodes | |
US6162665A (en) | High voltage transistors and thyristors | |
US6727128B2 (en) | Method of preparing polysilicon FET built on silicon carbide diode substrate | |
US3252003A (en) | Unipolar transistor | |
JPH04127480A (en) | High breakdown strength low resistance semiconductor device | |
US5654226A (en) | Wafer bonding for power devices | |
JP2518963B2 (en) | InAs hole element | |
EP0426252B1 (en) | A semiconductor device and method of manufacturing a semiconductor device | |
JP3313344B2 (en) | SiC / Si heterostructure semiconductor switch and method of manufacturing the same | |
CA1127322A (en) | Method of fabricating semiconductor device by bonding together silicon substrate and electrode or the like with aluminum | |
CA1305260C (en) | Semiconductor device having array of conductive rods | |
JPH05275688A (en) | Planar type power semiconductor element | |
US5858855A (en) | Semiconductor substrate, process for production thereof, and semiconductor device | |
US20210066495A1 (en) | Power Semiconductor Device and Method | |
JPH07153928A (en) | Semiconductor substrate and its manufacture | |
US20220139793A1 (en) | Power semiconductor devices with improved overcoat adhesion and/or protection | |
US20220336215A1 (en) | Fabrication of wide bandgap devices | |
JPS63138767A (en) | Semiconductor substrate for vertical type semi-conductor device and manufacture thereof | |
Cohen et al. | Si 3 N 4-masked thermally oxidized post-diffused mesa process (SIMTOP) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |