US20050233569A1 - Bump structure for a semiconductor device and method of manufacture - Google Patents
Bump structure for a semiconductor device and method of manufacture Download PDFInfo
- Publication number
- US20050233569A1 US20050233569A1 US11/091,869 US9186905A US2005233569A1 US 20050233569 A1 US20050233569 A1 US 20050233569A1 US 9186905 A US9186905 A US 9186905A US 2005233569 A1 US2005233569 A1 US 2005233569A1
- Authority
- US
- United States
- Prior art keywords
- bump
- conductive
- semiconductor device
- substrate
- bump structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0235—Shape of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02377—Fan-in arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13013—Shape in top view being rectangular or square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/1356—Disposition
- H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
- H01L2224/13566—Both on and outside the bonding interface of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
- H01L2224/14153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- TCP tape carrier package
- COF chip on film
- COG chip on glass
- TCP and COF tape automated bonding
- bumps provide an advantage over wire bonding by allowing for a reduction in the spacing between the solder bumps as compared to the spacing between wire bonds
- a semiconductor chip e.g., a liquid crystal display (LCD) driver integrated circuit (IC) package
- LCD liquid crystal display
- IC driver integrated circuit
- ACF anisotropic conductive film
- ACF tape contains electrically conductive particles that are embedded in an insulating material. The conductive particles provide electrical connection between the solder bumps and the pads on the LCD substrate. As the gap between bumps, however, becomes smaller, the particles in the ACF tape may provide electrical connection between bumps; thus, causing a short circuit.
- the present invention provides a bump structure that removes barriers on the spacing between solder bumps of semiconductor chips or packages. As such, the present invention allows for smaller and thinner semiconductor devices.
- a plurality of bump structures are arrayed along a substrate in a first direction.
- Each bump structure has a width in the first direction greater than a pitch gap between successively arrayed bump structures.
- the pitch gap may be thought of as a gap measured at the substrate along the first direction between planes of facing sidewalls of the successively arrayed bump structures.
- At least one bump structure has a sidewall facing in the first direction that is non-conductive. Because the sidewall is non-conductive, conductive particles disposed between this bump and the bump adjacent to the non-conductive sidewall should not form a short circuit between the two bumps.
- each bump structure has at least one non-conductive sidewall facing in the first direction.
- each bump structure has two oppositely facing non-conductive sidewalls facing in the first direction.
- each bump structure has one non-conductive sidewall facing in the first direction and one conductive sidewall facing in the first direction such that the conductive sidewall does not face the conductive sidewall of another bump structure.
- the array of bump structures alternate from a first type to a second type.
- the bump structure of the first type has two oppositely facing non-conductive sidewalls that face in the first direction
- the bump structure of the second type has two oppositely facing conductive sidewalls that face in the first direction.
- the successively arrayed bump structures may be disposed offset from one another in a second direction along the substrate.
- An exemplary embodiment,of the, present invention also includes a plurality of bumps arrayed along a substrate in a first direction and a plurality of conductive lines formed in a second direction.
- Each conductive line is associated with one of the bumps, and each conductive line is disposed over a top surface of the associated bump and over two oppositely facing sidewalls of the bump; the two oppositely facing sidewalls facing in the second direction.
- Each conductive line extends over the substrate from each of the two oppositely facing sidewalls. Because of this, the conductive line assists in maintaining the associated bump adhered to the substrate.
- FIG. 1 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention
- FIG. 2 illustrates a cross-section of the substrate shown in FIG. 1 along line II-II;
- FIG. 3 illustrates a cross-section of the substrate shown in FIG. 1 along line III-III;
- FIG. 4 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention
- FIG. 5 illustrates a cross-section of the semiconductor device shown in FIG. 4 along line V-V;
- FIG. 6 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention
- FIG. 7 illustrates a cross-section of the semiconductor device shown in FIG. 6 along line VII-VII;
- FIG. 8 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention.
- FIG. 9 illustrates a top down view of a semiconductor device having three groups of bump structures
- FIGS. 10A-15B illustrate an embodiment of a method of fabricating a bump structure according to the present invention where FIGS. 10A, 11A , 12 , 13 A, 14 and 15 A represent cross-sectional views of the substrate during the fabrication process, and FIGS. 10B, 11B , 13 B and 15 B represent top down views of the substrate during the fabrication process.
- the present invention provides a bump structure that removes barriers on the spacing between solder bumps of semiconductor chips or packages. As such, the present invention allows for smaller and thinner semiconductor devices.
- First, several structual embodiments according to the present invention will be described followed by a description of a method for forming a bump structure according to the present invention.
- FIG. 1 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention.
- bump structures 100 are arrayed on an insulating layer 202 over a substrate 200 in a first direction indicated by a double headed arrow A.
- Each bump structure 100 includes a non-conductive bump 102 .
- the non-conductive bump 102 has two oppositely facing sidewalls 104 that face in the first direction and two oppositely facing sidewalls 106 that face in a second direction, substantially perpendicular to the first direction, indicated by a double headed arrow B.
- each bump 102 has a height H of 2 to 30 um, a width Wb of 10 to 50 um and a length of 20 to 200 um.
- Each bump structure 100 also includes a conductive layer 108 disposed over a top surface of an associated bump 102 and each sidewall 106 facing in the second direction.
- the conductive layer 108 on the bump 102 forms part of a conductive line 110 that extends a shorter distance over the substrate 200 from one sidewall 104 , and extends a longer distance over the substrate 200 from the other sidewall 104 .
- the conductive line 110 extends in the second direction.
- the longer extension of the conductive line 110 leads to an associated chip pad 204 where the conductive layer 110 is electrically connected to the associated pad 204 .
- the pad 204 provides electrical connection between the conductive line 110 and circuitry (not shown) formed on the substrate 200 .
- FIG. 2 illustrates a cross-section of the substrate shown in FIG. 1 along line II-II
- FIG. 3 illustrates a cross-section of the substrate shown in FIG. 1 along line III-III.
- the bump structure according to this embodiment of the present invention further includes a passivation layer 180 formed over portions of the substrate 200 as shown in FIGS. 2 and 3 .
- FIG. 2 shows the pitch gap PG between consecutive bump structures 100 in FIG. 1 .
- the pitch gap PG is the distance between two bump structures; and more particularly, may be the gap as measured at the substrate 200 or passivation layer 180 along the first direction between the planes in which facing sidewalls 104 of the successively arrayed bump structures 100 lie.
- the width Wb of the bump structure 100 is greater than the pitch gap PG.
- the pitch gap PG may be about 10 um.
- the present invention provides a bump structure that removes barriers on the spacing between solder bumps of semiconductor chips or packages. As such, the present invention allows for smaller and thinner semiconductor devices.
- FIG. 4 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention
- FIG. 5 illustrates a cross-section of the semiconductor device shown in FIG. 4 along line V-V.
- the embodiment of FIG. 4 is the same as the embodiment of FIG. 1 except for the bump structures.
- each bump structure 100 ′ is the same as the bump structure 100 shown in FIG. 1 except that the conductive layer 108 covers a same one of the sidewalls 104 facing in the first direction.
- the conductive sidewall 104 of one bump structure 100 faces a non-conductive sidewall 104 of another bump structure 100 .
- the present invention provides a bump structure that removes barriers on the spacing between solder bumps of semiconductor chips or packages. As such, the present invention allows for smaller and thinner semiconductor devices.
- FIG. 6 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention
- FIG. 7 illustrates a cross-section of the semiconductor device shown in FIG. 6 along line VII-VII.
- the embodiment of FIG. 6 is the same as the embodiment of FIG. 1 except for the bump structures.
- the embodiment of FIG. 6 includes two alternating types of bump structures.
- the first type of bump structures 100 are the same as the bump structure 100 shown in FIG. 1 .
- the second type of bump structures 100 ′′ are the same as the bump structure 100 shown in FIG. 1 except that the conductive layer 108 covers both of the sidewalls 104 facing in the first direction.
- the present invention provides a bump structure that removes barriers on the spacing between solder bumps of semiconductor chips or packages. As such, the present invention allows for smaller and thinner semiconductor devices.
- FIG. 8 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention.
- the bump structure in FIG. 8 is the same as the bump structure shown in FIG. 1 , except that the successively arrayed bump structures are disposed offset from one another in the second direction.
- the bump structures 100 are divided into two groups.
- the bump structures 100 - 1 in the first group have shorter conductive lines 110 than the bump structures 100 - 2 in the second group, and bumps structures 100 - 1 of the first group alternate with bump structures 100 - 2 of the second group in the first direction.
- offsetting the bump structures 100 as shown in FIG. 8 further assists in preventing possible short circuits. Because successive bump structures 100 are not aligned, a short circuit is less likely to occur, and because the gap between aligned bump structures is large (e.g., greater than 20 um), a short circuit is less likely to occur.
- FIG. 8 has been shown and described using the bump structures 100 of FIG. 1 , it will be appreciated that this embodiment may be used in conjunction with the bump structures of any of the previously described embodiments.
- FIG. 9 illustrates a top down view of a semiconductor device having three groups of bump structures 100 .
- FIGS. 10A-15B where FIGS. 10A, 11A , 12 , 13 A, 14 and 15 A represent cross-sectional views of the substrate during the fabrication process, and FIGS. 10B, 11B , 13 B and 15 B represent top down views of the substrate during the fabrication process.
- the process begins with a substrate 200 having chip pads 204 formed thereon. For the purposes of clarity, only a single chip pad has been shown. Also, for clarity, the devices, circuits, etc. to which the chip pad 204 is electrically connected have not been shown.
- a first passivation layer 202 is formed over the substrate 200 and then patterned to expose a portion 225 of the chip pad 204 .
- the first passivation layer 202 may be SiN, SiO2, or SiN+SiO2, and may be formed by chemical vapor deposition (CVD).
- a dielectric layer such as polyimide, BCB (Benzo Cyclo Butane), PBO (polybenzo oxazole), photosensitive resin, etc. is formed over the substrates; for example, by spin coating.
- the dielectric layer may be formed to a thickness of 2-30 um.
- the dielectric layer is patterned using a mask to form non-conductive bumps 102 as shown in FIGS. 11A and 11B .
- the bumps 102 will have a height of 2-30 um, may have a width of 10-50 um and a length of 50-200 um. In one example embodiment, the width is 20 um and the length is 100 um.
- a first metal layer 140 is formed over the substrate 200 .
- the first metal layer 140 may have a thickness of 0.05-1 um.
- the first metal layer 140 may be formed of any metal having good adhesive properties and low electrical resistance such as TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr/Cu, TiW/Cu, TiW/Au, NiV/Cu, etc.
- the first metal layer 140 may be formed by a pressure vapor deposition (PVD) process, electro or electroless plating, etc.
- PVD pressure vapor deposition
- a photoresist pattern 150 is formed over the substrate 200 .
- the photoresist pattern 150 forms a mask as shown in FIG. 13B .
- a second metal layer 160 is formed over portions of the substrate 200 exposed by the mask.
- the first and second metal layers 140 and 160 form the conductive layer 108 and the conductive line 110 .
- the second metal layer 160 may be formed to a thickness of 1-10 um. In one example embodiment, the combined thickness of the first and second metal layers 140 and 160 is less than 10 um.
- the second metal layer 160 may be formed of Au, Ni, Cu, Pd, Ag, etc., or multiple layers of these metals by electro plating, for example.
- the photoresist pattern 150 is removed as shown in FIG. 14 leaving the bump structure 100 electrically connected to the pad 204 .
- a second passivation layer 180 may then be formed over the substrate 200 and patterned to expose the bump structures 100 as shown in FIGS. 15A and 15B .
- the second passivation layer may be polyimide, BCB, PBO, photosensitive resin etc., and may be applied by a spin coating process.
- the bump structures and method of fabrication described above may be applied to any technique in which bumps are used such as tape carrier package (TCP), chip on film (COF), and chip on glass (COG). Also, the bump structures and method of fabrication described above may be applied to the manufacture of any semiconductor chip or package (e.g., a liquid crystal display (LCD) driver integrated circuit (IC) package).
- TCP tape carrier package
- COF chip on film
- COG chip on glass
- the bump structures and method of fabrication described above may be applied to the manufacture of any semiconductor chip or package (e.g., a liquid crystal display (LCD) driver integrated circuit (IC) package).
- LCD liquid crystal display
- IC driver integrated circuit
Abstract
A semiconductor device employing the bump structure includes a plurality of bump structures arrayed along a substrate in a first direction. Each bump structure has a width in the first direction greater than a pitch gap between successively arrayed bump structures, and at least one bump structure has a sidewall facing in the first direction that is non-conductive.
Description
- A number of different techniques exist for providing electrical connection between a semiconductor chip or package and a circuit board or other substrate. The current trend in many of these techniques is the use of solder bumps to form electrical connections instead of wire bonding. For example, bumps are used in such techniques as tape carrier package (TCP), chip on film (COF), and chip on glass (COG). Often techniques such as TCP and COF are more broadly referred to as tape automated bonding (TAB).
- While bumps provide an advantage over wire bonding by allowing for a reduction in the spacing between the solder bumps as compared to the spacing between wire bonds, even bump techniques face potential limitations on the spacing between the bumps. For example, in the COG technique, a semiconductor chip (e.g., a liquid crystal display (LCD) driver integrated circuit (IC) package) may be bonded directly to the LCD substrate. In this technique, ACF (anisotropic conductive film) tape is disposed between pads of the LCD substrate and the associated bumps on the driver IC package to form the electrical connection. ACF tape contains electrically conductive particles that are embedded in an insulating material. The conductive particles provide electrical connection between the solder bumps and the pads on the LCD substrate. As the gap between bumps, however, becomes smaller, the particles in the ACF tape may provide electrical connection between bumps; thus, causing a short circuit.
- The present invention provides a bump structure that removes barriers on the spacing between solder bumps of semiconductor chips or packages. As such, the present invention allows for smaller and thinner semiconductor devices.
- In one exemplary embodiment, a plurality of bump structures are arrayed along a substrate in a first direction. Each bump structure has a width in the first direction greater than a pitch gap between successively arrayed bump structures. The pitch gap may be thought of as a gap measured at the substrate along the first direction between planes of facing sidewalls of the successively arrayed bump structures. At least one bump structure has a sidewall facing in the first direction that is non-conductive. Because the sidewall is non-conductive, conductive particles disposed between this bump and the bump adjacent to the non-conductive sidewall should not form a short circuit between the two bumps.
- In one exemplary embodiment, each bump structure has at least one non-conductive sidewall facing in the first direction.
- In another exemplary embodiment, each bump structure has two oppositely facing non-conductive sidewalls facing in the first direction.
- In a further exemplary embodiment, each bump structure has one non-conductive sidewall facing in the first direction and one conductive sidewall facing in the first direction such that the conductive sidewall does not face the conductive sidewall of another bump structure.
- In a still further exemplary embodiment, the array of bump structures alternate from a first type to a second type. The bump structure of the first type has two oppositely facing non-conductive sidewalls that face in the first direction, and the bump structure of the second type has two oppositely facing conductive sidewalls that face in the first direction.
- In association with any of the above described embodiments, the successively arrayed bump structures may be disposed offset from one another in a second direction along the substrate.
- An exemplary embodiment,of the, present invention also includes a plurality of bumps arrayed along a substrate in a first direction and a plurality of conductive lines formed in a second direction. Each conductive line is associated with one of the bumps, and each conductive line is disposed over a top surface of the associated bump and over two oppositely facing sidewalls of the bump; the two oppositely facing sidewalls facing in the second direction. Each conductive line extends over the substrate from each of the two oppositely facing sidewalls. Because of this, the conductive line assists in maintaining the associated bump adhered to the substrate.
- Other exemplary embodiments of the present invention provide for methods of forming the above described embodiments.
- The present invention will become more fully understood from the detailed description given herein below and the accompanying drawings, wherein like elements are represented by like reference numerals, which are given by way of illustration only and thus are not limiting of the present invention and wherein:
-
FIG. 1 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention; -
FIG. 2 illustrates a cross-section of the substrate shown inFIG. 1 along line II-II; -
FIG. 3 illustrates a cross-section of the substrate shown inFIG. 1 along line III-III; -
FIG. 4 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention; -
FIG. 5 illustrates a cross-section of the semiconductor device shown inFIG. 4 along line V-V; -
FIG. 6 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention; -
FIG. 7 illustrates a cross-section of the semiconductor device shown inFIG. 6 along line VII-VII; -
FIG. 8 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention. -
FIG. 9 illustrates a top down view of a semiconductor device having three groups of bump structures; -
FIGS. 10A-15B illustrate an embodiment of a method of fabricating a bump structure according to the present invention whereFIGS. 10A, 11A , 12, 13A, 14 and 15A represent cross-sectional views of the substrate during the fabrication process, andFIGS. 10B, 11B , 13B and 15B represent top down views of the substrate during the fabrication process. - The present invention provides a bump structure that removes barriers on the spacing between solder bumps of semiconductor chips or packages. As such, the present invention allows for smaller and thinner semiconductor devices. First, several structual embodiments according to the present invention will be described followed by a description of a method for forming a bump structure according to the present invention.
-
FIG. 1 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention. As shown,bump structures 100 are arrayed on aninsulating layer 202 over asubstrate 200 in a first direction indicated by a double headed arrow A. Eachbump structure 100 includes anon-conductive bump 102. Thenon-conductive bump 102 has two oppositely facingsidewalls 104 that face in the first direction and two oppositely facingsidewalls 106 that face in a second direction, substantially perpendicular to the first direction, indicated by a double headed arrow B. - In one example embodiment, each
bump 102 has a height H of 2 to 30 um, a width Wb of 10 to 50 um and a length of 20 to 200 um. - Each
bump structure 100 also includes aconductive layer 108 disposed over a top surface of an associatedbump 102 and eachsidewall 106 facing in the second direction. Theconductive layer 108 on thebump 102 forms part of aconductive line 110 that extends a shorter distance over thesubstrate 200 from onesidewall 104, and extends a longer distance over thesubstrate 200 from theother sidewall 104. As shown, theconductive line 110 extends in the second direction. The longer extension of theconductive line 110 leads to an associatedchip pad 204 where theconductive layer 110 is electrically connected to the associatedpad 204. As will be appreciated thepad 204 provides electrical connection between theconductive line 110 and circuitry (not shown) formed on thesubstrate 200. -
FIG. 2 illustrates a cross-section of the substrate shown inFIG. 1 along line II-II andFIG. 3 illustrates a cross-section of the substrate shown inFIG. 1 along line III-III. While not shown inFIG. 1 for the purposes of clarity, the bump structure according to this embodiment of the present invention further includes apassivation layer 180 formed over portions of thesubstrate 200 as shown inFIGS. 2 and 3 . -
FIG. 2 shows the pitch gap PG betweenconsecutive bump structures 100 inFIG. 1 . The pitch gap PG is the distance between two bump structures; and more particularly, may be the gap as measured at thesubstrate 200 orpassivation layer 180 along the first direction between the planes in which facingsidewalls 104 of the successively arrayedbump structures 100 lie. In this embodiment, the width Wb of thebump structure 100 is greater than the pitch gap PG. For example, the pitch gap PG may be about 10 um. - Because the pitch gap PG is less than the width WBb of the
bump structure 100, a short circuit when using, for example, an ACF tape might be expected. However, because thesidewalls 104 of thebump structures 100 facing in the first direction are non-conductive, such short circuits are prevented. Consequently, the present invention provides a bump structure that removes barriers on the spacing between solder bumps of semiconductor chips or packages. As such, the present invention allows for smaller and thinner semiconductor devices. -
FIG. 4 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention, andFIG. 5 illustrates a cross-section of the semiconductor device shown inFIG. 4 along line V-V. As shown, the embodiment ofFIG. 4 is the same as the embodiment ofFIG. 1 except for the bump structures. In the embodiment ofFIG. 4 , eachbump structure 100′ is the same as thebump structure 100 shown inFIG. 1 except that theconductive layer 108 covers a same one of thesidewalls 104 facing in the first direction. As such, theconductive sidewall 104 of onebump structure 100 faces anon-conductive sidewall 104 of anotherbump structure 100. - Because one of the
sidewalls 104 of thebump structures 100 facing in the first direction are non-conductive, short circuits are prevented. Consequently, the present invention provides a bump structure that removes barriers on the spacing between solder bumps of semiconductor chips or packages. As such, the present invention allows for smaller and thinner semiconductor devices. -
FIG. 6 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention, andFIG. 7 illustrates a cross-section of the semiconductor device shown inFIG. 6 along line VII-VII. As shown, the embodiment ofFIG. 6 is the same as the embodiment ofFIG. 1 except for the bump structures. The embodiment ofFIG. 6 includes two alternating types of bump structures. The first type ofbump structures 100 are the same as thebump structure 100 shown inFIG. 1 . The second type ofbump structures 100″ are the same as thebump structure 100 shown inFIG. 1 except that theconductive layer 108 covers both of thesidewalls 104 facing in the first direction. However, because the two types of bump structures alternate along the first direction of thesubstrate 200, aconductive sidewall 104 of the second type ofbump structure 100″ faces anon-conductive sidewall 104 of the first type ofbump structure 100. As a result, short circuits are prevented. Consequently, the present invention provides a bump structure that removes barriers on the spacing between solder bumps of semiconductor chips or packages. As such, the present invention allows for smaller and thinner semiconductor devices. -
FIG. 8 illustrates a semiconductor device having a bump structure according to an exemplary embodiment of the present invention. As shown, the bump structure inFIG. 8 is the same as the bump structure shown inFIG. 1 , except that the successively arrayed bump structures are disposed offset from one another in the second direction. More specifically, thebump structures 100 are divided into two groups. The bump structures 100-1 in the first group have shorterconductive lines 110 than the bump structures 100-2 in the second group, and bumps structures 100-1 of the first group alternate with bump structures 100-2 of the second group in the first direction. - As will be appreciated, offsetting the
bump structures 100 as shown inFIG. 8 further assists in preventing possible short circuits. Becausesuccessive bump structures 100 are not aligned, a short circuit is less likely to occur, and because the gap between aligned bump structures is large (e.g., greater than 20 um), a short circuit is less likely to occur. - While the embodiment of
FIG. 8 has been shown and described using thebump structures 100 ofFIG. 1 , it will be appreciated that this embodiment may be used in conjunction with the bump structures of any of the previously described embodiments. - Furthermore, while two groups o,f aligned bump structures have been illustrated, it will be appreciated that more than two groups of bump structures, each offset from the other, may be formed.
FIG. 9 illustrates a top down view of a semiconductor device having three groups ofbump structures 100. - Next, a method of fabricating a semiconductor device having a bump structure according to the present invention will be described. For the purposes of example only, the method will be described with respect to the fabrication of the
bump structure 100 illustrated inFIG. 1 . The method will be described with respect toFIGS. 10A-15B whereFIGS. 10A, 11A , 12, 13A, 14 and 15A represent cross-sectional views of the substrate during the fabrication process, andFIGS. 10B, 11B , 13B and 15B represent top down views of the substrate during the fabrication process. - As shown in
FIGS. 10A and 10B , the process begins with asubstrate 200 havingchip pads 204 formed thereon. For the purposes of clarity, only a single chip pad has been shown. Also, for clarity, the devices, circuits, etc. to which thechip pad 204 is electrically connected have not been shown. Afirst passivation layer 202 is formed over thesubstrate 200 and then patterned to expose aportion 225 of thechip pad 204. Thefirst passivation layer 202 may be SiN, SiO2, or SiN+SiO2, and may be formed by chemical vapor deposition (CVD). - Next, a dielectric layer such as polyimide, BCB (Benzo Cyclo Butane), PBO (polybenzo oxazole), photosensitive resin, etc. is formed over the substrates; for example, by spin coating. The dielectric layer may be formed to a thickness of 2-30 um. Then, the dielectric layer is patterned using a mask to form
non-conductive bumps 102 as shown inFIGS. 11A and 11B . Thebumps 102 will have a height of 2-30 um, may have a width of 10-50 um and a length of 50-200 um. In one example embodiment, the width is 20 um and the length is 100 um. - As shown in
FIG. 12 , afirst metal layer 140 is formed over thesubstrate 200. Thefirst metal layer 140 may have a thickness of 0.05-1 um. Thefirst metal layer 140 may be formed of any metal having good adhesive properties and low electrical resistance such as TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr/Cu, TiW/Cu, TiW/Au, NiV/Cu, etc. Also thefirst metal layer 140 may be formed by a pressure vapor deposition (PVD) process, electro or electroless plating, etc. - Next, as shown in
FIGS. 13A and 13B , aphotoresist pattern 150 is formed over thesubstrate 200. Thephotoresist pattern 150 forms a mask as shown inFIG. 13B . Using this mask, asecond metal layer 160 is formed over portions of thesubstrate 200 exposed by the mask. The first andsecond metal layers conductive layer 108 and theconductive line 110. - The
second metal layer 160 may be formed to a thickness of 1-10 um. In one example embodiment, the combined thickness of the first andsecond metal layers second metal layer 160 may be formed of Au, Ni, Cu, Pd, Ag, etc., or multiple layers of these metals by electro plating, for example. - Afterwards, the
photoresist pattern 150 is removed as shown inFIG. 14 leaving thebump structure 100 electrically connected to thepad 204. Asecond passivation layer 180 may then be formed over thesubstrate 200 and patterned to expose thebump structures 100 as shown inFIGS. 15A and 15B . The second passivation layer may be polyimide, BCB, PBO, photosensitive resin etc., and may be applied by a spin coating process. - The bump structures and method of fabrication described above may be applied to any technique in which bumps are used such as tape carrier package (TCP), chip on film (COF), and chip on glass (COG). Also, the bump structures and method of fabrication described above may be applied to the manufacture of any semiconductor chip or package (e.g., a liquid crystal display (LCD) driver integrated circuit (IC) package).
- The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the invention, and all such modifications are intended to be included within the scope of the invention.
Claims (49)
1. A semiconductor device, comprising:
a plurality of bump structures arrayed along a substrate in a first direction, each bump structure having a width in the first direction greater than a pitch gap between successively arrayed bump structures, and at least one bump structure having a sidewall facing in the first direction that is non-conductive.
2. The semiconductor device of claim 1 , wherein each bump structure has at least one non-conductive sidewall facing in the first direction.
3. The semiconductor device of claim 2 , wherein each bump structure has two oppositely facing non-conductive sidewalls facing in the first direction.
4. The semiconductor device of claim 3 , wherein each bump structure includes a conductive layer disposed over a top surface of the bump structure and disposed over at least one sidewall of the bump structure that faces in a second direction, the conductive layer extending from the sidewall facing in the second direction over a portion of the substrate.
5. The semiconductor device of claim 4 , wherein each conductive layer is electrically connected to an associated pad on the substrate, the associated pad being disposed away from the associated bump structure.
6. The semiconductor device of claim 4 , wherein each conductive layer includes at least a lower metal layer and an upper metal layer.
7. The semiconductor device of claim 4 , wherein successively arrayed bump structures are disposed offset from one another in the second direction along the substrate.
8. The semiconductor device of claim 7 , wherein the second direction is substantially perpendicular to the first direction.
9. The semiconductor device of claim 2 , wherein each bump structure has one non-conductive sidewall facing in the first direction and one conductive sidewall facing in the first direction such that the conductive sidewall does not face the conductive sidewall of another bump structure.
10. The semiconductor device of claim 9 , wherein each bump structure includes a conductive layer disposed over a top surface of the bump structure and disposed over at least one sidewall of the bump structure that faces in a second direction, the conductive layer extending from the sidewall facing in the second direction over a portion of the substrate.
11. The semiconductor device of claim 10 , wherein each conductive layer is electrically connected to an associated pad on the substrate, the associated pad being disposed away from the associated bump structure.
12. The semiconductor device of claim 10 , wherein each conductive layer includes at least a lower metal layer and an upper metal layer.
13. The semiconductor device of claim 10 , wherein successively arrayed bump structures are disposed offset from one another in the second direction along the substrate.
14. The semiconductor device of claim 13 , wherein the second direction is substantially perpendicular to the first direction.
15. The semiconductor device of claim 1 , Wherein the array of bump structures alternate from a first type to a second type, the bump structure of the first type has two oppositely facing non-conductive sidewalls that face in the first direction, and the bump structure of the second type has each sidewall being conductive.
16. The semiconductor device of claim 15 , wherein each bump structure includes a conductive layer disposed over a top surface of the bump structure and disposed over at least one sidewall of the bump structure that faces in a second direction, the conductive layer extending from the sidewall facing in the second direction over a portion of the substrate.
17. The semiconductor device of claim 16 , wherein each conductive layer is electrically connected to an associated pad on the substrate, the associated pad being disposed away from the associated bump structure.
18. The semiconductor device of claim 16 , wherein each conductive layer includes at least a lower metal layer and an upper metal layer.
19. The semiconductor device of claim 16 , wherein successively arrayed bump structures are disposed offset from one another in the second direction along the substrate.
20. The semiconductor device of claim 19 , wherein the second direction is substantially perpendicular to the first direction.
21. The semiconductor device of claim 1 , wherein each bump structure includes a conductive layer disposed over a top surface of the bump structure and disposed over at least one sidewall of the bump structure that faces in a second direction, the conductive layer extending from the sidewall facing in the second direction over a portion of the substrate.
22. The semiconductor device of claim 21 , wherein each conductive layer is electrically connected to an associated pad on the substrate, the associated pad being disposed away from the associated bump structure.
23. The semiconductor device of claim 21 , wherein each conductive layer includes at least a lower metal layer and an upper metal layer.
24. The semiconductor device of claim 23 , wherein the lower metal layer has a thickness of 0.05 to 1 um, and the upper metal layer has a thickness of 1 to 10 um.
25. The semiconductor device of claim 23 , wherein the lower metal layer includes at least one of TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr/Cu, TiW/Cu, TiW/Au, and NiV/Cu, and the upper metal layer includes at least one of Au, Ni, Cu, Pd, Ag, and Pt.
26. The semiconductor device of claim 1 , wherein successively arrayed bump structures are disposed offset from one another in a second direction along the substrate.
27. The semiconductor device of claim 26 , wherein the second direction is substantially perpendicular to the first direction.
28. The semiconductor device of claim 1 , wherein the bump structures have a width of 10 to 50 um.
29. The semiconductor device of claim 1 , wherein each bump structure includes a non-conductive bump and a conductive material disposed on at least a top surface of the non-conductive bump.
30. The semiconductor device of claim 29 , wherein each bump has a height of 2-30 um.
31. The semiconductor device of claim 29 , wherein each bump structure includes the conductive material disposed on two oppositely facing sidewalls that face in the second direction, and the conductive material extends over the substrate from each of the two oppositely facing sidewalls.
32. The semiconductor device of claim 29 , wherein each bump includes one of a polyimide, benzo cyclo butane, poly benzoxazole, and photosensitive resin.
33. A semiconductor device, comprising:
a plurality of bumps arrayed along a substrate in a first direction;
a plurality of conductive lines formed in a second direction, each conductive line associated with one of the bumps, each conductive line disposed over a top surface of the associated bump and disposed over two oppositely facing sidewalls of the bump that face in the second direction, and each conductive line extending over the substrate from each of the two oppositely facing sidewalls.
34. A semiconductor device, comprising:
a plurality of bumps arrayed along a substrate in a first direction, each bump having a width in the first direction greater than a pitch gap between successively arrayed bumps; and
a plurality of conductive lines formed in a second direction, each conductive line associated with one of the bumps, each conductive line disposed over a top surface of the associated bump and disposed over a sidewall of the associated bump that faces in the second direction, and each conductive line extending over the substrate from the sidewall facing in the second direction.
35. A method of forming a semiconductor device, comprising:
forming a plurality of bump structures arrayed along a substrate in a first direction, each bump structure having a width in the first direction greater than a pitch gap between successively arrayed bump structures, and at least one bump structure having a sidewall facing in the first direction that is non-conductive.
36. The method of claim 35 , wherein the forming step comprises:
forming a plurality of bumps arrayed along the substrate in the first direction; and
forming a conductive line associated with each bump in a second direction, each conductive line disposed over a top surface of the associated bump and disposed over a sidewall of the associated bump that faces in the second direction, and each conductive line extending over the substrate from the sidewall facing in the second direction.
37. The method of claim 35 , wherein the forming a plurality of bumps step comprises:
spin coating a bump material on the substrate; and
patterning the bump material to form the plurality of bumps.
38. The method of claim 37 , wherein each bump includes one of a polyimide, benzo cyclo butane, poly benzoxazole, and photosensitive resin.
39. The method of claim 37 , wherein the patterning step forms the plurality of bumps such that each bump has a width of 10 to 50 um.
40. The method of claim 37 , wherein the patterning step forms the plurality of bumps such that each bump has a height of 2-30 um.
41. The method of claim 35 , wherein each conductive line includes at least a lower metal layer and an upper metal layer.
42. The method of claim 41 , wherein the lower metal layer has a thickness of 0.05 to 1 um, and the upper metal layer has a thickness of 1 to 10 um.
43. The method of claim 41 , wherein the lower metal layer includes at least one of TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr/Cu, TiW/Cu, TiW/Au, and NiV/Cu, and the upper metal layer includes at least one of Au, Ni, Cu, Pd, Ag, and Pt.
44. The method of claim 41 , wherein the forming a conductive line step comprises:
forming the lower metal layer; and
electroplating the lower metal layer with an upper metal layer material to form the upper metal layer.
45. The semiconductor device of claim 35 , wherein each bump structure has at least one non-conductive sidewall facing in the first direction.
46. The semiconductor device of claim 35 , wherein each bump structure has two oppositely facing non-conductive sidewalls facing in the first direction.
47. The semiconductor device of claim 35 , wherein each bump structure has one non-conductive sidewall facing in the first direction and one conductive sidewall facing in the first direction such that the conductive sidewall does not face the conductive sidewall of another bump structure.
48. The semiconductor device of claim 35 , wherein the array of bump structures alternate from a first type to a second type, the bump structure of the first type has two oppositely facing non-conductive sidewalls that face in the first direction, and the bump structure of the second type has each sidewall being conductive.
49. A method of forming a semiconductor device, comprising:
forming a plurality of bumps arrayed along a substrate in a first direction, each bump having a width in the first direction greater than a pitch gap between successively arrayed bumps; and
forming a plurality of conductive lines formed in a second direction, each conductive line associated with one of the bumps, each conductive line disposed over a top surface of the associated bump and disposed over a sidewall of the associated bump that faces in the second direction, and each conductive line extending over the substrate from the sidewall facing in the second direction.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2005100649588A CN100527398C (en) | 2004-04-14 | 2005-04-12 | Bump structure for a semiconductor device and method of manufacture |
JP2005115158A JP5085012B2 (en) | 2004-04-14 | 2005-04-12 | Semiconductor device including bump structure and method of manufacturing the same |
DE102005018280A DE102005018280B4 (en) | 2004-04-14 | 2005-04-13 | Method for producing a semiconductor device with bump structures and semiconductor device |
US12/461,459 US8105934B2 (en) | 2004-04-14 | 2009-08-12 | Bump structure for a semiconductor device and method of manufacture |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040025853A KR100632472B1 (en) | 2004-04-14 | 2004-04-14 | Microelectronic device chip having a fine pitch bump structure having non-conductive sidewalls, a package thereof, a liquid crystal display device comprising the same, and a manufacturing method thereof |
KR2004-0025853 | 2004-04-14 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/461,459 Division US8105934B2 (en) | 2004-04-14 | 2009-08-12 | Bump structure for a semiconductor device and method of manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050233569A1 true US20050233569A1 (en) | 2005-10-20 |
Family
ID=35070683
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/091,869 Abandoned US20050233569A1 (en) | 2004-04-14 | 2005-03-29 | Bump structure for a semiconductor device and method of manufacture |
US12/461,459 Expired - Fee Related US8105934B2 (en) | 2004-04-14 | 2009-08-12 | Bump structure for a semiconductor device and method of manufacture |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/461,459 Expired - Fee Related US8105934B2 (en) | 2004-04-14 | 2009-08-12 | Bump structure for a semiconductor device and method of manufacture |
Country Status (2)
Country | Link |
---|---|
US (2) | US20050233569A1 (en) |
KR (1) | KR100632472B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090275191A1 (en) * | 2006-09-18 | 2009-11-05 | Jonas R Weiss | Method and apparatus for electrostatic discharge protection using a temporary conductive coating |
CN107958889A (en) * | 2016-10-14 | 2018-04-24 | 三星电子株式会社 | Semiconductor device |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100834441B1 (en) | 2007-01-11 | 2008-06-04 | 삼성전자주식회사 | Semiconductor device and package comprising the same |
US8535989B2 (en) | 2010-04-02 | 2013-09-17 | Intel Corporation | Embedded semiconductive chips in reconstituted wafers, and systems containing same |
TWI450345B (en) * | 2010-11-03 | 2014-08-21 | Xintec Inc | Chip package and method for forming the same |
US8937382B2 (en) | 2011-06-27 | 2015-01-20 | Intel Corporation | Secondary device integration into coreless microelectronic device packages |
US8848380B2 (en) | 2011-06-30 | 2014-09-30 | Intel Corporation | Bumpless build-up layer package warpage reduction |
US9257368B2 (en) | 2012-05-14 | 2016-02-09 | Intel Corporation | Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias |
CN104321864B (en) | 2012-06-08 | 2017-06-20 | 英特尔公司 | Microelectronics Packaging with the non-coplanar, microelectronic component of encapsulating and solderless buildup layer |
KR20210122401A (en) | 2020-03-31 | 2021-10-12 | 삼성디스플레이 주식회사 | Flexible curcuit board and display apparatus including the same |
TWI799226B (en) * | 2022-04-07 | 2023-04-11 | 頎邦科技股份有限公司 | Chip-on-film package |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5047644A (en) * | 1989-07-31 | 1991-09-10 | Texas Instruments Incorporated | Polyimide thermal isolation mesa for a thermal imaging system |
US5264326A (en) * | 1989-07-31 | 1993-11-23 | Texas Instruments Incorporated | Polyimide thermal isolation mesa for a thermal imaging system |
US5508228A (en) * | 1994-02-14 | 1996-04-16 | Microelectronics And Computer Technology Corporation | Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same |
US5604977A (en) * | 1994-04-29 | 1997-02-25 | Texas Instruments Incorporated | Method of fabricating focal plane array |
US5783465A (en) * | 1997-04-03 | 1998-07-21 | Lucent Technologies Inc. | Compliant bump technology |
US6284563B1 (en) * | 1995-10-31 | 2001-09-04 | Tessera, Inc. | Method of making compliant microelectronic assemblies |
US20020048924A1 (en) * | 2000-08-29 | 2002-04-25 | Ming-Yi Lay | Metal bump with an insulating sidewall and method of fabricating thereof |
US20020130412A1 (en) * | 1999-12-30 | 2002-09-19 | Akira Nagai | Semiconductor device and method of manufacture thereof |
US6486000B2 (en) * | 2000-01-21 | 2002-11-26 | Hyundai Electronics Industries Co., Ltd. | Semiconductor package and fabricating method thereof |
US6537854B1 (en) * | 1999-05-24 | 2003-03-25 | Industrial Technology Research Institute | Method for bonding IC chips having multi-layered bumps with corrugated surfaces and devices formed |
US6664176B2 (en) * | 2001-08-31 | 2003-12-16 | Infineon Technologies Ag | Method of making pad-rerouting for integrated circuit chips |
US20050191836A1 (en) * | 2004-02-26 | 2005-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to prevent passivation layer peeling in a solder bump formation process |
US7154176B2 (en) * | 2003-11-14 | 2006-12-26 | Industrial Technology Research Institute | Conductive bumps with non-conductive juxtaposed sidewalls |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62205648A (en) | 1986-03-06 | 1987-09-10 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
JPH02272737A (en) | 1989-04-14 | 1990-11-07 | Citizen Watch Co Ltd | Projecting electrode structure of semiconductor and formation of projecting electrode |
JPH07235564A (en) | 1993-12-27 | 1995-09-05 | Toshiba Corp | Semiconductor device |
US6211572B1 (en) * | 1995-10-31 | 2001-04-03 | Tessera, Inc. | Semiconductor chip package with fan-in leads |
CN1176487C (en) | 2000-09-18 | 2004-11-17 | 友达光电股份有限公司 | Structure with several convex and blocks having insulating side walls and its making method |
TW560017B (en) * | 2001-07-12 | 2003-11-01 | Hitachi Ltd | Semiconductor connection substrate |
KR100455387B1 (en) | 2002-05-17 | 2004-11-06 | 삼성전자주식회사 | Method for forming a bump on semiconductor chip and COG package including the bump |
US6893799B2 (en) * | 2003-03-06 | 2005-05-17 | International Business Machines Corporation | Dual-solder flip-chip solder bump |
CN100356559C (en) | 2003-09-24 | 2007-12-19 | 财团法人工业技术研究院 | Crystal coated packing structure and its mfg method |
-
2004
- 2004-04-14 KR KR1020040025853A patent/KR100632472B1/en not_active IP Right Cessation
-
2005
- 2005-03-29 US US11/091,869 patent/US20050233569A1/en not_active Abandoned
-
2009
- 2009-08-12 US US12/461,459 patent/US8105934B2/en not_active Expired - Fee Related
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5047644A (en) * | 1989-07-31 | 1991-09-10 | Texas Instruments Incorporated | Polyimide thermal isolation mesa for a thermal imaging system |
US5264326A (en) * | 1989-07-31 | 1993-11-23 | Texas Instruments Incorporated | Polyimide thermal isolation mesa for a thermal imaging system |
US5508228A (en) * | 1994-02-14 | 1996-04-16 | Microelectronics And Computer Technology Corporation | Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same |
US5604977A (en) * | 1994-04-29 | 1997-02-25 | Texas Instruments Incorporated | Method of fabricating focal plane array |
US6284563B1 (en) * | 1995-10-31 | 2001-09-04 | Tessera, Inc. | Method of making compliant microelectronic assemblies |
US5783465A (en) * | 1997-04-03 | 1998-07-21 | Lucent Technologies Inc. | Compliant bump technology |
US6537854B1 (en) * | 1999-05-24 | 2003-03-25 | Industrial Technology Research Institute | Method for bonding IC chips having multi-layered bumps with corrugated surfaces and devices formed |
US20020130412A1 (en) * | 1999-12-30 | 2002-09-19 | Akira Nagai | Semiconductor device and method of manufacture thereof |
US6486000B2 (en) * | 2000-01-21 | 2002-11-26 | Hyundai Electronics Industries Co., Ltd. | Semiconductor package and fabricating method thereof |
US20020048924A1 (en) * | 2000-08-29 | 2002-04-25 | Ming-Yi Lay | Metal bump with an insulating sidewall and method of fabricating thereof |
US6664176B2 (en) * | 2001-08-31 | 2003-12-16 | Infineon Technologies Ag | Method of making pad-rerouting for integrated circuit chips |
US7154176B2 (en) * | 2003-11-14 | 2006-12-26 | Industrial Technology Research Institute | Conductive bumps with non-conductive juxtaposed sidewalls |
US20050191836A1 (en) * | 2004-02-26 | 2005-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to prevent passivation layer peeling in a solder bump formation process |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090275191A1 (en) * | 2006-09-18 | 2009-11-05 | Jonas R Weiss | Method and apparatus for electrostatic discharge protection using a temporary conductive coating |
US7629202B2 (en) * | 2006-09-18 | 2009-12-08 | International Business Machines Corporation | Method and apparatus for electrostatic discharge protection using a temporary conductive coating |
CN107958889A (en) * | 2016-10-14 | 2018-04-24 | 三星电子株式会社 | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
KR100632472B1 (en) | 2006-10-09 |
US20090305494A1 (en) | 2009-12-10 |
US8105934B2 (en) | 2012-01-31 |
KR20050100771A (en) | 2005-10-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8105934B2 (en) | Bump structure for a semiconductor device and method of manufacture | |
USRE46618E1 (en) | Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices | |
US7246432B2 (en) | Method of manufacturing semiconductor device | |
US6232563B1 (en) | Bump electrode and method for fabricating the same | |
US7632719B2 (en) | Wafer-level chip scale package and method for fabricating and using the same | |
KR20070096016A (en) | Interconnect structures with bond-pads and methods of forming bump sites on bond-pads | |
US10515919B2 (en) | Bump-on-trace design for enlarge bump-to-trace distance | |
US7626263B2 (en) | Semiconductor device and package including the same | |
US6861749B2 (en) | Semiconductor device with bump electrodes | |
US20140361433A1 (en) | Semiconductor device | |
US20040262758A1 (en) | Electronic device and method of manufacturing the same, and electronic instrument | |
US20080017982A1 (en) | Semiconductor Chip And Method For Manufacturing Same, Electrode Structure Of Semiconductor Chip And Method For Forming Same, And Semiconductor Device | |
US7728424B2 (en) | Semiconductor device and method of manufacturing the same | |
KR100539040B1 (en) | Semiconductor integrated circuit device | |
CN100438005C (en) | Semiconductor device | |
US7235879B2 (en) | Semiconductor device and method of manufacturing the same, electronic device and method of manufacturing the same, and electronic instrument | |
CN1901149B (en) | Semiconductor device and method of manufacturing the same | |
JP5085012B2 (en) | Semiconductor device including bump structure and method of manufacturing the same | |
US7154176B2 (en) | Conductive bumps with non-conductive juxtaposed sidewalls | |
KR100225398B1 (en) | Bonding structure of semiconductor bump and its method | |
KR100705757B1 (en) | Flip Chip Having Ultra-fine Pitch and Fabrication Method thereof | |
KR100551519B1 (en) | Semiconductor device | |
US11538798B2 (en) | Semiconductor package with multiple redistribution substrates | |
US7576424B2 (en) | Semiconductor device | |
KR100712548B1 (en) | Wafer level package having floated metal line and method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KWON, YONGHWAN;LEE, CHUNGSUN;KANG, SAYOON;REEL/FRAME:016431/0626;SIGNING DATES FROM 20050314 TO 20050316 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |