US20050242425A1 - Semiconductor device with a protected active die region and method therefor - Google Patents
Semiconductor device with a protected active die region and method therefor Download PDFInfo
- Publication number
- US20050242425A1 US20050242425A1 US10/837,266 US83726604A US2005242425A1 US 20050242425 A1 US20050242425 A1 US 20050242425A1 US 83726604 A US83726604 A US 83726604A US 2005242425 A1 US2005242425 A1 US 2005242425A1
- Authority
- US
- United States
- Prior art keywords
- encapsulant
- contact
- barrier
- semiconductor die
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
- H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the present invention relates to semiconductor devices, and more specifically to protecting specific regions of semiconductor devices.
- the molding material used to encapsulate the semiconductor die e.g., resin
- the molding material used to encapsulate the semiconductor die can bleed over to active regions of the semiconductor where such molding material is undesired.
- bleed prevention techniques utilize trenches or dams to prevent the molding material from bleeding onto the substrate or lead frame leads. However, if, for example, the trench or damn depth is not sufficient enough to hold the molding material, these techniques will not necessarily prevent the molding material from bleeding onto the die face itself.
- Other bleed prevention techniques rely on high clamping force to prevent resin from bleeding onto the exposed pad of an exposed pad package. Although the high clamping force may prove useful in some situations, using such a method is sometimes unpredictable in terms of reliability and yield.
- Another way to deal with molding material that has bleed over into active regions of the semiconductor die is to apply surface treatments to prevent wetting on the active region or to remove the unwanted molding material. Although using surface treatments may prevent or facilitate removal of the unwanted molding material, the excess chemicals utilized often have undesirable effects on the active regions of the semiconductor die.
- FIG. 1 illustrates a cross-sectional view of a semiconductor device in accordance with one embodiment of the present invention
- FIG. 2 illustrates the semiconductor device of FIG. 1 taken along line 2 - 2 ;
- FIG. 3 illustrates a bottom view of a semiconductor device, in accordance with one embodiment of the present invention
- FIG. 4 illustrates a bottom view of a semiconductor device, in accordance with another embodiment of the present invention.
- FIG. 5 illustrates a cross-sectional view of a semiconductor device, in accordance with one embodiment of the present invention
- FIG. 6 illustrates a cross-sectional view of a semiconductor device, in accordance with another embodiment of the present invention.
- FIG. 7 illustrates a bottom plan view of a semiconductor device, in accordance with another embodiment of the present invention.
- a semiconductor device includes a semiconductor die, a plurality of contact pads, an encapsulant barrier, a first layer, a second layer, and an encapsulant.
- the semiconductor die has a first surface and a second surface that are opposite each other.
- the first surface of the semiconductor die has a plurality of contact pad sites.
- Each of the plurality of contact pads have substantially the same predetermined height and have a first end and a second end. The first end of each of the plurality of contact pads is in electrical contact with a predetermined corresponding different one of the plurality of contact pad sites.
- the encapsulant barrier is positioned at a periphery of the plurality of contact pads and has substantially the same predetermined height of the plurality of contact pads.
- the encapsulant barrier is in physical contact with the first surface of the semiconductor die.
- the first layer has a first surface and a second surface, the first surface of the first layer being in direct physical contact with the second end of each of the plurality of contact pads.
- the second layer is in direct physical contact with the first layer.
- the encapsulant surrounds the second surface of the semiconductor die and is blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier.
- the first layer and the second layer are releasable from the semiconductor die after curing of the encapsulant.
- the encapsulant barrier is a same material as the plurality of contact pads. In another form the encapsulant barrier is a different material than the plurality of contact pads.
- a semiconductor device in one embodiment, includes a semiconductor die, a plurality of contact pads, an encapsulant barrier, a removable first layer, a second removable layer, and an encapsulant.
- the semiconductor die has a plurality of contact pad sites.
- the plurality of contact pads are in electrical contact with a predetermined corresponding different one of the plurality of contact pad sites.
- the encapsulant barrier is positioned at an outer perimeter of the semiconductor die.
- the encapsulant barrier has a height that is substantially as large as a highest of the plurality of contact pads.
- the encapsulant barrier is in physical contact with a same surface of the semiconductor die as the contact pad sites.
- the removable first layer has a first surface and a second surface.
- the first surface of the first layer is in direct physical contact with each of the plurality of contact pads.
- the second removable layer is in direct physical contact with the first removable layer.
- the encapsulant surrounds the semiconductor die but is blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier. The first layer and the second layer are removed from the semiconductor die after curing of the encapsulant.
- a semiconductor device in one embodiment, includes a semiconductor die, a plurality of contact pads, an encapsulant barrier, and an encapsulant.
- the semiconductor die has a plurality of contact pad sites.
- the plurality of contact pads are in electrical contact with a predetermined corresponding different one of the plurality of contact pad sites.
- the encapsulant barrier is positioned at an outer perimeter of the semiconductor die.
- the encapsulant barrier has a height that is as high as or greater than a highest of the plurality of contact pads.
- the encapsulant barrier is in physical contact with a same surface of the semiconductor die as the contact pad sites.
- the encapsulant surrounds the semiconductor die and one side of the encapsulant barrier. The encapsulant is blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier when the device is encapsulated while being supported by a temporary base support layer.
- a plurality of contact pad sites is provided on a side of the semiconductor die.
- a plurality of contact pads are formed within the plurality of contact pad sites.
- Each of the plurality of contact pads have substantially the same predetermined height and have a first end and a second end.
- the first end of each of the plurality of contact pads are in electrical contact with a predetermined corresponding different one of the plurality of contact pad sites.
- An encapsulant barrier is provided at a periphery of the plurality of contact pads.
- the encapsulant barrier has substantially the same predetermined height of the plurality of contact pads.
- the encapsulant barrier is in physical contact with the first surface of the semiconductor die.
- a first layer having a first surface and a second surface.
- the first surface of the first layer is in direct physical contact with the second end of each of the plurality of contact pads.
- a second layer is provided that is in direct physical contact with the first layer.
- the second surface of the semiconductor die is encapsulated and the encapsulant is blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier.
- the first layer and the second layer are removed from the semiconductor die after the encapsulant has cured.
- FIG. 1 illustrates a semiconductor device 10 according to one embodiment of the present invention.
- Semiconductor device 10 includes a base layer 12 , an adhesive layer 14 , a semiconductor die 16 , an encapsulant barrier 18 , a contact pad 20 , a contact pad 21 , a contact pad 22 , a contact pad 23 , a contact pad 24 , a contact pad 25 , a contact pad 26 , an active surface 28 , and an encapsulant 30 .
- adhesive layer 14 may be formed of any material that is adhesive.
- adhesive layer 14 is a tape having an adhesive surface in contact with contact pads 20 - 26 .
- adhesive layer 14 is a silicone or acrylic-based material.
- adhesive layer 14 may be removed, for example, if the adhesive layer 14 is an adhesive tape.
- encapsulant 30 may be any type of non-electrically conductive material that can be molded, such as, for example, thermoset mold compounds or filled thermoplastic resins which act as insulating materials.
- encapsulant 30 may be any type of electrically conductive material that can be molded, such as, for example, thermoset epoxy with metallic filler or thermoplastic with metallic filler.
- the metallic filler may be any suitable electrically conductive material, such as, for example, silver, copper, electrically conductive coated polymer spheres, and conductive nano-particles.
- the metallic filler may be in particle form.
- encapsulant barrier 18 may be formed of metal, such as aluminum, copper, aluminum alloys, copper alloys, etc.
- encapsulant barrier 18 may be polyimide, or other organic base passivation materials.
- contact pads 20 - 26 and encapsulant barrier 18 are formed on active region 28 of semiconductor die 16 using standard metallization techniques, such as, for example, an additive plating technique or a subtractive etching technique.
- active region 28 includes a plurality of contact pads 20 - 26 and the corresponding air gaps (spaces) located between contact pads 20 - 26 .
- Alternate embodiments of the present invention may include a greater or lesser number of contact pads then those shown in FIG. 1 .
- active region 28 excludes the portion of the semiconductor die 16 outside of encapsulation barrier 18 .
- active region 28 may include other portions of semiconductor die 16 within other encapsulation barriers.
- active region 28 of semiconductor die 16 is adhesively coupled to adhesive layer 14 .
- adhesive layer 14 is adhesively coupled to base layer 12 in such a fashion that both the adhesive layer 14 and base layer 12 may be removed.
- semiconductor 16 has been separated into several portions: a top portion 17 , a side portion 13 , a side portion 15 , a partial-bottom portion 11 , a partial-bottom portion 9 , and a bottom surface 29 .
- Top portion 17 , side portion 13 , side portion 15 , partial-bottom portion 11 , and partial-bottom portion 9 of semiconductor die 16 are encapsulated up to encapsulant barrier 18 using encapsulant 30 .
- Encapsulant 30 may be provided using any appropriate encapsulating method, such as, for example, dispense, injection or transfer molding, screen printing or extrusion coating.
- Encapsulant barrier 18 when in contact with adhesive layer 14 acts as a barrier to prevent encapsulant 30 from bleeding onto active region 28 .
- adhesive layer 14 and base layer 12 are removed allowing contact pads 20 - 26 to be available conductors free of encapsulant 30 .
- encapsulation barrier 18 prevents encapsulant 30 from bleeding onto or permeating active region 28 of semiconductor die 16 .
- encapsulation barrier 18 may be located at several locations on semiconductor die 16 , such that encapsulation barrier 18 surrounds a region or regions of semiconductor die 16 (active or non-active), that are to remain free of encapsulant 30 .
- encapsulation barrier 18 may be located around the perimeter of semiconductor device 16 such that encapsulation barrier 18 is in the form of a ring.
- encapsulation barrier 18 may take the form of shapes other than a ring.
- encapsulation barrier 18 may be in the form of a spiral, spiraling around contact pads that are to remain free of encapsulant 30 .
- the height of encapsulation barrier 18 may vary depending on the height of contact pads 20 - 26 being used by semiconductor device 10 . In one embodiment, the height of the encapsulant barrier 18 must be at least the height of the contact pad of contact pads 20 - 26 that has the maximum height. That is, the height of contact pads 20 - 26 may vary, but as long as the height of encapsulation barrier 18 is at least the height of the contact pad with the maximum height, encapsulation barrier 18 will prevent encapsulant 30 from permeating beyond encapsulant barrier 18 .
- Encapsulation barrier 18 may be formed at different times within the semiconductor manufacturing process. The exact time when encapsulation barrier 18 is formed varies depending on the metallization process, panelization process, etc., being used to manufacture semiconductor device 10 . For example, encapsulant barrier 18 may be formed using redistribution metal added to semiconductor die 16 .
- FIG. 2 illustrates a bottom view of semiconductor device 10 depicted in FIG. 1 .
- encapsulant barrier 18 is positioned along the outer edges of semiconductor die 16 surrounding the contact pads, such as contact pads 20 - 26 .
- Encapsulant barrier 18 prevents encapsulant 30 of FIG. 1 from bleeding into active region 28 of FIG. 1 .
- FIG. 3 illustrates a semiconductor device 32 according to one embodiment of the present invention.
- Semiconductor device 32 may be manufactured according to the manufacturing processes described earlier in the description of FIG. 1 .
- An encapsulation barrier 36 is located on semiconductor die 34 .
- Encapsulation barrier 36 surrounds the contact pads such as contact pad 38 .
- encapsulation barrier 36 is in the form of a spiral having a height substantially equivalent to the tallest of the contact pads, such as contact pad 38 , as measured from the die surface.
- Encapsulation barrier 36 has a vent opening 33 which allows for expanding gases to be released out of active region 35 while preventing encapsulant 30 of FIGS. 1 and 2 from entering active region 35 .
- FIG. 4 illustrates a semiconductor device 40 according to one embodiment of the present invention.
- Semiconductor device 40 includes semiconductor die 42 , a plurality of contact pads such as contact pad 55 , encapsulation barrier 44 , active region 57 , vent 49 , vent 51 , vent 56 , and vent 59 .
- semiconductor device 40 includes several variations of ventilation, such as, for example, venting portion 48 , venting portion 54 , venting portion 58 , and venting portion 50 .
- Each venting portion 48 , 54 and 58 is illustrated in FIG. 4 by a dashed line solely for purposes of illustration and does not indicate a hidden underlying structure.
- venting portion allows for expanding gases to be circulated out of active region 57 while preventing encapsulant 30 of FIGS. 1 and 2 from entering active region 57 .
- encapsulation barrier 45 is placed parallel to the portion of encapsulation barrier 44 having vent 56 .
- encapsulation barrier 47 is placed inside active region 57 and parallel to the portion of encapsulation barrier 44 having vent 51 .
- venting portion 48 takes the shape of an elongated staple having a portion of encapsulation barrier 44 fit into its opening.
- Other embodiments of ventilating portions may exist that take the form of the ventilating portions shown or not shown.
- FIG. 5 illustrates a semiconductor device 60 according to one embodiment of the present invention.
- semiconductor device 60 includes a base layer 62 , an adhesive layer 64 , a semiconductor die 66 , an encapsulant barrier 80 , a contact pad 71 , a contact pad 72 , a contact pad 73 , a contact pad 74 , a contact pad 75 , a contact pad 76 , and a contact pad 77 .
- Semiconductor device 60 further includes an active region 67 , and a passivation layer having a passivation layer portion 101 , a passivation layer portion 102 , a passivation layer portion 103 , a passivation layer portion 104 , a passivation layer portion 105 , a passivation layer portion 106 , a passivation layer portion 107 , a passivation layer portion 108 and a passivation layer portion 109 .
- Semiconductor device 60 also includes an encapsulant 86 and an air gap 84 .
- adhesive layer 64 may be formed of any material that is adhesive.
- adhesive layer 64 is a tape having an adhesive surface in contact with contact pads 71 - 77 .
- adhesive layer 64 may be an epoxy based material.
- adhesive layer 64 may be removed, for example, if the adhesive layer 64 is an adhesive tape.
- encapsulant 86 may be any type of non-electrically conductive material that can be molded, such as, for example, thermoset mold compounds or filled thermoplastic resins which act as insulating materials.
- encapsulant 30 may be any type of electrically conductive material that can be molded, such as, for example, thermoset epoxy with metallic filler or thermoplastic with metallic filler.
- the metallic filler may be any suitable electrically conductive material, such as, for example, silver, copper, electrically conductive coated polymer spheres, and conductive nano-particles.
- the metallic filler may be in particle form.
- encapsulant barrier 80 may be formed of metal, such as aluminum, copper, aluminum alloys, copper alloys, etc.
- encapsulant barrier 80 may be polyimide, or other organic base passivation materials.
- the passivation layer formed of portions 101 - 109 is formed on semiconductor die 66 .
- contact pads 71 - 77 and encapsulant barrier 80 are formed on active region 67 of semiconductor die 66 using any one of various metallization techniques known in the art.
- the passivation layer formed of portions 101 - 109 is interposed between contact pads 71 - 77 and the bottom surface 68 of semiconductor die 66 .
- An air gap 84 surrounds contact pads 71 - 77 . The air gap 84 is enclosed within encapsulant barrier 80 and between adhesive layer 64 and the passivation layer formed of portions 101 - 109 .
- Alternate embodiments of the present invention may include a greater or lesser number of contact pads in active region 67 .
- active region 67 may be considered the bottom of semiconductor die 66 , excluding the portions of the semiconductor die 66 outside of encapsulant barrier 80 .
- active region 67 may include other portions of semiconductor die 66 within encapsulant barrier 80 .
- active region 67 of semiconductor die 66 is adhesively coupled to adhesive layer 64 .
- adhesive layer 64 is adhesively coupled to base layer 62 which allows adhesive layer 64 and base layer 62 to be removed.
- semiconductor 60 has been separated into several portions: a top portion 87 , a side portion 88 , a side portion 89 , a partial-bottom portion 83 , and a partial-bottom 85 .
- Top portion 87 , side portion 88 , side portion 89 , partial-bottom portion 83 , and partial-bottom portion 85 of semiconductor die 66 are encapsulated up to encapsulant barrier 80 using encapsulant 86 .
- Encapsulant 86 is provided using any appropriate encapsulating method, such as, for example, injection molding or transfer molding. Other methods of encapsulation may alternately be used, such as, for example, dispense molding, screen printing or extrusion coating.
- encapsulant barrier 80 acts as a barrier to prevent encapsulant 86 from bleeding onto active region 67 . It should be noted that in the embodiment of FIG. 5 that encapsulant barrier 80 laps over the edge of the passivation layer having portions 101 - 109 so that a portion of the encapsulant barrier 80 is in direct contact with die surface 68 while the other portion of encapsulant barrier 80 is located entirely between the passivation layer formed of portions 101 - 109 and the adhesive layer 64 . Adhesive layer 64 and base layer 62 may then be removed allowing contact pads 71 - 77 to be available as contact pads free of encapsulant 86 .
- FIG. 6 illustrates semiconductor device 60 according to one embodiment of the present invention.
- encapsulant barrier 80 of FIG. 5 has been replaced with encapsulant barrier 82 , the entire portion of which is located entirely between the passivation layer having portions 101 - 109 and the adhesive layer 64 , thereby forming a seal.
- the description of the semiconductor device 60 of FIG. 5 applies to the description of semiconductor device 60 of FIG. 6 and will not be discussed further in detail.
- FIG. 7 illustrates a bottom plan view of a semiconductor device 90 according to one embodiment of the present invention.
- Semiconductor device 90 includes a semiconductor die 95 , a circuit 94 , an active region 98 , an encapsulation barrier 92 , and a conductor 96 .
- Circuit 94 may be positioned in any area of the semiconductor die 95 and may be of any size. It should be understood that as illustrated FIG. 7 is not necessarily drawn to scale.
- conductor 96 provides conductive connection between circuit 94 and encapsulation barrier 92 .
- encapsulation barrier 92 serves not only to prevent encapsulant material 30 of FIGS. 1 and 2 from bleeding onto active region 98 , but may also serve as a conductor to propagate or shield electrical signals.
- encapsulant barrier 92 may be used as an electrical shield for circuit 94 to isolate electromagnetic interference. In another embodiment, encapsulant barrier 92 may be electrically coupled to circuit 94 and used to implement an electrical function in the circuit. For example, in one embodiment encapsulant barrier 92 may be used as an antenna. In another embodiment, encapsulant barrier 92 may implement the electrical function of an inductor.
- plurality is defined as two or more than two.
- another is defined as at least a second or more.
- the terms including and/or having, as used herein, are defined as comprising (i.e., open language).
- coupled is defined as connected, although not necessarily directly, and not necessarily mechanically.
- substantially is defined as at least approaching a given state or value (e.g., preferably within 10% of).
Abstract
A semiconductor device includes a semiconductor die having a plurality of contact pad sites, a plurality of contact pads, an encapsulant barrier, and an encapsulant. A plurality of contact pads is in electrical contact with a predetermined corresponding different one of the contact pad sites. An encapsulant barrier is positioned at an outer perimeter of the semiconductor die. The encapsulant barrier has a height that is as high as or greater than a highest of the plurality of contact pads. The encapsulant barrier is in physical contact with a same surface of the semiconductor die as the contact pad sites. An encapsulant surrounds the semiconductor die and one side of the encapsulant barrier. The encapsulant is blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier when the device is encapsulated while being supported by a temporary base support layer.
Description
- The present invention relates to semiconductor devices, and more specifically to protecting specific regions of semiconductor devices.
- During the semiconductor manufacturing process, it is often desirable to prevent molding material from bleeding over to active regions of the semiconductor. That is, during the encapsulation process of manufacturing semiconductor devices, the molding material used to encapsulate the semiconductor die (e.g., resin) can bleed over to active regions of the semiconductor where such molding material is undesired.
- Current bleed prevention techniques utilize trenches or dams to prevent the molding material from bleeding onto the substrate or lead frame leads. However, if, for example, the trench or damn depth is not sufficient enough to hold the molding material, these techniques will not necessarily prevent the molding material from bleeding onto the die face itself. Other bleed prevention techniques rely on high clamping force to prevent resin from bleeding onto the exposed pad of an exposed pad package. Although the high clamping force may prove useful in some situations, using such a method is sometimes unpredictable in terms of reliability and yield. Another way to deal with molding material that has bleed over into active regions of the semiconductor die is to apply surface treatments to prevent wetting on the active region or to remove the unwanted molding material. Although using surface treatments may prevent or facilitate removal of the unwanted molding material, the excess chemicals utilized often have undesirable effects on the active regions of the semiconductor die.
- The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:
-
FIG. 1 illustrates a cross-sectional view of a semiconductor device in accordance with one embodiment of the present invention; -
FIG. 2 illustrates the semiconductor device ofFIG. 1 taken along line 2-2; -
FIG. 3 illustrates a bottom view of a semiconductor device, in accordance with one embodiment of the present invention; -
FIG. 4 illustrates a bottom view of a semiconductor device, in accordance with another embodiment of the present invention; and -
FIG. 5 illustrates a cross-sectional view of a semiconductor device, in accordance with one embodiment of the present invention; -
FIG. 6 illustrates a cross-sectional view of a semiconductor device, in accordance with another embodiment of the present invention; and -
FIG. 7 illustrates a bottom plan view of a semiconductor device, in accordance with another embodiment of the present invention. - Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
- There is disclosed herein an improved encapsulant bleed prevention technique that prevents molding material from permeating an active region of a semiconductor die. In one embodiment, a semiconductor device includes a semiconductor die, a plurality of contact pads, an encapsulant barrier, a first layer, a second layer, and an encapsulant. The semiconductor die has a first surface and a second surface that are opposite each other. The first surface of the semiconductor die has a plurality of contact pad sites. Each of the plurality of contact pads have substantially the same predetermined height and have a first end and a second end. The first end of each of the plurality of contact pads is in electrical contact with a predetermined corresponding different one of the plurality of contact pad sites. The encapsulant barrier is positioned at a periphery of the plurality of contact pads and has substantially the same predetermined height of the plurality of contact pads. The encapsulant barrier is in physical contact with the first surface of the semiconductor die. The first layer has a first surface and a second surface, the first surface of the first layer being in direct physical contact with the second end of each of the plurality of contact pads. The second layer is in direct physical contact with the first layer. The encapsulant surrounds the second surface of the semiconductor die and is blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier. The first layer and the second layer are releasable from the semiconductor die after curing of the encapsulant. In one form the encapsulant barrier is a same material as the plurality of contact pads. In another form the encapsulant barrier is a different material than the plurality of contact pads.
- In one embodiment, a semiconductor device includes a semiconductor die, a plurality of contact pads, an encapsulant barrier, a removable first layer, a second removable layer, and an encapsulant. The semiconductor die has a plurality of contact pad sites. The plurality of contact pads are in electrical contact with a predetermined corresponding different one of the plurality of contact pad sites. The encapsulant barrier is positioned at an outer perimeter of the semiconductor die. The encapsulant barrier has a height that is substantially as large as a highest of the plurality of contact pads. The encapsulant barrier is in physical contact with a same surface of the semiconductor die as the contact pad sites. The removable first layer has a first surface and a second surface. The first surface of the first layer is in direct physical contact with each of the plurality of contact pads. The second removable layer is in direct physical contact with the first removable layer. The encapsulant surrounds the semiconductor die but is blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier. The first layer and the second layer are removed from the semiconductor die after curing of the encapsulant.
- In one embodiment, a semiconductor device includes a semiconductor die, a plurality of contact pads, an encapsulant barrier, and an encapsulant. The semiconductor die has a plurality of contact pad sites. The plurality of contact pads are in electrical contact with a predetermined corresponding different one of the plurality of contact pad sites. The encapsulant barrier is positioned at an outer perimeter of the semiconductor die. The encapsulant barrier has a height that is as high as or greater than a highest of the plurality of contact pads. The encapsulant barrier is in physical contact with a same surface of the semiconductor die as the contact pad sites. The encapsulant surrounds the semiconductor die and one side of the encapsulant barrier. The encapsulant is blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier when the device is encapsulated while being supported by a temporary base support layer.
- Another embodiment of the present invention relates to a method of protecting a semiconductor die during encapsulation. A plurality of contact pad sites is provided on a side of the semiconductor die. A plurality of contact pads are formed within the plurality of contact pad sites. Each of the plurality of contact pads have substantially the same predetermined height and have a first end and a second end. The first end of each of the plurality of contact pads are in electrical contact with a predetermined corresponding different one of the plurality of contact pad sites. An encapsulant barrier is provided at a periphery of the plurality of contact pads. The encapsulant barrier has substantially the same predetermined height of the plurality of contact pads. The encapsulant barrier is in physical contact with the first surface of the semiconductor die. A first layer is provided having a first surface and a second surface. The first surface of the first layer is in direct physical contact with the second end of each of the plurality of contact pads. A second layer is provided that is in direct physical contact with the first layer. The second surface of the semiconductor die is encapsulated and the encapsulant is blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier. The first layer and the second layer are removed from the semiconductor die after the encapsulant has cured.
-
FIG. 1 illustrates asemiconductor device 10 according to one embodiment of the present invention.Semiconductor device 10 includes abase layer 12, anadhesive layer 14, asemiconductor die 16, anencapsulant barrier 18, acontact pad 20, acontact pad 21, acontact pad 22, acontact pad 23, acontact pad 24, acontact pad 25, acontact pad 26, anactive surface 28, and anencapsulant 30. - In one embodiment of the present invention,
adhesive layer 14 may be formed of any material that is adhesive. In one form,adhesive layer 14 is a tape having an adhesive surface in contact with contact pads 20-26. In another form,adhesive layer 14 is a silicone or acrylic-based material. For some embodiments,adhesive layer 14 may be removed, for example, if theadhesive layer 14 is an adhesive tape. - In one embodiment of the present invention,
encapsulant 30 may be any type of non-electrically conductive material that can be molded, such as, for example, thermoset mold compounds or filled thermoplastic resins which act as insulating materials. In alternate embodiments of the present invention,encapsulant 30 may be any type of electrically conductive material that can be molded, such as, for example, thermoset epoxy with metallic filler or thermoplastic with metallic filler. The metallic filler may be any suitable electrically conductive material, such as, for example, silver, copper, electrically conductive coated polymer spheres, and conductive nano-particles. The metallic filler may be in particle form. In one embodiment,encapsulant barrier 18 may be formed of metal, such as aluminum, copper, aluminum alloys, copper alloys, etc. In another embodiment,encapsulant barrier 18 may be polyimide, or other organic base passivation materials. - During the semiconductor manufacturing process, contact pads 20-26 and
encapsulant barrier 18 are formed onactive region 28 of semiconductor die 16 using standard metallization techniques, such as, for example, an additive plating technique or a subtractive etching technique. In the embodiment,active region 28 includes a plurality of contact pads 20-26 and the corresponding air gaps (spaces) located between contact pads 20-26. Alternate embodiments of the present invention may include a greater or lesser number of contact pads then those shown inFIG. 1 . In the illustrated embodiment,active region 28 excludes the portion of the semiconductor die 16 outside ofencapsulation barrier 18. In alternate embodiments,active region 28 may include other portions of semiconductor die 16 within other encapsulation barriers. In one embodiment,active region 28 of semiconductor die 16 is adhesively coupled toadhesive layer 14. In addition,adhesive layer 14 is adhesively coupled tobase layer 12 in such a fashion that both theadhesive layer 14 andbase layer 12 may be removed. - For ease of explanation,
semiconductor 16 has been separated into several portions: atop portion 17, aside portion 13, aside portion 15, a partial-bottom portion 11, a partial-bottom portion 9, and abottom surface 29.Top portion 17,side portion 13,side portion 15, partial-bottom portion 11, and partial-bottom portion 9 of semiconductor die 16 are encapsulated up toencapsulant barrier 18 usingencapsulant 30.Encapsulant 30 may be provided using any appropriate encapsulating method, such as, for example, dispense, injection or transfer molding, screen printing or extrusion coating.Encapsulant barrier 18 when in contact withadhesive layer 14 acts as a barrier to preventencapsulant 30 from bleeding ontoactive region 28. In one embodiment, after encapsulation occurs,adhesive layer 14 andbase layer 12 are removed allowing contact pads 20-26 to be available conductors free ofencapsulant 30. - As stated previously, the use of
encapsulation barrier 18 preventsencapsulant 30 from bleeding onto or permeatingactive region 28 of semiconductor die 16. In one embodiment,encapsulation barrier 18 may be located at several locations on semiconductor die 16, such thatencapsulation barrier 18 surrounds a region or regions of semiconductor die 16 (active or non-active), that are to remain free ofencapsulant 30. For example, in oneembodiment encapsulation barrier 18 may be located around the perimeter ofsemiconductor device 16 such thatencapsulation barrier 18 is in the form of a ring. Alternatively,encapsulation barrier 18 may take the form of shapes other than a ring. For example, in oneembodiment encapsulation barrier 18 may be in the form of a spiral, spiraling around contact pads that are to remain free ofencapsulant 30. - The height of
encapsulation barrier 18 may vary depending on the height of contact pads 20-26 being used bysemiconductor device 10. In one embodiment, the height of theencapsulant barrier 18 must be at least the height of the contact pad of contact pads 20-26 that has the maximum height. That is, the height of contact pads 20-26 may vary, but as long as the height ofencapsulation barrier 18 is at least the height of the contact pad with the maximum height,encapsulation barrier 18 will preventencapsulant 30 from permeating beyondencapsulant barrier 18. -
Encapsulation barrier 18 may be formed at different times within the semiconductor manufacturing process. The exact time whenencapsulation barrier 18 is formed varies depending on the metallization process, panelization process, etc., being used to manufacturesemiconductor device 10. For example,encapsulant barrier 18 may be formed using redistribution metal added to semiconductor die 16. -
FIG. 2 illustrates a bottom view ofsemiconductor device 10 depicted inFIG. 1 . In the embodiment shown,encapsulant barrier 18 is positioned along the outer edges of semiconductor die 16 surrounding the contact pads, such as contact pads 20-26.Encapsulant barrier 18 preventsencapsulant 30 ofFIG. 1 from bleeding intoactive region 28 ofFIG. 1 . -
FIG. 3 illustrates asemiconductor device 32 according to one embodiment of the present invention.Semiconductor device 32 may be manufactured according to the manufacturing processes described earlier in the description ofFIG. 1 . Anencapsulation barrier 36 is located on semiconductor die 34.Encapsulation barrier 36 surrounds the contact pads such ascontact pad 38. In one embodiment,encapsulation barrier 36 is in the form of a spiral having a height substantially equivalent to the tallest of the contact pads, such ascontact pad 38, as measured from the die surface.Encapsulation barrier 36 has avent opening 33 which allows for expanding gases to be released out ofactive region 35 while preventingencapsulant 30 ofFIGS. 1 and 2 from enteringactive region 35. -
FIG. 4 illustrates asemiconductor device 40 according to one embodiment of the present invention.Semiconductor device 40 includes semiconductor die 42, a plurality of contact pads such ascontact pad 55,encapsulation barrier 44,active region 57, vent 49, vent 51, vent 56, and vent 59. In one embodiment,semiconductor device 40 includes several variations of ventilation, such as, for example, ventingportion 48, ventingportion 54, ventingportion 58, and ventingportion 50. Each ventingportion FIG. 4 by a dashed line solely for purposes of illustration and does not indicate a hidden underlying structure. Each venting portion allows for expanding gases to be circulated out ofactive region 57 while preventingencapsulant 30 ofFIGS. 1 and 2 from enteringactive region 57. In one embodiment,encapsulation barrier 45 is placed parallel to the portion ofencapsulation barrier 44 havingvent 56. In another embodiment,encapsulation barrier 47 is placed insideactive region 57 and parallel to the portion ofencapsulation barrier 44 havingvent 51. In one embodiment, ventingportion 48 takes the shape of an elongated staple having a portion ofencapsulation barrier 44 fit into its opening. Other embodiments of ventilating portions may exist that take the form of the ventilating portions shown or not shown. -
FIG. 5 illustrates asemiconductor device 60 according to one embodiment of the present invention. In one embodiment,semiconductor device 60 includes abase layer 62, anadhesive layer 64, asemiconductor die 66, anencapsulant barrier 80, acontact pad 71, acontact pad 72, acontact pad 73, acontact pad 74, acontact pad 75, acontact pad 76, and acontact pad 77.Semiconductor device 60 further includes anactive region 67, and a passivation layer having apassivation layer portion 101, apassivation layer portion 102, apassivation layer portion 103, apassivation layer portion 104, apassivation layer portion 105, apassivation layer portion 106, apassivation layer portion 107, apassivation layer portion 108 and apassivation layer portion 109.Semiconductor device 60 also includes anencapsulant 86 and anair gap 84. - In one embodiment of
semiconductor device 60 illustrated inFIG. 5 ,adhesive layer 64 may be formed of any material that is adhesive. In one embodiment,adhesive layer 64 is a tape having an adhesive surface in contact with contact pads 71-77. In an alternate embodiment,adhesive layer 64 may be an epoxy based material. For some embodiments of the present invention,adhesive layer 64 may be removed, for example, if theadhesive layer 64 is an adhesive tape. - In some embodiments of the present invention,
encapsulant 86 may be any type of non-electrically conductive material that can be molded, such as, for example, thermoset mold compounds or filled thermoplastic resins which act as insulating materials. In alternate embodiments of the present invention,encapsulant 30 may be any type of electrically conductive material that can be molded, such as, for example, thermoset epoxy with metallic filler or thermoplastic with metallic filler. The metallic filler may be any suitable electrically conductive material, such as, for example, silver, copper, electrically conductive coated polymer spheres, and conductive nano-particles. The metallic filler may be in particle form. In one embodiment,encapsulant barrier 80 may be formed of metal, such as aluminum, copper, aluminum alloys, copper alloys, etc. In another embodiment,encapsulant barrier 80 may be polyimide, or other organic base passivation materials. - Referring to
semiconductor device 60, during the manufacturing process, the passivation layer formed of portions 101-109 is formed on semiconductor die 66. In one embodiment, contact pads 71-77 andencapsulant barrier 80 are formed onactive region 67 of semiconductor die 66 using any one of various metallization techniques known in the art. In one embodiment, the passivation layer formed of portions 101-109 is interposed between contact pads 71-77 and thebottom surface 68 of semiconductor die 66. Anair gap 84 surrounds contact pads 71-77. Theair gap 84 is enclosed withinencapsulant barrier 80 and betweenadhesive layer 64 and the passivation layer formed of portions 101-109. Alternate embodiments of the present invention may include a greater or lesser number of contact pads inactive region 67. In the illustrated embodiment,active region 67 may be considered the bottom of semiconductor die 66, excluding the portions of the semiconductor die 66 outside ofencapsulant barrier 80. In alternate embodiments,active region 67 may include other portions of semiconductor die 66 withinencapsulant barrier 80. In one embodiment,active region 67 of semiconductor die 66 is adhesively coupled toadhesive layer 64. In addition,adhesive layer 64 is adhesively coupled tobase layer 62 which allowsadhesive layer 64 andbase layer 62 to be removed. - For ease of explanation,
semiconductor 60 has been separated into several portions: atop portion 87, aside portion 88, aside portion 89, a partial-bottom portion 83, and a partial-bottom 85.Top portion 87,side portion 88,side portion 89, partial-bottom portion 83, and partial-bottom portion 85 of semiconductor die 66 are encapsulated up toencapsulant barrier 80 usingencapsulant 86.Encapsulant 86 is provided using any appropriate encapsulating method, such as, for example, injection molding or transfer molding. Other methods of encapsulation may alternately be used, such as, for example, dispense molding, screen printing or extrusion coating. In one embodiment,encapsulant barrier 80 acts as a barrier to preventencapsulant 86 from bleeding ontoactive region 67. It should be noted that in the embodiment ofFIG. 5 thatencapsulant barrier 80 laps over the edge of the passivation layer having portions 101-109 so that a portion of theencapsulant barrier 80 is in direct contact withdie surface 68 while the other portion ofencapsulant barrier 80 is located entirely between the passivation layer formed of portions 101-109 and theadhesive layer 64.Adhesive layer 64 andbase layer 62 may then be removed allowing contact pads 71-77 to be available as contact pads free ofencapsulant 86. -
FIG. 6 illustratessemiconductor device 60 according to one embodiment of the present invention. In one embodiment shown inFIG. 6 ,encapsulant barrier 80 ofFIG. 5 has been replaced withencapsulant barrier 82, the entire portion of which is located entirely between the passivation layer having portions 101-109 and theadhesive layer 64, thereby forming a seal. The description of thesemiconductor device 60 ofFIG. 5 applies to the description ofsemiconductor device 60 ofFIG. 6 and will not be discussed further in detail. -
FIG. 7 illustrates a bottom plan view of asemiconductor device 90 according to one embodiment of the present invention.Semiconductor device 90 includes asemiconductor die 95, acircuit 94, anactive region 98, anencapsulation barrier 92, and aconductor 96.Circuit 94 may be positioned in any area of the semiconductor die 95 and may be of any size. It should be understood that as illustratedFIG. 7 is not necessarily drawn to scale. In one embodiment,conductor 96 provides conductive connection betweencircuit 94 andencapsulation barrier 92. In addition,encapsulation barrier 92 serves not only to preventencapsulant material 30 ofFIGS. 1 and 2 from bleeding ontoactive region 98, but may also serve as a conductor to propagate or shield electrical signals. In one embodiment,encapsulant barrier 92 may be used as an electrical shield forcircuit 94 to isolate electromagnetic interference. In another embodiment,encapsulant barrier 92 may be electrically coupled tocircuit 94 and used to implement an electrical function in the circuit. For example, in oneembodiment encapsulant barrier 92 may be used as an antenna. In another embodiment,encapsulant barrier 92 may implement the electrical function of an inductor. - In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
- Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms a or an, as used herein, are defined as one or more than one. The term plurality, as used herein, is defined as two or more than two. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically. The term substantially, as used herein, is defined as at least approaching a given state or value (e.g., preferably within 10% of).
Claims (17)
1. A semiconductor device, comprising:
a semiconductor die having a first surface and a second surface that are opposite each other, the first surface having a plurality of contact pad sites;
a plurality of contact pads, each of the plurality of contact pads having a substantially same predetermined height and having a first end and a second end, the first end of each of the plurality of contact pads being in electrical contact with a predetermined corresponding different one of the plurality of contact pad sites;
an encapsulant barrier positioned at a periphery of the plurality of contact pads, the encapsulant barrier having substantially the same predetermined height of the plurality of contact pads, the encapsulant barrier having a first surface and an opposing second surface, the first surface being in physical contact with the first surface of the semiconductor die;
a first layer having a first surface and a second surface, the first surface of the first layer being in direct physical contact with the second surface of the encapsulant barrier and the second end of each of the plurality of contact pads;
a second layer in direct physical contact with the first layer; and
an encapsulant surrounding the second surface of the semiconductor die and being blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier, wherein the first layer and the second layer are releasable from the semiconductor die after curing of the encapsulant.
2. The semiconductor device of claim 1 wherein the encapsulant barrier further comprises at least one vent for release of any expanding gases within air space separating the plurality of contact pads.
3. The semiconductor device of claim 1 wherein the encapsulant barrier is comprised of a same material as the plurality of contact pads.
4. The semiconductor device of claim 1 wherein the encapsulant barrier is comprised of a different material than the plurality of contact pads.
5. The semiconductor device of claim 1 further comprising:
a circuit implemented on the semiconductor die, the circuit using the encapsulant barrier as one of an electrical shield to isolate electromagnetic interference, an antenna or an inductor.
6. The semiconductor device of claim 5 wherein the circuit is electrically coupled to the encapsulant barrier.
7. The semiconductor device of claim 1 further comprising:
a circuit implemented on the semiconductor die, the circuit being electrically coupled to the encapsulant barrier for using the encapsulant barrier to implement an electrical function in the circuit.
8. The semiconductor device of claim 1 further comprising:
a passivation layer interposed between the plurality of contact pads and the first surface of the semiconductor die, wherein a portion of the encapsulant barrier is in physical contact with the passivation layer.
9. A semiconductor device, comprising:
a semiconductor die having a plurality of contact pad sites;
a plurality of contact pads in electrical contact with a predetermined corresponding different one of the plurality of contact pad sites;
an encapsulant barrier positioned at an outer perimeter of the semiconductor die, the encapsulant barrier having a height that is substantially as large as a highest of the plurality of contact pads, the encapsulant barrier having a first surface and a second surface, the first surface being in physical contact with a same surface of the semiconductor die as the plurality of contact pad sites;
a removable first layer having a first surface and a second surface, the first surface of the removable first layer being in direct physical contact with the second surface of the encapsulant barrier;
a second removable layer in direct physical contact with the removable first layer; and
an encapsulant surrounding the semiconductor die but being blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier, wherein the removable first layer and the removable second layer are removed from the semiconductor die after curing of the encapsulant.
10. The semiconductor device of claim 9 wherein the encapsulant barrier further comprises at least one vent for release of any expanding gases within an air space separating the plurality of con tact pads.
11. The semiconductor device of claim 9 further comprising:
a circuit implemented on the semiconductor die, the circuit using the encapsulant barrier as one of an electrical shield to isolate electromagnetic interference, an antenna or an inductor.
12. The semiconductor device of claim 9 further comprising:
a circuit implemented on the semiconductor die, the circuit being electrically coupled to the encapsulant barrier for using the encapsulant barrier to implement an electrical function in the circuit.
13. A semiconductor device, comprising:
a semiconductor die having a plurality of contact pad sites;
a plurality of contact pads in electrical contact with a predetermined corresponding different one of the plurality of contact pad sites;
an encapsulant barrier positioned at an outer perimeter of the semiconductor die, the encapsulant barrier having a height that is as high as or greater than a highest of the plurality of contact pads, the encapsulant barrier being in physical contact with a same surface of the semiconductor die as the contact pad sites; and
an encapsulant surrounding the semiconductor die and one side of the encapsulant barrier, the encapsulant being blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier when the semiconductor device is encapsulated while being supported by a temporary base support layer.
14. The semiconductor device of claim 13 wherein the encapsulant barrier further comprises at least one vent for release of any expanding gases within air spaces separating the plurality of contact pads.
15. The semiconductor device of claim 13 further comprising:
a circuit implemented on the semiconductor die, the circuit using the encapsulant barrier as one of an electrical shield to isolate electromagnetic interference, an antenna or an inductor.
16. The semiconductor device of claim 13 further comprising:
a circuit implemented on the semiconductor die, the circuit being electrically coupled to the encapsulant barrier for using the encapsulant barrier to implement an electrical function in the circuit.
17-20. (canceled)
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/837,266 US20050242425A1 (en) | 2004-04-30 | 2004-04-30 | Semiconductor device with a protected active die region and method therefor |
KR1020067022666A KR20070006880A (en) | 2004-04-30 | 2005-03-16 | Semiconductor device with a protected active die region and method thereof |
CNB2005800131280A CN100424865C (en) | 2004-04-30 | 2005-03-16 | Semiconductor device with a protected active die region and method therefor |
PCT/US2005/008910 WO2005112116A1 (en) | 2004-04-30 | 2005-03-16 | Semiconductor device with a protected active die region and method therefor |
JP2007510732A JP2007535811A (en) | 2004-04-30 | 2005-03-16 | Semiconductor device with protected activated die region and method thereof |
TW094110544A TW200603220A (en) | 2004-04-30 | 2005-04-01 | Semiconductor device with a protected active die region and method therefor |
MYPI20051573A MY140584A (en) | 2004-04-30 | 2005-04-08 | Semiconductor device with a protected active die region and method therefor |
US11/373,087 US7579219B2 (en) | 2004-04-30 | 2006-03-10 | Semiconductor device with a protected active die region and method therefor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/837,266 US20050242425A1 (en) | 2004-04-30 | 2004-04-30 | Semiconductor device with a protected active die region and method therefor |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/373,087 Division US7579219B2 (en) | 2004-04-30 | 2006-03-10 | Semiconductor device with a protected active die region and method therefor |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050242425A1 true US20050242425A1 (en) | 2005-11-03 |
Family
ID=35186217
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/837,266 Abandoned US20050242425A1 (en) | 2004-04-30 | 2004-04-30 | Semiconductor device with a protected active die region and method therefor |
US11/373,087 Active 2026-02-17 US7579219B2 (en) | 2004-04-30 | 2006-03-10 | Semiconductor device with a protected active die region and method therefor |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/373,087 Active 2026-02-17 US7579219B2 (en) | 2004-04-30 | 2006-03-10 | Semiconductor device with a protected active die region and method therefor |
Country Status (7)
Country | Link |
---|---|
US (2) | US20050242425A1 (en) |
JP (1) | JP2007535811A (en) |
KR (1) | KR20070006880A (en) |
CN (1) | CN100424865C (en) |
MY (1) | MY140584A (en) |
TW (1) | TW200603220A (en) |
WO (1) | WO2005112116A1 (en) |
Cited By (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080119015A1 (en) * | 2006-11-17 | 2008-05-22 | Mangrum Marc A | Method of packaging a semiconductor device and a prefabricated connector |
US20080116560A1 (en) * | 2006-11-17 | 2008-05-22 | Mangrum Marc A | Method of packaging a device having a tangible element and device thereof |
US20080164593A1 (en) * | 2007-01-05 | 2008-07-10 | Hess Kevin J | Method of packaging semiconductor devices |
WO2008088306A2 (en) * | 2006-12-20 | 2008-07-24 | Solid State Cooling, Inc. | Thermoenergy devices and methods for manufacturing same |
US7476563B2 (en) | 2006-11-17 | 2009-01-13 | Freescale Semiconductor, Inc. | Method of packaging a device using a dielectric layer |
US7671457B1 (en) | 2002-05-01 | 2010-03-02 | Amkor Technology, Inc. | Semiconductor package including top-surface terminals for mounting another semiconductor package |
US20100052106A1 (en) * | 2008-08-29 | 2010-03-04 | Chu-Chung Lee | Package device having crack arrest feature and method of forming |
US7692286B1 (en) | 2002-11-08 | 2010-04-06 | Amkor Technology, Inc. | Two-sided fan-out wafer escape package |
US7723210B2 (en) | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US7807511B2 (en) | 2006-11-17 | 2010-10-05 | Freescale Semiconductor, Inc. | Method of packaging a device having a multi-contact elastomer connector contact area and device thereof |
US7825520B1 (en) | 2006-11-16 | 2010-11-02 | Amkor Technology, Inc. | Stacked redistribution layer (RDL) die assembly package |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US7960827B1 (en) | 2009-04-09 | 2011-06-14 | Amkor Technology, Inc. | Thermal via heat spreader package and method |
US7977163B1 (en) | 2005-12-08 | 2011-07-12 | Amkor Technology, Inc. | Embedded electronic component package fabrication method |
US8018068B1 (en) | 2004-03-23 | 2011-09-13 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
US8222538B1 (en) | 2009-06-12 | 2012-07-17 | Amkor Technology, Inc. | Stackable via package and method |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8300423B1 (en) | 2010-05-25 | 2012-10-30 | Amkor Technology, Inc. | Stackable treated via package and method |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8337657B1 (en) | 2010-10-27 | 2012-12-25 | Amkor Technology, Inc. | Mechanical tape separation package and method |
US8338229B1 (en) | 2010-07-30 | 2012-12-25 | Amkor Technology, Inc. | Stackable plasma cleaned via package and method |
US8341835B1 (en) | 2002-05-01 | 2013-01-01 | Amkor Technology, Inc. | Buildup dielectric layer having metallization pattern semiconductor package fabrication method |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US8471154B1 (en) | 2009-08-06 | 2013-06-25 | Amkor Technology, Inc. | Stackable variable height via package and method |
US8482134B1 (en) | 2010-11-01 | 2013-07-09 | Amkor Technology, Inc. | Stackable package and method |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
US8525318B1 (en) | 2010-11-10 | 2013-09-03 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8536462B1 (en) | 2010-01-22 | 2013-09-17 | Amkor Technology, Inc. | Flex circuit package and method |
US8535961B1 (en) | 2010-12-09 | 2013-09-17 | Amkor Technology, Inc. | Light emitting diode (LED) package and method |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
US8557629B1 (en) | 2010-12-03 | 2013-10-15 | Amkor Technology, Inc. | Semiconductor device having overlapped via apertures |
US8623753B1 (en) | 2009-05-28 | 2014-01-07 | Amkor Technology, Inc. | Stackable protruding via package and method |
US8633598B1 (en) | 2011-09-20 | 2014-01-21 | Amkor Technology, Inc. | Underfill contacting stacking balls package fabrication method and structure |
US8653674B1 (en) | 2011-09-15 | 2014-02-18 | Amkor Technology, Inc. | Electronic component package fabrication method and structure |
US8717775B1 (en) | 2010-08-02 | 2014-05-06 | Amkor Technology, Inc. | Fingerprint sensor package and method |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US8890329B2 (en) | 2011-04-26 | 2014-11-18 | Amkor Technology, Inc. | Semiconductor device |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US9013011B1 (en) | 2011-03-11 | 2015-04-21 | Amkor Technology, Inc. | Stacked and staggered die MEMS package and method |
US9029962B1 (en) | 2011-10-12 | 2015-05-12 | Amkor Technology, Inc. | Molded cavity substrate MEMS package fabrication method and structure |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US9391043B2 (en) | 2012-11-20 | 2016-07-12 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US9543242B1 (en) | 2013-01-29 | 2017-01-10 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
US9691635B1 (en) | 2002-05-01 | 2017-06-27 | Amkor Technology, Inc. | Buildup dielectric layer having metallization pattern semiconductor package fabrication method |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US9704842B2 (en) | 2013-11-04 | 2017-07-11 | Amkor Technology, Inc. | Interposer, manufacturing method thereof, semiconductor package using the same, and method for fabricating the semiconductor package |
US9704747B2 (en) | 2013-03-29 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US9721872B1 (en) | 2011-02-18 | 2017-08-01 | Amkor Technology, Inc. | Methods and structures for increasing the allowable die size in TMV packages |
US9748154B1 (en) | 2010-11-04 | 2017-08-29 | Amkor Technology, Inc. | Wafer level fan out semiconductor device and manufacturing method thereof |
US20170352613A1 (en) * | 2016-06-03 | 2017-12-07 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US9960328B2 (en) | 2016-09-06 | 2018-05-01 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US10811277B2 (en) | 2004-03-23 | 2020-10-20 | Amkor Technology, Inc. | Encapsulated semiconductor package |
US11081370B2 (en) | 2004-03-23 | 2021-08-03 | Amkor Technology Singapore Holding Pte. Ltd. | Methods of manufacturing an encapsulated semiconductor device |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102008058003B4 (en) * | 2008-11-19 | 2012-04-05 | Infineon Technologies Ag | Method for producing a semiconductor module and semiconductor module |
KR101429344B1 (en) | 2012-08-08 | 2014-08-12 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor Package and Manufacturing Methode thereof |
KR20140038116A (en) | 2012-09-20 | 2014-03-28 | 제이앤제이 패밀리 주식회사 | Led lamp |
KR101494417B1 (en) * | 2013-04-22 | 2015-02-17 | 주식회사 네패스 | Semiconductor package and method of manufacturing the same |
US9929078B2 (en) * | 2016-01-14 | 2018-03-27 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
Citations (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4630096A (en) * | 1984-05-30 | 1986-12-16 | Motorola, Inc. | High density IC module assembly |
US4722914A (en) * | 1984-05-30 | 1988-02-02 | Motorola Inc. | Method of making a high density IC module assembly |
US4783695A (en) * | 1986-09-26 | 1988-11-08 | General Electric Company | Multichip integrated circuit packaging configuration and method |
US4792533A (en) * | 1987-03-13 | 1988-12-20 | Motorola Inc. | Coplanar die to substrate bond method |
US4890156A (en) * | 1987-03-13 | 1989-12-26 | Motorola Inc. | Multichip IC module having coplanar dice and substrate |
US5147815A (en) * | 1990-05-14 | 1992-09-15 | Motorola, Inc. | Method for fabricating a multichip semiconductor device having two interdigitated leadframes |
US5161093A (en) * | 1990-07-02 | 1992-11-03 | General Electric Company | Multiple lamination high density interconnect process and structure employing a variable crosslinking adhesive |
US5222014A (en) * | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
US5315486A (en) * | 1991-12-16 | 1994-05-24 | General Electric Company | Hermetically packaged HDI electronic system |
US5353498A (en) * | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US5450283A (en) * | 1992-11-03 | 1995-09-12 | Motorola, Inc. | Thermally enhanced semiconductor device having exposed backside and method for making the same |
US5495398A (en) * | 1992-05-22 | 1996-02-27 | National Semiconductor Corporation | Stacked multi-chip modules and method of manufacturing |
US5592025A (en) * | 1992-08-06 | 1997-01-07 | Motorola, Inc. | Pad array semiconductor device |
US5841193A (en) * | 1996-05-20 | 1998-11-24 | Epic Technologies, Inc. | Single chip modules, repairable multichip modules, and methods of fabrication thereof |
US5989935A (en) * | 1996-11-19 | 1999-11-23 | Texas Instruments Incorporated | Column grid array for semiconductor packaging and method |
US6001672A (en) * | 1997-02-25 | 1999-12-14 | Micron Technology, Inc. | Method for transfer molding encapsulation of a semiconductor die with attached heat sink |
US6211462B1 (en) * | 1998-11-05 | 2001-04-03 | Texas Instruments Incorporated | Low inductance power package for integrated circuits |
US6225688B1 (en) * | 1997-12-11 | 2001-05-01 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
US20010013643A1 (en) * | 1998-09-18 | 2001-08-16 | Hiroyuki Nakanishi | Semiconductor integrated circuit device |
US6298551B1 (en) * | 1996-12-23 | 2001-10-09 | General Electric Company | Methods of forming compliant interface structures with partially open interiors for coupling two electrically conductive contact areas |
US6329224B1 (en) * | 1998-04-28 | 2001-12-11 | Tessera, Inc. | Encapsulation of microelectronic assemblies |
US6376914B2 (en) * | 1999-12-09 | 2002-04-23 | Atmel Corporation | Dual-die integrated circuit package |
US20020064931A1 (en) * | 2000-07-03 | 2002-05-30 | E. C. Ong | Method and apparatus for applying a protective over-coating to a ball-grid-array (BGA) structure |
US6426565B1 (en) * | 2000-03-22 | 2002-07-30 | International Business Machines Corporation | Electronic package and method of making same |
US20030087088A1 (en) * | 1999-12-27 | 2003-05-08 | Nitto Denko Corporation | Resin sealing method for semiconductors and release film used therefor |
US6661083B2 (en) * | 2001-02-27 | 2003-12-09 | Chippac, Inc | Plastic semiconductor package |
US6781229B1 (en) * | 2001-12-19 | 2004-08-24 | Skyworks Solutions, Inc. | Method for integrating passives on-die utilizing under bump metal and related structure |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0384338A (en) | 1989-08-28 | 1991-04-09 | Sanyo Electric Co Ltd | Exterior member |
JPH03132876A (en) | 1989-10-19 | 1991-06-06 | Nec Corp | Graphic data restoring system |
KR0149798B1 (en) | 1994-04-15 | 1998-10-01 | 모리시다 요이치 | Semiconductor device and method of manufacture and lead frame |
CN1146029C (en) * | 1995-06-30 | 2004-04-14 | 株式会社东芝 | Electronic component and method of production thereof |
US5866952A (en) | 1995-11-30 | 1999-02-02 | Lockheed Martin Corporation | High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate |
US6531763B1 (en) * | 2000-08-15 | 2003-03-11 | Micron Technology, Inc. | Interposers having encapsulant fill control features |
US6734534B1 (en) | 2000-08-16 | 2004-05-11 | Intel Corporation | Microelectronic substrate with integrated devices |
US6586822B1 (en) | 2000-09-08 | 2003-07-01 | Intel Corporation | Integrated core microelectronic package |
US6617524B2 (en) | 2001-12-11 | 2003-09-09 | Motorola, Inc. | Packaged integrated circuit and method therefor |
-
2004
- 2004-04-30 US US10/837,266 patent/US20050242425A1/en not_active Abandoned
-
2005
- 2005-03-16 WO PCT/US2005/008910 patent/WO2005112116A1/en active Application Filing
- 2005-03-16 JP JP2007510732A patent/JP2007535811A/en active Pending
- 2005-03-16 KR KR1020067022666A patent/KR20070006880A/en not_active Application Discontinuation
- 2005-03-16 CN CNB2005800131280A patent/CN100424865C/en active Active
- 2005-04-01 TW TW094110544A patent/TW200603220A/en unknown
- 2005-04-08 MY MYPI20051573A patent/MY140584A/en unknown
-
2006
- 2006-03-10 US US11/373,087 patent/US7579219B2/en active Active
Patent Citations (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4630096A (en) * | 1984-05-30 | 1986-12-16 | Motorola, Inc. | High density IC module assembly |
US4722914A (en) * | 1984-05-30 | 1988-02-02 | Motorola Inc. | Method of making a high density IC module assembly |
US4783695A (en) * | 1986-09-26 | 1988-11-08 | General Electric Company | Multichip integrated circuit packaging configuration and method |
US4792533A (en) * | 1987-03-13 | 1988-12-20 | Motorola Inc. | Coplanar die to substrate bond method |
US4890156A (en) * | 1987-03-13 | 1989-12-26 | Motorola Inc. | Multichip IC module having coplanar dice and substrate |
US5147815A (en) * | 1990-05-14 | 1992-09-15 | Motorola, Inc. | Method for fabricating a multichip semiconductor device having two interdigitated leadframes |
US5161093A (en) * | 1990-07-02 | 1992-11-03 | General Electric Company | Multiple lamination high density interconnect process and structure employing a variable crosslinking adhesive |
US5315486A (en) * | 1991-12-16 | 1994-05-24 | General Electric Company | Hermetically packaged HDI electronic system |
US5222014A (en) * | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
US5495398A (en) * | 1992-05-22 | 1996-02-27 | National Semiconductor Corporation | Stacked multi-chip modules and method of manufacturing |
US5592025A (en) * | 1992-08-06 | 1997-01-07 | Motorola, Inc. | Pad array semiconductor device |
US5450283A (en) * | 1992-11-03 | 1995-09-12 | Motorola, Inc. | Thermally enhanced semiconductor device having exposed backside and method for making the same |
US5353498A (en) * | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US5841193A (en) * | 1996-05-20 | 1998-11-24 | Epic Technologies, Inc. | Single chip modules, repairable multichip modules, and methods of fabrication thereof |
US6159767A (en) * | 1996-05-20 | 2000-12-12 | Epic Technologies, Inc. | Single chip modules, repairable multichip modules, and methods of fabrication thereof |
US5989935A (en) * | 1996-11-19 | 1999-11-23 | Texas Instruments Incorporated | Column grid array for semiconductor packaging and method |
US6298551B1 (en) * | 1996-12-23 | 2001-10-09 | General Electric Company | Methods of forming compliant interface structures with partially open interiors for coupling two electrically conductive contact areas |
US6403387B1 (en) * | 1997-02-25 | 2002-06-11 | Micron Technology | Method and apparatus for transfer molding encapsulation of a semiconductor die with attached heat sink |
US6001672A (en) * | 1997-02-25 | 1999-12-14 | Micron Technology, Inc. | Method for transfer molding encapsulation of a semiconductor die with attached heat sink |
US20040033644A1 (en) * | 1997-02-25 | 2004-02-19 | Wensel Richard W. | Methods for transfer molding encapsulation of a semiconductor die with attached heat sink |
US6225688B1 (en) * | 1997-12-11 | 2001-05-01 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
US6329224B1 (en) * | 1998-04-28 | 2001-12-11 | Tessera, Inc. | Encapsulation of microelectronic assemblies |
US20010013643A1 (en) * | 1998-09-18 | 2001-08-16 | Hiroyuki Nakanishi | Semiconductor integrated circuit device |
US6211462B1 (en) * | 1998-11-05 | 2001-04-03 | Texas Instruments Incorporated | Low inductance power package for integrated circuits |
US6376914B2 (en) * | 1999-12-09 | 2002-04-23 | Atmel Corporation | Dual-die integrated circuit package |
US20030087088A1 (en) * | 1999-12-27 | 2003-05-08 | Nitto Denko Corporation | Resin sealing method for semiconductors and release film used therefor |
US6426565B1 (en) * | 2000-03-22 | 2002-07-30 | International Business Machines Corporation | Electronic package and method of making same |
US20020064931A1 (en) * | 2000-07-03 | 2002-05-30 | E. C. Ong | Method and apparatus for applying a protective over-coating to a ball-grid-array (BGA) structure |
US6661083B2 (en) * | 2001-02-27 | 2003-12-09 | Chippac, Inc | Plastic semiconductor package |
US6781229B1 (en) * | 2001-12-19 | 2004-08-24 | Skyworks Solutions, Inc. | Method for integrating passives on-die utilizing under bump metal and related structure |
Cited By (129)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10461006B1 (en) | 2002-05-01 | 2019-10-29 | Amkor Technology, Inc. | Encapsulated semiconductor package |
US8341835B1 (en) | 2002-05-01 | 2013-01-01 | Amkor Technology, Inc. | Buildup dielectric layer having metallization pattern semiconductor package fabrication method |
US8110909B1 (en) | 2002-05-01 | 2012-02-07 | Amkor Technology, Inc. | Semiconductor package including top-surface terminals for mounting another semiconductor package |
US9691635B1 (en) | 2002-05-01 | 2017-06-27 | Amkor Technology, Inc. | Buildup dielectric layer having metallization pattern semiconductor package fabrication method |
US8026587B1 (en) | 2002-05-01 | 2011-09-27 | Amkor Technology, Inc. | Semiconductor package including top-surface terminals for mounting another semiconductor package |
US9812386B1 (en) | 2002-05-01 | 2017-11-07 | Amkor Technology, Inc. | Encapsulated semiconductor package |
US7671457B1 (en) | 2002-05-01 | 2010-03-02 | Amkor Technology, Inc. | Semiconductor package including top-surface terminals for mounting another semiconductor package |
US7714431B1 (en) | 2002-11-08 | 2010-05-11 | Amkor Technology, Inc. | Electronic component package comprising fan-out and fan-in traces |
US8298866B1 (en) | 2002-11-08 | 2012-10-30 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US8710649B1 (en) | 2002-11-08 | 2014-04-29 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US9871015B1 (en) | 2002-11-08 | 2018-01-16 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US10665567B1 (en) | 2002-11-08 | 2020-05-26 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US7692286B1 (en) | 2002-11-08 | 2010-04-06 | Amkor Technology, Inc. | Two-sided fan-out wafer escape package |
US8691632B1 (en) | 2002-11-08 | 2014-04-08 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US8952522B1 (en) | 2002-11-08 | 2015-02-10 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US7723210B2 (en) | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US9054117B1 (en) | 2002-11-08 | 2015-06-09 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US8501543B1 (en) | 2002-11-08 | 2013-08-06 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US8486764B1 (en) | 2002-11-08 | 2013-07-16 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US8188584B1 (en) | 2002-11-08 | 2012-05-29 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US7932595B1 (en) | 2002-11-08 | 2011-04-26 | Amkor Technology, Inc. | Electronic component package comprising fan-out traces |
US8119455B1 (en) | 2002-11-08 | 2012-02-21 | Amkor Technology, Inc. | Wafer level package fabrication method |
US9406645B1 (en) | 2002-11-08 | 2016-08-02 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US10811277B2 (en) | 2004-03-23 | 2020-10-20 | Amkor Technology, Inc. | Encapsulated semiconductor package |
US8018068B1 (en) | 2004-03-23 | 2011-09-13 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
US11094560B1 (en) | 2004-03-23 | 2021-08-17 | Amkor Technology Singapore Holding Pte. Ltd. | Encapsulated semiconductor package |
US11081370B2 (en) | 2004-03-23 | 2021-08-03 | Amkor Technology Singapore Holding Pte. Ltd. | Methods of manufacturing an encapsulated semiconductor device |
US8227338B1 (en) | 2004-03-23 | 2012-07-24 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
US7977163B1 (en) | 2005-12-08 | 2011-07-12 | Amkor Technology, Inc. | Embedded electronic component package fabrication method |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US11848214B2 (en) | 2006-08-01 | 2023-12-19 | Amkor Technology Singapore Holding Pte. Ltd. | Encapsulated semiconductor package |
US8203203B1 (en) | 2006-11-16 | 2012-06-19 | Amkor Technology, Inc. | Stacked redistribution layer (RDL) die assembly package |
US8629546B1 (en) | 2006-11-16 | 2014-01-14 | Amkor Technology, Inc. | Stacked redistribution layer (RDL) die assembly package |
US7825520B1 (en) | 2006-11-16 | 2010-11-02 | Amkor Technology, Inc. | Stacked redistribution layer (RDL) die assembly package |
US7588951B2 (en) | 2006-11-17 | 2009-09-15 | Freescale Semiconductor, Inc. | Method of packaging a semiconductor device and a prefabricated connector |
US7807511B2 (en) | 2006-11-17 | 2010-10-05 | Freescale Semiconductor, Inc. | Method of packaging a device having a multi-contact elastomer connector contact area and device thereof |
US20080119015A1 (en) * | 2006-11-17 | 2008-05-22 | Mangrum Marc A | Method of packaging a semiconductor device and a prefabricated connector |
US7696016B2 (en) | 2006-11-17 | 2010-04-13 | Freescale Semiconductor, Inc. | Method of packaging a device having a tangible element and device thereof |
US20090286390A1 (en) * | 2006-11-17 | 2009-11-19 | Freescale Semiconductor, Inc. | Method of packaging a semiconductor device and a prefabricated connector |
US7476563B2 (en) | 2006-11-17 | 2009-01-13 | Freescale Semiconductor, Inc. | Method of packaging a device using a dielectric layer |
US20080116560A1 (en) * | 2006-11-17 | 2008-05-22 | Mangrum Marc A | Method of packaging a device having a tangible element and device thereof |
US7655502B2 (en) | 2006-11-17 | 2010-02-02 | Freescale Semiconductor, Inc. | Method of packaging a semiconductor device and a prefabricated connector |
WO2008088306A3 (en) * | 2006-12-20 | 2009-04-09 | Solid State Cooling Inc | Thermoenergy devices and methods for manufacturing same |
WO2008088306A2 (en) * | 2006-12-20 | 2008-07-24 | Solid State Cooling, Inc. | Thermoenergy devices and methods for manufacturing same |
US7632715B2 (en) * | 2007-01-05 | 2009-12-15 | Freescale Semiconductor, Inc. | Method of packaging semiconductor devices |
US20080164593A1 (en) * | 2007-01-05 | 2008-07-10 | Hess Kevin J | Method of packaging semiconductor devices |
US7821104B2 (en) | 2008-08-29 | 2010-10-26 | Freescale Semiconductor, Inc. | Package device having crack arrest feature and method of forming |
US20100052106A1 (en) * | 2008-08-29 | 2010-03-04 | Chu-Chung Lee | Package device having crack arrest feature and method of forming |
US7960827B1 (en) | 2009-04-09 | 2011-06-14 | Amkor Technology, Inc. | Thermal via heat spreader package and method |
US8623753B1 (en) | 2009-05-28 | 2014-01-07 | Amkor Technology, Inc. | Stackable protruding via package and method |
US10034372B1 (en) | 2009-06-12 | 2018-07-24 | Amkor Technology, Inc. | Stackable via package and method |
US10206285B1 (en) | 2009-06-12 | 2019-02-12 | Amkor Technology, Inc. | Stackable via package and method |
US10548221B1 (en) | 2009-06-12 | 2020-01-28 | Amkor Technology, Inc. | Stackable via package and method |
US11089685B2 (en) | 2009-06-12 | 2021-08-10 | Amkor Technology Singapore Holding Pte. Ltd. | Stackable via package and method |
US9012789B1 (en) | 2009-06-12 | 2015-04-21 | Amkor Technology, Inc. | Stackable via package and method |
US8704368B1 (en) | 2009-06-12 | 2014-04-22 | Amkor Technology, Inc. | Stackable via package and method |
US9730327B1 (en) | 2009-06-12 | 2017-08-08 | Amkor Technology, Inc. | Stackable via package and method |
US11700692B2 (en) | 2009-06-12 | 2023-07-11 | Amkor Technology Singapore Holding Pte. Ltd. | Stackable via package and method |
US8222538B1 (en) | 2009-06-12 | 2012-07-17 | Amkor Technology, Inc. | Stackable via package and method |
US8471154B1 (en) | 2009-08-06 | 2013-06-25 | Amkor Technology, Inc. | Stackable variable height via package and method |
US10257942B1 (en) | 2009-08-06 | 2019-04-09 | Amkor Technology, Inc. | Stackable variable height via package and method |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US10546833B2 (en) | 2009-12-07 | 2020-01-28 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US8536462B1 (en) | 2010-01-22 | 2013-09-17 | Amkor Technology, Inc. | Flex circuit package and method |
US9324614B1 (en) | 2010-04-06 | 2016-04-26 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8300423B1 (en) | 2010-05-25 | 2012-10-30 | Amkor Technology, Inc. | Stackable treated via package and method |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8338229B1 (en) | 2010-07-30 | 2012-12-25 | Amkor Technology, Inc. | Stackable plasma cleaned via package and method |
US8717775B1 (en) | 2010-08-02 | 2014-05-06 | Amkor Technology, Inc. | Fingerprint sensor package and method |
US9159672B1 (en) | 2010-08-02 | 2015-10-13 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US8900995B1 (en) | 2010-10-05 | 2014-12-02 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
US8337657B1 (en) | 2010-10-27 | 2012-12-25 | Amkor Technology, Inc. | Mechanical tape separation package and method |
US8753730B1 (en) | 2010-10-27 | 2014-06-17 | Amkor Technology, Inc. | Mechanical tape separation package |
US9496210B1 (en) | 2010-11-01 | 2016-11-15 | Amkor Technology, Inc. | Stackable package and method |
US8482134B1 (en) | 2010-11-01 | 2013-07-09 | Amkor Technology, Inc. | Stackable package and method |
US11855023B2 (en) | 2010-11-04 | 2023-12-26 | Amkor Technology Singapore Holding Pte. Ltd. | Wafer level fan out semiconductor device and manufacturing method thereof |
US9748154B1 (en) | 2010-11-04 | 2017-08-29 | Amkor Technology, Inc. | Wafer level fan out semiconductor device and manufacturing method thereof |
US10903181B2 (en) | 2010-11-04 | 2021-01-26 | Amkor Technology Singapore Holding Pte. Ltd. | Wafer level fan out semiconductor device and manufacturing method thereof |
US8525318B1 (en) | 2010-11-10 | 2013-09-03 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8557629B1 (en) | 2010-12-03 | 2013-10-15 | Amkor Technology, Inc. | Semiconductor device having overlapped via apertures |
US9177932B1 (en) | 2010-12-03 | 2015-11-03 | Amkor Technology, Inc. | Semiconductor device having overlapped via apertures |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
US9837331B1 (en) | 2010-12-03 | 2017-12-05 | Amkor Technology, Inc. | Semiconductor device having overlapped via apertures |
US8535961B1 (en) | 2010-12-09 | 2013-09-17 | Amkor Technology, Inc. | Light emitting diode (LED) package and method |
US9082833B1 (en) | 2011-01-06 | 2015-07-14 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
US10347562B1 (en) | 2011-02-18 | 2019-07-09 | Amkor Technology, Inc. | Methods and structures for increasing the allowable die size in TMV packages |
US9721872B1 (en) | 2011-02-18 | 2017-08-01 | Amkor Technology, Inc. | Methods and structures for increasing the allowable die size in TMV packages |
US11488892B2 (en) | 2011-02-18 | 2022-11-01 | Amkor Technology Singapore Holding Pte. Ltd. | Methods and structures for increasing the allowable die size in TMV packages |
US9013011B1 (en) | 2011-03-11 | 2015-04-21 | Amkor Technology, Inc. | Stacked and staggered die MEMS package and method |
US8890329B2 (en) | 2011-04-26 | 2014-11-18 | Amkor Technology, Inc. | Semiconductor device |
US8941250B1 (en) | 2011-09-15 | 2015-01-27 | Amkor Technology, Inc. | Electronic component package fabrication method and structure |
US8653674B1 (en) | 2011-09-15 | 2014-02-18 | Amkor Technology, Inc. | Electronic component package fabrication method and structure |
US8890337B1 (en) | 2011-09-20 | 2014-11-18 | Amkor Technology, Inc. | Column and stacking balls package fabrication method and structure |
US8633598B1 (en) | 2011-09-20 | 2014-01-21 | Amkor Technology, Inc. | Underfill contacting stacking balls package fabrication method and structure |
US9029962B1 (en) | 2011-10-12 | 2015-05-12 | Amkor Technology, Inc. | Molded cavity substrate MEMS package fabrication method and structure |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
US10410967B1 (en) | 2011-11-29 | 2019-09-10 | Amkor Technology, Inc. | Electronic device comprising a conductive pad on a protruding-through electrode |
US8981572B1 (en) | 2011-11-29 | 2015-03-17 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
US9431323B1 (en) | 2011-11-29 | 2016-08-30 | Amkor Technology, Inc. | Conductive pad on protruding through electrode |
US11043458B2 (en) | 2011-11-29 | 2021-06-22 | Amkor Technology Singapore Holding Pte. Ltd. | Method of manufacturing an electronic device comprising a conductive pad on a protruding-through electrode |
US9947623B1 (en) | 2011-11-29 | 2018-04-17 | Amkor Technology, Inc. | Semiconductor device comprising a conductive pad on a protruding-through electrode |
US10014240B1 (en) | 2012-03-29 | 2018-07-03 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US11527496B2 (en) | 2012-11-20 | 2022-12-13 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device comprising semiconductor die and interposer and manufacturing method thereof |
US9728514B2 (en) | 2012-11-20 | 2017-08-08 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US9391043B2 (en) | 2012-11-20 | 2016-07-12 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US10679952B2 (en) | 2012-11-20 | 2020-06-09 | Amkor Technology, Inc. | Semiconductor device having an encapsulated front side and interposer and manufacturing method thereof |
US9543242B1 (en) | 2013-01-29 | 2017-01-10 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
US9852976B2 (en) | 2013-01-29 | 2017-12-26 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
US9704747B2 (en) | 2013-03-29 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US9704842B2 (en) | 2013-11-04 | 2017-07-11 | Amkor Technology, Inc. | Interposer, manufacturing method thereof, semiconductor package using the same, and method for fabricating the semiconductor package |
US10943858B2 (en) | 2013-11-19 | 2021-03-09 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor package and fabricating method thereof |
US11652038B2 (en) | 2013-11-19 | 2023-05-16 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor package with front side and back side redistribution structures and fabricating method thereof |
US10192816B2 (en) | 2013-11-19 | 2019-01-29 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
US10504827B2 (en) * | 2016-06-03 | 2019-12-10 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US11444013B2 (en) | 2016-06-03 | 2022-09-13 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and manufacturing method thereof |
US20170352613A1 (en) * | 2016-06-03 | 2017-12-07 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US10784422B2 (en) | 2016-09-06 | 2020-09-22 | Amkor Technology, Inc. | Semiconductor device with optically-transmissive layer and manufacturing method thereof |
US11437552B2 (en) | 2016-09-06 | 2022-09-06 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device with transmissive layer and manufacturing method thereof |
US10490716B2 (en) | 2016-09-06 | 2019-11-26 | Amkor Technology, Inc. | Semiconductor device with optically-transmissive layer and manufacturing method thereof |
US9960328B2 (en) | 2016-09-06 | 2018-05-01 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US11942581B2 (en) | 2016-09-06 | 2024-03-26 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device with transmissive layer and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
US7579219B2 (en) | 2009-08-25 |
JP2007535811A (en) | 2007-12-06 |
WO2005112116A1 (en) | 2005-11-24 |
CN1947246A (en) | 2007-04-11 |
CN100424865C (en) | 2008-10-08 |
MY140584A (en) | 2009-12-31 |
TW200603220A (en) | 2006-01-16 |
KR20070006880A (en) | 2007-01-11 |
US20060192301A1 (en) | 2006-08-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7579219B2 (en) | Semiconductor device with a protected active die region and method therefor | |
US10978406B2 (en) | Semiconductor package including EMI shielding structure and method for forming the same | |
US11081453B2 (en) | Semiconductor package structure with antenna | |
US9899335B2 (en) | Method for fabricating package structure | |
EP3091571B1 (en) | Fan-out package structure including a conductive shielding layer | |
US7998791B2 (en) | Panel level methods and systems for packaging integrated circuits with integrated heat sinks | |
US7851894B1 (en) | System and method for shielding of package on package (PoP) assemblies | |
US5989941A (en) | Encapsulated integrated circuit packaging | |
US11158554B2 (en) | Shielded fan-out packaged semiconductor device and method of manufacturing | |
TWI470747B (en) | Plastic packaged device with die interface layer | |
US20210242113A1 (en) | Land structure for semiconductor package and method therefor | |
US20170084519A1 (en) | Semiconductor package and method of manufacturing same | |
US11004775B2 (en) | SMDS integration on QFN by 3D stacked solution | |
EP3576145A1 (en) | Semiconductor package with antenna and fabrication method thereof | |
US11342295B2 (en) | Electronic assembly, package structure having hollow cylinders and method of fabricating the same | |
US10797004B2 (en) | Semiconductor device package | |
US20110316130A1 (en) | Thin semiconductor package and method for manufacturing same | |
KR20200106001A (en) | Control of sub-charge for double-sided ball grid array packages | |
US20150200177A1 (en) | Wafer level package with redistribution layer formed with metallic powder | |
US9324641B2 (en) | Integrated circuit packaging system with external interconnect and method of manufacture thereof | |
CN113539978A (en) | Fan-out packaging structure | |
US20150115420A1 (en) | Sensor die grid array package | |
TWI466199B (en) | Wafer level clip and process of manufacture | |
KR101494371B1 (en) | Semiconductor package with different type substrates | |
US9748163B1 (en) | Die support for enlarging die size |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEAL, GEORGE R.;FAY, OWEN R.;WENZEL, ROBERT J.;REEL/FRAME:015307/0536;SIGNING DATES FROM 20040427 TO 20040428 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |