US20050249945A1 - Manufacturing tool for wafer level package and method of placing dies - Google Patents

Manufacturing tool for wafer level package and method of placing dies Download PDF

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Publication number
US20050249945A1
US20050249945A1 US10/842,959 US84295904A US2005249945A1 US 20050249945 A1 US20050249945 A1 US 20050249945A1 US 84295904 A US84295904 A US 84295904A US 2005249945 A1 US2005249945 A1 US 2005249945A1
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United States
Prior art keywords
base
elastic material
tool
dice
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US10/842,959
Inventor
Wen Kun Yang
Wen Ping Yang
Shih Li Chen
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Advanced Chip Engineering Technology Inc
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Individual
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Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US10/842,959 priority Critical patent/US20050249945A1/en
Priority to TW093114832A priority patent/TWI240391B/en
Priority to SG200403353A priority patent/SG129292A1/en
Priority to KR1020040050088A priority patent/KR100590394B1/en
Priority to DE102004033645A priority patent/DE102004033645B4/en
Priority to CNB200410063849XA priority patent/CN100372053C/en
Priority to JP2004209770A priority patent/JP4095047B2/en
Assigned to ADVANCED CHIP ENGINEERING TECHNOLOGY reassignment ADVANCED CHIP ENGINEERING TECHNOLOGY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, SHIN-LI, YANG, WEN-PIN, YANG, WEN-KUN
Priority to US11/158,167 priority patent/US7985626B2/en
Publication of US20050249945A1 publication Critical patent/US20050249945A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/53—Means to assemble or disassemble
    • Y10T29/5313—Means to assemble electrical device
    • Y10T29/53174—Means to fasten electrical component to wiring board, base, or substrate
    • Y10T29/53178—Chip component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/53—Means to assemble or disassemble
    • Y10T29/5313—Means to assemble electrical device
    • Y10T29/53191—Means to apply vacuum directly to position or hold work part
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/53—Means to assemble or disassemble
    • Y10T29/53274—Means to disassemble electrical device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/28—Web or sheet containing structurally defined element or component and having an adhesive outermost layer

Definitions

  • This invention relates to a manufacturing tool for wafer level package, and more particularly to a die placing tool for wafer level package and placing method of the same by selecting good dies from the processed wafer, thereafter placing the good die on the tool by using a pick and place system.
  • a number of distinct semiconductor devices such as memory chips or microprocessors, are fabricated on a semiconductor substrate, such as a silicon wafer. After the desired structures, circuitry, and other features of each of the semiconductor devices have been fabricated upon the semiconductor substrate, the substrate is typically singulated to separate the individual semiconductor devices from one another.
  • post-fabricating processes such as testing the circuits of each of the semiconductor devices and burn-in processes, may be employed either prior to or following singulation of the semiconductor substrate. These post-fabricating processes may be employed to impart the semiconductor devices with their intended functionality and to determine whether or not each of the individual semiconductor devices meets quality control specifications.
  • chip-scale package or “chip-sized package” (“CSP”)
  • CSP Chip-sized package
  • Such chip-scale packages typically include a carrier substrate having approximately the same surface area as the semiconductor device.
  • any type package technique of IC device is adopted firstly sawing the die on wafer to be individual die, and then packaging and testing of the sawed dies.
  • Such package technique of sawing prior to packaging and testing causes a tedious and complicated process and increasing cost of packaging and testing of the IC device, owing to continuously repeating packaging and testing of the sawed die.
  • a new type wafer level package “process of fan out wafer level package” (filed by Taiwan Patent Number 177,766) discloses that the sawed die need be placed on a glass substrate after sawing. In convention, the sawed dice are adopted one by one placing to the glass substrate. The above-mentioned step needs continuously repeating a pick and place action. The action by using labor power or machine may cause a burden on time, cost and yield for a packaging and testing factory.
  • the present provides a new tool of wafer level package to improve die placing efficiency of wafer level package and decrease time and cost.
  • the main objective of the present invention is to provide a tool of wafer level package and placing method of dies.
  • the good dies are selected from the processed wafer and place the good dies on a tool by using a pick and place system.
  • the placing method of dies of the present invention can improve placing efficiency and yield of the dies of wafer level package.
  • a tool for wafer level package comprising a first base; an elastic material on the first base, the elastic material having viscosity in a first condition to adhere a die; and a second base having adhesive material to adhere the die, the die could be departed from the elastic material in a second condition.
  • material of the first base is silicon, glass, quartz or ceramic.
  • the material of the second base is silicon, glass, quartz, ceramic, or PCB.
  • the structure of the second base is lead-frame.
  • the material of the elastic material is silicon resin, elastic PU, porous PU, acrylic rubber or die sawing tape (Blue tape/UV tape).
  • the elastic material is formed on the surface of the first base by spin coating, printing or adhering.
  • the adhesive material is formed on the surface of the second base by spin coating or printing. Wherein the plurality of dice are back upwardly fixed on the elastic material, and the dice back adhered to the adhesive material.
  • the second condition comprises DI water, solvent, or UV light.
  • FIG. 1 is a schematic diagram of coating an adhesive material on a second base of the present invention.
  • FIG. 2 is a schematic diagram of adhering a plurality of dies on an elastic material of the present invention.
  • FIG. 3 is a schematic diagram of adhering a plurality of dies on a second base of the present invention.
  • FIG. 4 is a schematic diagram of stripping a plurality of dies from an elastic material of the present invention.
  • FIG. 5 is a top view of adhering a plurality of dies on a second base of the present invention.
  • FIG. 6 is a schematic diagram of mechanical structure of pick and place of the present invention.
  • FIG. 7 is a schematic diagram of adhering a plurality of dies on an elastic material on pick and place system of the present invention.
  • FIG. 1 it is a schematic diagram of coating an adhesive material on a second base of the present invention.
  • an adhesive material 101 is coated on a base 100 .
  • the adhesive material 101 is formed on surface of the base 100 by spin coating or printing.
  • the material of the base 100 is silicon, glass, quartz, ceramic, PCB etc. or the base 100 could be a lead-frame.
  • FIG. 2 it is a schematic diagram of adhering a plurality of dice on an elastic material of the present invention.
  • pluralities of dice 202 are placed on an elastic material 201 .
  • the elastic material 201 is formed on a base 200 .
  • the elastic material 201 has viscosity in common state or at atmosphere environment.
  • material of the elastic material 201 is silicon resin, elastic PU, porous PU, acrylic rubber or die sawing tape (Blue tape/UV tape) etc.
  • material of the base 200 is silicon, glass, quartz or ceramic etc.
  • the elastic material 201 may be formed on surface of the base 200 by spin coating, printing or adhering. As noted, positive side (AI pads side) of the die is placed on the adhesive material 201 .
  • FIG. 3 it is a schematic diagram of adhering a plurality of dice on the base 100 of the present invention.
  • the base 100 can be reversed to face the dies 202 with adhesive material side.
  • the dice 202 are adhered to the base 100 by the adhesive material 101 .
  • a step of UV curing or heat curing is performed after adhering to enhance adhering effect.
  • the plurality of dice 202 are back upwardly fixed on the elastic material 201 , and the dice are adhered to the adhesive material 101 on the back side surface. That is to say, the base 100 can be reversed to adhere the plurality of dice's 202 back.
  • FIG. 4 it is a schematic diagram of stripping a plurality of dies from an elastic material of the present invention.
  • the pluralities of dice 202 are stripped from the elastic material 201 by a special or predetermined environment. That is to say, surface of the elastic material 201 has viscosity in common state, and it lose viscosity when the elastic material 201 is placed in a special environment to.
  • the special or predetermined environment may be the solution of DI water, special solvent, predetermined temperature around 20-40 centigrade degree depending on the solution, or specific light (such as UV light) etc.
  • the engagement of the elastic material 201 and the base 200 can be reused through cleaning. Subsequently, other batch dice 202 can be adhered to the base 100 again by the adhesive material 101 , thereby repeating the similar process as aforementioned, as shown in FIG. 5 . Therefore, the design of the present invention can be reuse and recycle.
  • FIG. 6 it is a schematic diagram of mechanical structure of pick and place according to the present invention.
  • the plurality of dice 202 are placed on the elastic material 201 by using a pick and place system.
  • the pick and place system can be regarded as a movable flip chip bonder.
  • a processed wafer 605 is placed on a frame 604 of a pick station.
  • the processed wafer 605 has dice 202 , and the dice 202 are placed on a tool 600 of a place station by a pick and place arm 601 .
  • the pick station and the place station are in the same carrier stage.
  • the tool 600 is consisted of the elastic material 201 and the base 200 .
  • the pick and place arm 601 can move toward up and down directions by a Y direction step motor 603 . Besides, pick and place arm 601 can also move in horizontal direction by an X direction step motor 602 . That is to say, the pick and place arm 601 can precisely place the plurality of dice 202 on the tool 600 by the Y-step motor 603 and X-step motor 602 .
  • FIG. 7 it is a schematic diagram of adhering a plurality of dice on an elastic material on picks and place system of the present invention.
  • the plurality of dies 202 of the sawed wafer 605 may be slightly pressed and attached by using an attaching head 701 of the pick and place arm 601 to make the dies 202 flipping away from the processed wafer 605 through a die ejecting module 701 under the processed wafer 605 . And then, the plurality of dies 202 can be precisely placed on the elastic material 201 by the Y-step motor 603 and X-step motor 602 .
  • the pick and place system has a fine alignment function so that its accuracy can reach less 5 micro.
  • the plurality of dice of the present invention can be simultaneously adhered to the base. It is a different method from conventional method which is adhere the die one by one on the base. Therefore, the sawed dies can be simultaneously placed by using tool of the present invention to improve die placing efficiency of wafer level package.
  • the tool design according to the present invention can be reuse and recycle.

Abstract

A tool of wafer level package comprises a first base, an elastic material and a second base. The elastic material is coated on the first base, and the elastic material has viscosity in common state to adhere a plurality of dies. The second base is coated by adhesive material to adhere the dies. The plurality of dies are departed from the elastic material by a special environment after adhering.

Description

    TECHNICAL FIELD
  • This invention relates to a manufacturing tool for wafer level package, and more particularly to a die placing tool for wafer level package and placing method of the same by selecting good dies from the processed wafer, thereafter placing the good die on the tool by using a pick and place system.
    • BACKGROUND
  • In conventional semiconductor device fabrication processes, a number of distinct semiconductor devices, such as memory chips or microprocessors, are fabricated on a semiconductor substrate, such as a silicon wafer. After the desired structures, circuitry, and other features of each of the semiconductor devices have been fabricated upon the semiconductor substrate, the substrate is typically singulated to separate the individual semiconductor devices from one another.
  • Various post-fabricating processes, such as testing the circuits of each of the semiconductor devices and burn-in processes, may be employed either prior to or following singulation of the semiconductor substrate. These post-fabricating processes may be employed to impart the semiconductor devices with their intended functionality and to determine whether or not each of the individual semiconductor devices meets quality control specifications.
  • The individual semiconductor devices may then be packaged. Along with the trend in the semiconductor industry to decrease semiconductor device size and increase the density of structures of semiconductor devices, package sizes are also ever-decreasing. One type of semiconductor device package, the so-called “chip-scale package” or “chip-sized package” (“CSP”), consumes about the same amount of real estate upon a substrate as the bare semiconductor device itself. Such chip-scale packages typically include a carrier substrate having approximately the same surface area as the semiconductor device.
  • Presently, any type package technique of IC device is adopted firstly sawing the die on wafer to be individual die, and then packaging and testing of the sawed dies. Such package technique of sawing prior to packaging and testing causes a tedious and complicated process and increasing cost of packaging and testing of the IC device, owing to continuously repeating packaging and testing of the sawed die.
  • Moreover, a new type wafer level package “process of fan out wafer level package” (filed by Taiwan Patent Number 177,766) discloses that the sawed die need be placed on a glass substrate after sawing. In convention, the sawed dice are adopted one by one placing to the glass substrate. The above-mentioned step needs continuously repeating a pick and place action. The action by using labor power or machine may cause a burden on time, cost and yield for a packaging and testing factory.
  • Therefore, the present provides a new tool of wafer level package to improve die placing efficiency of wafer level package and decrease time and cost.
    • SUMMARY
  • The main objective of the present invention is to provide a tool of wafer level package and placing method of dies. The good dies are selected from the processed wafer and place the good dies on a tool by using a pick and place system. The placing method of dies of the present invention can improve placing efficiency and yield of the dies of wafer level package.
  • A tool for wafer level package, comprising a first base; an elastic material on the first base, the elastic material having viscosity in a first condition to adhere a die; and a second base having adhesive material to adhere the die, the die could be departed from the elastic material in a second condition. Wherein material of the first base is silicon, glass, quartz or ceramic. The material of the second base is silicon, glass, quartz, ceramic, or PCB. The structure of the second base is lead-frame. The material of the elastic material is silicon resin, elastic PU, porous PU, acrylic rubber or die sawing tape (Blue tape/UV tape). The elastic material is formed on the surface of the first base by spin coating, printing or adhering. The adhesive material is formed on the surface of the second base by spin coating or printing. Wherein the plurality of dice are back upwardly fixed on the elastic material, and the dice back adhered to the adhesive material. The second condition comprises DI water, solvent, or UV light.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic diagram of coating an adhesive material on a second base of the present invention.
  • FIG. 2 is a schematic diagram of adhering a plurality of dies on an elastic material of the present invention.
  • FIG. 3 is a schematic diagram of adhering a plurality of dies on a second base of the present invention.
  • FIG. 4 is a schematic diagram of stripping a plurality of dies from an elastic material of the present invention.
  • FIG. 5 is a top view of adhering a plurality of dies on a second base of the present invention.
  • FIG. 6 is a schematic diagram of mechanical structure of pick and place of the present invention.
  • FIG. 7 is a schematic diagram of adhering a plurality of dies on an elastic material on pick and place system of the present invention.
    • DETAILED DESCRIPTION
  • Some sample embodiments of the invention will now be described in greater detail. Nevertheless, it should be recognized that the present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is expressly not limited expect as specified in the accompanying claims.
  • Then, the components of the different elements are not shown to scale. Some dimensions of the related components are exaggerated and meaningless portions are not drawn to provide a more clear description and comprehension of the present invention.
  • Referring to FIG. 1, it is a schematic diagram of coating an adhesive material on a second base of the present invention. As shown in FIG. 1, an adhesive material 101 is coated on a base 100. In one embodiment, the adhesive material 101 is formed on surface of the base 100 by spin coating or printing. The material of the base 100 is silicon, glass, quartz, ceramic, PCB etc. or the base 100 could be a lead-frame.
  • Referring to FIG. 2, it is a schematic diagram of adhering a plurality of dice on an elastic material of the present invention. As shown in FIG. 2, pluralities of dice 202 are placed on an elastic material 201. The elastic material 201 is formed on a base 200. The elastic material 201 has viscosity in common state or at atmosphere environment. In one embodiment, material of the elastic material 201 is silicon resin, elastic PU, porous PU, acrylic rubber or die sawing tape (Blue tape/UV tape) etc. Moreover, material of the base 200 is silicon, glass, quartz or ceramic etc. The elastic material 201 may be formed on surface of the base 200 by spin coating, printing or adhering. As noted, positive side (AI pads side) of the die is placed on the adhesive material 201.
  • Referring to FIG. 3, it is a schematic diagram of adhering a plurality of dice on the base 100 of the present invention. As shown in FIG. 3, the base 100 can be reversed to face the dies 202 with adhesive material side. The dice 202 are adhered to the base 100 by the adhesive material 101. A step of UV curing or heat curing is performed after adhering to enhance adhering effect. The plurality of dice 202 are back upwardly fixed on the elastic material 201, and the dice are adhered to the adhesive material 101 on the back side surface. That is to say, the base 100 can be reversed to adhere the plurality of dice's 202 back.
  • Referring to FIG. 4, it is a schematic diagram of stripping a plurality of dies from an elastic material of the present invention. As shown in FIG. 4, the pluralities of dice 202 are stripped from the elastic material 201 by a special or predetermined environment. That is to say, surface of the elastic material 201 has viscosity in common state, and it lose viscosity when the elastic material 201 is placed in a special environment to. The special or predetermined environment may be the solution of DI water, special solvent, predetermined temperature around 20-40 centigrade degree depending on the solution, or specific light (such as UV light) etc. The engagement of the elastic material 201 and the base 200 can be reused through cleaning. Subsequently, other batch dice 202 can be adhered to the base 100 again by the adhesive material 101, thereby repeating the similar process as aforementioned, as shown in FIG. 5. Therefore, the design of the present invention can be reuse and recycle.
  • Referring to FIG. 6, it is a schematic diagram of mechanical structure of pick and place according to the present invention. As shown in FIG. 6, the plurality of dice 202 are placed on the elastic material 201 by using a pick and place system. The pick and place system can be regarded as a movable flip chip bonder. A processed wafer 605 is placed on a frame 604 of a pick station. The processed wafer 605 has dice 202, and the dice 202 are placed on a tool 600 of a place station by a pick and place arm 601. The pick station and the place station are in the same carrier stage. The tool 600 is consisted of the elastic material 201 and the base 200. The pick and place arm 601 can move toward up and down directions by a Y direction step motor 603. Besides, pick and place arm 601 can also move in horizontal direction by an X direction step motor 602. That is to say, the pick and place arm 601 can precisely place the plurality of dice 202 on the tool 600 by the Y-step motor 603 and X-step motor 602.
  • Referring to FIG. 7, it is a schematic diagram of adhering a plurality of dice on an elastic material on picks and place system of the present invention. The plurality of dies 202 of the sawed wafer 605 may be slightly pressed and attached by using an attaching head 701 of the pick and place arm 601 to make the dies 202 flipping away from the processed wafer 605 through a die ejecting module 701 under the processed wafer 605. And then, the plurality of dies 202 can be precisely placed on the elastic material 201 by the Y-step motor 603 and X-step motor 602. The pick and place system has a fine alignment function so that its accuracy can reach less 5 micro.
  • The plurality of dice of the present invention can be simultaneously adhered to the base. It is a different method from conventional method which is adhere the die one by one on the base. Therefore, the sawed dies can be simultaneously placed by using tool of the present invention to improve die placing efficiency of wafer level package. The tool design according to the present invention can be reuse and recycle.
  • Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from what is intended to be limited solely by the appended claims.

Claims (21)

1. A tool for wafer level package, comprising:
a first base;
an elastic material on said first base, said elastic material having viscosity in a first condition to adhere a die; and
a second base having adhesive material to adhere said die, said die could be departed from said elastic material in a second condition.
2. The tool in claim 1, wherein material of said first base is silicon, glass, quartz or ceramic.
3. The tool in claim 1, wherein material of said second base is silicon, glass, quartz, ceramic, or PCB.
4. The tool in claim 1, wherein said second base is lead-frame.
5. The tool in claim 1, wherein material of said elastic material is silicon resin, elastic PU, porous PU, acrylic rubber or die sawing tape (Blue tape/UV tape).
6. The tool in claim 1, wherein said elastic material is formed on the surface of said first base by spin coating, printing or adhering.
7. The tool in claim 1, wherein said adhesive material is formed on the surface of said second base by spin coating or printing.
8. The tool in claim 1, wherein said plurality of dice are back upwardly fixed on said elastic material, and said dice back adhered to said adhesive material.
9. The tool in claim 1, wherein said second condition comprises DI water, solvent, or UV light.
10. The tool in claim 1, further comprising a step of performing UV curing or heat curing after adhering .
11. A placing method of die for wafer level package, comprising:
placing a plurality of dice on an elastic material, said elastic material formed on a first base, said elastic material having viscosity in a first condition to adhere said plurality of dice;
forming an adhesive material on a second base;
adhering said plurality of dice on said adhesive material of said second base; and
stripping said plurality of dies from said elastic material in a second condition.
12. The method in claim 11, wherein said placing a plurality of dice on an elastic material is performed by using a pick and place system.
13. The method in claim 11, wherein the material of said first base is silicon, glass, quartz or ceramic.
14. The method in claim 11, wherein the material of said second base is silicon, glass, quartz, ceramic or PCB.
15. The method in claim 11, wherein said second base is lead frame.
16. The method in claim 11, wherein material of said elastic material is silicon resin, elastic PU, porous PU, acrylic rubber or die sawing tape (Blue tape/UV tape).
17. The method in claim 11, wherein said elastic material is formed on surface of said first base by spin coating, printing or adhering.
18. The method in claim 11, wherein said adhesive material is formed on the surface of said second base by spin coating or printing.
19. The method in claim 11, wherein said plurality of dice are back upwardly fixed on said elastic material, and said die's back adhering to said adhesive material.
20. The method in claim 11, wherein said first condition comprises DI water, solvent, or UV light.
21. The method in claim 11, further comprising a step of UV curing or heat curing after adhering.
US10/842,959 2004-05-10 2004-05-10 Manufacturing tool for wafer level package and method of placing dies Abandoned US20050249945A1 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US10/842,959 US20050249945A1 (en) 2004-05-10 2004-05-10 Manufacturing tool for wafer level package and method of placing dies
TW093114832A TWI240391B (en) 2004-05-10 2004-05-25 Manufacturing tool for wafer level package and method of placing dies
SG200403353A SG129292A1 (en) 2004-05-10 2004-06-04 Manufacturing tool for wafer level package and method of placing dice
KR1020040050088A KR100590394B1 (en) 2004-05-10 2004-06-30 Manufacturing tool for wafer level package and method of placing dice
DE102004033645A DE102004033645B4 (en) 2004-05-10 2004-07-12 Wafer level package fabrication tool and method of arranging chips
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US20050247398A1 (en) 2005-11-10
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KR20050107720A (en) 2005-11-15
JP4095047B2 (en) 2008-06-04
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KR100590394B1 (en) 2006-06-19
DE102004033645B4 (en) 2006-08-31

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