US20050275014A1 - Integration method of a semiconductor device having a recessed gate electrode - Google Patents

Integration method of a semiconductor device having a recessed gate electrode Download PDF

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US20050275014A1
US20050275014A1 US11/195,525 US19552505A US2005275014A1 US 20050275014 A1 US20050275014 A1 US 20050275014A1 US 19552505 A US19552505 A US 19552505A US 2005275014 A1 US2005275014 A1 US 2005275014A1
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region
layer
gate
gate electrode
transistors
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US11/195,525
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Ji-Young Kim
Hyoung-sub Kim
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • This disclosure relates to an integration manufacturing method of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM), and, more specifically, to a method to produce DRAM cells having a recessed gate and a planer gate electrode.
  • DRAM Dynamic Random Access Memory
  • Integrated circuits such as ultra-large scale integrated (ULSI) circuits, can include as many as one billion transistors or more.
  • ULSI circuits are formed of Field Effect Transistors (FETs) formed in a Complementary Metal Oxide Semiconductor (CMOS) process.
  • FETs Field Effect Transistors
  • CMOS Complementary Metal Oxide Semiconductor
  • Each MOSFET includes a gate electrode formed over a channel region of the semiconductor substrate, which runs between a drain region and source region.
  • the feature size of transistor within the circuits must be reduced.
  • sub-micron scale MOS transistors have to overcome many technical challenges. As the MOS transistors become narrower, that is, their channel length decreases, problems such as junction leakage, source/drain breakdown voltage, and data retention time become more pronounced.
  • ULSI circuits One solution to decrease the physical dimension of ULSI circuits is to form recessed gate or “trench-type” transistors, which have a gate electrode buried in a groove formed in a semiconductor substrate. This type of transistor reduces short channel effects by effectively lengthening the effective channel length by having the gate extend into the semiconductor substrate.
  • An example of a portion of a combined ULSI circuit including a standard transistor and a recessed gate transistor is illustrated in FIG. 1 .
  • effectively forming recessed gate transistors in ULSI circuits that also contain non recessed gate transistors has been a difficult task.
  • Embodiments of the invention address these and other problems in the prior art.
  • FIG. 1 is a cross-sectional diagram of a MOSFET having a recessed gate according to the prior art.
  • FIGS. 2, 3 , 4 , 5 A, 6 A and 7 A are cross-sectional diagrams of a method of forming a MOSFET with a recessed gate and a planer gate electrode according to an embodiment of the present invention.
  • FIGS. 5B and 6B are cross-sectional diagrams illustrating alternative processes that were illustrated in FIGS. 5A and 6A , respectively.
  • FIG. 7B is a cross-sectional diagram illustrating another alternative process that was illustrated in FIG. 7A .
  • FIGS. 8 to 12 are cross-sectional diagrams illustrating a method of forming a MOSFET having a recessed gate and a planer gate electrode according to another embodiment of the present invention.
  • FIGS. 13 to 17 are cross-sectional diagrams illustrating a method of forming a MOSFET having a recessed gate and a planer gate electrode according to yet another embodiment of the present invention.
  • FIGS. 18 to 22 are cross-sectional diagrams illustrating of a method of forming a MOSFET having a recessed gate transistor in a cell region and a recessed gate in a peripheral region of a semiconductor substrate according to still a further embodiment of the present invention.
  • Embodiments of the invention can provide, compared to conventional memory circuits, an increase in effective channel length, a decrease in channel dosing, and improved qualities in junction leakage and data retention time in a memory circuit that includes at least two types of transistors on a single substrate: transistors having a recessed gate, and transistors having a planer gate electrode.
  • a semiconductor device includes a memory cell array section A and a peripheral circuit section B.
  • the memory cell array section is illustrated in the left-had portion of the figures, while the peripheral circuit section is illustrated in the right-hand portion.
  • An isolation region 15 is formed on a silicon substrate 10 .
  • a thin pad oxide film 18 is formed on the isolation 15 and over an active region in the memory cell array section.
  • An etch stopper layer 20 is formed on the pad oxide film 18 .
  • the etch stopper layer 20 is preferably made of nitride, for example SiN, with a thickness of about 100 to 200 angstroms.
  • a first oxide layer 25 is formed on the etch stopper layer 20 .
  • the first oxide layer 25 can be formed to a thickness of approximately 1000 angstroms in some embodiments.
  • a recess mask, for forming the recessed gates for the memory cells is formed in a photoresist layer 30 by conventional photolithography and etching processes. As shown in FIG. 3 , a recess gate hole 28 is formed in the memory cell side of the substrate 10 by etching the first oxide layer 25 , the pad oxide 18 , and the etch stopper layer 20 . On the peripheral side of the substrate 10 , the first oxide layer 25 , the pad oxide 18 , and the etch stopper layer are all removed.
  • a gate oxide 35 is formed on the silicon substrate 10 and within the recess holes 28 .
  • a gate electrode layer is formed on the gate oxide 35 .
  • the gate electrode layer is formed as a two layer structure including a lower gate electrode poly layer 40 and an upper gate electrode layer 45 , which could be, for example, Wsi.
  • a gate mask layer 50 is formed on the upper gate electrode layer 45 .
  • the gate electrode is completed by performing conventional photolithography and etching processes on the gate mask layer 50 , the upper gate electrode 45 , and the gate oxide layer 35 .
  • a deposited insulating layer is etched back to form a spacer 60 .
  • a Cosi (Cobalt-Silicon) layer 70 is formed on the peripheral circuit region. The Cosi layer 70 reduces sheet resistance in the peripheral region.
  • FIGS. 5B, 6B , and 7 B Some alternative methods for forming the memory circuit according to embodiments of the invention are illustrated in FIGS. 5B, 6B , and 7 B.
  • the first oxide layer 25 and gate oxide 35 are removed from areas other than under the gate stack in the cell region ( FIG. 5B ), and gate stack spacers 60 are formed around the gate stack ( FIG. 6B ).
  • FIG. 6B is similar to FIG. 6A , except for the removed oxide layer 25 , etch stopper layer 20 and pad oxide layer 18 .
  • FIG. 7B shows that another alternative embodiment is to add the spacers 60 before etching the oxide layer 25 , etch stopper layer 20 and pad oxide layer 18 .
  • FIGS. 8-12 Another embodiment of forming a semiconductor memory device is illustrated in FIGS. 8-12 .
  • a semiconductor device according to embodiments of the present invention includes a memory cell array section A and a peripheral circuit section B.
  • An isolation region 15 is formed on a silicon substrate 10 .
  • a thin pad oxide film 18 is formed on the isolation 15 and over an active region in the memory cell array section.
  • An etch stopper layer 20 is formed on the pad oxide film 18 .
  • the etch stopper layer 20 is preferably made of nitride, for example SiN, with a thickness of about 100 to 200 angstroms.
  • a first oxide layer 25 is formed on the etch stopper layer 20 .
  • a recess mask for forming the recessed gates for the memory cells is formed in a photoresist layer 30 by conventional photolithography and etching processes.
  • a recess gate hole 28 is formed in the memory cell side of the substrate 10 by wet etching the first oxide layer 25 , the etch stopper layer 20 , and the pad oxide layer 18 .
  • a gate oxide 35 is formed on the silicon substrate 10 and within the recess holes 28 .
  • a gate electrode having a two layer structure formed of a lower gate electrode poly 40 and an upper gate electrode Wsi 45 is formed on the gate oxide 35 .
  • a gate mask layer 50 is formed on the Wsi layer.
  • FIG. 10 illustrates that the lower gate electrode layer 40 , the upper gate electrode Wsi layer 45 , and the gate mask layer 50 are all at even levels in both the peripheral area and the cell area of the semiconductor substrate 10 .
  • a gate electrode is formed by conventional photolithography and etching processes.
  • a spacer 60 is formed that covers the gate structures in the cell area and the peripheral area of the semiconductor substrate 10 .
  • FIGS. 13-17 A further embodiment of forming a semiconductor memory device is illustrated in FIGS. 13-17 .
  • a semiconductor device according to embodiments of the present invention includes a memory cell array section A and a peripheral circuit section B.
  • An isolation region 15 is formed on a silicon substrate 10 .
  • a thin pad oxide film 18 is formed on the isolation 15 and over an active region in the memory cell array section.
  • An etch stopper layer 20 is formed on the pad oxide film 18 .
  • the etch stopper layer 20 is preferably made of nitride, for example SiN, with a thickness of about 100 to 200 angstroms.
  • a first oxide layer 25 is formed on the etch stopper layer 20 .
  • the first oxide layer 25 is formed thicker than illustrated in FIGS. 2 and 8 , and is formed to a height roughly equal to the height of a gate stack in the peripheral region of the substrate 10 .
  • a photoresist layer 30 is formed over the first oxide layer 25 .
  • a recess mask for forming the recessed gates for the memory cells and for forming a planer gate hole 29 ( FIG. 14 ) is formed in a photoresist layer 30 , by conventional photolithography and etching processes.
  • the recess gate hole 28 is formed in the first oxide layer 25 , etch stopper layer 20 , and the pad oxide layer 18 , as well as the silicon substrate 10 .
  • the planer gate hole 29 is formed in the first oxide layer 25 on the peripheral portion of the substrate 10 by an etching process.
  • the first oxide layer 25 on the peripheral side of the substrate 10 is thicker than the first oxide layer 25 on the cell region portion of the substrate 10 .
  • a gate oxide 35 is formed by oxidation process on the substrate 10 and within the recess hole 28 and planer hole 29 .
  • a gate electrode stack having a two layer structure is then formed on the gate oxide 35 .
  • the gate electrode stack is formed of a lower gate electrode poly layer 40 and an upper gate electrode Wsi layer 45 .
  • a gate layer mask 50 is formed on the Wsi layer within the recess hole 28 and the planer hole 29 . Then, the first oxide layer 25 is removed in areas not covered by the gate layer mask 50 by, for example, a wet etch process. Finally, as illustrated in FIG. 17 , spacers 60 are formed on the gate stacks in the cell region and in the peripheral region of the semiconductor substrate.
  • a semiconductor device includes a memory cell array section A and a peripheral circuit section B.
  • An isolation region 15 is formed on a silicon substrate 10 .
  • a thin pad oxide film 18 is formed on the isolation 15 and over an active region in the memory cell array section.
  • An etch stopper layer 20 is formed on the pad oxide film 18 .
  • the etch stopper layer 20 is preferably made of nitride, for example SiN, with a thickness of about 100 to 200 angstroms.
  • a first oxide layer 25 is formed on the etch stopper layer 20 .
  • a recess mask 30 is formed by conventional photolithography and etching processes.
  • a recess gate hole 28 is formed by etch process in the memory cell region and in the peripheral region of the substrate 10 .
  • a gate oxide 30 is formed by, for example, an oxidation process in the recess holes 28 .
  • a gate electrode layer is formed on the gate oxide 35 .
  • the gate electrode layer of FIG. 20 has a two layer structure formed of a lower gate electrode poly 40 and an upper gate electrode Wsi 45 .
  • the lower gate electrode poly 40 extends into the recessed gate holes in the cell region and in the peripheral region of the substrate 10 .
  • a gate mask layer 50 is formed on the Wsi layer.
  • a set of gates is formed by conventional photolithography and etching processes in the cell region and the peripheral region.
  • a spacer 60 is formed by, for example, an etch back process.
  • a recessed gate cell and a planer gate electrode are simultaneously formed in the same photolithography step. This allows memory circuits to be developed so that the manufacturing processes will be reasonable without increasing the number of the photolithography steps.

Abstract

Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.

Description

  • This is a Divisional of U.S. patent application Ser. No. 10/649,262, filed on Aug. 26, 2003, now pending, which claims priority from Korean Patent Application No. 2003-48079, filed on Jul. 13, 2003, which is incorporated by reference in is entirety.
    • TECHNICAL FIELD
  • This disclosure relates to an integration manufacturing method of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM), and, more specifically, to a method to produce DRAM cells having a recessed gate and a planer gate electrode.
    • BACKGROUND
  • Integrated circuits, such as ultra-large scale integrated (ULSI) circuits, can include as many as one billion transistors or more. Most typically, ULSI circuits are formed of Field Effect Transistors (FETs) formed in a Complementary Metal Oxide Semiconductor (CMOS) process. Each MOSFET includes a gate electrode formed over a channel region of the semiconductor substrate, which runs between a drain region and source region. To increase the device density and operation speed of the integrated circuits, the feature size of transistor within the circuits must be reduced. However, with the continued reduction in device size, sub-micron scale MOS transistors have to overcome many technical challenges. As the MOS transistors become narrower, that is, their channel length decreases, problems such as junction leakage, source/drain breakdown voltage, and data retention time become more pronounced.
  • One solution to decrease the physical dimension of ULSI circuits is to form recessed gate or “trench-type” transistors, which have a gate electrode buried in a groove formed in a semiconductor substrate. This type of transistor reduces short channel effects by effectively lengthening the effective channel length by having the gate extend into the semiconductor substrate. An example of a portion of a combined ULSI circuit including a standard transistor and a recessed gate transistor is illustrated in FIG. 1. However, effectively forming recessed gate transistors in ULSI circuits that also contain non recessed gate transistors has been a difficult task.
  • Embodiments of the invention address these and other problems in the prior art.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention will be understood more fully from the detailed description given below and from the accompanying drawings of embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are to facilitate explanation and understanding.
  • FIG. 1 is a cross-sectional diagram of a MOSFET having a recessed gate according to the prior art.
  • FIGS. 2, 3, 4, 5A, 6A and 7A are cross-sectional diagrams of a method of forming a MOSFET with a recessed gate and a planer gate electrode according to an embodiment of the present invention.
  • FIGS. 5B and 6B are cross-sectional diagrams illustrating alternative processes that were illustrated in FIGS. 5A and 6A, respectively.
  • FIG. 7B is a cross-sectional diagram illustrating another alternative process that was illustrated in FIG. 7A.
  • FIGS. 8 to 12 are cross-sectional diagrams illustrating a method of forming a MOSFET having a recessed gate and a planer gate electrode according to another embodiment of the present invention.
  • FIGS. 13 to 17 are cross-sectional diagrams illustrating a method of forming a MOSFET having a recessed gate and a planer gate electrode according to yet another embodiment of the present invention.
  • FIGS. 18 to 22 are cross-sectional diagrams illustrating of a method of forming a MOSFET having a recessed gate transistor in a cell region and a recessed gate in a peripheral region of a semiconductor substrate according to still a further embodiment of the present invention.
    • DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
  • In the following detailed descriptions, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
  • Embodiments of the invention can provide, compared to conventional memory circuits, an increase in effective channel length, a decrease in channel dosing, and improved qualities in junction leakage and data retention time in a memory circuit that includes at least two types of transistors on a single substrate: transistors having a recessed gate, and transistors having a planer gate electrode.
  • A manufacturing method of a semiconductor device of an embodiment of the present invention is described with reference to FIGS. 2 to 7. As shown in FIG. 2, a semiconductor device according to embodiments of the present invention includes a memory cell array section A and a peripheral circuit section B. The memory cell array section is illustrated in the left-had portion of the figures, while the peripheral circuit section is illustrated in the right-hand portion.
  • An isolation region 15 is formed on a silicon substrate 10. A thin pad oxide film 18 is formed on the isolation 15 and over an active region in the memory cell array section. An etch stopper layer 20 is formed on the pad oxide film 18. The etch stopper layer 20 is preferably made of nitride, for example SiN, with a thickness of about 100 to 200 angstroms. A first oxide layer 25 is formed on the etch stopper layer 20. The first oxide layer 25 can be formed to a thickness of approximately 1000 angstroms in some embodiments.
  • A recess mask, for forming the recessed gates for the memory cells is formed in a photoresist layer 30 by conventional photolithography and etching processes. As shown in FIG. 3, a recess gate hole 28 is formed in the memory cell side of the substrate 10 by etching the first oxide layer 25, the pad oxide 18, and the etch stopper layer 20. On the peripheral side of the substrate 10, the first oxide layer 25, the pad oxide 18, and the etch stopper layer are all removed.
  • As shown in FIG. 4, a gate oxide 35 is formed on the silicon substrate 10 and within the recess holes 28. A gate electrode layer is formed on the gate oxide 35. The gate electrode layer is formed as a two layer structure including a lower gate electrode poly layer 40 and an upper gate electrode layer 45, which could be, for example, Wsi. Next, a gate mask layer 50 is formed on the upper gate electrode layer 45. As shown in FIG. 5A, the gate electrode is completed by performing conventional photolithography and etching processes on the gate mask layer 50, the upper gate electrode 45, and the gate oxide layer 35.
  • Next, as illustrated in FIG. 6A, a deposited insulating layer is etched back to form a spacer 60. Finally, as illustrated in FIG. 7A, a Cosi (Cobalt-Silicon) layer 70 is formed on the peripheral circuit region. The Cosi layer 70 reduces sheet resistance in the peripheral region.
  • Some alternative methods for forming the memory circuit according to embodiments of the invention are illustrated in FIGS. 5B, 6B, and 7B. As shown in FIGS. 5B and 6B, the first oxide layer 25 and gate oxide 35 are removed from areas other than under the gate stack in the cell region (FIG. 5B), and gate stack spacers 60 are formed around the gate stack (FIG. 6B). FIG. 6B is similar to FIG. 6A, except for the removed oxide layer 25, etch stopper layer 20 and pad oxide layer 18. FIG. 7B shows that another alternative embodiment is to add the spacers 60 before etching the oxide layer 25, etch stopper layer 20 and pad oxide layer 18.
  • Another embodiment of forming a semiconductor memory device is illustrated in FIGS. 8-12. As shown in FIG. 8, a semiconductor device according to embodiments of the present invention includes a memory cell array section A and a peripheral circuit section B. An isolation region 15 is formed on a silicon substrate 10. A thin pad oxide film 18 is formed on the isolation 15 and over an active region in the memory cell array section. An etch stopper layer 20 is formed on the pad oxide film 18. The etch stopper layer 20 is preferably made of nitride, for example SiN, with a thickness of about 100 to 200 angstroms. A first oxide layer 25 is formed on the etch stopper layer 20.
  • A recess mask for forming the recessed gates for the memory cells is formed in a photoresist layer 30 by conventional photolithography and etching processes. As shown in FIG. 9, a recess gate hole 28 is formed in the memory cell side of the substrate 10 by wet etching the first oxide layer 25, the etch stopper layer 20, and the pad oxide layer 18. As shown in FIG. 10, a gate oxide 35 is formed on the silicon substrate 10 and within the recess holes 28. A gate electrode having a two layer structure formed of a lower gate electrode poly 40 and an upper gate electrode Wsi 45 is formed on the gate oxide 35. A gate mask layer 50 is formed on the Wsi layer. As compared to FIG. 4, described above, FIG. 10 illustrates that the lower gate electrode layer 40, the upper gate electrode Wsi layer 45, and the gate mask layer 50 are all at even levels in both the peripheral area and the cell area of the semiconductor substrate 10.
  • As shown in FIG. 11, a gate electrode is formed by conventional photolithography and etching processes. Next, as illustrated in FIG. 12, a spacer 60 is formed that covers the gate structures in the cell area and the peripheral area of the semiconductor substrate 10.
  • A further embodiment of forming a semiconductor memory device is illustrated in FIGS. 13-17. As shown in FIG. 13, a semiconductor device according to embodiments of the present invention includes a memory cell array section A and a peripheral circuit section B. An isolation region 15 is formed on a silicon substrate 10. A thin pad oxide film 18 is formed on the isolation 15 and over an active region in the memory cell array section. An etch stopper layer 20 is formed on the pad oxide film 18. The etch stopper layer 20 is preferably made of nitride, for example SiN, with a thickness of about 100 to 200 angstroms. A first oxide layer 25 is formed on the etch stopper layer 20. The first oxide layer 25 is formed thicker than illustrated in FIGS. 2 and 8, and is formed to a height roughly equal to the height of a gate stack in the peripheral region of the substrate 10.
  • A photoresist layer 30 is formed over the first oxide layer 25. Next, a recess mask for forming the recessed gates for the memory cells and for forming a planer gate hole 29 (FIG. 14) is formed in a photoresist layer 30, by conventional photolithography and etching processes. Then, the recess gate hole 28 is formed in the first oxide layer 25, etch stopper layer 20, and the pad oxide layer 18, as well as the silicon substrate 10. Additionally, the planer gate hole 29 is formed in the first oxide layer 25 on the peripheral portion of the substrate 10 by an etching process.
  • The first oxide layer 25 on the peripheral side of the substrate 10 is thicker than the first oxide layer 25 on the cell region portion of the substrate 10.
  • Next, as shown in FIG. 15, a gate oxide 35 is formed by oxidation process on the substrate 10 and within the recess hole 28 and planer hole 29. A gate electrode stack having a two layer structure is then formed on the gate oxide 35. The gate electrode stack is formed of a lower gate electrode poly layer 40 and an upper gate electrode Wsi layer 45.
  • As illustrated in FIG. 16, a gate layer mask 50 is formed on the Wsi layer within the recess hole 28 and the planer hole 29. Then, the first oxide layer 25 is removed in areas not covered by the gate layer mask 50 by, for example, a wet etch process. Finally, as illustrated in FIG. 17, spacers 60 are formed on the gate stacks in the cell region and in the peripheral region of the semiconductor substrate.
  • Yet further methods to form a semiconductor memory device are illustrated in FIGS. 18-22. As shown in FIG. 18, a semiconductor device according to embodiments of the present invention includes a memory cell array section A and a peripheral circuit section B. An isolation region 15 is formed on a silicon substrate 10. A thin pad oxide film 18 is formed on the isolation 15 and over an active region in the memory cell array section. An etch stopper layer 20 is formed on the pad oxide film 18. The etch stopper layer 20 is preferably made of nitride, for example SiN, with a thickness of about 100 to 200 angstroms.
  • A first oxide layer 25 is formed on the etch stopper layer 20. Next, a recess mask 30 is formed by conventional photolithography and etching processes. As shown in FIG. 19, a recess gate hole 28 is formed by etch process in the memory cell region and in the peripheral region of the substrate 10. Next, as shown in FIG. 20, a gate oxide 30 is formed by, for example, an oxidation process in the recess holes 28.
  • As illustrated in FIG. 20, a gate electrode layer is formed on the gate oxide 35. The gate electrode layer of FIG. 20 has a two layer structure formed of a lower gate electrode poly 40 and an upper gate electrode Wsi 45. In this embodiment, the lower gate electrode poly 40 extends into the recessed gate holes in the cell region and in the peripheral region of the substrate 10. A gate mask layer 50 is formed on the Wsi layer.
  • As shown in FIG. 21, a set of gates is formed by conventional photolithography and etching processes in the cell region and the peripheral region. Finally, as illustrated in FIG. 22, a spacer 60 is formed by, for example, an etch back process.
  • As described above in detail, in embodiments of the present invention, a recessed gate cell and a planer gate electrode are simultaneously formed in the same photolithography step. This allows memory circuits to be developed so that the manufacturing processes will be reasonable without increasing the number of the photolithography steps.
  • Those skilled in the art recognize that the method of forming integrated circuits described herein can be implemented in many different variations. Therefore, although various embodiments are specifically illustrated and described herein, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appending claims without departing from the spirit and intended scope of the invention

Claims (7)

1. A memory device, comprising:
a substrate divided into a memory cell region and a peripheral circuit region;
a plurality of memory cells having recessed gates formed in the memory cell region; and
at least one transistor in the peripheral circuit region, the transistor including:
a channel region formed between a source region and a drain region,
a gate structure disposed over the channel region, and
a resistance-reducing layer formed over the source and drain regions.
2. The memory device of claim 1 wherein the resistance-reducing layer comprises Cobalt.
3. The memory device of claim 2 wherein the resistance-reducing layer comprises a Cobalt-Silicon material.
4. The memory device of claim 1, further comprising an epitaxially grown silicon structure disposed between the source and drain regions and the resistance-reducing layer.
5. The memory device of claim 4 wherein the epitaxially grown silicon structure is formed by SEG (Selective Epitaxial Growing).
6. A memory device comprising:
a substrate divided into a cell region and a peripheral region;
a plurality of memory cells formed in the cell region, the plurality of memory cells each having a recessed gate structure; and
a plurality of transistors in the peripheral region, the plurality of transistors each having a recessed gate structure.
7. The memory device of claim 6 wherein gates of the memory cells in the cell region and gates of the cells in the peripheral region are formed simultaneously.
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