US20060023517A1 - Method and system for dynamic address translation - Google Patents

Method and system for dynamic address translation Download PDF

Info

Publication number
US20060023517A1
US20060023517A1 US11/186,062 US18606205A US2006023517A1 US 20060023517 A1 US20060023517 A1 US 20060023517A1 US 18606205 A US18606205 A US 18606205A US 2006023517 A1 US2006023517 A1 US 2006023517A1
Authority
US
United States
Prior art keywords
bits
target data
unit
copying
data unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/186,062
Inventor
Gilbert Cabillic
Salam Majoul
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CABILLIC, GILBERT, MAJOUL, SALAM
Publication of US20060023517A1 publication Critical patent/US20060023517A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1081Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017Runtime instruction translation, e.g. macros
    • G06F9/30174Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/455Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60Details of cache memory
    • G06F2212/601Reconfiguration of cache memory
    • G06F2212/6012Reconfiguration of cache memory of operating mode, e.g. cache mode or local memory mode
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Mobile electronic devices such as personal digital assistants (PDAs) and digital cellular telephones are increasingly including applications written in the JavaTM programming language.
  • Many of the processors used in these mobile devices have fixed address modes using byte and/or word addressing.
  • the JavaTM applications executing on such processors may need to access data that does not match the size of a Java object field, or a Java array element.
  • Such data may be stored in memory that is allocated to components comprised in the electronic device, e.g., pixels stored in memory by a display component.
  • a Java application uses a Java data structure to provide data to, or receive data from a corresponding data structure in the memory allocated to the component.
  • This corresponding data structure may contain fields that do not match the size of fields in the Java data structure.
  • a translation between the application data structure and the component memory data structure is performed, either in software or by special hardware. Performing the translation from a Java data structure to the data structure in the component memory in software can be computationally intensive. Enhancements to improve the efficiency of performing the translations in Java applications are desirable. Such enhancements may also be desirable in other high level languages such as C and C++.
  • Some embodiments provide a method copying data from a source memory space to a target memory space.
  • the method comprises extracting a plurality of source data units from the source memory space, wherein each source data unit is of size s bits and translating the plurality of source data units into a plurality of target data units, wherein a target data unit is an addressable unit of the target memory space and each target data unit is of size t bits.
  • the method further comprises copying the plurality of target data units into a plurality of contiguous transfer units in the target memory space, wherein each transfer unit is of size b bits.
  • Some embodiments provide a computer-readable medium that stores a software program that when executed by a processor performs the above-described method.
  • Other embodiments provide a system that comprises a processor, a memory coupled to the processor, and instructions stored in the memory, that when executed by the processor, perform the above-described method.
  • FIG. 1 shows a diagram of a system in accordance with embodiments of the invention
  • FIG. 2 further illustrates the system of FIG. 1 ;
  • FIG. 3-8 illustrate the operation of a dynamic memory translation method in accordance with embodiments of the invention.
  • FIG. 9 depicts an illustrative embodiment of the system described herein.
  • the subject matter disclosed herein is directed to a software solution that dynamically translates n-bit addressable data in a logical memory space to an m-bit addressable representation in a physical memory space and vice versa.
  • the data is translated by a software translation algorithm to an addressable format of the physical memory (i.e., from an n-bit based addressable logical memory to an m-bit based addressable physical memory).
  • the data is translated by a software translation algorithm to an addressable format of the logical memory (i.e., from an m-bit based addressable physical memory to an n-bit based addressable logical memory).
  • some of the embodiments described herein are directed to a Java application that accesses the physical memory allocated to a display device.
  • the principles disclosed herein have applicability apart from the Java language and display devices.
  • FIG. 1 shows a system 100 in accordance with embodiments of the invention.
  • the system may comprise at least two processors 102 and 104 .
  • Processor 102 may be referred to for purposes of this disclosure as a Java Stack Machine (“JSM”) and processor 104 may be referred to as a Main Processor Unit (“MPU”).
  • System 100 may also comprise memory 106 , and a display 114 coupled to both the JSM 102 and MPU 104 via one or more busses 122 .
  • At least a portion of the memory 106 may be shared by both processors, and if desired, other portions of the memory 106 may be designated as private to one processor or the other.
  • Other components (not specifically shown) may be included as desired for various applications.
  • System 100 also comprises a Java Virtual Machine (“JVM”) 108 , compiler 110 , Java APIs 120 , Java native APIs 124 , and Java applications 118 .
  • the JVM may comprise a class loader, bytecode verifier, garbage collector, and a bytecode interpreter loop to interpret the bytecodes that are not executed on the JSM processor 102 .
  • the Java applications 118 are written in Java language source code and may comprise references to one or more classes of the Java Application Program Interfaces (“APIs”) 120 and the Java native APIs 124 .
  • the Java native APIs 124 comprises interfaces to classes and methods implemented in other languages such as C++, C or assembler.
  • the Java source code is converted or compiled to a series of bytecodes 112 , with each individual one of the bytecodes referred to as an “opcode.”
  • Bytecodes 112 are provided to the JVM 108 , possibly compiled by compiler 110 , and provided to the JSM 102 and/or MPU 104 for execution.
  • the JSM 102 may execute at least some Java bytecodes directly.
  • the JVM 108 may also request the MPU 104 to execute one or more Java bytecodes not executed or executable by the JSM 102 .
  • the MPU 104 also may execute non-Java instructions.
  • the MPU 104 may also host an operating system (“O/S”) (not specifically shown) which performs various functions such as system memory management, the system task management that schedules the software aspects of the JVM 108 and most or all other native tasks running on the system, and management of the display 114 .
  • O/S operating system
  • Java code may be used to perform any one of a variety of applications such as multimedia, games or web based applications in the system 100 , while non-Java code, which may comprise the O/S and other native applications, may still run on the system on the MPU 104 .
  • FIG. 2 shows various components related to the management of the display 114 .
  • the Java application 150 comprises an application data structure 152 .
  • the application data structure 152 is presented as an array for purposes of explanation but may be any suitable type of data structure.
  • the application array 152 links to translation software 154 which, in turn, links to display memory 156 .
  • Display memory 156 may comprise a portion of memory 106 allocated for use by the display 114 .
  • Information to be shown on the display 114 is stored in the display memory 156 .
  • a display interface 160 extracts display data from the display memory 156 and provides an appropriate electrical interface to cause the desired information to be shown correctly on the display 114 .
  • the Java application 150 comprises an application array 152 usable for managing the display 114 .
  • the application array 152 is a Java array and thus comports with the applicable requirements of the Java programming language.
  • the array 152 may be an n-bit addressable data structure.
  • n is typically 32 bits meaning that array 152 is addressed in units of 32-bit (four byte) increments.
  • the display memory 156 may be formatted differently than the Java array 152 .
  • the application array 152 may be an n-bit addressable data structure
  • the display memory 156 may comprise an m-bit addressable data structure where m is different than n. In some embodiments, for example, m could be 8, but m could also be any number of bits appropriate to the display color definition.
  • the Java application 150 accesses the display memory 156 through application array 152 .
  • the Java application 150 can cause text and/or graphics data (“display data”) to be shown on display 114 by writing such display data to the application array 152 .
  • the application array 152 is n-bit addressable and the display memory is m-bit addressable, where n may be different (e.g., greater) than m.
  • the application array is formatted differently than the display memory. With n being different than m, the display data from the application array 152 cannot be copied directly into the display memory 156 without being re-formatted, nor can the data be copied directly from the display memory 156 to the application array 152 without re-formatting.
  • the data within the application array 152 is written by the application software, the data is automatically reformatted by the translation software 154 into a format compatible with the display memory 156 .
  • the data within the display memory 156 is placed in the application array 152 , the data is automatically reformatted by the translation software 154 into a format compatible with the application array 152 .
  • FIG. 3 presents an example further illustrating the functionality of the translation software 154 .
  • Logical address space 300 associated with application array 152 may comprise display data from application 150 to be written to a physical address space 302 that is stored in display memory 156 .
  • the size of an addressable data unit in the logical address space 300 i.e., logical data unit
  • the size of an addressable data unit in the physical address space 302 i.e., physical data unit
  • the translation software 154 maps the high level representation (32-bit-based memory block) in the logical address space 300 on to a low-level representation (8-bit-based memory block) in the physical address space 302 and vice versa.
  • the number of meaningful bits in an addressable data unit in the logical address space 300 may not exceed the size of a physical data unit. For example, if the physical address space 302 is 8-bits wide, then the logical address space 300 associated with the application array 152 stores meaningful data in chunks of eight bits.
  • meaningful data chunks are shown at addresses 0xA003, 0xA007, 0XA00B, and so on, while the remaining portions of the address space (e.g., 0xA000-0xA003, 0xA004-0xA006, and so on) are set to a predetermined value of 0.
  • the translation software 154 copies only the meaningful bits of each addressable data unit in the logical address space 300 to the physical address space 302 .
  • the meaningful data chunks at addresses 0xA003, 0xA007, 0xA00B, and so on of the logical address space 300 are copied to addresses 0x0C00, 0x0C01, 0x0C02, and so on by translation software 154 .
  • the translation software 154 copies the data in each of the locations at addresses 0x0C00-0x0C04 to the least significant bits of addresses 0XA000, 0xA004, 0xA008, and so on of the logical address space 300 .
  • the translation software 154 fills the remainder of each addressable data unit with zeros if the data is unsigned, or with a sign extension value if the data is signed.
  • embodiments of the translation software 154 translate the data from an n-bit based addressable contiguous source memory space (e.g., logical address space 300 ) to an m-bit based addressable target memory (e.g., physical address space 302 ).
  • the size s of an addressable data unit in the source memory space i.e., a source data unit
  • the translation software 154 receives as inputs the address of the source memory space, the address of the target memory space, the size (in bits) of a source data unit, the size (in bits) of a target data unit, and the number of source data units in the source memory space to be copied to the target memory space. For each of the source data units, the translation software 154 builds a target data unit of t bits representing the source data unit of s bits, and then copies the series of t bits into the target memory space.
  • the translation software 154 copies all the bits in each source data unit 400 to a target data unit 402 . No extra computation is required to form a target data unit.
  • the translation software 154 copies the least significant t bits 504 of each source data unit 500 to a target data unit 502 .
  • the translation software 154 copies the s bits of the source data unit 600 into the s least significant bits 604 of the target data unit 602 .
  • a build process applied by the translation software 154 to each s i of the set S to create each t i of the set T comprises: 1) if s ⁇ t, a target data unit t i is formed by the least significant t bits extracted from the corresponding source data unit s i ; and 2 ). if s ⁇ t, a target data unit t i is formed by s bits of the corresponding source data unit s i and t-s bits of zero value or sign extension, where the s bits from the source data unit s i constitute the least significant bits of the target data unit t i , and the t-s zero-value or sign extension bits constitute the most significant bits of the target data unit t i .
  • the t-s bits are zero value if the data is unsigned, and sign extension if the data is signed.
  • the translation software 154 copies the t bits of each t i to the target memory space in one or more transfer units where each transfer unit is b bits in size.
  • FIGS. 7 and 8 show examples of the operation of a copy process used in embodiments of the translation software 154 .
  • the copy process copies t 1 into the most significant bits of b 1 , t 2 into the least significant bits of b 1 , t 3 into the most significant bits of b 2 , t 4 into the least significant bits of b 2 , and so on.
  • FIG. 8 shows an example where the t i do not fit evenly in the transfer units of the target memory space.
  • Table 1 contains pseudo code illustrating the operation of at least one embodiment of a copy process used in the translation software 154 . Note that this pseudo code is intended to illustrate the logic of the copy process and does not contain the details of performing the bit operations to place the bits of a target data unit in a transfer unit of the target memory space.
  • the number of bits from the current element t i to be copied is denoted by nbBitsToBeCopied
  • the number of empty bits in the current transfer unit b j to be filled is denoted by nbEmptyBits
  • the number of bits of the current element t i that cannot be copied in the current transfer unit b j is denoted by nbBitsCannotBeCopied
  • the current target data unit t i from T to be copied is denoted by currentDataUnit
  • the current transfer unit b j in B to be filled is denoted by currentTransferUnit.
  • the currentDataUnit is t 1
  • nbBitsToBeCopied is t
  • currentTransferUnit is b 1
  • nbEmptyBits b.
  • the operation of the pseudo code is explained in the context of the example of FIG. 8 .
  • the currentDataUnit is t 1
  • currentTransferUnit is b 1
  • nbEmptyBits is set to 2
  • currentDataUnit is set to t 2 (line 12 ) since all bits of t 1 have been copied.
  • a check is made to determine whether b 1 is full (line 15 ). Because nbEmptyBits is currently two, this test fails.
  • Table 2 contains a C language source code embodiment of a method that may be used in embodiments of the translation software 154 .
  • This code example is presented by way of example only and other implementations are possible and fall within the scope of this disclosure.
  • the C source code of Table 3 contains an example implementation of a function translate that copies meaningful data bits from a source address space to a target address space.
  • This example implementation uses a byte as a transfer unit, so the size of the transfer unit is 8 bits.
  • the function has five parameters: 1) a pointer to the source address space containing the data to be translated, sourcespace; 2) a pointer to the beginning of the target address space, targetspace; 3) the number of bits in a source data unit, sourceUnitSize; 4) the number of bits in a target data unit, targetUnitSize; and 5) the number of source data units to be copied to the target memory space, nbElem.
  • the function also uses several variables during the translation process. Table 2 contains the definitions of these variables.
  • vUnit The bits from a source data unit to be copied into the target address space.
  • the number of bits in vUnit the size of a target data unit.
  • transferUnitSize The number of bits in a transfer unit of the target address space CurrentTransferUnit Holds the transfer unit of data currently being constructed isTruncated A flag indicating whether the bits remaining in vUnit will fit in a transfer unit or not. This flag is initially set to false.
  • nbEmptyBits The number of empty bits to be filled in CurrentTransferUnit.
  • nbBitsToBeCopied The number of bits of the data to be copied into CurrentTransferUnit; initially set to targetUnitSize nbBitsCannotBeCopied The number of bits that cannot be copied into CurrentTransferUnit; nbUnits Holds a count of the number of source data units that have been moved from the source address space to the target address space nbOfTransferUnits The number of transfer units to be filled in the target address space index Holds an index of the current source data unit in the source address space ptr A pointer to the transfer unit in the target address space to be filled
  • the translate function begins by initializing variables and data structures used during the translation process.
  • the number of transfer units to be filled in the target address space, nbOfTransferUnits, is determined using the values of the parameters nbElem and targetUnitSize (lines 20 - 32 ). For purposes of this example, the size of a transfer unit in the target address space is assumed to be eight bits (line 1 ).
  • the function also initializes several variables to be used during the compression process (lines 71 - 87 ) and initializes a mask table, mask, with a number of entries equal to targetUnitSize (lines 57 - 68 ). The entries in this mask table are used to extract the meaningful data bits from a source data unit.
  • the translation process begins by determining whether all of the transfer units in the target address space have been filled (line 91 ). If the target address space is full, the translate function terminates, returning the number of transfer units filled (line 1 56 ). If the target address space is not full, the number of empty bits in the current transfer unit, i.e., nbEmptyBits, is initialized to be the number of bits in a transfer unit of the target address space and a variable to hold the data bits to be written to the next transfer unit location in the target address space, i.e., CurrentTransferUnit, is initialized to 0 (lines 93 - 97 ).
  • the relevant bits of the next source data unit are extracted from the next source data unit in the source address space and placed in vUnit (line 109 ). Note that an entry of the mask table corresponding to a mask value that will extract a number of bits equal to targetUnitSize is used. If the size of a source data unit is less than the size of a target data unit, the targetUnitSize-sourceUnitSize most significant bits of vUnit are set to zero. Otherwise, the process continues with the previously extracted relevant bits of the current source data unit.
  • nbBitsCannotBeCopied the number of bits of the source data unit that cannot be copied into the current transfer unit. If the number of bits that cannot be written is zero (line 115 ), then the remaining bits of the source data unit will fit into the current transfer unit.
  • the truncation flag is set to indicate that all bits of the source data unit have been copied (line 119 ) and the count of the number of empty bits left in the current transfer unit, nbEmptyBits, is reduced by the number of bits to be copied into the current transfer unit (line 122 ).
  • the remaining number of bits of the source data unit are then copied from vUnit to CurrentTransferUnit using the appropriate mask from the mask table (lines 124 - 126 ). This copy operation will shift the bits left as needed to place them in the appropriate position of CurrentTransferUnit.
  • the number of bits to be placed in the next iteration, nbBitsToBeCopied, is set to be the number of bits in a target data unit (line 129 ), and the source address space index is incremented (line 132 ). Processing then continues with the check to determine if there are empty bits in the current transfer unit (line 100 ).
  • nbBitsToBeCopied The number of bits to be placed in the next iteration, nbBitsToBeCopied, is set to be the number of bits that cannot be copied (line 149 ), and processing continues with the check to determine if there are empty bits in the current transfer unit (line 100 ).
  • res.quot res.quot + 1; 33 34 char * ptr; 35 36 unsigned short vUnit; 37 int index; 38 39 int isTruncated; 40 int nbEmptyBits; 41 int nbBitsToBeCopied; 42 int nbBitsCannotBeCopied; 43 int nbUnits; 44 45 int i, j, vMask, v; 46 47 char CurrentTransferUnit; 48 49 /*************************************************************************** 50
  • the mask table is used to extract the least significant K bits from the 51 source data unit.
  • Initialize 75 a truncation flag.
  • a vUnit from the source address space is truncated 76 if all bits do not fit in the current transfer unit of the target space.
  • the system 100 may be implemented as a mobile device 915 such as that shown in FIG. 9 .
  • the mobile device 915 comprises an integrated keypad 912 and display 914 .
  • the JSM processor 102 and MPU processor 104 and other components may be comprised in electronics package 910 connected to the keypad 912 , display 914 , and radio frequency (“RF”) circuitry 916 .
  • the RF circuitry 916 may be connected to an antenna 918 .

Abstract

Methods, computer-readable media, and systems for dynamic address translation between a source memory space and a target memory space are provided. In some illustrative embodiments, a method is provided for copying data from a source memory space to a target memory space. The method includes extracting a plurality of source data units, each of size s bits, from the source memory space and translating the plurality of source data units into a plurality of target data units. A target data unit is an addressable unit of the target memory space and each target data unit is of size t bits. The method further includes copying the plurality of target data units into a plurality of contiguous transfer units, each of size b bits, in the target memory space.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of European Patent Application No. 04291918.3, filed Jul. 27, 2004, incorporated by reference herein as if reproduced in full below.
  • BACKGROUND OF THE INVENTION
  • Mobile electronic devices such as personal digital assistants (PDAs) and digital cellular telephones are increasingly including applications written in the Java™ programming language. Many of the processors used in these mobile devices have fixed address modes using byte and/or word addressing. However, the Java™ applications executing on such processors may need to access data that does not match the size of a Java object field, or a Java array element. Such data may be stored in memory that is allocated to components comprised in the electronic device, e.g., pixels stored in memory by a display component.
  • Generally, a Java application uses a Java data structure to provide data to, or receive data from a corresponding data structure in the memory allocated to the component. This corresponding data structure may contain fields that do not match the size of fields in the Java data structure. A translation between the application data structure and the component memory data structure is performed, either in software or by special hardware. Performing the translation from a Java data structure to the data structure in the component memory in software can be computationally intensive. Enhancements to improve the efficiency of performing the translations in Java applications are desirable. Such enhancements may also be desirable in other high level languages such as C and C++.
  • SUMMARY
  • Accordingly, there are disclosed herein methods and systems dynamic address translation from a data representation in a source memory space to a data representation in a target memory space. Some embodiments provide a method copying data from a source memory space to a target memory space. The method comprises extracting a plurality of source data units from the source memory space, wherein each source data unit is of size s bits and translating the plurality of source data units into a plurality of target data units, wherein a target data unit is an addressable unit of the target memory space and each target data unit is of size t bits. The method further comprises copying the plurality of target data units into a plurality of contiguous transfer units in the target memory space, wherein each transfer unit is of size b bits.
  • Some embodiments provide a computer-readable medium that stores a software program that when executed by a processor performs the above-described method. Other embodiments provide a system that comprises a processor, a memory coupled to the processor, and instructions stored in the memory, that when executed by the processor, perform the above-described method.
  • NOTATION AND NOMENCLATURE
  • Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, semiconductor companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ”. Also, the term “couple” or “couples” is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a more detailed description of the preferred embodiments of the present invention, reference will now be made to the accompanying drawings, wherein:
  • FIG. 1 shows a diagram of a system in accordance with embodiments of the invention;
  • FIG. 2 further illustrates the system of FIG. 1;
  • FIG. 3-8 illustrate the operation of a dynamic memory translation method in accordance with embodiments of the invention; and
  • FIG. 9 depicts an illustrative embodiment of the system described herein.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, unless otherwise specified. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiments is meant only to be exemplary of those embodiments, and not intended to intimate that the scope of the disclosure, is limited to those embodiments.
  • The subject matter disclosed herein is directed to a software solution that dynamically translates n-bit addressable data in a logical memory space to an m-bit addressable representation in a physical memory space and vice versa. When data is transferred from the logical memory space to the physical memory representation, the data is translated by a software translation algorithm to an addressable format of the physical memory (i.e., from an n-bit based addressable logical memory to an m-bit based addressable physical memory). When data is transferred from the physical memory representation to the logical memory space the data is translated by a software translation algorithm to an addressable format of the logical memory (i.e., from an m-bit based addressable physical memory to an n-bit based addressable logical memory).
  • Merely by way of example, some of the embodiments described herein are directed to a Java application that accesses the physical memory allocated to a display device. As one of ordinary skill in the art will appreciate, the principles disclosed herein have applicability apart from the Java language and display devices.
  • FIG. 1 shows a system 100 in accordance with embodiments of the invention. As shown, the system may comprise at least two processors 102 and 104. Processor 102 may be referred to for purposes of this disclosure as a Java Stack Machine (“JSM”) and processor 104 may be referred to as a Main Processor Unit (“MPU”). System 100 may also comprise memory 106, and a display 114 coupled to both the JSM 102 and MPU 104 via one or more busses 122. At least a portion of the memory 106 may be shared by both processors, and if desired, other portions of the memory 106 may be designated as private to one processor or the other. Other components (not specifically shown) may be included as desired for various applications.
  • System 100 also comprises a Java Virtual Machine (“JVM”) 108, compiler 110, Java APIs 120, Java native APIs 124, and Java applications 118. The JVM may comprise a class loader, bytecode verifier, garbage collector, and a bytecode interpreter loop to interpret the bytecodes that are not executed on the JSM processor 102. The Java applications 118 are written in Java language source code and may comprise references to one or more classes of the Java Application Program Interfaces (“APIs”) 120 and the Java native APIs 124. The Java native APIs 124 comprises interfaces to classes and methods implemented in other languages such as C++, C or assembler.
  • The Java source code is converted or compiled to a series of bytecodes 112, with each individual one of the bytecodes referred to as an “opcode.” Bytecodes 112 are provided to the JVM 108, possibly compiled by compiler 110, and provided to the JSM 102 and/or MPU 104 for execution. In some embodiments, the JSM 102 may execute at least some Java bytecodes directly. When appropriate, however, the JVM 108 may also request the MPU 104 to execute one or more Java bytecodes not executed or executable by the JSM 102. In addition to executing compiled Java bytecodes, the MPU 104 also may execute non-Java instructions.
  • The MPU 104 may also host an operating system (“O/S”) (not specifically shown) which performs various functions such as system memory management, the system task management that schedules the software aspects of the JVM 108 and most or all other native tasks running on the system, and management of the display 114. Java code may be used to perform any one of a variety of applications such as multimedia, games or web based applications in the system 100, while non-Java code, which may comprise the O/S and other native applications, may still run on the system on the MPU 104.
  • FIG. 2 shows various components related to the management of the display 114. As shown, the Java application 150 comprises an application data structure 152. The application data structure 152 is presented as an array for purposes of explanation but may be any suitable type of data structure. The application array 152 links to translation software 154 which, in turn, links to display memory 156. Display memory 156 may comprise a portion of memory 106 allocated for use by the display 114. Information to be shown on the display 114 is stored in the display memory 156. A display interface 160 extracts display data from the display memory 156 and provides an appropriate electrical interface to cause the desired information to be shown correctly on the display 114.
  • As noted above, the Java application 150 comprises an application array 152 usable for managing the display 114. The application array 152 is a Java array and thus comports with the applicable requirements of the Java programming language. For example, the array 152 may be an n-bit addressable data structure. In Java, n is typically 32 bits meaning that array 152 is addressed in units of 32-bit (four byte) increments. The display memory 156, however, may be formatted differently than the Java array 152. For example, while the application array 152 may be an n-bit addressable data structure, the display memory 156 may comprise an m-bit addressable data structure where m is different than n. In some embodiments, for example, m could be 8, but m could also be any number of bits appropriate to the display color definition.
  • The Java application 150 accesses the display memory 156 through application array 152. The Java application 150 can cause text and/or graphics data (“display data”) to be shown on display 114 by writing such display data to the application array 152. As noted above, the application array 152 is n-bit addressable and the display memory is m-bit addressable, where n may be different (e.g., greater) than m. Thus, the application array is formatted differently than the display memory. With n being different than m, the display data from the application array 152 cannot be copied directly into the display memory 156 without being re-formatted, nor can the data be copied directly from the display memory 156 to the application array 152 without re-formatting. When the data within the application array 152 is written by the application software, the data is automatically reformatted by the translation software 154 into a format compatible with the display memory 156. When the data within the display memory 156 is placed in the application array 152, the data is automatically reformatted by the translation software 154 into a format compatible with the application array 152.
  • FIG. 3 presents an example further illustrating the functionality of the translation software 154. Logical address space 300 associated with application array 152 may comprise display data from application 150 to be written to a physical address space 302 that is stored in display memory 156. In this example, the size of an addressable data unit in the logical address space 300 (i.e., logical data unit) is 32 bits and the size of an addressable data unit in the physical address space 302 (i.e., physical data unit) is 8 bits.
  • The translation software 154 maps the high level representation (32-bit-based memory block) in the logical address space 300 on to a low-level representation (8-bit-based memory block) in the physical address space 302 and vice versa. The number of meaningful bits in an addressable data unit in the logical address space 300 may not exceed the size of a physical data unit. For example, if the physical address space 302 is 8-bits wide, then the logical address space 300 associated with the application array 152 stores meaningful data in chunks of eight bits.
  • In the example of FIG. 3, meaningful data chunks are shown at addresses 0xA003, 0xA007, 0XA00B, and so on, while the remaining portions of the address space (e.g., 0xA000-0xA003, 0xA004-0xA006, and so on) are set to a predetermined value of 0. When writing to the physical address space 302, the translation software 154 copies only the meaningful bits of each addressable data unit in the logical address space 300 to the physical address space 302. The meaningful data chunks at addresses 0xA003, 0xA007, 0xA00B, and so on of the logical address space 300 are copied to addresses 0x0C00, 0x0C01, 0x0C02, and so on by translation software 154. When reading from the physical address space 300, the translation software 154 copies the data in each of the locations at addresses 0x0C00-0x0C04 to the least significant bits of addresses 0XA000, 0xA004, 0xA008, and so on of the logical address space 300. The translation software 154 fills the remainder of each addressable data unit with zeros if the data is unsigned, or with a sign extension value if the data is signed.
  • In general, embodiments of the translation software 154 translate the data from an n-bit based addressable contiguous source memory space (e.g., logical address space 300) to an m-bit based addressable target memory (e.g., physical address space 302). The size s of an addressable data unit in the source memory space (i.e., a source data unit) is
    s=n*u bits where u>0.
    u is the number of addressable elements of the source memory space that are included in a source data unit. Note that if u=1, then s=n, which is the size of the smallest data unit that can be addressed in the source memory space. The size t of an addressable data unit in the target memory space (i.e., a target data unit) is
    t=m* v where v>0.
    v is the number of addressable elements of the target memory space that are included in a target data unit. Note that if v=1, then t=m, which is the size of the smallest data unit that can be addressed in the target memory space. The translation software 154 copies data from the source memory space to the target memory space, taking into account the respective addressing modes. That is, each source data unit of size s=n*u bits is copied into the target memory space as a target data unit of size t=m*v.
  • In some embodiments, the translation software 154 receives as inputs the address of the source memory space, the address of the target memory space, the size (in bits) of a source data unit, the size (in bits) of a target data unit, and the number of source data units in the source memory space to be copied to the target memory space. For each of the source data units, the translation software 154 builds a target data unit of t bits representing the source data unit of s bits, and then copies the series of t bits into the target memory space. FIGS. 4, 5, and 6 illustrate building target data units when s=t, s>t, and s<t.
  • As the example in FIG. 4 shows, when s=t, embodiments of the translation software 154 copy all the bits in each source data unit 400 to a target data unit 402. No extra computation is required to form a target data unit. As the example in FIG. 5 shows, when s>t, the translation software 154 copies the least significant t bits 504 of each source data unit 500 to a target data unit 502. In this example, s=8 and t=4. As the example in FIG. 6 shows, when s<t, the translation software 154 copies the s bits of the source data unit 600 into the s least significant bits 604 of the target data unit 602. The translation software 154 also fills the most significant t-s bits 606 of the target data unit 602 with zeroes. In this example, s=8 and t=16.
  • Stated more formally, the translation software 154 iterates through a set S of source data units that are to be copied to the target memory space
    S={s1, s2, s3, . . . , sp},
    where each si, iε[1, p], denotes a source data unit of size s bits to build a set T of target data units,
    T={t1, t2, t3, . . . , tp},
    where each ti denotes a target data unit of size t bits such that ti contains the bits of the corresponding source data unit si. In some embodiments, a build process applied by the translation software 154 to each si of the set S to create each ti of the set T comprises: 1) if s≦t, a target data unit ti is formed by the least significant t bits extracted from the corresponding source data unit si; and 2). if s<t, a target data unit ti is formed by s bits of the corresponding source data unit si and t-s bits of zero value or sign extension, where the s bits from the source data unit si constitute the least significant bits of the target data unit ti, and the t-s zero-value or sign extension bits constitute the most significant bits of the target data unit ti. The t-s bits are zero value if the data is unsigned, and sign extension if the data is signed.
  • The translation software 154 copies the t bits of each ti to the target memory space in one or more transfer units where each transfer unit is b bits in size. The copy process used by the translation software 154 is configured to handle both cases where b=t and b≠t. The copy process copies the bit values in the set T to fill a set of transfer units B in the target memory,
    B={bi, b2, b3, . . . , bq},
    where q is the number of transfer units needed to contain the bits comprising set T. The value of q may be determined as follows:
    If rem(t*p, b)=0 then q=div(t*p, b) else q=div(t*p, b)+1
    where p is the number of target data units ti in the set T, rem(a, b) is the operation that computes the remainder of dividing a by b and div(a, b) is the operation that divides a by b.
  • FIGS. 7 and 8 show examples of the operation of a copy process used in embodiments of the translation software 154. FIG. 7 shows a simple example where t=4 and b=8. In cases such as this, where b is evenly divisible by t, each target data unit ti may be entirely copied into a portion of a transfer unit bi of the target memory space. In the example of FIG. 7, the copy process copies t1 into the most significant bits of b1, t2 into the least significant bits of b1, t3 into the most significant bits of b2, t4 into the least significant bits of b2, and so on.
  • FIG. 8 shows an example where the ti do not fit evenly in the transfer units of the target memory space. In this example, t=6 and b=8. The copy process first copies the t bits of target data unit t1 into transfer unit b1 of the target memory space. After copying t1, b−t=2 bits in the current transfer unit b1 remain empty. The copy process fills these two bits with bit values from the next target data unit t2. The copy process extracts the two most significant bits from t2 to fill these two empty bits of transfer unit b1. The copy process then places remaining t−(b−t)=4 bits from t2 in the most significant four bits of the next transfer unit b2. The copy process repeats this procedure to copy all of the of target data units ti in the set T to transfer units in B.
  • Table 1 contains pseudo code illustrating the operation of at least one embodiment of a copy process used in the translation software 154. Note that this pseudo code is intended to illustrate the logic of the copy process and does not contain the details of performing the bit operations to place the bits of a target data unit in a transfer unit of the target memory space. In this pseudo code, the number of bits from the current element ti to be copied is denoted by nbBitsToBeCopied, the number of empty bits in the current transfer unit bj to be filled is denoted by nbEmptyBits, the number of bits of the current element ti that cannot be copied in the current transfer unit bj is denoted by nbBitsCannotBeCopied, the current target data unit ti from T to be copied is denoted by currentDataUnit, and the current transfer unit bj in B to be filled is denoted by currentTransferUnit. Initially, the currentDataUnit is t1, nbBitsToBeCopied is t, currentTransferUnit is b1, and nbEmptyBits=b.
  • The operation of the pseudo code is explained in the context of the example of FIG. 8. Initially, the currentDataUnit is t1, nbBitsToBeCopied is t=6, currentTransferUnit is b1, and nbEmptyBits is b=8. The pseudo code begins with a determination of whether there is sufficient space in the current transfer unit b1 to hold the number of bits to be copied (line 1). Since nbBitsToBeCopied=6 and nbEmptyBits=8, this determination is true and lines 3-18 are executed. All six bits of t1 are copied to b1 (line 4), nbEmptyBits is set to 2, nbBitsToBeCopied is set to t=6 for the next iteration (line 6) and currentDataUnit is set to t2 (line 12) since all bits of t1 have been copied. A check is made to determine whether b1 is full (line 15). Because nbEmptyBits is currently two, this test fails.
  • On the next iteration, a check is again made to determine whether there is sufficient space in the current transfer unit b1 to hold the number of bits to be copied (line 1). Since nbBitsToBeCopied=6 and nbEmptyBits=2, this determination is false and lines 22-29 are executed. nbBitsCannotBeCopied is set to nbBitsToBeCopied−nbEmptyBits=4 (line 22). Then, the most significant 2 bits of t2 are copied into the least significant 2 bits of b1 (line 23). nbEmptyBits is set to b for the next iteration since b1 is full and a new transfer unit is filled beginning with the next iteration (line 24) and nbBitsToBeCopied is set to nbBitsCannotBeCopied=4, the number of bits remaining to be copied in t2. Because all of the bits in b1 are full, cuffentTransferUnit is set to b2.
  • On the subsequent iteration, the check is made to determine whether there is sufficient space in the current transfer unit b2 to hold the number of bits to be copied (line 1). Since nbBitsToBeCopied=4 and nbEmptyBits=8, this determination is true and lines 3-18 are executed. The least significant four bits of t2 are copied to the most significant four bits of b2 (line 4), nbEmptyBits is set to 4 (line 5), and nbBitsToBeCopied is set to t (line 6) and currentDataUnit is set to t3 for the next iteration. This iterative process is repeated until all the bits of the tI are copied to transfer units in the target memory space.
    TABLE 1
    1 if (nbBitsToBeCopied <= nbEmptyBits) then
    2 {
    3  nbBitsCannotBeCopied = 0; // because all bits of ti are copied
    4  copy in currentTransferUnit nbBitsToBeCopied from
     currentDataUnit;
    5  nbEmptyBits = nbEmptyBits − nbBitsToBeCopied;
    6  nbBitsToBeCopied = t; // because all bits of ti are copied, the
    7 // empty bits of the current transfer unit,
    8 // if there are any, will be set by
    9 // values from the next element t i+1
    10
    11  //get from T the next element to be copied in the next iteration
    12  currentDataUnit = t i+1;
    13
    14  //update the current transfer unit if needed
    15  if (nbEmptyBits = 0) then // if all bits of the current transfer unit
     are set
    16  {
    17   currentTransferUnit = bj+1; // then get the next transfer unit
    18  }
    19 }
    20 else
    21 {
    22  nbBitsCannotBeCopied = nbBitsToBeCopied − nbEmptyBits;
    23  copy in currentTransferUnit nbEmptyBits from currentDataUnit;
    24  nbEmptyBits = b;     // because all bits of bj
     are full
    25  nbBitsToBeCopied = nbBitsCannotBeCopied;
    26  // the remaining bits from ti to be copied in the next transfer
     unit b
    j+1
    27
    28  // all bits of the current transfer unit are set; get the next transfer
     unit
    29  currentTransferUnit = bj+1;
    30 }
  • Table 2 contains a C language source code embodiment of a method that may be used in embodiments of the translation software 154. One of ordinary skill will appreciate that this code example is presented by way of example only and other implementations are possible and fall within the scope of this disclosure.
  • The C source code of Table 3 contains an example implementation of a function translate that copies meaningful data bits from a source address space to a target address space. This example implementation uses a byte as a transfer unit, so the size of the transfer unit is 8 bits. The function has five parameters: 1) a pointer to the source address space containing the data to be translated, sourcespace; 2) a pointer to the beginning of the target address space, targetspace; 3) the number of bits in a source data unit, sourceUnitSize; 4) the number of bits in a target data unit, targetUnitSize; and 5) the number of source data units to be copied to the target memory space, nbElem. The function also uses several variables during the translation process. Table 2 contains the definitions of these variables.
    TABLE 2
    Variable Name Definition
    vUnit The bits from a source data unit
    to be copied into the target
    address space. The number of bits
    in vUnit = the size of a target
    data unit.
    transferUnitSize The number of bits in a transfer
    unit of the target address space
    CurrentTransferUnit Holds the transfer unit of data
    currently being constructed
    isTruncated A flag indicating whether the bits
    remaining in vUnit will fit in a
    transfer unit or not. This flag
    is initially set to false.
    nbEmptyBits The number of empty bits to be
    filled in CurrentTransferUnit.
    Initially set to transferUnitSize
    nbBitsToBeCopied The number of bits of the data
    to be copied into
    CurrentTransferUnit; initially
    set to targetUnitSize
    nbBitsCannotBeCopied The number of bits that cannot
    be copied into
    CurrentTransferUnit;
    nbUnits Holds a count of the number of
    source data units that have
    been moved from the source
    address space to the target
    address space
    nbOfTransferUnits The number of transfer units to
    be filled in the target address
    space
    index Holds an index of the current
    source data unit in the source
    address space
    ptr A pointer to the transfer unit
    in the target address space to be
    filled
  • The translate function begins by initializing variables and data structures used during the translation process. The number of transfer units to be filled in the target address space, nbOfTransferUnits, is determined using the values of the parameters nbElem and targetUnitSize (lines 20-32). For purposes of this example, the size of a transfer unit in the target address space is assumed to be eight bits (line1). The function also initializes several variables to be used during the compression process (lines 71-87) and initializes a mask table, mask, with a number of entries equal to targetUnitSize (lines 57-68). The entries in this mask table are used to extract the meaningful data bits from a source data unit. The number of entries in the mask table corresponds to the number of bits in a target data unit (i.e., targetUnitSize). For example, if the size of target data unit is four bits, then mask[0]=1, mask[1]=3, mask[2]=7, and mask[3]=15. mask[<number of bits to be extracted>1] is used to extract the <number of bits to be extracted> least significant meaningful data bits from a source data unit. That is, to extract the three least significant bits, mask[3-1] is used.
  • The translation process begins by determining whether all of the transfer units in the target address space have been filled (line 91). If the target address space is full, the translate function terminates, returning the number of transfer units filled (line1 56). If the target address space is not full, the number of empty bits in the current transfer unit, i.e., nbEmptyBits, is initialized to be the number of bits in a transfer unit of the target address space and a variable to hold the data bits to be written to the next transfer unit location in the target address space, i.e., CurrentTransferUnit, is initialized to 0 (lines 93-97).
  • A check is then made to determine if there are still some empty bits to be filled in the current transfer unit location of the target address space (line 100). If there are not, CurrentTransferUnit is written to the target address space (line 152), the count of the number of transfer units copied, nbUnits, is incremented (line 153), and processing resumes with the determination of whether all of the transfer units have been filled (line 91). If there are empty bits to be filled, then a check is made to determine whether the current source data unit has been completely copied (line 102). This determination is made by checking the value of a truncation flag, isTruncated. If the current source data unit has been copied, the relevant bits of the next source data unit are extracted from the next source data unit in the source address space and placed in vUnit (line 109). Note that an entry of the mask table corresponding to a mask value that will extract a number of bits equal to targetUnitSize is used. If the size of a source data unit is less than the size of a target data unit, the targetUnitSize-sourceUnitSize most significant bits of vUnit are set to zero. Otherwise, the process continues with the previously extracted relevant bits of the current source data unit.
  • Next, the number of bits of the source data unit that cannot be copied into the current transfer unit, nbBitsCannotBeCopied, is determined (lines 112-113). If the number of bits that cannot be written is zero (line 115), then the remaining bits of the source data unit will fit into the current transfer unit. The truncation flag is set to indicate that all bits of the source data unit have been copied (line 119) and the count of the number of empty bits left in the current transfer unit, nbEmptyBits, is reduced by the number of bits to be copied into the current transfer unit (line 122). The remaining number of bits of the source data unit are then copied from vUnit to CurrentTransferUnit using the appropriate mask from the mask table (lines 124-126). This copy operation will shift the bits left as needed to place them in the appropriate position of CurrentTransferUnit. The number of bits to be placed in the next iteration, nbBitsToBeCopied, is set to be the number of bits in a target data unit (line 129), and the source address space index is incremented (line 132). Processing then continues with the check to determine if there are empty bits in the current transfer unit (line 100).
  • If the number of bits that cannot be copied is not zero (line 134), then there are not enough empty bits in the current transfer unit to hold the data bits remaining the source data unit. The truncation flag is set to indicate that all bits of the source data unit have not been copied (line 138), and the count of the number of empty bits left in the current transfer unit, nbEmptyBits, is set to zero since the current transfer unit will be full after the copy operation (line 141). The number of bits of the source data unit that will fit into the current transfer unit are then copied from vUnit to CurrentTransferUnit using the appropriate mask from the mask table (lines 144-145). This copy operation will shift the bits right as needed to place them in the appropriate position of CurrentTransferUnit. The number of bits to be placed in the next iteration, nbBitsToBeCopied, is set to be the number of bits that cannot be copied (line 149), and processing continues with the check to determine if there are empty bits in the current transfer unit (line 100).
    TABLE 3
    1 int transferUnitSize = 8; /* # bits in a byte */
    2
    3 /*
    4  * fills the target space from data coming from the source space
    5  * @param sourceSpace: pointer to the source memory space
    6  * @param targetSpace : pointer to the target memory space
    7  * @param sourceUnitSize: # of bits of in a source data unit
    8  * @param targetUnitSize: # of bits in a target data unit
    9  * @param nbElem: # of elements in the source space to be copied
    10  * @return # of generated transfer units in the target space
    11  */
    12 int translate ( unsigned short* sourceSpace,
    13      char** targetSpace,
    14      int sourceUnitSize,
    15      int targetUnitSize,
    16      int nbElem)
    17 {
    18  /* useful data deduced from parameters */
    19
    20  /* # of bits to be copied in the target space */
    21  int nbOfBits = nbElem * targetUnitSize;
    22
    23  /*
    24  Compute the # of transfer units to be filled in the target space by
    dividing the #
    25  of bits in the target space by the size of one transfer unit. If the
    remainder of
    26  divide operation is 0, the # of transfer units is the result of the divide.
    27  Otherwise, the # transfer units is the result of the divide operation plus
    one.
    28  */
    29  div_t res = div(nbOfBits,transferUnitSize);
    30
    31  /* # of transfer units generated in the target space */
    32  int nbOfTransferUnits = (res.rem == 0) ? res.quot : res.quot + 1;
    33
    34  char * ptr;
    35
    36  unsigned short vUnit;
    37  int index;
    38
    39  int isTruncated;
    40  int nbEmptyBits;
    41  int nbBitsToBeCopied;
    42  int nbBitsCannotBeCopied;
    43  int nbUnits;
    44
    45  int i, j, vMask, v;
    46
    47  char CurrentTransferUnit;
    48
    49  /*****************************************************************
    50  The mask table is used to extract the least significant K bits from the
    51   source data unit. For example, if targetUnitSize = 4, then
    52   mask[0] = 1, mask[1] = 3, mask[2] = 7, and mask[3] = 15. Mask[3−1]
    53   Is used to extract the least significant 3 bits.
    54  */
    55
    56  /* int of the mask table */
    57  int * mask = (int *) malloc(sizeof(int) * targetUnitSize);
    58  for (i = 1; i <= targetUnitSize; i++)
    59   {
    60   vMask= 0;
    61   v = 1;
    62   for (j = 0; j < i; j++)
    63    {
    64     vMask = vMask + v;
    65     v = v * 2;
    66    }
    67   mask[i−1] = vMask;
    68   }
    69
    70  /* Index in the source space.*/
    71  index = 0;
    72
    73  /*
    74   Fill the target space with nbOfTransferUnits transfer units. Initialize
    75   a truncation flag. A vUnit from the source address space is truncated
    76   if all bits do not fit in the current transfer unit of the target space.
    77  */
    78  isTruncated = 0; /*false*/
    79
    80  /* # bits to be copied */
    81  nbBitsToBeCopied = targetUnitSize;
    82
    83  /* Pointer in the target space */
    84  ptr = *targetSpace;
    85
    86  /* Current number of transfer units filled in the target space */
    87  nbUnits = 0;
    88
    89  /* Construct transfer units of the target space */
    90
    91  while (nbUnits < nbOfTransferUnits)
    92   {
    93   /* # bits of the current transfer unit to be updated */
    94   nbEmptyBits = transferUnitSize;
    95
    96   /* Holds the target transfer unit being constructed */
    97   CurrentTransferUnit = (char) 0;
    98
    99   /* There are some empty bits to be filled in the current transfer unit */
    100   while ((nbEmptyBits > 0) && (index < nbElem))
    101   {
    102    if (! isTruncated)
    103    {
    104     /*
    105     The current source data unit copied to the target space is not
    106     truncated. Get the next one from the source data space and
    107     extract targetUnitSize bits
    108    */
    109     vUnit = sourceSpace[index] & mask[targetUnitSize − 1];
    110    }
    111
    112    nbBitsCannotBeCopied = (nbEmptyBits >= nbBitsToBeCopied) ?
    113     0 : nbBitsToBeCopied − nbEmptyBits;
    114
    115    if (nbBitsCannotBeCopied == 0)
    116    {
    117     /* There are enough empty bits in the current transfer unit, so
    118      the source data unit will not be truncated */
    119     isTruncated = 0;
    120
    121     /* Update the number of empty bits in the current transfer unit */
    122     nbEmptyBits = nbEmptyBits − nbBitsToBeCopied;
    123
    124    /* fill the transfer unit, extracting the bits and shifting left */
    125     CurrentTransferUnit = (char) ((vUnit & mask[nbBitsToBeCopied
    126        − 1]) << nbEmptyBits) | CurrentTransferUnit;
    127
    128    /* # of bits to be placed for the next data unit */
    129     nbBitsToBeCopied = targetUnitSize;
    130
    131    /* increment index to next data unit in the source space. */
    132     index++;
    133    }
    134    else
    135    {
    136    /* There are not enough empty bits in the current transfer unit; the
    137      current data will be truncated (if it is not yet) */
    138     isTruncated = 1;
    139
    140     /* and there will be no empty bits in the current transfer unit */
    141     nbEmptyBits = 0;
    142
    143     /* Copy data into the current transfer unit*/
    144     CurrentTransferUnit = (char) (((vUnit & mask[nbBitsToBeCopied
    145        − 1]) >> nbBitsCannotBeCopied)) | CurrentTransferUnit;
    146
    147     /* The # of bits to be placed in the next iteration = # of bits
    148      that cannot be placed */
    149     nbBitsToBeCopied = nbBitsCannotBeCopied;
    150    }
    151   }
    152   *ptr = CurrentTransferUnit; /* put constructed transfer unit in target
    space */
    153   nbUnits++; /* increment the number of transfer units copied */
    154   ptr++; /* move to the next transfer unit */
    155   }
    156  return nbOfTransferUnits;
    157 }
  • The system 100 may be implemented as a mobile device 915 such as that shown in FIG. 9. As shown, the mobile device 915 comprises an integrated keypad 912 and display 914. The JSM processor 102 and MPU processor 104 and other components may be comprised in electronics package 910 connected to the keypad 912, display 914, and radio frequency (“RF”) circuitry 916. The RF circuitry 916 may be connected to an antenna 918.
  • While the various embodiments of the invention have been shown and described, modifications thereof can be made by one skilled in the art without departing from the spirit and teachings of the invention. The embodiments described herein are illustrative only, and are not intended to be limiting. Many variations and modifications of the invention disclosed herein are possible and are within the scope of the invention. Accordingly, the scope of protection is not limited by the description set out above. Each and every claim is incorporated into the specification as an embodiment of the present invention.

Claims (19)

1. A method for copying data from a source memory space to a target memory space, the method comprising:
extracting a plurality of source data units from the source memory space, wherein each source data unit is of size s bits;
translating the plurality of source data units into a plurality of target data units, wherein a target data unit is an addressable unit of the target memory space and each target data unit is of size t bits; and
copying the plurality of target data units into a plurality of contiguous transfer units in the target memory space, wherein each transfer unit is of size b bits.
2. The method of claim 1, wherein translating the plurality of source data units further comprises copying the s bits of each source data unit of the plurality of source data units to a target data unit of the plurality of target data units if s=t.
3. The method of claim 1, wherein translating the plurality of source data units further comprises copying a least significant t bits of each source data unit to a target data unit of the plurality of target data units if s>t.
4. The method of claim 1, wherein translating the plurality of source data units further comprises:
if s<t, copying the s bits of each source data unit to an s least significant bits of a target data unit of the plurality of target data units, and setting a t-s most significant bits of the target data unit to zero if the s bits are unsigned or to a sign extension value if the s bits are signed.
5. The method of claim 1, wherein copying the plurality of target data units further comprises:
copying n bits of the t bits of a first target data unit to an n most significant bits of a first transfer unit of the plurality of transfer units, wherein the transfer unit has x empty bits before the copying; and
if n<x, copying x-n bits of a second target data unit to an x-n least significant bits of the first transfer unit and copying t-(x-n) bits of the second target data unit to a t-(x-n) most significant bits of a second transfer unit contiguous to the first transfer unit.
6. The method of claim 1, wherein copying the plurality of target data units further comprises:
if a number of bits n to be copied in a target data unit is less than or equal to a number of empty bits x in a transfer unit, copying n bits of the target data unit to an n most significant bits of the x empty bits of the transfer unit; and
if the number of bits n is greater than the number of empty bits x, copying an x most significant bits of the n bits of the target data unit to the x empty bits of the transfer unit.
7. A computer-readable medium storing a software program that, when executed by a processor, performs a method for copying a source memory space to a target memory space, the method comprising:
extracting a plurality of source data units from the source memory space, wherein each source data unit is of size s bits;
translating the plurality of source data units into a plurality of target data units, wherein a target data unit is an addressable unit of the target memory space and each target data unit is of size t bits; and
copying the plurality of target data units into a plurality of contiguous transfer units in the target memory space, wherein each transfer unit is of size b bits.
8. The computer-readable medium of claim 7, wherein translating the plurality of source data units further comprises copying the s bits of each source data unit of the plurality of source data units to a target data unit of the plurality of target data units if s=t.
9. The computer-readable medium of claim 7, wherein translating the plurality of source data units further comprises copying a least significant t bits of each source data unit to a target data unit of the plurality of target data units if s>t.
10. The computer-readable medium of claim 7, wherein translating the plurality of source data units further comprises:
if s<t, copying the s bits of each source data unit to an s least significant bits of a target data unit of the plurality of target data units, and setting a t-s most significant bits of the target data unit to zero if the s bits are unsigned or to a sign extension value if the s bits are signed.
11. The computer-readable medium of claim 7, wherein copying the plurality of target data units further comprises:
copying n bits of the t bits of a first target data unit to an n most significant bits of a first transfer unit of the plurality of transfer units, wherein the transfer unit has x empty bits before the copying; and
if n<x, copying x-n bits of a second target data unit to an x-n least significant bits of the first transfer unit and copying t-(x-n) bits of the second target data unit to a t-(x-n) most significant bits of a second transfer unit contiguous to the first transfer unit.
12. The computer-readable medium of claim 7, wherein copying the plurality of target data units further comprises:
if a number of bits n to be copied in a target data unit is less than or equal to a number of empty bits x in a transfer unit, copying n bits of the target data unit to an n most significant bits of the x empty bits of the transfer unit; and
if the number of bits n is greater than the number of empty bits x, copying an x most significant bits of the n bits of the target data unit to the x empty bits of the transfer unit.
13. A system, comprising:
a processor;
a memory coupled to the processor; and
instructions stored in the memory that, when executed by the processor, perform a method for copying a source memory space to a target memory space, the method comprising:
extracting a plurality of source data units from the source memory space, wherein each source data unit is of size s bits;
translating the plurality of source data units into a plurality of target data units, wherein a target data unit is an addressable unit of the target memory space and each target data unit is of size t bits; and
copying the plurality of target data units into a plurality of contiguous transfer units in the target memory space, wherein each transfer unit is of size b bits.
14. The system of claim 13, wherein translating the plurality of source data units further comprises copying the s bits of each source data unit of the plurality of source data units to a target data unit of the plurality of target data units if s=t.
15. The system of claim 13, wherein translating the plurality of source data units further comprises copying a least significant t bits of each source data unit to a target data unit of the plurality of target data units if s>t.
16. The system of claim 13, wherein translating the plurality of source data units further comprises:
if s<t, copying the s bits of each source data unit to an s least significant bits of a target data unit of the plurality of target data units, and setting a t-s most significant bits of the target data unit to zero if the s bits are unsigned or to a sign extension value if the s bits are signed.
17. The system of claim 13, wherein copying the plurality of target data units further comprises:
copying n bits of the t bits of a first target data unit to an n most significant bits of a first transfer unit of the plurality of transfer units, wherein the transfer unit has x empty bits before the copying; and
if n<x, copying x-n bits of a second target data unit to an x-n least significant bits of the first transfer unit and copying t-(x-n) bits of the second target data unit to a t-(x-n) most significant bits of a second transfer unit contiguous to the first transfer unit.
18. The system of claim 13, wherein copying the plurality of target data units further comprises:
if a number of bits n to be copied in a target data unit is less than or equal to a number of empty bits x in a transfer unit, copying n bits of the target data unit to an n most significant bits of the x empty bits of the transfer unit; and
if the number of bits n is greater than the number of empty bits x, copying an x most significant bits of the n bits of the target data unit to the x empty bits of the transfer unit.
19. The system of claim 13, wherein the system comprises a mobile device.
US11/186,062 2004-07-27 2005-07-21 Method and system for dynamic address translation Abandoned US20060023517A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04291918A EP1622009A1 (en) 2004-07-27 2004-07-27 JSM architecture and systems
EP04291918.3 2004-07-27

Publications (1)

Publication Number Publication Date
US20060023517A1 true US20060023517A1 (en) 2006-02-02

Family

ID=34931294

Family Applications (37)

Application Number Title Priority Date Filing Date
US11/116,918 Abandoned US20060026398A1 (en) 2004-07-27 2005-04-28 Unpack instruction
US11/116,522 Active 2029-06-29 US8185666B2 (en) 2004-07-27 2005-04-28 Compare instruction
US11/116,897 Abandoned US20060026397A1 (en) 2004-07-27 2005-04-28 Pack instruction
US11/116,893 Abandoned US20060026396A1 (en) 2004-07-27 2005-04-28 Memory access instruction with optional error check
US11/135,796 Abandoned US20060026392A1 (en) 2004-07-27 2005-05-24 Method and system of informing a micro-sequence of operand width
US11/186,063 Abandoned US20060026183A1 (en) 2004-07-27 2005-07-21 Method and system provide concurrent access to a software object
US11/186,330 Abandoned US20060026394A1 (en) 2004-07-27 2005-07-21 Optimizing data manipulation in media processing applications
US11/186,239 Active 2027-12-15 US7574584B2 (en) 2004-07-27 2005-07-21 Splitting execution of a floating-point add instruction between an integer pipeline for performing mantissa addition and a hardware state machine
US11/186,271 Active 2029-06-12 US7930689B2 (en) 2004-07-27 2005-07-21 Method and system for accessing indirect memories
US11/186,315 Active 2030-12-08 US8516496B2 (en) 2004-07-27 2005-07-21 Storing contexts for thread switching
US11/186,036 Active 2030-06-19 US8078842B2 (en) 2004-07-27 2005-07-21 Removing local RAM size limitations when executing software code
US11/186,062 Abandoned US20060023517A1 (en) 2004-07-27 2005-07-21 Method and system for dynamic address translation
US11/187,199 Abandoned US20060026200A1 (en) 2004-07-27 2005-07-22 Method and system for shared object data member zones
US11/188,550 Abandoned US20060026201A1 (en) 2004-07-27 2005-07-25 Method and system for multiple object representation
US11/188,336 Abandoned US20060026401A1 (en) 2004-07-27 2005-07-25 Method and system to disable the "wide" prefix
US11/188,670 Active 2031-03-01 US8380906B2 (en) 2004-07-27 2005-07-25 Method and system for implementing interrupt service routines
US11/188,491 Active 2027-06-12 US7546437B2 (en) 2004-07-27 2005-07-25 Memory usable in cache mode or scratch pad mode to reduce the frequency of memory accesses
US11/188,311 Active 2026-10-10 US7533250B2 (en) 2004-07-27 2005-07-25 Automatic operand load, modify and store
US11/188,411 Active 2028-03-27 US7606977B2 (en) 2004-07-27 2005-07-25 Context save and restore with a stack-based memory structure
US11/188,668 Active 2026-05-05 US7260682B2 (en) 2004-07-27 2005-07-25 Cache memory usable as scratch pad storage
US11/188,667 Abandoned US20060026312A1 (en) 2004-07-27 2005-07-25 Emulating a direct memory access controller
US11/188,502 Active 2029-03-09 US7757223B2 (en) 2004-07-27 2005-07-25 Method and system to construct a data-flow analyzer for a bytecode verifier
US11/188,309 Abandoned US20060026407A1 (en) 2004-07-27 2005-07-25 Delegating tasks between multiple processor cores
US11/188,592 Active 2029-02-28 US8024554B2 (en) 2004-07-27 2005-07-25 Modifying an instruction stream using one or more bits to replace an instruction or to replace an instruction and to subsequently execute the replaced instruction
US11/188,551 Active 2032-03-09 US9201807B2 (en) 2004-07-27 2005-07-25 Method and system for managing virtual memory
US11/188,923 Abandoned US20060026322A1 (en) 2004-07-27 2005-07-25 Interrupt management in dual core processors
US11/188,827 Active 2026-08-09 US7493476B2 (en) 2004-07-27 2005-07-25 Method and system for obtaining an immediate operand of a bytecode for use by a micro-sequence
US11/188,310 Active 2029-05-11 US8046748B2 (en) 2004-07-27 2005-07-25 Method and system to emulate an M-bit instruction set
US11/188,504 Active 2026-10-13 US7500085B2 (en) 2004-07-27 2005-07-25 Identifying code for compilation
US11/188,503 Active 2027-01-25 US7587583B2 (en) 2004-07-27 2005-07-25 Method and system for processing a “WIDE” opcode when it is not used as a prefix for an immediately following opcode
US11/189,245 Abandoned US20060026126A1 (en) 2004-07-27 2005-07-26 Method and system for making a java system call
US11/189,422 Active 2029-04-16 US7743384B2 (en) 2004-07-27 2005-07-26 Method and system for implementing an interrupt handler
US11/189,367 Active 2026-10-25 US7624382B2 (en) 2004-07-27 2005-07-26 Method and system of control flow graph construction
US11/189,410 Active 2027-04-17 US7543285B2 (en) 2004-07-27 2005-07-26 Method and system of adaptive dynamic compiler resolution
US11/189,637 Active 2028-06-25 US7752610B2 (en) 2004-07-27 2005-07-26 Method and system for thread abstraction
US11/189,211 Active 2028-02-02 US8024716B2 (en) 2004-07-27 2005-07-26 Method and apparatus for code optimization
US11/189,411 Abandoned US20060026580A1 (en) 2004-07-27 2005-07-26 Method and related system of dynamic compiler resolution

Family Applications Before (11)

Application Number Title Priority Date Filing Date
US11/116,918 Abandoned US20060026398A1 (en) 2004-07-27 2005-04-28 Unpack instruction
US11/116,522 Active 2029-06-29 US8185666B2 (en) 2004-07-27 2005-04-28 Compare instruction
US11/116,897 Abandoned US20060026397A1 (en) 2004-07-27 2005-04-28 Pack instruction
US11/116,893 Abandoned US20060026396A1 (en) 2004-07-27 2005-04-28 Memory access instruction with optional error check
US11/135,796 Abandoned US20060026392A1 (en) 2004-07-27 2005-05-24 Method and system of informing a micro-sequence of operand width
US11/186,063 Abandoned US20060026183A1 (en) 2004-07-27 2005-07-21 Method and system provide concurrent access to a software object
US11/186,330 Abandoned US20060026394A1 (en) 2004-07-27 2005-07-21 Optimizing data manipulation in media processing applications
US11/186,239 Active 2027-12-15 US7574584B2 (en) 2004-07-27 2005-07-21 Splitting execution of a floating-point add instruction between an integer pipeline for performing mantissa addition and a hardware state machine
US11/186,271 Active 2029-06-12 US7930689B2 (en) 2004-07-27 2005-07-21 Method and system for accessing indirect memories
US11/186,315 Active 2030-12-08 US8516496B2 (en) 2004-07-27 2005-07-21 Storing contexts for thread switching
US11/186,036 Active 2030-06-19 US8078842B2 (en) 2004-07-27 2005-07-21 Removing local RAM size limitations when executing software code

Family Applications After (25)

Application Number Title Priority Date Filing Date
US11/187,199 Abandoned US20060026200A1 (en) 2004-07-27 2005-07-22 Method and system for shared object data member zones
US11/188,550 Abandoned US20060026201A1 (en) 2004-07-27 2005-07-25 Method and system for multiple object representation
US11/188,336 Abandoned US20060026401A1 (en) 2004-07-27 2005-07-25 Method and system to disable the "wide" prefix
US11/188,670 Active 2031-03-01 US8380906B2 (en) 2004-07-27 2005-07-25 Method and system for implementing interrupt service routines
US11/188,491 Active 2027-06-12 US7546437B2 (en) 2004-07-27 2005-07-25 Memory usable in cache mode or scratch pad mode to reduce the frequency of memory accesses
US11/188,311 Active 2026-10-10 US7533250B2 (en) 2004-07-27 2005-07-25 Automatic operand load, modify and store
US11/188,411 Active 2028-03-27 US7606977B2 (en) 2004-07-27 2005-07-25 Context save and restore with a stack-based memory structure
US11/188,668 Active 2026-05-05 US7260682B2 (en) 2004-07-27 2005-07-25 Cache memory usable as scratch pad storage
US11/188,667 Abandoned US20060026312A1 (en) 2004-07-27 2005-07-25 Emulating a direct memory access controller
US11/188,502 Active 2029-03-09 US7757223B2 (en) 2004-07-27 2005-07-25 Method and system to construct a data-flow analyzer for a bytecode verifier
US11/188,309 Abandoned US20060026407A1 (en) 2004-07-27 2005-07-25 Delegating tasks between multiple processor cores
US11/188,592 Active 2029-02-28 US8024554B2 (en) 2004-07-27 2005-07-25 Modifying an instruction stream using one or more bits to replace an instruction or to replace an instruction and to subsequently execute the replaced instruction
US11/188,551 Active 2032-03-09 US9201807B2 (en) 2004-07-27 2005-07-25 Method and system for managing virtual memory
US11/188,923 Abandoned US20060026322A1 (en) 2004-07-27 2005-07-25 Interrupt management in dual core processors
US11/188,827 Active 2026-08-09 US7493476B2 (en) 2004-07-27 2005-07-25 Method and system for obtaining an immediate operand of a bytecode for use by a micro-sequence
US11/188,310 Active 2029-05-11 US8046748B2 (en) 2004-07-27 2005-07-25 Method and system to emulate an M-bit instruction set
US11/188,504 Active 2026-10-13 US7500085B2 (en) 2004-07-27 2005-07-25 Identifying code for compilation
US11/188,503 Active 2027-01-25 US7587583B2 (en) 2004-07-27 2005-07-25 Method and system for processing a “WIDE” opcode when it is not used as a prefix for an immediately following opcode
US11/189,245 Abandoned US20060026126A1 (en) 2004-07-27 2005-07-26 Method and system for making a java system call
US11/189,422 Active 2029-04-16 US7743384B2 (en) 2004-07-27 2005-07-26 Method and system for implementing an interrupt handler
US11/189,367 Active 2026-10-25 US7624382B2 (en) 2004-07-27 2005-07-26 Method and system of control flow graph construction
US11/189,410 Active 2027-04-17 US7543285B2 (en) 2004-07-27 2005-07-26 Method and system of adaptive dynamic compiler resolution
US11/189,637 Active 2028-06-25 US7752610B2 (en) 2004-07-27 2005-07-26 Method and system for thread abstraction
US11/189,211 Active 2028-02-02 US8024716B2 (en) 2004-07-27 2005-07-26 Method and apparatus for code optimization
US11/189,411 Abandoned US20060026580A1 (en) 2004-07-27 2005-07-26 Method and related system of dynamic compiler resolution

Country Status (2)

Country Link
US (37) US20060026398A1 (en)
EP (1) EP1622009A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102929981A (en) * 2012-10-17 2013-02-13 Tcl通力电子(惠州)有限公司 Media scanned file indexing method and device
US9135170B2 (en) 2012-05-15 2015-09-15 Futurewei Technologies, Inc. Memory mapping and translation for arbitrary number of memory units
WO2019229538A3 (en) * 2018-05-30 2020-05-22 赛灵思公司 Data conversion structure, method and on-chip implementation thereof

Families Citing this family (280)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4386732B2 (en) 2002-01-08 2009-12-16 セブン ネットワークス, インコーポレイテッド Mobile network connection architecture
US7917468B2 (en) 2005-08-01 2011-03-29 Seven Networks, Inc. Linking of personal information management data
US8468126B2 (en) 2005-08-01 2013-06-18 Seven Networks, Inc. Publishing data in an information community
US7853563B2 (en) 2005-08-01 2010-12-14 Seven Networks, Inc. Universal data aggregation
US7249128B2 (en) * 2003-08-05 2007-07-24 International Business Machines Corporation Performance prediction system with query mining
EP1622009A1 (en) * 2004-07-27 2006-02-01 Texas Instruments Incorporated JSM architecture and systems
US7441271B2 (en) 2004-10-20 2008-10-21 Seven Networks Method and apparatus for intercepting events in a communication system
US8010082B2 (en) 2004-10-20 2011-08-30 Seven Networks, Inc. Flexible billing architecture
US7643818B2 (en) * 2004-11-22 2010-01-05 Seven Networks, Inc. E-mail messaging to/from a mobile terminal
US7706781B2 (en) 2004-11-22 2010-04-27 Seven Networks International Oy Data security in a mobile e-mail service
FI117152B (en) 2004-12-03 2006-06-30 Seven Networks Internat Oy E-mail service provisioning method for mobile terminal, involves using domain part and further parameters to generate new parameter set in list of setting parameter sets, if provisioning of e-mail service is successful
EP1828932A4 (en) * 2004-12-10 2008-03-05 Seven Networks Internat Oy Database synchronization
FI120165B (en) * 2004-12-29 2009-07-15 Seven Networks Internat Oy Synchronization of a database through a mobile network
US7752633B1 (en) 2005-03-14 2010-07-06 Seven Networks, Inc. Cross-platform event engine
US7796742B1 (en) 2005-04-21 2010-09-14 Seven Networks, Inc. Systems and methods for simplified provisioning
US8438633B1 (en) 2005-04-21 2013-05-07 Seven Networks, Inc. Flexible real-time inbox access
US7200700B2 (en) * 2005-05-19 2007-04-03 Inventec Corporation Shared-IRQ user defined interrupt signal handling method and system
WO2006136661A1 (en) * 2005-06-21 2006-12-28 Seven Networks International Oy Network-initiated data transfer in a mobile network
WO2006136660A1 (en) 2005-06-21 2006-12-28 Seven Networks International Oy Maintaining an ip connection in a mobile network
US8069166B2 (en) * 2005-08-01 2011-11-29 Seven Networks, Inc. Managing user-to-user contact with inferred presence information
US8261024B1 (en) * 2005-09-15 2012-09-04 Oracle America, Inc. Address level synchronization of shared data
US7895597B2 (en) * 2005-09-15 2011-02-22 Nokia Corporation Method, apparatus and computer program product enabling full pre-emptive scheduling of green threads on a virtual machine
US7590774B2 (en) * 2005-12-01 2009-09-15 Kabushiki Kaisha Toshiba Method and system for efficient context swapping
US7873953B1 (en) * 2006-01-20 2011-01-18 Altera Corporation High-level language code sequence optimization for implementing programmable chip designs
US8265349B2 (en) * 2006-02-07 2012-09-11 Qualcomm Incorporated Intra-mode region-of-interest video object segmentation
US7769395B2 (en) 2006-06-20 2010-08-03 Seven Networks, Inc. Location-based operations and messaging
KR100809294B1 (en) 2006-03-10 2008-03-07 삼성전자주식회사 Apparatus and method for executing thread scheduling in virtual machine
US7538760B2 (en) 2006-03-30 2009-05-26 Apple Inc. Force imaging input device and system
KR20070109432A (en) * 2006-05-11 2007-11-15 삼성전자주식회사 Apparatus and method for kernel aware debugging
US7594094B2 (en) * 2006-05-19 2009-09-22 International Business Machines Corporation Move data facility with optional specifications
US20080001717A1 (en) * 2006-06-20 2008-01-03 Trevor Fiatal System and method for group management
US8176491B1 (en) * 2006-08-04 2012-05-08 Oracle America, Inc. Fast synchronization of simple synchronized methods
US8400998B2 (en) * 2006-08-23 2013-03-19 Motorola Mobility Llc Downlink control channel signaling in wireless communication systems
US7885112B2 (en) 2007-09-07 2011-02-08 Sandisk Corporation Nonvolatile memory and method for on-chip pseudo-randomization of data within a page and between pages
US9069547B2 (en) 2006-09-22 2015-06-30 Intel Corporation Instruction and logic for processing text strings
US7844959B2 (en) * 2006-09-29 2010-11-30 Microsoft Corporation Runtime optimization of distributed execution graph
US8201142B2 (en) * 2006-09-29 2012-06-12 Microsoft Corporation Description language for structured graphs
US20080082644A1 (en) * 2006-09-29 2008-04-03 Microsoft Corporation Distributed parallel computing
US8292689B2 (en) * 2006-10-02 2012-10-23 Mattel, Inc. Electronic playset
US20080148241A1 (en) * 2006-10-11 2008-06-19 Scott Thomas Jones Method and apparatus for profiling heap objects
WO2008047180A1 (en) * 2006-10-20 2008-04-24 Freescale Semiconductor, Inc. System and method for fetching an information unit
US8069440B2 (en) * 2006-10-27 2011-11-29 Oracle America, Inc. Adaptive code through self steered execution
US8190861B2 (en) * 2006-12-04 2012-05-29 Texas Instruments Incorporated Micro-sequence based security model
US20080141268A1 (en) * 2006-12-12 2008-06-12 Tirumalai Partha P Utility function execution using scout threads
US8429623B2 (en) * 2007-01-16 2013-04-23 Oracle America Inc. Processing engine for enabling a set of code intended for a first platform to be executed on a second platform
US8468494B2 (en) * 2007-01-22 2013-06-18 Oracle Taleo Llc In-line editor
US7698534B2 (en) * 2007-02-21 2010-04-13 Arm Limited Reordering application code to improve processing performance
US7949848B2 (en) * 2007-03-08 2011-05-24 Arm Limited Data processing apparatus, method and computer program product for reducing memory usage of an object oriented program
US8805425B2 (en) 2007-06-01 2014-08-12 Seven Networks, Inc. Integrated messaging
US8693494B2 (en) 2007-06-01 2014-04-08 Seven Networks, Inc. Polling
US10452820B2 (en) * 2007-06-26 2019-10-22 International Business Machines Corporation Thread-based software license management
US20090031108A1 (en) * 2007-07-24 2009-01-29 Via Technologies Configurable fuse mechanism for implementing microcode patches
US20090031110A1 (en) * 2007-07-24 2009-01-29 Via Technologies Microcode patch expansion mechanism
US20090031109A1 (en) * 2007-07-24 2009-01-29 Via Technologies Apparatus and method for fast microcode patch from memory
US20090031121A1 (en) * 2007-07-24 2009-01-29 Via Technologies Apparatus and method for real-time microcode patch
US20090031107A1 (en) * 2007-07-24 2009-01-29 Via Technologies On-chip memory providing for microcode patch overlay and constant update functions
US20090031090A1 (en) * 2007-07-24 2009-01-29 Via Technologies Apparatus and method for fast one-to-many microcode patch
US20090031103A1 (en) * 2007-07-24 2009-01-29 Via Technologies Mechanism for implementing a microcode patch during fabrication
US7752424B2 (en) * 2007-08-08 2010-07-06 Arm Limited Null value checking instruction
US8453143B2 (en) 2007-09-19 2013-05-28 Vmware, Inc. Reducing the latency of virtual interrupt delivery in virtual machines
WO2009037668A2 (en) * 2007-09-19 2009-03-26 Kpit Cummins Infosystems Ltd. Mechanism to enable plug and play hardware components for semi-automatic software migration
US8336031B2 (en) * 2007-09-28 2012-12-18 Texas Instruments Incorporated Method and system of performing thread scheduling
US20090112570A1 (en) * 2007-10-26 2009-04-30 Microsoft Corporation Declarative model interpretation
US9798524B1 (en) * 2007-12-04 2017-10-24 Axway, Inc. System and method for exposing the dynamic web server-side
US8364181B2 (en) 2007-12-10 2013-01-29 Seven Networks, Inc. Electronic-mail filtering for mobile devices
US9002828B2 (en) 2007-12-13 2015-04-07 Seven Networks, Inc. Predictive content delivery
US8793305B2 (en) 2007-12-13 2014-07-29 Seven Networks, Inc. Content delivery to a mobile device from a content service
US8281109B2 (en) 2007-12-27 2012-10-02 Intel Corporation Compressed instruction format
US8291388B2 (en) 2008-01-09 2012-10-16 International Business Machines Corporation System, method and program for executing a debugger
US8107921B2 (en) 2008-01-11 2012-01-31 Seven Networks, Inc. Mobile virtual network operator
US20090182657A1 (en) 2008-01-15 2009-07-16 Omx Technology Ab Distributed ranking and matching of messages
DE102008005124A1 (en) * 2008-01-18 2009-07-23 Kuka Roboter Gmbh Computer system, control device for a machine, in particular for an industrial robot, and industrial robots
US8862657B2 (en) 2008-01-25 2014-10-14 Seven Networks, Inc. Policy based content service
US20090193338A1 (en) 2008-01-28 2009-07-30 Trevor Fiatal Reducing network and battery consumption during content delivery and playback
JP2009181558A (en) * 2008-02-01 2009-08-13 Panasonic Corp Program conversion device
US8356289B2 (en) * 2008-03-26 2013-01-15 Avaya Inc. Efficient encoding of instrumented data in real-time concurrent systems
US8205196B2 (en) * 2008-04-08 2012-06-19 Broadcom Corporation Systems and methods for using operating system (OS) virtualisation for minimizing power consumption in mobile phones
FR2930447B1 (en) * 2008-04-25 2010-07-30 Sod Conseils Rech Applic THERAPEUTIC USE OF AT LEAST ONE BOTULINUM NEUROTOXIN FOR THE TREATMENT OF PAIN IN THE CASE OF DIABETIC NEUROPATHY
US8677337B2 (en) * 2008-05-01 2014-03-18 Oracle America, Inc. Static profitability control for speculative automatic parallelization
US8359587B2 (en) * 2008-05-01 2013-01-22 Oracle America, Inc. Runtime profitability control for speculative automatic parallelization
US8739141B2 (en) * 2008-05-19 2014-05-27 Oracle America, Inc. Parallelizing non-countable loops with hardware transactional memory
US8140820B2 (en) * 2008-05-21 2012-03-20 Arm Limited Data processing apparatus and method for handling address translation for access requests issued by processing circuitry
US7870257B2 (en) * 2008-06-02 2011-01-11 International Business Machines Corporation Enhancing real-time performance for java application serving
US8787947B2 (en) 2008-06-18 2014-07-22 Seven Networks, Inc. Application discovery on mobile devices
WO2009153620A1 (en) * 2008-06-19 2009-12-23 Freescale Semiconductor, Inc. A system, method and computer program product for scheduling a processing entity task
US9058206B2 (en) * 2008-06-19 2015-06-16 Freescale emiconductor, Inc. System, method and program product for determining execution flow of the scheduler in response to setting a scheduler control variable by the debugger or by a processing entity
WO2009153621A1 (en) * 2008-06-19 2009-12-23 Freescale Semiconductor, Inc. A system, method and computer program product for scheduling processor entity tasks in a multiple-processing entity system
US8078158B2 (en) 2008-06-26 2011-12-13 Seven Networks, Inc. Provisioning applications for a mobile device
US9135054B1 (en) * 2008-07-16 2015-09-15 Apple Inc. Method and apparatus to migrate stacks for thread execution
US8823723B2 (en) * 2008-08-07 2014-09-02 Mitsubishi Electric Corporation Semiconductor integrated circuit device, facility appliance control device, and appliance state display apparatus
US8407678B2 (en) * 2008-08-27 2013-03-26 Red Hat, Inc. Method of array interception using data-flow analysis
US8276009B2 (en) 2008-09-05 2012-09-25 Broadcom Corporation Operating system (OS) virtualisation and processor utilization thresholds for minimizing power consumption in mobile phones
US9675443B2 (en) 2009-09-10 2017-06-13 Johnson & Johnson Vision Care, Inc. Energized ophthalmic lens including stacked integrated components
US8909759B2 (en) 2008-10-10 2014-12-09 Seven Networks, Inc. Bandwidth measurement
US8645923B1 (en) * 2008-10-31 2014-02-04 Symantec Corporation Enforcing expected control flow in program execution
US8612929B2 (en) * 2008-12-10 2013-12-17 Oracle America, Inc. Compiler implementation of lock/unlock using hardware transactional memory
US8806457B2 (en) * 2008-12-15 2014-08-12 Apple Inc. Deferred constant pool generation
US8528001B2 (en) * 2008-12-15 2013-09-03 Oracle America, Inc. Controlling and dynamically varying automatic parallelization
US7685586B1 (en) 2009-03-19 2010-03-23 International Business Machines Corporation Global escape analysis using instantiated type analysis
US7712093B1 (en) 2009-03-19 2010-05-04 International Business Machines Corporation Determining intra-procedural object flow using enhanced stackmaps
US8195923B2 (en) * 2009-04-07 2012-06-05 Oracle America, Inc. Methods and mechanisms to support multiple features for a number of opcodes
US7996595B2 (en) 2009-04-14 2011-08-09 Lstar Technologies Llc Interrupt arbitration for multiprocessors
US8260996B2 (en) * 2009-04-24 2012-09-04 Empire Technology Development Llc Interrupt optimization for multiprocessors
US8321614B2 (en) * 2009-04-24 2012-11-27 Empire Technology Development Llc Dynamic scheduling interrupt controller for multiprocessors
US8549404B2 (en) * 2009-04-30 2013-10-01 Apple Inc. Auditioning tools for a media editing application
DE102009019891B3 (en) * 2009-05-04 2010-11-25 Texas Instruments Deutschland Gmbh Microcontroller- or microprocessor unit for multiple current consumption modes, has register or memory, which contains bit fields for defining selected current consumption modes
US8458676B2 (en) * 2009-06-30 2013-06-04 International Business Machines Corporation Executing platform-independent code on multi-core heterogeneous processors
US8561046B2 (en) * 2009-09-14 2013-10-15 Oracle America, Inc. Pipelined parallelization with localized self-helper threading
US20110087861A1 (en) * 2009-10-12 2011-04-14 The Regents Of The University Of Michigan System for High-Efficiency Post-Silicon Verification of a Processor
US8234431B2 (en) * 2009-10-13 2012-07-31 Empire Technology Development Llc Interrupt masking for multi-core processors
KR101612780B1 (en) * 2009-11-13 2016-04-18 삼성전자주식회사 Computing system and method for controling memory of computing system
US20110131381A1 (en) * 2009-11-27 2011-06-02 Advanced Micro Devices, Inc. Cache scratch-pad and method therefor
US9009692B2 (en) * 2009-12-26 2015-04-14 Oracle America, Inc. Minimizing register spills by using register moves
US8578355B1 (en) * 2010-03-19 2013-11-05 Google Inc. Scenario based optimization
TW201209697A (en) 2010-03-30 2012-03-01 Michael Luna 3D mobile user interface with configurable workspace management
US8752058B1 (en) 2010-05-11 2014-06-10 Vmware, Inc. Implicit co-scheduling of CPUs
US20120005450A1 (en) * 2010-07-02 2012-01-05 International Business Machines Corporation User control of file data and metadata blocks
CA2857458A1 (en) 2010-07-26 2012-02-09 Michael Luna Mobile application traffic optimization
US9077630B2 (en) 2010-07-26 2015-07-07 Seven Networks, Inc. Distributed implementation of dynamic wireless traffic policy
US8838783B2 (en) 2010-07-26 2014-09-16 Seven Networks, Inc. Distributed caching for resource and mobile network traffic management
US9043433B2 (en) 2010-07-26 2015-05-26 Seven Networks, Inc. Mobile network traffic coordination across multiple applications
US20120030652A1 (en) * 2010-07-30 2012-02-02 Jakub Jelinek Mechanism for Describing Values of Optimized Away Parameters in a Compiler-Generated Debug Output
JP6034787B2 (en) 2010-08-27 2016-11-30 ノボマー, インコーポレイテッド Polymer compositions and methods
GB2499534B (en) 2010-11-01 2018-09-19 Seven Networks Llc Caching adapted for mobile application behavior and network conditions
US8843153B2 (en) 2010-11-01 2014-09-23 Seven Networks, Inc. Mobile traffic categorization and policy for network use optimization while preserving user experience
US9330196B2 (en) 2010-11-01 2016-05-03 Seven Networks, Llc Wireless traffic management system cache optimization using http headers
US8484314B2 (en) 2010-11-01 2013-07-09 Seven Networks, Inc. Distributed caching in a wireless network of content delivered for a mobile application over a long-held request
US9060032B2 (en) 2010-11-01 2015-06-16 Seven Networks, Inc. Selective data compression by a distributed traffic management system to reduce mobile data traffic and signaling traffic
WO2012061430A2 (en) 2010-11-01 2012-05-10 Michael Luna Distributed management of keep-alive message signaling for mobile network resource conservation and optimization
US8166164B1 (en) 2010-11-01 2012-04-24 Seven Networks, Inc. Application and network-based long poll request detection and cacheability assessment therefor
WO2012060995A2 (en) 2010-11-01 2012-05-10 Michael Luna Distributed caching in a wireless network of content delivered for a mobile application over a long-held request
US8190701B2 (en) 2010-11-01 2012-05-29 Seven Networks, Inc. Cache defeat detection and caching of content addressed by identifiers intended to defeat cache
TW201220048A (en) * 2010-11-05 2012-05-16 Realtek Semiconductor Corp for enhancing access efficiency of cache memory
CN103404193B (en) 2010-11-22 2018-06-05 七网络有限责任公司 The connection that adjustment data transmission is established with the transmission being optimized for through wireless network
GB2500327B (en) 2010-11-22 2019-11-06 Seven Networks Llc Optimization of resource polling intervals to satisfy mobile device requests
US9323551B2 (en) * 2011-01-07 2016-04-26 International Business Machines Corporation Modifying code sequence with replacement parts of which non-beginning parts trigger exception when jumped to
US9325662B2 (en) 2011-01-07 2016-04-26 Seven Networks, Llc System and method for reduction of mobile network traffic used for domain name system (DNS) queries
US8874888B1 (en) 2011-01-13 2014-10-28 Google Inc. Managed boot in a cloud system
US9135037B1 (en) 2011-01-13 2015-09-15 Google Inc. Virtual network protocol
US9405637B2 (en) * 2011-01-18 2016-08-02 Texas Instruments Incorporated Locking/unlocking CPUs to operate in safety mode or performance mode without rebooting
US8745329B2 (en) * 2011-01-20 2014-06-03 Google Inc. Storing data across a plurality of storage nodes
WO2012105174A1 (en) * 2011-01-31 2012-08-09 パナソニック株式会社 Program generation device, program generation method, processor device, and multiprocessor system
US8950862B2 (en) 2011-02-28 2015-02-10 Johnson & Johnson Vision Care, Inc. Methods and apparatus for an ophthalmic lens with functional insert layers
US9063818B1 (en) 2011-03-16 2015-06-23 Google Inc. Automated software updating based on prior activity
US9237087B1 (en) 2011-03-16 2016-01-12 Google Inc. Virtual machine name resolution
US8533796B1 (en) 2011-03-16 2013-09-10 Google Inc. Providing application programs with access to secured resources
US10451897B2 (en) 2011-03-18 2019-10-22 Johnson & Johnson Vision Care, Inc. Components with multiple energization elements for biomedical devices
US9110310B2 (en) 2011-03-18 2015-08-18 Johnson & Johnson Vision Care, Inc. Multiple energization elements in stacked integrated component devices
US9698129B2 (en) 2011-03-18 2017-07-04 Johnson & Johnson Vision Care, Inc. Stacked integrated component devices with energization
US9889615B2 (en) 2011-03-18 2018-02-13 Johnson & Johnson Vision Care, Inc. Stacked integrated component media insert for an ophthalmic device
US9804418B2 (en) 2011-03-21 2017-10-31 Johnson & Johnson Vision Care, Inc. Methods and apparatus for functional insert with power layer
WO2012129650A1 (en) * 2011-03-25 2012-10-04 Nanospeed Diagnostics Inc. Lateral flow immunoassay for detecting vitamins
US9053037B2 (en) 2011-04-04 2015-06-09 International Business Machines Corporation Allocating cache for use as a dedicated local storage
WO2012145541A2 (en) 2011-04-19 2012-10-26 Seven Networks, Inc. Social caching for device resource sharing and management
GB2505585B (en) 2011-04-27 2015-08-12 Seven Networks Inc Detecting and preserving state for satisfying application requests in a distributed proxy and cache system
CA2797631C (en) 2011-04-27 2013-11-19 Seven Networks, Inc. System and method for making requests on behalf of a mobile device based on atomic processes for mobile network traffic relief
US8984581B2 (en) 2011-07-27 2015-03-17 Seven Networks, Inc. Monitoring mobile application activities for malicious traffic on a mobile device
US20130089721A1 (en) 2011-08-02 2013-04-11 Tracy Paolilli Non-iridescent film with polymeric particles in primer layer
US9075979B1 (en) 2011-08-11 2015-07-07 Google Inc. Authentication based on proximity to mobile device
US8966198B1 (en) 2011-09-01 2015-02-24 Google Inc. Providing snapshots of virtual storage devices
US8934414B2 (en) 2011-12-06 2015-01-13 Seven Networks, Inc. Cellular or WiFi mobile traffic optimization based on public or private network destination
US8868753B2 (en) 2011-12-06 2014-10-21 Seven Networks, Inc. System of redundantly clustered machines to provide failover mechanisms for mobile traffic management and network resource conservation
US8958293B1 (en) 2011-12-06 2015-02-17 Google Inc. Transparent load-balancing for cloud computing services
US9009250B2 (en) 2011-12-07 2015-04-14 Seven Networks, Inc. Flexible and dynamic integration schemas of a traffic management system with various network operators for network traffic alleviation
WO2013086447A1 (en) 2011-12-07 2013-06-13 Seven Networks, Inc. Radio-awareness of mobile device for sending server-side control signals using a wireless network optimized transport protocol
US20130159511A1 (en) 2011-12-14 2013-06-20 Seven Networks, Inc. System and method for generating a report to a network operator by distributing aggregation of data
US9832095B2 (en) 2011-12-14 2017-11-28 Seven Networks, Llc Operation modes for mobile traffic optimization and concurrent management of optimized and non-optimized traffic
WO2013090821A1 (en) 2011-12-14 2013-06-20 Seven Networks, Inc. Hierarchies and categories for management and deployment of policies for distributed wireless traffic optimization
WO2013095337A1 (en) * 2011-12-19 2013-06-27 Intel Corporation A system and deterministic method for servicing msi interrupts using direct cache access
US8800009B1 (en) 2011-12-30 2014-08-05 Google Inc. Virtual machine service access
WO2013103988A1 (en) 2012-01-05 2013-07-11 Seven Networks, Inc. Detection and management of user interactions with foreground applications on a mobile device in distributed caching
US8857983B2 (en) 2012-01-26 2014-10-14 Johnson & Johnson Vision Care, Inc. Ophthalmic lens assembly having an integrated antenna structure
US8983860B1 (en) 2012-01-30 2015-03-17 Google Inc. Advertising auction system
US9203864B2 (en) 2012-02-02 2015-12-01 Seven Networks, Llc Dynamic categorization of applications for network access in a mobile network
WO2013116852A1 (en) 2012-02-03 2013-08-08 Seven Networks, Inc. User as an end point for profiling and optimizing the delivery of content and data in a wireless network
CN103294517B (en) 2012-02-22 2018-05-11 国际商业机器公司 Stack overflow protective device, stack protection method, dependent compilation device and computing device
US9483303B2 (en) * 2012-02-29 2016-11-01 Red Hat, Inc. Differential stack-based symmetric co-routines
US8677449B1 (en) 2012-03-19 2014-03-18 Google Inc. Exposing data to virtual machines
US9973335B2 (en) * 2012-03-28 2018-05-15 Intel Corporation Shared buffers for processing elements on a network device
US8812695B2 (en) 2012-04-09 2014-08-19 Seven Networks, Inc. Method and system for management of a virtual network connection without heartbeat messages
US20130268656A1 (en) 2012-04-10 2013-10-10 Seven Networks, Inc. Intelligent customer service/call center services enhanced using real-time and historical mobile application and traffic-related statistics collected by a distributed caching system in a mobile network
CN103377132B (en) * 2012-04-16 2016-02-10 群联电子股份有限公司 The method in diode-capacitor storage space, Memory Controller and memorizer memory devices
US9134980B1 (en) * 2012-05-01 2015-09-15 Amazon Technologies, Inc. Compiler optimization in a computing environment
WO2013165475A1 (en) * 2012-05-02 2013-11-07 Bedoukian Research, Inc. Killing of bed bugs
JP6050721B2 (en) * 2012-05-25 2016-12-21 株式会社半導体エネルギー研究所 Semiconductor device
US9367292B2 (en) * 2012-06-11 2016-06-14 Empire Technology Development Llc Modulating dynamic optimizations of a computer program
US8775631B2 (en) 2012-07-13 2014-07-08 Seven Networks, Inc. Dynamic bandwidth adjustment for browsing or streaming activity in a wireless network based on prediction of user behavior when interacting with mobile applications
US9161258B2 (en) 2012-10-24 2015-10-13 Seven Networks, Llc Optimized and selective management of policy deployment to mobile clients in a congested network to prevent further aggravation of network congestion
KR20140054948A (en) * 2012-10-30 2014-05-09 한국전자통신연구원 Tool composition for supporting opencl application software development for embedded system and method thereof
US9311243B2 (en) 2012-11-30 2016-04-12 Intel Corporation Emulated message signaled interrupts in multiprocessor systems
US10235208B2 (en) * 2012-12-11 2019-03-19 Nvidia Corporation Technique for saving and restoring thread group operating state
US9307493B2 (en) 2012-12-20 2016-04-05 Seven Networks, Llc Systems and methods for application management of mobile device radio state promotion and demotion
US8930920B2 (en) * 2012-12-31 2015-01-06 Oracle International Corporation Self-optimizing interpreter and snapshot compilation
US20140201416A1 (en) * 2013-01-17 2014-07-17 Xockets IP, LLC Offload processor modules for connection to system memory, and corresponding methods and systems
US9271238B2 (en) 2013-01-23 2016-02-23 Seven Networks, Llc Application or context aware fast dormancy
US8874761B2 (en) 2013-01-25 2014-10-28 Seven Networks, Inc. Signaling optimization in a wireless network for traffic utilizing proprietary and non-proprietary protocols
US8750123B1 (en) 2013-03-11 2014-06-10 Seven Networks, Inc. Mobile device equipped with mobile network congestion recognition to make intelligent decisions regarding connecting to an operator network
US9424165B2 (en) * 2013-03-14 2016-08-23 Applied Micro Circuits Corporation Debugging processor hang situations using an external pin
CN104079613B (en) * 2013-03-29 2018-04-13 国际商业机器公司 Method and system for sharing application program object between multi-tenant
US9065765B2 (en) 2013-07-22 2015-06-23 Seven Networks, Inc. Proxy server associated with a mobile carrier for enhancing mobile traffic management in a mobile network
CN103632099B (en) * 2013-09-29 2016-08-17 广州华多网络科技有限公司 The Native api function acquisition methods do not derived and device
GB2519103B (en) * 2013-10-09 2020-05-06 Advanced Risc Mach Ltd Decoding a complex program instruction corresponding to multiple micro-operations
US9539005B2 (en) 2013-11-08 2017-01-10 C.R. Bard, Inc. Surgical fastener deployment system
CN104679585B (en) * 2013-11-28 2017-10-24 中国航空工业集团公司第六三一研究所 Floating-point context switching method
CN104699627B (en) * 2013-12-06 2019-05-07 上海芯豪微电子有限公司 A kind of caching system and method
KR102219288B1 (en) 2013-12-09 2021-02-23 삼성전자 주식회사 Memory device supporting both cache and memory mode and operating method of the same
US9542211B2 (en) * 2014-03-26 2017-01-10 Intel Corporation Co-designed dynamic language accelerator for a processor
US9600286B2 (en) 2014-06-30 2017-03-21 International Business Machines Corporation Latent modification instruction for transactional execution
US9710271B2 (en) 2014-06-30 2017-07-18 International Business Machines Corporation Collecting transactional execution characteristics during transactional execution
US9348643B2 (en) 2014-06-30 2016-05-24 International Business Machines Corporation Prefetching of discontiguous storage locations as part of transactional execution
US9448939B2 (en) 2014-06-30 2016-09-20 International Business Machines Corporation Collecting memory operand access characteristics during transactional execution
US9336047B2 (en) 2014-06-30 2016-05-10 International Business Machines Corporation Prefetching of discontiguous storage locations in anticipation of transactional execution
US9715130B2 (en) 2014-08-21 2017-07-25 Johnson & Johnson Vision Care, Inc. Methods and apparatus to form separators for biocompatible energization elements for biomedical devices
US10361405B2 (en) 2014-08-21 2019-07-23 Johnson & Johnson Vision Care, Inc. Biomedical energization elements with polymer electrolytes
US10627651B2 (en) 2014-08-21 2020-04-21 Johnson & Johnson Vision Care, Inc. Methods and apparatus to form biocompatible energization primary elements for biomedical devices with electroless sealing layers
US9793536B2 (en) 2014-08-21 2017-10-17 Johnson & Johnson Vision Care, Inc. Pellet form cathode for use in a biocompatible battery
US9599842B2 (en) 2014-08-21 2017-03-21 Johnson & Johnson Vision Care, Inc. Device and methods for sealing and encapsulation for biocompatible energization elements
US10381687B2 (en) 2014-08-21 2019-08-13 Johnson & Johnson Vision Care, Inc. Methods of forming biocompatible rechargable energization elements for biomedical devices
US9383593B2 (en) 2014-08-21 2016-07-05 Johnson & Johnson Vision Care, Inc. Methods to form biocompatible energization elements for biomedical devices comprising laminates and placed separators
US9941547B2 (en) 2014-08-21 2018-04-10 Johnson & Johnson Vision Care, Inc. Biomedical energization elements with polymer electrolytes and cavity structures
US10361404B2 (en) 2014-08-21 2019-07-23 Johnson & Johnson Vision Care, Inc. Anodes for use in biocompatible energization elements
US9811464B2 (en) * 2014-12-11 2017-11-07 Intel Corporation Apparatus and method for considering spatial locality in loading data elements for execution
US20160357965A1 (en) * 2015-06-04 2016-12-08 Ut Battelle, Llc Automatic clustering of malware variants based on structured control flow
CN104965409B (en) * 2015-06-19 2017-06-09 北京甘为科技发展有限公司 A kind of industrial circulating water system energy consumption self-learning optimization control method
US10332775B2 (en) * 2015-07-15 2019-06-25 Chip Solutions, LLC Releasable carrier and method
US10417056B2 (en) 2015-08-04 2019-09-17 Oracle International Corporation Systems and methods for performing concurrency restriction and throttling over contended locks
US10158647B2 (en) * 2015-08-25 2018-12-18 Oracle International Corporation Permissive access control for modular reflection
US10503502B2 (en) 2015-09-25 2019-12-10 Intel Corporation Data element rearrangement, processors, methods, systems, and instructions
GB2543304B (en) * 2015-10-14 2020-10-28 Advanced Risc Mach Ltd Move prefix instruction
US10620957B2 (en) * 2015-10-22 2020-04-14 Texas Instruments Incorporated Method for forming constant extensions in the same execute packet in a VLIW processor
JP2017130527A (en) * 2016-01-19 2017-07-27 力祥半導體股▲フン▼有限公司UBIQ Semiconductor Corp. Semiconductor device
US10345620B2 (en) 2016-02-18 2019-07-09 Johnson & Johnson Vision Care, Inc. Methods and apparatus to form biocompatible energization elements incorporating fuel cells for biomedical devices
US10394528B2 (en) 2016-03-30 2019-08-27 Oracle International Corporation Returning a runtime type loaded from an archive in a module system
US10191753B2 (en) 2016-03-30 2019-01-29 Oracle International Corporation Generating verification metadata and verifying a runtime type based on verification metadata
US20170300521A1 (en) * 2016-04-18 2017-10-19 Sap Se Concurrent accessing and processing of data during upgrade
US10387142B2 (en) 2016-09-16 2019-08-20 Oracle International Corporation Using annotation processors defined by modules with annotation processors defined by non-module code
US10360008B2 (en) 2016-09-16 2019-07-23 Oracle International Corporation Metadata application constraints within a module system based on modular encapsulation
US10262208B2 (en) * 2016-09-23 2019-04-16 Microsoft Technology Licensing, Llc Automatic selection of cinemagraphs
US10327200B2 (en) 2016-09-28 2019-06-18 Intel Corporation Communication network management system and method
US10565024B2 (en) * 2016-10-19 2020-02-18 Oracle International Corporation Generic concurrency restriction
KR20180071463A (en) * 2016-12-19 2018-06-28 삼성전자주식회사 Semiconductor memory device
US10114795B2 (en) * 2016-12-30 2018-10-30 Western Digital Technologies, Inc. Processor in non-volatile storage memory
US10891326B2 (en) * 2017-01-05 2021-01-12 International Business Machines Corporation Representation of a data analysis using a flow graph
US10318250B1 (en) * 2017-03-17 2019-06-11 Symantec Corporation Systems and methods for locating functions for later interception
US10848410B2 (en) 2017-03-29 2020-11-24 Oracle International Corporation Ranking service implementations for a service interface
US10564977B2 (en) 2017-04-18 2020-02-18 International Business Machines Corporation Selective register allocation
US10838733B2 (en) 2017-04-18 2020-11-17 International Business Machines Corporation Register context restoration based on rename register recovery
US11010192B2 (en) 2017-04-18 2021-05-18 International Business Machines Corporation Register restoration using recovery buffers
US10552164B2 (en) 2017-04-18 2020-02-04 International Business Machines Corporation Sharing snapshots between restoration and recovery
US10545766B2 (en) 2017-04-18 2020-01-28 International Business Machines Corporation Register restoration using transactional memory register snapshots
US10572265B2 (en) 2017-04-18 2020-02-25 International Business Machines Corporation Selecting register restoration or register reloading
US10963261B2 (en) 2017-04-18 2021-03-30 International Business Machines Corporation Sharing snapshots across save requests
US10782979B2 (en) 2017-04-18 2020-09-22 International Business Machines Corporation Restoring saved architected registers and suppressing verification of registers to be restored
US10740108B2 (en) 2017-04-18 2020-08-11 International Business Machines Corporation Management of store queue based on restoration operation
US10540184B2 (en) 2017-04-18 2020-01-21 International Business Machines Corporation Coalescing store instructions for restoration
US10649785B2 (en) 2017-04-18 2020-05-12 International Business Machines Corporation Tracking changes to memory via check and recovery
US10489382B2 (en) * 2017-04-18 2019-11-26 International Business Machines Corporation Register restoration invalidation based on a context switch
US10388039B2 (en) 2017-05-31 2019-08-20 International Business Machines Corporation Accelerating data-driven scientific discovery
CA3073525C (en) * 2017-08-24 2022-07-05 Lutron Technology Company Llc Stack safety for independently defined operations
US10497774B2 (en) * 2017-10-23 2019-12-03 Blackberry Limited Small-gap coplanar tunable capacitors and methods for manufacturing thereof
CN111295279B (en) * 2017-11-06 2022-01-11 本田技研工业株式会社 Resin molded product unit and method for molding resin molded product unit
US10698686B2 (en) * 2017-11-14 2020-06-30 International Business Machines Corporation Configurable architectural placement control
US10592164B2 (en) 2017-11-14 2020-03-17 International Business Machines Corporation Portions of configuration state registers in-memory
US10901738B2 (en) 2017-11-14 2021-01-26 International Business Machines Corporation Bulk store and load operations of configuration state registers
US10664181B2 (en) 2017-11-14 2020-05-26 International Business Machines Corporation Protecting in-memory configuration state registers
US10496437B2 (en) 2017-11-14 2019-12-03 International Business Machines Corporation Context switch by changing memory pointers
US10552070B2 (en) * 2017-11-14 2020-02-04 International Business Machines Corporation Separation of memory-based configuration state registers based on groups
US10642757B2 (en) 2017-11-14 2020-05-05 International Business Machines Corporation Single call to perform pin and unpin operations
US10558366B2 (en) 2017-11-14 2020-02-11 International Business Machines Corporation Automatic pinning of units of memory
US10761751B2 (en) 2017-11-14 2020-09-01 International Business Machines Corporation Configuration state registers grouped based on functional affinity
US10635602B2 (en) * 2017-11-14 2020-04-28 International Business Machines Corporation Address translation prior to receiving a storage reference using the address to be translated
US10761983B2 (en) * 2017-11-14 2020-09-01 International Business Machines Corporation Memory based configuration state registers
US11416251B2 (en) * 2017-11-16 2022-08-16 Arm Limited Apparatus for storing, reading and modifying constant values
US20190163492A1 (en) * 2017-11-28 2019-05-30 International Business Machines Corporation Employing a stack accelerator for stack-type accesses
US10613842B2 (en) * 2018-04-30 2020-04-07 International Business Machines Corporation Simplifying a control flow graph based on profiling data
US11106463B2 (en) 2019-05-24 2021-08-31 Texas Instruments Incorporated System and method for addressing data in memory
US11080227B2 (en) * 2019-08-08 2021-08-03 SambaNova Systems, Inc. Compiler flow logic for reconfigurable architectures
JP2021166010A (en) * 2020-04-08 2021-10-14 富士通株式会社 Operation processing device
CN115668142A (en) * 2020-05-30 2023-01-31 华为技术有限公司 Processor, processing method and related equipment
CN115421864B (en) * 2022-09-14 2023-04-28 北京计算机技术及应用研究所 Universal PowerPC architecture processor instruction set virtualization simulation method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4398243A (en) * 1980-04-25 1983-08-09 Data General Corporation Data processing system having a unique instruction processor system
US6217234B1 (en) * 1994-07-29 2001-04-17 Discovision Associates Apparatus and method for processing data with an arithmetic unit
US20030105945A1 (en) * 2001-11-01 2003-06-05 Bops, Inc. Methods and apparatus for a bit rake instruction
US20040015533A1 (en) * 1995-08-16 2004-01-22 Microunity Systems Engineering, Inc. Multiplier array processing system with enhanced utilization at lower precision
US20040158689A1 (en) * 1995-08-16 2004-08-12 Microunity Systems Engineering, Inc. System and software for matched aligned and unaligned storage instructions
US20060129723A1 (en) * 2004-12-15 2006-06-15 Microsoft Corporation Retry strategies for use in a streaming environment
US7171543B1 (en) * 2000-03-28 2007-01-30 Intel Corp. Method and apparatus for executing a 32-bit application by confining the application to a 32-bit address space subset in a 64-bit processor

Family Cites Families (273)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4080650A (en) * 1976-07-28 1978-03-21 Bell Telephone Laboratories, Incorporated Facilitating return from an on-line debugging program to a target program breakpoint
US4258419A (en) * 1978-12-29 1981-03-24 Bell Telephone Laboratories, Incorporated Data processing apparatus providing variable operand width operation
US4484271A (en) 1979-01-31 1984-11-20 Honeywell Information Systems Inc. Microprogrammed system having hardware interrupt apparatus
US4312034A (en) 1979-05-21 1982-01-19 Motorola, Inc. ALU and Condition code control unit for data processor
US4268419A (en) * 1979-11-16 1981-05-19 Uop Inc. Support matrices for immobilized enzymes
US4598365A (en) * 1983-04-01 1986-07-01 Honeywell Information Systems Inc. Pipelined decimal character execution unit
US4729094A (en) * 1983-04-18 1988-03-01 Motorola, Inc. Method and apparatus for coordinating execution of an instruction by a coprocessor
US5021991A (en) * 1983-04-18 1991-06-04 Motorola, Inc. Coprocessor instruction format
JPH0827716B2 (en) * 1985-10-25 1996-03-21 株式会社日立製作所 Data processing device and data processing method
US5155807A (en) * 1986-02-24 1992-10-13 International Business Machines Corporation Multi-processor communications channel utilizing random access/sequential access memories
JPS62221732A (en) * 1986-03-24 1987-09-29 Nec Corp Register saving and recovery system
US4821183A (en) * 1986-12-04 1989-04-11 International Business Machines Corporation A microsequencer circuit with plural microprogrom instruction counters
US5142628A (en) * 1986-12-26 1992-08-25 Hitachi, Ltd. Microcomputer system for communication
US5119484A (en) * 1987-02-24 1992-06-02 Digital Equipment Corporation Selections between alternate control word and current instruction generated control word for alu in respond to alu output and current instruction
US5099417A (en) * 1987-03-13 1992-03-24 Texas Instruments Incorporated Data processing device with improved direct memory access
US5142677A (en) * 1989-05-04 1992-08-25 Texas Instruments Incorporated Context switching devices, systems and methods
US5822578A (en) * 1987-12-22 1998-10-13 Sun Microsystems, Inc. System for inserting instructions into processor instruction stream in order to perform interrupt processing
JPH0652521B2 (en) * 1988-11-30 1994-07-06 株式会社日立製作所 Information processing system
US5313614A (en) * 1988-12-06 1994-05-17 At&T Bell Laboratories Method and apparatus for direct conversion of programs in object code form between different hardware architecture computer systems
JP3063006B2 (en) * 1989-02-08 2000-07-12 インテル・コーポレーション Microprogrammed computer device and method for addressing microcode sequence memory
US5167028A (en) * 1989-11-13 1992-11-24 Lucid Corporation System for controlling task operation of slave processor by switching access to shared memory banks by master processor
US5390329A (en) * 1990-06-11 1995-02-14 Cray Research, Inc. Responding to service requests using minimal system-side context in a multiprocessor environment
US5522072A (en) * 1990-09-04 1996-05-28 At&T Corp. Arrangement for efficiently transferring program execution between subprograms
US5390304A (en) * 1990-09-28 1995-02-14 Texas Instruments, Incorporated Method and apparatus for processing block instructions in a data processor
US5826101A (en) * 1990-09-28 1998-10-20 Texas Instruments Incorporated Data processing device having split-mode DMA channel
US5276835A (en) * 1990-12-14 1994-01-04 International Business Machines Corporation Non-blocking serialization for caching data in a shared cache
US5537574A (en) * 1990-12-14 1996-07-16 International Business Machines Corporation Sysplex shared data coherency method
US5410710A (en) * 1990-12-21 1995-04-25 Intel Corporation Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems
US5613128A (en) * 1990-12-21 1997-03-18 Intel Corporation Programmable multi-processor interrupt controller system with a processor integrated local interrupt controller
US5507030A (en) * 1991-03-07 1996-04-09 Digitial Equipment Corporation Successive translation, execution and interpretation of computer program having code at unknown locations due to execution transfer instructions having computed destination addresses
CA2109799A1 (en) * 1991-05-24 1992-12-10 Daniel Mark Nosenchuck Optimizing compiler for computers
CA2067576C (en) * 1991-07-10 1998-04-14 Jimmie D. Edrington Dynamic load balancing for a multiprocessor pipeline
US5355483A (en) * 1991-07-18 1994-10-11 Next Computers Asynchronous garbage collection
US5274815A (en) * 1991-11-01 1993-12-28 Motorola, Inc. Dynamic instruction modifying controller and operation method
US5187644A (en) * 1991-11-14 1993-02-16 Compaq Computer Corporation Compact portable computer having an expandable full size keyboard with extendable supports
EP0551531A1 (en) * 1991-12-20 1993-07-21 International Business Machines Corporation Apparatus for executing ADD/SUB operations between IEEE standard floating-point numbers
US5309567A (en) * 1992-01-24 1994-05-03 C-Cube Microsystems Structure and method for an asynchronous communication protocol between master and slave processors
US5257215A (en) * 1992-03-31 1993-10-26 Intel Corporation Floating point and integer number conversions in a floating point adder
JP2786574B2 (en) * 1992-05-06 1998-08-13 インターナショナル・ビジネス・マシーンズ・コーポレイション Method and apparatus for improving the performance of out-of-order load operations in a computer system
US5272660A (en) * 1992-06-01 1993-12-21 Motorola, Inc. Method and apparatus for performing integer and floating point division using a single SRT divider in a data processor
EP0648404B1 (en) * 1992-06-29 1998-11-25 Elonex Technologies, Inc. Modular notebook computer
US5426783A (en) 1992-11-02 1995-06-20 Amdahl Corporation System for processing eight bytes or less by the move, pack and unpack instruction of the ESA/390 instruction set
US5384722A (en) * 1993-03-10 1995-01-24 Intel Corporation Apparatus and method for determining the Manhattan distance between two points
US5825921A (en) * 1993-03-19 1998-10-20 Intel Corporation Memory transfer apparatus and method useful within a pattern recognition system
US5459798A (en) * 1993-03-19 1995-10-17 Intel Corporation System and method of pattern recognition employing a multiprocessing pipelined apparatus with private pattern memory
DE69427265T2 (en) * 1993-10-29 2002-05-02 Advanced Micro Devices Inc Superskalarbefehlsdekoder
US5781750A (en) 1994-01-11 1998-07-14 Exponential Technology, Inc. Dual-instruction-set architecture CPU with hidden software emulation mode
US5490272A (en) * 1994-01-28 1996-02-06 International Business Machines Corporation Method and apparatus for creating multithreaded time slices in a multitasking operating system
JPH07281890A (en) * 1994-04-06 1995-10-27 Mitsubishi Electric Corp Instruction set and its executing method by microcomputer
GB2289353B (en) 1994-05-03 1997-08-27 Advanced Risc Mach Ltd Data processing with multiple instruction sets
JP3619939B2 (en) * 1994-09-26 2005-02-16 株式会社ルネサステクノロジ Central processing unit
US5634046A (en) * 1994-09-30 1997-05-27 Microsoft Corporation General purpose use of a stack pointer register
US5634076A (en) * 1994-10-04 1997-05-27 Analog Devices, Inc. DMA controller responsive to transition of a request signal between first state and second state and maintaining of second state for controlling data transfer
JP3494489B2 (en) * 1994-11-30 2004-02-09 株式会社ルネサステクノロジ Instruction processing unit
BR9509845A (en) * 1994-12-02 1997-12-30 Intel Corp Microprocessor with compacting operation of composite operating elements
US5560013A (en) * 1994-12-06 1996-09-24 International Business Machines Corporation Method of using a target processor to execute programs of a source architecture that uses multiple address spaces
US5613162A (en) * 1995-01-04 1997-03-18 Ast Research, Inc. Method and apparatus for performing efficient direct memory access data transfers
US5638525A (en) 1995-02-10 1997-06-10 Intel Corporation Processor capable of executing programs that contain RISC and CISC instructions
US5708815A (en) * 1995-05-05 1998-01-13 Intel Corporation DMA emulation via interrupt muxing
JP3218932B2 (en) * 1995-07-06 2001-10-15 株式会社日立製作所 Data prefetch code generation method
US5933847A (en) * 1995-09-28 1999-08-03 Canon Kabushiki Kaisha Selecting erase method based on type of power supply for flash EEPROM
US5774737A (en) * 1995-10-13 1998-06-30 Matsushita Electric Industrial Co., Ltd. Variable word length very long instruction word instruction processor with word length register or instruction number register
US6035123A (en) * 1995-11-08 2000-03-07 Digital Equipment Corporation Determining hardware complexity of software operations
US5727227A (en) * 1995-11-20 1998-03-10 Advanced Micro Devices Interrupt coprocessor configured to process interrupts in a computer system
US5850558A (en) * 1995-12-19 1998-12-15 Advanced Micro Devices System and method for referencing interrupt request information in a programmable interrupt controller
US5850555A (en) * 1995-12-19 1998-12-15 Advanced Micro Devices, Inc. System and method for validating interrupts before presentation to a CPU
US5894578A (en) * 1995-12-19 1999-04-13 Advanced Micro Devices, Inc. System and method for using random access memory in a programmable interrupt controller
US5892956A (en) * 1995-12-19 1999-04-06 Advanced Micro Devices, Inc. Serial bus for transmitting interrupt information in a multiprocessing system
US5727217A (en) * 1995-12-20 1998-03-10 Intel Corporation Circuit and method for emulating the functionality of an advanced programmable interrupt controller
WO1997027544A1 (en) * 1996-01-24 1997-07-31 Sun Microsystems, Inc. Processor with accelerated array access bounds checking
US6038643A (en) * 1996-01-24 2000-03-14 Sun Microsystems, Inc. Stack management unit and method for a processor having a stack
US6125439A (en) * 1996-01-24 2000-09-26 Sun Microsystems, Inc. Process of executing a method on a stack-based processor
US5842017A (en) * 1996-01-29 1998-11-24 Digital Equipment Corporation Method and apparatus for forming a translation unit
JPH09212371A (en) * 1996-02-07 1997-08-15 Nec Corp Register saving and restoring system
US5761515A (en) * 1996-03-14 1998-06-02 International Business Machines Corporation Branch on cache hit/miss for compiler-assisted miss delay tolerance
US5983313A (en) * 1996-04-10 1999-11-09 Ramtron International Corporation EDRAM having a dynamically-sized cache memory and associated method
US5923877A (en) * 1996-05-01 1999-07-13 Electronic Data Systems Corporation Object-oriented programming memory management framework and method
US5889999A (en) 1996-05-15 1999-03-30 Motorola, Inc. Method and apparatus for sequencing computer instruction execution in a data processing system
US5778236A (en) * 1996-05-17 1998-07-07 Advanced Micro Devices, Inc. Multiprocessing interrupt controller on I/O bus
US5754884A (en) * 1996-05-20 1998-05-19 Advanced Micro Devices Method for improving the real-time functionality of a personal computer which employs an interrupt servicing DMA controller
US6711667B1 (en) * 1996-06-28 2004-03-23 Legerity, Inc. Microprocessor configured to translate instructions from one instruction set to another, and to store the translated instructions
WO1998006030A1 (en) * 1996-08-07 1998-02-12 Sun Microsystems Multifunctional execution unit
US6061711A (en) * 1996-08-19 2000-05-09 Samsung Electronics, Inc. Efficient context saving and restoring in a multi-tasking computing system environment
US5909578A (en) * 1996-09-30 1999-06-01 Hewlett-Packard Company Use of dynamic translation to burst profile computer applications
US6438573B1 (en) * 1996-10-09 2002-08-20 Iowa State University Research Foundation, Inc. Real-time programming method
US5937193A (en) * 1996-11-27 1999-08-10 Vlsi Technology, Inc. Circuit arrangement for translating platform-independent instructions for execution on a hardware platform and method thereof
US6052699A (en) * 1996-12-11 2000-04-18 Lucent Technologies Inc. Garbage collection without fine-grain synchronization
US5796972A (en) 1997-01-14 1998-08-18 Unisys Corporation Method and apparatus for performing microcode paging during instruction execution in an instruction processor
US5898850A (en) * 1997-03-31 1999-04-27 International Business Machines Corporation Method and system for executing a non-native mode-sensitive instruction within a computer system
US6167488A (en) * 1997-03-31 2000-12-26 Sun Microsystems, Inc. Stack caching circuit with overflow/underflow unit
US6003038A (en) * 1997-03-31 1999-12-14 Sun Microsystems, Inc. Object-oriented processor architecture and operating method
US5875336A (en) 1997-03-31 1999-02-23 International Business Machines Corporation Method and system for translating a non-native bytecode to a set of codes native to a processor within a computer system
US6049810A (en) * 1997-04-23 2000-04-11 Sun Microsystems, Inc. Method and apparatus for implementing a write barrier of a garbage collected heap
US6199075B1 (en) * 1997-05-30 2001-03-06 Sun Microsystems, Inc. Method and apparatus for generational garbage collection of a heap memory shared by multiple processors
US5983337A (en) 1997-06-12 1999-11-09 Advanced Micro Devices, Inc. Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction
US6006321A (en) * 1997-06-13 1999-12-21 Malleable Technologies, Inc. Programmable logic datapath that may be used in a field programmable device
US5892966A (en) 1997-06-27 1999-04-06 Sun Microsystems, Inc. Processor complex for executing multimedia functions
US6321323B1 (en) 1997-06-27 2001-11-20 Sun Microsystems, Inc. System and method for executing platform-independent code on a co-processor
US6240440B1 (en) * 1997-06-30 2001-05-29 Sun Microsystems Incorporated Method and apparatus for implementing virtual threads
US6513156B2 (en) * 1997-06-30 2003-01-28 Sun Microsystems, Inc. Interpreting functions utilizing a hybrid of virtual and native machine instructions
US6078744A (en) 1997-08-01 2000-06-20 Sun Microsystems Method and apparatus for improving compiler performance during subsequent compilations of a source program
US6366876B1 (en) 1997-09-29 2002-04-02 Sun Microsystems, Inc. Method and apparatus for assessing compatibility between platforms and applications
US6006301A (en) * 1997-09-30 1999-12-21 Intel Corporation Multi-delivery scheme interrupt router
US6233733B1 (en) 1997-09-30 2001-05-15 Sun Microsystems, Inc. Method for generating a Java bytecode data flow graph
JP3816961B2 (en) * 1997-10-02 2006-08-30 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Data processing apparatus for processing virtual machine instructions
US6085208A (en) * 1997-10-23 2000-07-04 Advanced Micro Devices, Inc. Leading one prediction unit for normalizing close path subtraction results within a floating point arithmetic unit
US6061770A (en) * 1997-11-04 2000-05-09 Adaptec, Inc. System and method for real-time data backup using snapshot copying with selective compaction of backup data
US6341342B1 (en) * 1997-11-04 2002-01-22 Compaq Information Technologies Group, L.P. Method and apparatus for zeroing a transfer buffer memory as a background task
US6021484A (en) 1997-11-14 2000-02-01 Samsung Electronics Co., Ltd. Dual instruction set architecture
US6862650B1 (en) * 1997-11-14 2005-03-01 International Business Machines Corporation Data processing system and method for managing memory of an interpretive system
US6066181A (en) 1997-12-08 2000-05-23 Analysis & Technology, Inc. Java native interface code generator
US6009261A (en) * 1997-12-16 1999-12-28 International Business Machines Corporation Preprocessing of stored target routines for emulating incompatible instructions on a target processor
US6081665A (en) * 1997-12-19 2000-06-27 Newmonics Inc. Method for efficient soft real-time execution of portable byte code computer programs
US6192368B1 (en) * 1998-02-11 2001-02-20 International Business Machines Corporation Apparatus and method for automatically propagating a change made to at least one of a plurality of objects to at least one data structure containing data relating to the plurality of objects
US5999732A (en) * 1998-03-23 1999-12-07 Sun Microsystems, Inc. Techniques for reducing the cost of dynamic class initialization checks in compiled code
US6594708B1 (en) * 1998-03-26 2003-07-15 Sun Microsystems, Inc. Apparatus and method for object-oriented memory system
US6052739A (en) * 1998-03-26 2000-04-18 Sun Microsystems, Inc. Method and apparatus for object-oriented interrupt system
US6374286B1 (en) * 1998-04-06 2002-04-16 Rockwell Collins, Inc. Real time processor capable of concurrently running multiple independent JAVA machines
US6915307B1 (en) * 1998-04-15 2005-07-05 Inktomi Corporation High performance object cache
US6115777A (en) * 1998-04-21 2000-09-05 Idea Corporation LOADRS instruction and asynchronous context switch
US6275903B1 (en) * 1998-04-22 2001-08-14 Sun Microsystems, Inc. Stack cache miss handling
US6192442B1 (en) * 1998-04-29 2001-02-20 Intel Corporation Interrupt controller
US6075942A (en) * 1998-05-04 2000-06-13 Sun Microsystems, Inc. Encoding machine-specific optimization in generic byte code by using local variables as pseudo-registers
US6148316A (en) * 1998-05-05 2000-11-14 Mentor Graphics Corporation Floating point unit equipped also to perform integer addition as well as floating point to integer conversion
US6397242B1 (en) * 1998-05-15 2002-05-28 Vmware, Inc. Virtualization system including a virtual machine monitor for a computer with a segmented architecture
US6480952B2 (en) 1998-05-26 2002-11-12 Advanced Micro Devices, Inc. Emulation coprocessor
US6745384B1 (en) 1998-05-29 2004-06-01 Microsoft Corporation Anticipatory optimization with composite folding
US6205540B1 (en) 1998-06-19 2001-03-20 Franklin Electronic Publishers Incorporated Processor with enhanced instruction set
US6219678B1 (en) * 1998-06-25 2001-04-17 Sun Microsystems, Inc. System and method for maintaining an association for an object
US6202147B1 (en) * 1998-06-29 2001-03-13 Sun Microsystems, Inc. Platform-independent device drivers
EP0969377B1 (en) * 1998-06-30 2009-01-07 International Business Machines Corporation Method of replication-based garbage collection in a multiprocessor system
US6854113B1 (en) * 1998-08-28 2005-02-08 Borland Software Corporation Mixed-mode execution for object-oriented programming languages
US6008621A (en) * 1998-10-15 1999-12-28 Electronic Classroom Furniture Systems Portable computer charging system and storage cart
US20020108025A1 (en) 1998-10-21 2002-08-08 Nicholas Shaylor Memory management unit for java environment computers
US6684323B2 (en) * 1998-10-27 2004-01-27 Stmicroelectronics, Inc. Virtual condition codes
US6519594B1 (en) * 1998-11-14 2003-02-11 Sony Electronics, Inc. Computer-implemented sharing of java classes for increased memory efficiency and communication method
GB9825102D0 (en) * 1998-11-16 1999-01-13 Insignia Solutions Plc Computer system
US6115719A (en) * 1998-11-20 2000-09-05 Revsoft Corporation Java compatible object oriented component data structure
US6530075B1 (en) * 1998-12-03 2003-03-04 International Business Machines Corporation JIT/compiler Java language extensions to enable field performance and serviceability
US6718457B2 (en) * 1998-12-03 2004-04-06 Sun Microsystems, Inc. Multiple-thread processor for threaded software applications
US20020073398A1 (en) * 1998-12-14 2002-06-13 Jeffrey L. Tinker Method and system for modifying executable code to add additional functionality
US7013456B1 (en) * 1999-01-28 2006-03-14 Ati International Srl Profiling execution of computer programs
US7275246B1 (en) * 1999-01-28 2007-09-25 Ati International Srl Executing programs for a first computer architecture on a computer of a second architecture
US6954923B1 (en) * 1999-01-28 2005-10-11 Ati International Srl Recording classification of instructions executed by a computer
US7065633B1 (en) * 1999-01-28 2006-06-20 Ati International Srl System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU
US7111290B1 (en) * 1999-01-28 2006-09-19 Ati International Srl Profiling program execution to identify frequently-executed portions and to assist binary translation
US6412109B1 (en) 1999-01-29 2002-06-25 Sun Microsystems, Inc. Method for optimizing java bytecodes in the presence of try-catch blocks
US6385764B1 (en) * 1999-01-29 2002-05-07 International Business Machines Corporation Method and apparatus for improving invocation speed of Java methods
US6848111B1 (en) * 1999-02-02 2005-01-25 Sun Microsystems, Inc. Zero overhead exception handling
US6260157B1 (en) 1999-02-16 2001-07-10 Kurt Schurecht Patching of a read only memory
US6738846B1 (en) * 1999-02-23 2004-05-18 Sun Microsystems, Inc. Cooperative processing of tasks in a multi-threaded computing system
US6308253B1 (en) * 1999-03-31 2001-10-23 Sony Corporation RISC CPU instructions particularly suited for decoding digital signal processing applications
US6412029B1 (en) * 1999-04-29 2002-06-25 Agere Systems Guardian Corp. Method and apparatus for interfacing between a digital signal processor and a baseband circuit for wireless communication system
US6412108B1 (en) * 1999-05-06 2002-06-25 International Business Machines Corporation Method and apparatus for speeding up java methods prior to a first execution
US6510493B1 (en) * 1999-07-15 2003-01-21 International Business Machines Corporation Method and apparatus for managing cache line replacement within a computer system
US6535958B1 (en) * 1999-07-15 2003-03-18 Texas Instruments Incorporated Multilevel cache system coherence with memory selectively configured as cache or direct access memory and direct memory access
US6510352B1 (en) * 1999-07-29 2003-01-21 The Foxboro Company Methods and apparatus for object-based process control
US6341318B1 (en) * 1999-08-10 2002-01-22 Chameleon Systems, Inc. DMA data streaming
US7000222B1 (en) * 1999-08-19 2006-02-14 International Business Machines Corporation Method, system, and program for accessing variables from an operating system for use by an application program
US6507947B1 (en) * 1999-08-20 2003-01-14 Hewlett-Packard Company Programmatic synthesis of processor element arrays
US6418540B1 (en) * 1999-08-27 2002-07-09 Lucent Technologies Inc. State transfer with throw-away thread
US6549959B1 (en) * 1999-08-30 2003-04-15 Ati International Srl Detecting modification to computer memory by a DMA device
US6671707B1 (en) * 1999-10-19 2003-12-30 Intel Corporation Method for practical concurrent copying garbage collection offering minimal thread block times
US6418489B1 (en) * 1999-10-25 2002-07-09 Motorola, Inc. Direct memory access controller and method therefor
SE514318C2 (en) * 1999-10-28 2001-02-12 Appeal Virtual Machines Ab Process for streamlining a data processing process using a virtual machine and using a garbage collection procedure
US6711739B1 (en) * 1999-11-08 2004-03-23 Sun Microsystems, Inc. System and method for handling threads of execution
US6477666B1 (en) * 1999-11-22 2002-11-05 International Business Machines Corporation Automatic fault injection into a JAVA virtual machine (JVM)
EP1111511B1 (en) * 1999-12-06 2017-09-27 Texas Instruments France Cache with multiple fill modes
EP1107123B1 (en) * 1999-12-06 2007-11-21 Texas Instruments France Smart cache
US6668287B1 (en) * 1999-12-15 2003-12-23 Transmeta Corporation Software direct memory access
US6691308B1 (en) 1999-12-30 2004-02-10 Stmicroelectronics, Inc. Method and apparatus for changing microcode to be executed in a processor
US6986128B2 (en) * 2000-01-07 2006-01-10 Sony Computer Entertainment Inc. Multiple stage program recompiler and method
JP2001243079A (en) * 2000-03-02 2001-09-07 Omron Corp Information processing system
US6618737B2 (en) * 2000-03-09 2003-09-09 International Business Machines Corporation Speculative caching of individual fields in a distributed object system
US7093102B1 (en) * 2000-03-29 2006-08-15 Intel Corporation Code sequence for vector gather and scatter
US7086066B2 (en) * 2000-03-31 2006-08-01 Schlumbergersema Telekom Gmbh & Co. Kg System and method for exception handling
US6408383B1 (en) * 2000-05-04 2002-06-18 Sun Microsystems, Inc. Array access boundary check by executing BNDCHK instruction with comparison specifiers
US20020099902A1 (en) * 2000-05-12 2002-07-25 Guillaume Comeau Methods and systems for applications to interact with hardware
US7159223B1 (en) * 2000-05-12 2007-01-02 Zw Company, Llc Methods and systems for applications to interact with hardware
US7020766B1 (en) * 2000-05-30 2006-03-28 Intel Corporation Processing essential and non-essential code separately
US20020099863A1 (en) * 2000-06-02 2002-07-25 Guillaume Comeau Software support layer for processors executing interpreted language applications
US6735687B1 (en) * 2000-06-15 2004-05-11 Hewlett-Packard Development Company, L.P. Multithreaded microprocessor with asymmetrical central processing units
US7093239B1 (en) * 2000-07-14 2006-08-15 Internet Security Systems, Inc. Computer immune system and method for detecting unwanted code in a computer system
US6662359B1 (en) * 2000-07-20 2003-12-09 International Business Machines Corporation System and method for injecting hooks into Java classes to handle exception and finalization processing
US6704860B1 (en) 2000-07-26 2004-03-09 International Business Machines Corporation Data processing system and method for fetching instruction blocks in response to a detected block sequence
EP1182565B1 (en) * 2000-08-21 2012-09-05 Texas Instruments France Cache and DMA with a global valid bit
US6816921B2 (en) * 2000-09-08 2004-11-09 Texas Instruments Incorporated Micro-controller direct memory access (DMA) operation with adjustable word size transfers and address alignment/incrementing
US7000227B1 (en) 2000-09-29 2006-02-14 Intel Corporation Iterative optimizing compiler
GB2367653B (en) * 2000-10-05 2004-10-20 Advanced Risc Mach Ltd Restarting translated instructions
US6684232B1 (en) * 2000-10-26 2004-01-27 International Business Machines Corporation Method and predictor for streamlining execution of convert-to-integer operations
GB0027053D0 (en) * 2000-11-06 2000-12-20 Ibm A computer system with two heaps in contiguous storage
US6993754B2 (en) * 2001-11-13 2006-01-31 Hewlett-Packard Development Company, L.P. Annotations to executable images for improved dynamic optimization functions
EP1211598A1 (en) * 2000-11-29 2002-06-05 Texas Instruments Incorporated Data processing apparatus, system and method
US7085705B2 (en) * 2000-12-21 2006-08-01 Microsoft Corporation System and method for the logical substitution of processor control in an emulated computing environment
US7069545B2 (en) * 2000-12-29 2006-06-27 Intel Corporation Quantization and compression for computation reuse
US7185330B1 (en) 2001-01-05 2007-02-27 Xilinx, Inc. Code optimization method and system
US6988167B2 (en) * 2001-02-08 2006-01-17 Analog Devices, Inc. Cache system with DMA capabilities and method for operating same
US20020161957A1 (en) * 2001-02-09 2002-10-31 Guillaume Comeau Methods and systems for handling interrupts
US7080373B2 (en) * 2001-03-07 2006-07-18 Freescale Semiconductor, Inc. Method and device for creating and using pre-internalized program files
US6775763B2 (en) * 2001-03-09 2004-08-10 Koninklijke Philips Electronics N.V. Bytecode instruction processor with switch instruction handling logic
FR2822256B1 (en) * 2001-03-13 2003-05-30 Gemplus Card Int VERIFICATION OF CONFORMITY OF ACCESS TO OBJECTS IN A DATA PROCESSING SYSTEM WITH A SECURITY POLICY
GB2373349B (en) * 2001-03-15 2005-02-23 Proksim Software Inc Data definition language
US7184003B2 (en) * 2001-03-16 2007-02-27 Dualcor Technologies, Inc. Personal electronics device with display switching
US7017154B2 (en) * 2001-03-23 2006-03-21 International Business Machines Corporation Eliminating store/restores within hot function prolog/epilogs using volatile registers
US6452426B1 (en) * 2001-04-16 2002-09-17 Nagesh Tamarapalli Circuit for switching between multiple clocks
US7032158B2 (en) * 2001-04-23 2006-04-18 Quickshift, Inc. System and method for recognizing and configuring devices embedded on memory modules
US20020166004A1 (en) * 2001-05-02 2002-11-07 Kim Jason Seung-Min Method for implementing soft-DMA (software based direct memory access engine) for multiple processor systems
US6574708B2 (en) * 2001-05-18 2003-06-03 Broadcom Corporation Source controlled cache allocation
GB2376097B (en) * 2001-05-31 2005-04-06 Advanced Risc Mach Ltd Configuration control within data processing systems
GB2376100B (en) * 2001-05-31 2005-03-09 Advanced Risc Mach Ltd Data processing using multiple instruction sets
US7152223B1 (en) * 2001-06-04 2006-12-19 Microsoft Corporation Methods and systems for compiling and interpreting one or more associations between declarations and implementations in a language neutral fashion
US6961941B1 (en) * 2001-06-08 2005-11-01 Vmware, Inc. Computer configuration for resource management in systems including a virtual machine
US20030195989A1 (en) * 2001-07-02 2003-10-16 Globespan Virata Incorporated Communications system using rings architecture
CN1529847A (en) 2001-07-16 2004-09-15 任宇清 Embedded software update system
US7107439B2 (en) * 2001-08-10 2006-09-12 Mips Technologies, Inc. System and method of controlling software decompression through exceptions
US7434030B2 (en) * 2001-09-12 2008-10-07 Renesas Technology Corp. Processor system having accelerator of Java-type of programming language
WO2003025757A2 (en) * 2001-09-14 2003-03-27 Sun Microsystems, Inc. Method and apparatus for decoupling tag and data accesses in a cache memory
WO2003027842A2 (en) * 2001-09-25 2003-04-03 Koninklijke Philips Electronics N.V. Software support for virtual machine interpreter (vmi) acceleration hardware
FR2831289B1 (en) * 2001-10-19 2004-01-23 St Microelectronics Sa MICROPROCESSOR WITH EXTENDED ADDRESSABLE SPACE
US7003778B2 (en) * 2001-10-24 2006-02-21 Sun Microsystems, Inc. Exception handling in java computing environments
US6915513B2 (en) * 2001-11-29 2005-07-05 Hewlett-Packard Development Company, L.P. System and method for dynamically replacing code
US7062762B2 (en) * 2001-12-12 2006-06-13 Texas Instruments Incorporated Partitioning symmetric nodes efficiently in a split register file architecture
US7363467B2 (en) 2002-01-03 2008-04-22 Intel Corporation Dependence-chain processing using trace descriptors having dependency descriptors
US6912649B2 (en) * 2002-03-13 2005-06-28 International Business Machines Corporation Scheme to encode predicted values into an instruction stream/cache without additional bits/area
US7131120B2 (en) * 2002-05-16 2006-10-31 Sun Microsystems, Inc. Inter Java virtual machine (JVM) resource locking mechanism
US7065613B1 (en) * 2002-06-06 2006-06-20 Maxtor Corporation Method for reducing access to main memory using a stack cache
US6957322B1 (en) * 2002-07-25 2005-10-18 Advanced Micro Devices, Inc. Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion
EP1387253B1 (en) 2002-07-31 2017-09-20 Texas Instruments Incorporated Dynamic translation and execution of instructions within a processor
US7051177B2 (en) * 2002-07-31 2006-05-23 International Business Machines Corporation Method for measuring memory latency in a hierarchical memory system
EP1387249B1 (en) * 2002-07-31 2019-03-13 Texas Instruments Incorporated RISC processor having a stack and register architecture
EP1391821A3 (en) * 2002-07-31 2007-06-06 Texas Instruments Inc. A multi processor computing system having a java stack machine and a risc based processor
US7237236B2 (en) * 2002-08-22 2007-06-26 International Business Machines Corporation Method and apparatus for automatically determining optimum placement of privileged code locations in existing code
GB2392515B (en) * 2002-08-28 2005-08-17 Livedevices Ltd Improvements relating to stack usage in computer-related operating systems
US7165156B1 (en) * 2002-09-06 2007-01-16 3Pardata, Inc. Read-write snapshots
US7146607B2 (en) * 2002-09-17 2006-12-05 International Business Machines Corporation Method and system for transparent dynamic optimization in a multiprocessing environment
US7246346B2 (en) * 2002-09-17 2007-07-17 Microsoft Corporation System and method for persisting dynamically generated code in a directly addressable and executable storage medium
US7313797B2 (en) * 2002-09-18 2007-12-25 Wind River Systems, Inc. Uniprocessor operating system design facilitating fast context switching
US7200721B1 (en) * 2002-10-09 2007-04-03 Unisys Corporation Verification of memory operations by multiple processors to a shared memory
US20040083467A1 (en) * 2002-10-29 2004-04-29 Sharp Laboratories Of America, Inc. System and method for executing intermediate code
US7155708B2 (en) * 2002-10-31 2006-12-26 Src Computers, Inc. Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation
KR100503077B1 (en) * 2002-12-02 2005-07-21 삼성전자주식회사 A java execution device and a java execution method
US7194736B2 (en) * 2002-12-10 2007-03-20 Intel Corporation Dynamic division optimization for a just-in-time compiler
US6883074B2 (en) * 2002-12-13 2005-04-19 Sun Microsystems, Inc. System and method for efficient write operations for repeated snapshots by copying-on-write to most recent snapshot
US7383550B2 (en) * 2002-12-23 2008-06-03 International Business Machines Corporation Topology aware grid services scheduler architecture
WO2004079583A1 (en) * 2003-03-05 2004-09-16 Fujitsu Limited Data transfer controller and dma data transfer control method
JP3899046B2 (en) * 2003-03-20 2007-03-28 インターナショナル・ビジネス・マシーンズ・コーポレーション Compiler device, compiler program, recording medium, and compiling method
JP3992102B2 (en) * 2003-06-04 2007-10-17 インターナショナル・ビジネス・マシーンズ・コーポレーション Compiler device, compilation method, compiler program, and recording medium
JP2004318628A (en) * 2003-04-18 2004-11-11 Hitachi Industries Co Ltd Processor unit
US7051146B2 (en) * 2003-06-25 2006-05-23 Lsi Logic Corporation Data processing systems including high performance buses and interfaces, and associated communication methods
US7194732B2 (en) * 2003-06-26 2007-03-20 Hewlett-Packard Development Company, L.P. System and method for facilitating profiling an application
US7917734B2 (en) * 2003-06-30 2011-03-29 Intel Corporation Determining length of instruction with multiple byte escape code based on information from other than opcode byte
US7073007B1 (en) * 2003-07-22 2006-07-04 Cisco Technology, Inc. Interrupt efficiency across expansion busses
US20050028132A1 (en) * 2003-07-31 2005-02-03 Srinivasamurthy Venugopal K. Application specific optimization of interpreters for embedded systems
EP1660993B1 (en) * 2003-08-28 2008-11-19 MIPS Technologies, Inc. Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
US7207038B2 (en) 2003-08-29 2007-04-17 Nokia Corporation Constructing control flows graphs of binary executable programs at post-link time
US7328436B2 (en) * 2003-09-15 2008-02-05 Motorola, Inc. Dynamic allocation of internal memory at runtime
US20050071611A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus for counting data accesses and instruction executions that exceed a threshold
US20050086662A1 (en) * 2003-10-21 2005-04-21 Monnie David J. Object monitoring system in shared object space
US7631307B2 (en) * 2003-12-05 2009-12-08 Intel Corporation User-programmable low-overhead multithreading
US7401328B2 (en) * 2003-12-18 2008-07-15 Lsi Corporation Software-implemented grouping techniques for use in a superscalar data processing system
US7380039B2 (en) * 2003-12-30 2008-05-27 3Tera, Inc. Apparatus, method and system for aggregrating computing resources
US7370180B2 (en) * 2004-03-08 2008-05-06 Arm Limited Bit field extraction with sign or zero extend
US7802080B2 (en) * 2004-03-24 2010-09-21 Arm Limited Null exception handling
US20050262487A1 (en) * 2004-05-11 2005-11-24 International Business Machines Corporation System, apparatus, and method for identifying authorization requirements in component-based systems
US7376674B2 (en) * 2004-05-14 2008-05-20 Oracle International Corporation Storage of multiple pre-modification short duration copies of database information in short term memory
JP2005338987A (en) * 2004-05-25 2005-12-08 Fujitsu Ltd Exception test support program and device
EP1622009A1 (en) 2004-07-27 2006-02-01 Texas Instruments Incorporated JSM architecture and systems
US20060031820A1 (en) * 2004-08-09 2006-02-09 Aizhong Li Method for program transformation and apparatus for COBOL to Java program transformation
US7818723B2 (en) * 2004-09-07 2010-10-19 Sap Ag Antipattern detection processing for a multithreaded application
US7194606B2 (en) * 2004-09-28 2007-03-20 Hewlett-Packard Development Company, L.P. Method and apparatus for using predicates in a processing device
US20060236000A1 (en) * 2005-04-15 2006-10-19 Falkowski John T Method and system of split-streaming direct memory access
US7877740B2 (en) * 2005-06-13 2011-01-25 Hewlett-Packard Development Company, L.P. Handling caught exceptions
US7899661B2 (en) * 2006-02-16 2011-03-01 Synopsys, Inc. Run-time switching for simulation with dynamic run-time accuracy adjustment

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4398243A (en) * 1980-04-25 1983-08-09 Data General Corporation Data processing system having a unique instruction processor system
US6799246B1 (en) * 1993-06-24 2004-09-28 Discovision Associates Memory interface for reading/writing data from/to a memory
US6217234B1 (en) * 1994-07-29 2001-04-17 Discovision Associates Apparatus and method for processing data with an arithmetic unit
US20040015533A1 (en) * 1995-08-16 2004-01-22 Microunity Systems Engineering, Inc. Multiplier array processing system with enhanced utilization at lower precision
US20040158689A1 (en) * 1995-08-16 2004-08-12 Microunity Systems Engineering, Inc. System and software for matched aligned and unaligned storage instructions
US7171543B1 (en) * 2000-03-28 2007-01-30 Intel Corp. Method and apparatus for executing a 32-bit application by confining the application to a 32-bit address space subset in a 64-bit processor
US20030105945A1 (en) * 2001-11-01 2003-06-05 Bops, Inc. Methods and apparatus for a bit rake instruction
US20060129723A1 (en) * 2004-12-15 2006-06-15 Microsoft Corporation Retry strategies for use in a streaming environment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9135170B2 (en) 2012-05-15 2015-09-15 Futurewei Technologies, Inc. Memory mapping and translation for arbitrary number of memory units
CN102929981A (en) * 2012-10-17 2013-02-13 Tcl通力电子(惠州)有限公司 Media scanned file indexing method and device
WO2019229538A3 (en) * 2018-05-30 2020-05-22 赛灵思公司 Data conversion structure, method and on-chip implementation thereof

Also Published As

Publication number Publication date
US20060026400A1 (en) 2006-02-02
US20060026575A1 (en) 2006-02-02
US20060026398A1 (en) 2006-02-02
US20060026580A1 (en) 2006-02-02
US20060026370A1 (en) 2006-02-02
US7260682B2 (en) 2007-08-21
US8380906B2 (en) 2013-02-19
US8024716B2 (en) 2011-09-20
US20060026395A1 (en) 2006-02-02
US20060026353A1 (en) 2006-02-02
US20060026403A1 (en) 2006-02-02
US20060026183A1 (en) 2006-02-02
US20060026390A1 (en) 2006-02-02
US20060026574A1 (en) 2006-02-02
US20060026565A1 (en) 2006-02-02
US7533250B2 (en) 2009-05-12
US7743384B2 (en) 2010-06-22
US8516496B2 (en) 2013-08-20
US20060026394A1 (en) 2006-02-02
US7752610B2 (en) 2010-07-06
EP1622009A1 (en) 2006-02-01
US20060026200A1 (en) 2006-02-02
US7624382B2 (en) 2009-11-24
US7587583B2 (en) 2009-09-08
US20060026564A1 (en) 2006-02-02
US7546437B2 (en) 2009-06-09
US7500085B2 (en) 2009-03-03
US9201807B2 (en) 2015-12-01
US20060026126A1 (en) 2006-02-02
US20060026412A1 (en) 2006-02-02
US8024554B2 (en) 2011-09-20
US7930689B2 (en) 2011-04-19
US20060025986A1 (en) 2006-02-02
US20060026402A1 (en) 2006-02-02
US20060026404A1 (en) 2006-02-02
US7543285B2 (en) 2009-06-02
US20060026312A1 (en) 2006-02-02
US20060026407A1 (en) 2006-02-02
US7493476B2 (en) 2009-02-17
US7606977B2 (en) 2009-10-20
US20060026391A1 (en) 2006-02-02
US20060026392A1 (en) 2006-02-02
US20060026322A1 (en) 2006-02-02
US8078842B2 (en) 2011-12-13
US20060026393A1 (en) 2006-02-02
US20060026405A1 (en) 2006-02-02
US7757223B2 (en) 2010-07-13
US8046748B2 (en) 2011-10-25
US20060026354A1 (en) 2006-02-02
US20060026571A1 (en) 2006-02-02
US20060026566A1 (en) 2006-02-02
US20060026563A1 (en) 2006-02-02
US20060026201A1 (en) 2006-02-02
US7574584B2 (en) 2009-08-11
US20060026357A1 (en) 2006-02-02
US20060026396A1 (en) 2006-02-02
US8185666B2 (en) 2012-05-22
US20060026397A1 (en) 2006-02-02
US20060026401A1 (en) 2006-02-02

Similar Documents

Publication Publication Date Title
US20060023517A1 (en) Method and system for dynamic address translation
RU2571364C2 (en) Method and computer system for hiding selected installed functions of multifunctional command
US7146613B2 (en) JAVA DSP acceleration by byte-code optimization
US5734874A (en) Central processing unit with integrated graphics functions
US7430734B2 (en) Interface invoke mechanism
US6499095B1 (en) Machine-independent memory management system within a run-time environment
US6704926B1 (en) Bimodal Java just-in-time complier
US7840782B2 (en) Mixed stack-based RISC processor
US20040024729A1 (en) Method and system for storing sparse data in memory and accessing stored sparse data
EP1503291B1 (en) Reformat logic to reformat a memory access to a device
US20050146449A1 (en) Mechanism to improve performance monitoring overhead
US6826672B1 (en) Capability addressing with tight object bounds
US6829686B2 (en) Method and apparatus for bag-to-set, buffering remembered set
US10733095B2 (en) Performing garbage collection on an object array using array chunk references
US6925640B2 (en) Method and apparatus for extending a program element in a dynamically typed programming language
US20220374353A1 (en) Write barrier for remembered set maintenance in generational z garbage collector
Brown et al. The Persistent Abstract Machine
US7496930B2 (en) Accessing device driver memory in programming language representation
US6671783B1 (en) Method and article for managing references between objects in memories of different durations in a run-time environment
US9977737B2 (en) Method and an apparatus for memory address allignment
US8453133B2 (en) Optimization of N-base typed arithmetic instructions via rework
US7010786B2 (en) Predictive arithmetic overflow detection
US7207037B2 (en) Overflow sensitive arithmetic instruction optimization using chaining
US6877161B1 (en) Address calculation of invariant references within a run-time environment
US20200050542A1 (en) Fast initialization of complex in-memory data structures

Legal Events

Date Code Title Description
AS Assignment

Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CABILLIC, GILBERT;MAJOUL, SALAM;REEL/FRAME:016802/0554

Effective date: 20050721

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION